/*
 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "fsl-ls208xa.dtsi"

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x0>;
		clocks = <&clockgen 1 0>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x1>;
		clocks = <&clockgen 1 0>;
		next-level-cache = <&cluster0_l2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x100>;
		clocks = <&clockgen 1 1>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x101>;
		clocks = <&clockgen 1 1>;
		next-level-cache = <&cluster1_l2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x200>;
		clocks = <&clockgen 1 2>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x201>;
		clocks = <&clockgen 1 2>;
		next-level-cache = <&cluster2_l2>;
	};

	cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x300>;
		clocks = <&clockgen 1 3>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x301>;
		clocks = <&clockgen 1 3>;
		next-level-cache = <&cluster3_l2>;
	};

	cluster0_l2: l2-cache0 {
		compatible = "cache";
	};

	cluster1_l2: l2-cache1 {
		compatible = "cache";
	};

	cluster2_l2: l2-cache2 {
		compatible = "cache";
	};

	cluster3_l2: l2-cache3 {
		compatible = "cache";
	};
};

&pcie1 {
	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
};

&pcie2 {
	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
};

&pcie3 {
	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
};

&pcie4 {
	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
};