/* * Device Tree Source for the r8a7790 SoC * * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include / { compatible = "renesas,r8a7790"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &iic0; i2c5 = &iic1; i2c6 = &iic2; i2c7 = &iic3; spi0 = &qspi; spi1 = &msiof0; spi2 = &msiof1; spi3 = &msiof2; spi4 = &msiof3; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, <1225000 1000000>, <1050000 1000000>, < 875000 1000000>, < 700000 1000000>, < 350000 1000000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; }; cpu4: cpu@4 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; }; cpu5: cpu@5 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; }; cpu6: cpu@6 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; }; cpu7: cpu@7 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; }; }; gic: interrupt-controller@f1001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6050000 0 0x50>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6051000 0 0x50>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6052000 0 0x50>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6053000 0 0x50>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6054000 0 0x50>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6055000 0 0x50>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; }; thermal@e61f0000 { compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; cmt0: timer@ffca0000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_CMT0>; clock-names = "fck"; renesas,channels-mask = <0x60>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, <0 121 IRQ_TYPE_LEVEL_HIGH>, <0 122 IRQ_TYPE_LEVEL_HIGH>, <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 124 IRQ_TYPE_LEVEL_HIGH>, <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_CMT1>; clock-names = "fck"; renesas,channels-mask = <0xff>; status = "disabled"; }; irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7790", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6508000 0 0x40>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C0>; status = "disabled"; }; i2c1: i2c@e6518000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6518000 0 0x40>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C1>; status = "disabled"; }; i2c2: i2c@e6530000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6530000 0 0x40>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C2>; status = "disabled"; }; i2c3: i2c@e6540000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6540000 0 0x40>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C3>; status = "disabled"; }; iic0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC0>; status = "disabled"; }; iic1: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC1>; status = "disabled"; }; iic2: i2c@e6520000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x425>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC2>; status = "disabled"; }; iic3: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; status = "disabled"; }; mmcif0: mmcif@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; reg-io-width = <4>; status = "disabled"; }; mmcif1: mmc@ee220000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; reg-io-width = <4>; status = "disabled"; }; pfc: pfc@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; }; sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; cap-sd-highspeed; status = "disabled"; }; sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x200>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; cap-sd-highspeed; status = "disabled"; }; sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; cap-sd-highspeed; status = "disabled"; }; sdhi3: sd@ee160000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; cap-sd-highspeed; status = "disabled"; }; scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7790", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "sci_ick"; status = "disabled"; }; scifa1: serial@e6c50000 { compatible = "renesas,scifa-r8a7790", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; clock-names = "sci_ick"; status = "disabled"; }; scifa2: serial@e6c60000 { compatible = "renesas,scifa-r8a7790", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; clock-names = "sci_ick"; status = "disabled"; }; scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7790", "renesas,scifb"; reg = <0 0xe6c20000 0 64>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "sci_ick"; status = "disabled"; }; scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7790", "renesas,scifb"; reg = <0 0xe6c30000 0 64>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "sci_ick"; status = "disabled"; }; scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7790", "renesas,scifb"; reg = <0 0xe6ce0000 0 64>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "sci_ick"; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7790", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; clock-names = "sci_ick"; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a7790", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; clock-names = "sci_ick"; status = "disabled"; }; hscif0: serial@e62c0000 { compatible = "renesas,hscif-r8a7790", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; clock-names = "sci_ick"; status = "disabled"; }; hscif1: serial@e62c8000 { compatible = "renesas,hscif-r8a7790", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; clock-names = "sci_ick"; status = "disabled"; }; ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7790"; reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_ETHER>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; sata0: sata@ee300000 { compatible = "renesas,sata-r8a7790"; reg = <0 0xee300000 0 0x2000>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_SATA0>; status = "disabled"; }; sata1: sata@ee500000 { compatible = "renesas,sata-r8a7790"; reg = <0 0xee500000 0 0x2000>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_SATA1>; status = "disabled"; }; clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clock */ extal_clk: extal_clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; clock-output-names = "extal"; }; /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "pcie_bus"; status = "disabled"; }; /* * The external audio clocks are configured as 0 Hz fixed frequency clocks by * default. Boards that provide audio clocks should override them. */ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; clock-output-names = "audio_clk_c"; }; /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7790-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z"; }; /* Variable factor clocks */ sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd2"; }; sd3_clk: sd3_clk@e615007c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615007c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "mmc0"; }; mmc1_clk: mmc1_clk@e6150244 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "mmc1"; }; ssp_clk: ssp_clk@e6150248 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150248 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "ssp"; }; ssprs_clk: ssprs_clk@e615024c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615024c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "ssprs"; }; /* Fixed factor clocks */ pll1_div2_clk: pll1_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "pll1_div2"; }; z2_clk: z2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "z2"; }; zg_clk: zg_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; clock-output-names = "zg"; }; zx_clk: zx_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; clock-output-names = "zx"; }; zs_clk: zs_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; clock-output-names = "zs"; }; hp_clk: hp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "hp"; }; i_clk: i_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "i"; }; b_clk: b_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "b"; }; p_clk: p_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; clock-output-names = "p"; }; cl_clk: cl_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; clock-output-names = "cl"; }; m2_clk: m2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "m2"; }; imp_clk: imp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "imp"; }; rclk_clk: rclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; clock-output-names = "rclk"; }; oscclk_clk: oscclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; clock-output-names = "oscclk"; }; zb3_clk: zb3_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "zb3"; }; zb3d2_clk: zb3d2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "zb3d2"; }; ddr_clk: ddr_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "ddr"; }; mp_clk: mp_clk { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; clock-output-names = "mp"; }; cp_clk: cp_clk { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "cp"; }; /* Gate clocks */ mstp0_clks: mstp0_clks@e6150130 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; clocks = <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = ; clock-output-names = "msiof0"; }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", "scifb1", "msiof1", "msiof3", "scifb2"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "iic0", "pciec", "iic1", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; clocks = <&extal_clk>, <&p_clk>; #clock-cells = <1>; renesas,clock-indices = ; clock-output-names = "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 >; clock-output-names = "ehci", "hsusb", "hscif1", "hscif0", "scif1", "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 >; clock-output-names = "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 >; clock-output-names = "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "iic3", "i2c3", "i2c2", "i2c1", "i2c0"; }; mstp10_clks: mstp10_clks@e6150998 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; #clock-cells = <1>; clock-indices = < R8A7790_CLK_SSI_ALL R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 R8A7790_CLK_SCU_ALL R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 >; clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", "scu-all", "scu-dvc1", "scu-dvc0", "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; }; }; qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7790"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7790"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7790"; reg = <0 0xe6e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof3: spi@e6c90000 { compatible = "renesas,msiof-r8a7790"; reg = <0 0xe6c90000 0 0x0064>; interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pci0: pci@ee090000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; clocks = <&mstp7_clks R8A7790_CLK_EHCI>; reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; }; pci1: pci@ee0b0000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; clocks = <&mstp7_clks R8A7790_CLK_EHCI>; reg = <0 0xee0b0000 0 0xc00>, <0 0xee0a0000 0 0x1100>; interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; bus-range = <1 1>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; }; pci2: pci@ee0d0000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; clocks = <&mstp7_clks R8A7790_CLK_EHCI>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; bus-range = <2 2>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; interrupt-map-mask = <0xff00 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; }; pciec: pcie@fe000000 { compatible = "renesas,pcie-r8a7790"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; device_type = "pci"; ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; /* Map all possible DDR as inbound ranges */ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 118 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; status = "disabled"; }; rcar_sound: rcar_sound@0xec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; interrupt-parent = <&gic>; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x1280>; /* SSI */ clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; status = "disabled"; rcar_sound,dvc { dvc0: dvc@0 { }; dvc1: dvc@1 { }; }; rcar_sound,src { src0: src@0 { }; src1: src@1 { }; src2: src@2 { }; src3: src@3 { }; src4: src@4 { }; src5: src@5 { }; src6: src@6 { }; src7: src@7 { }; src8: src@8 { }; src9: src@9 { }; }; rcar_sound,ssi { ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; }; }; };