Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or "jaguar2", or "amazon,alpine-dw-apb-ssi" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. - clocks : phandles for the clocks, see the description of clock-names below. The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock is optional. If a single clock is specified but no clock-name, it is the "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first. Optional properties: - clock-names : Contains the names of the clocks: "ssi_clk", for the core clock used to generate the external SPI clock. "pclk", the interface clock, required for register access. - cs-gpios : Specifies the gpio pins to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. Example: spi@fff00000 { compatible = "snps,dw-apb-ssi"; reg = <0xfff00000 0x1000>; interrupts = <0 154 4>; #address-cells = <1>; #size-cells = <0>; clocks = <&spi_m_clk>; num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; };