Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6
[sfrench/cifs-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
146 {
147         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
148         struct kvm_lapic_irq irqe;
149
150         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
151                      "vector=%x trig_mode=%x\n",
152                      entry->fields.dest, entry->fields.dest_mode,
153                      entry->fields.delivery_mode, entry->fields.vector,
154                      entry->fields.trig_mode);
155
156         irqe.dest_id = entry->fields.dest_id;
157         irqe.vector = entry->fields.vector;
158         irqe.dest_mode = entry->fields.dest_mode;
159         irqe.trig_mode = entry->fields.trig_mode;
160         irqe.delivery_mode = entry->fields.delivery_mode << 8;
161         irqe.level = 1;
162         irqe.shorthand = 0;
163
164 #ifdef CONFIG_X86
165         /* Always delivery PIT interrupt to vcpu 0 */
166         if (irq == 0) {
167                 irqe.dest_mode = 0; /* Physical mode. */
168                 irqe.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
169         }
170 #endif
171         return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
172 }
173
174 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
175 {
176         u32 old_irr = ioapic->irr;
177         u32 mask = 1 << irq;
178         union kvm_ioapic_redirect_entry entry;
179         int ret = 1;
180
181         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
182                 entry = ioapic->redirtbl[irq];
183                 level ^= entry.fields.polarity;
184                 if (!level)
185                         ioapic->irr &= ~mask;
186                 else {
187                         ioapic->irr |= mask;
188                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
189                             || !entry.fields.remote_irr)
190                                 ret = ioapic_service(ioapic, irq);
191                 }
192         }
193         return ret;
194 }
195
196 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
197                                     int trigger_mode)
198 {
199         union kvm_ioapic_redirect_entry *ent;
200
201         ent = &ioapic->redirtbl[pin];
202
203         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
204
205         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
206                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
207                 ent->fields.remote_irr = 0;
208                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
209                         ioapic_service(ioapic, pin);
210         }
211 }
212
213 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
214 {
215         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
216         int i;
217
218         for (i = 0; i < IOAPIC_NUM_PINS; i++)
219                 if (ioapic->redirtbl[i].fields.vector == vector)
220                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
221 }
222
223 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
224                            int len, int is_write)
225 {
226         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
227
228         return ((addr >= ioapic->base_address &&
229                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
230 }
231
232 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
233                              void *val)
234 {
235         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
236         u32 result;
237
238         ioapic_debug("addr %lx\n", (unsigned long)addr);
239         ASSERT(!(addr & 0xf));  /* check alignment */
240
241         addr &= 0xff;
242         switch (addr) {
243         case IOAPIC_REG_SELECT:
244                 result = ioapic->ioregsel;
245                 break;
246
247         case IOAPIC_REG_WINDOW:
248                 result = ioapic_read_indirect(ioapic, addr, len);
249                 break;
250
251         default:
252                 result = 0;
253                 break;
254         }
255         switch (len) {
256         case 8:
257                 *(u64 *) val = result;
258                 break;
259         case 1:
260         case 2:
261         case 4:
262                 memcpy(val, (char *)&result, len);
263                 break;
264         default:
265                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
266         }
267 }
268
269 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
270                               const void *val)
271 {
272         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
273         u32 data;
274
275         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
276                      (void*)addr, len, val);
277         ASSERT(!(addr & 0xf));  /* check alignment */
278         if (len == 4 || len == 8)
279                 data = *(u32 *) val;
280         else {
281                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
282                 return;
283         }
284
285         addr &= 0xff;
286         switch (addr) {
287         case IOAPIC_REG_SELECT:
288                 ioapic->ioregsel = data;
289                 break;
290
291         case IOAPIC_REG_WINDOW:
292                 ioapic_write_indirect(ioapic, data);
293                 break;
294 #ifdef  CONFIG_IA64
295         case IOAPIC_REG_EOI:
296                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
297                 break;
298 #endif
299
300         default:
301                 break;
302         }
303 }
304
305 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
306 {
307         int i;
308
309         for (i = 0; i < IOAPIC_NUM_PINS; i++)
310                 ioapic->redirtbl[i].fields.mask = 1;
311         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
312         ioapic->ioregsel = 0;
313         ioapic->irr = 0;
314         ioapic->id = 0;
315 }
316
317 int kvm_ioapic_init(struct kvm *kvm)
318 {
319         struct kvm_ioapic *ioapic;
320
321         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
322         if (!ioapic)
323                 return -ENOMEM;
324         kvm->arch.vioapic = ioapic;
325         kvm_ioapic_reset(ioapic);
326         ioapic->dev.read = ioapic_mmio_read;
327         ioapic->dev.write = ioapic_mmio_write;
328         ioapic->dev.in_range = ioapic_in_range;
329         ioapic->dev.private = ioapic;
330         ioapic->kvm = kvm;
331         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
332         return 0;
333 }
334