virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  25 {
  26         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  27
  28         cpuif->vgic_hcr |= ICH_HCR_UIE;
  29 }
  30
  31 static bool lr_signals_eoi_mi(u64 lr_val)
  32 {
  33         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  34                !(lr_val & ICH_LR_HW);
  35 }
  36
  37 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  38 {
  39         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  40         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  41         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  42         int lr;
  43
  44         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
  45
  46         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  47                 u64 val = cpuif->vgic_lr[lr];
  48                 u32 intid;
  49                 struct vgic_irq *irq;
  50
  51                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  52                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  53                 else
  54                         intid = val & GICH_LR_VIRTUALID;
  55
  56                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  57                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  58                         kvm_notify_acked_irq(vcpu->kvm, 0,
  59                                              intid - VGIC_NR_PRIVATE_IRQS);
  60
  61                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  62                 if (!irq)       /* An LPI could have been unmapped. */
  63                         continue;
  64
  65                 spin_lock(&irq->irq_lock);
  66
  67                 /* Always preserve the active bit */
  68                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  69
  70                 /* Edge is the only case where we preserve the pending bit */
  71                 if (irq->config == VGIC_CONFIG_EDGE &&
  72                     (val & ICH_LR_PENDING_BIT)) {
  73                         irq->pending_latch = true;
  74
  75                         if (vgic_irq_is_sgi(intid) &&
  76                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  77                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  78
  79                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  80                                 irq->source |= (1 << cpuid);
  81                         }
  82                 }
  83
  84                 /*
  85                  * Clear soft pending state when level irqs have been acked.
  86                  * Always regenerate the pending state.
  87                  */
  88                 if (irq->config == VGIC_CONFIG_LEVEL) {
  89                         if (!(val & ICH_LR_PENDING_BIT))
  90                                 irq->pending_latch = false;
  91                 }
  92
  93                 spin_unlock(&irq->irq_lock);
  94                 vgic_put_irq(vcpu->kvm, irq);
  95         }
  96
  97         vgic_cpu->used_lrs = 0;
  98 }
  99
 100 /* Requires the irq to be locked already */
 101 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 102 {
 103         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 104         u64 val = irq->intid;
 105
 106         if (irq_is_pending(irq)) {
 107                 val |= ICH_LR_PENDING_BIT;
 108
 109                 if (irq->config == VGIC_CONFIG_EDGE)
 110                         irq->pending_latch = false;
 111
 112                 if (vgic_irq_is_sgi(irq->intid) &&
 113                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 114                         u32 src = ffs(irq->source);
 115
 116                         BUG_ON(!src);
 117                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 118                         irq->source &= ~(1 << (src - 1));
 119                         if (irq->source)
 120                                 irq->pending_latch = true;
 121                 }
 122         }
 123
 124         if (irq->active)
 125                 val |= ICH_LR_ACTIVE_BIT;
 126
 127         if (irq->hw) {
 128                 val |= ICH_LR_HW;
 129                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 130                 /*
 131                  * Never set pending+active on a HW interrupt, as the
 132                  * pending state is kept at the physical distributor
 133                  * level.
 134                  */
 135                 if (irq->active && irq_is_pending(irq))
 136                         val &= ~ICH_LR_PENDING_BIT;
 137         } else {
 138                 if (irq->config == VGIC_CONFIG_LEVEL)
 139                         val |= ICH_LR_EOI;
 140         }
 141
 142         /*
 143          * We currently only support Group1 interrupts, which is a
 144          * known defect. This needs to be addressed at some point.
 145          */
 146         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 147                 val |= ICH_LR_GROUP;
 148
 149         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 150
 151         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 152 }
 153
 154 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 155 {
 156         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 157 }
 158
 159 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 160 {
 161         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 162         u32 vmcr;
 163
 164         /*
 165          * Ignore the FIQen bit, because GIC emulation always implies
 166          * SRE=1 which means the vFIQEn bit is also RES1.
 167          */
 168         vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
 169                  ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 170         vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 171         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 172         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 173         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 174         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 175         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 176
 177         cpu_if->vgic_vmcr = vmcr;
 178 }
 179
 180 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 181 {
 182         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 183         u32 vmcr;
 184
 185         vmcr = cpu_if->vgic_vmcr;
 186
 187         /*
 188          * Ignore the FIQen bit, because GIC emulation always implies
 189          * SRE=1 which means the vFIQEn bit is also RES1.
 190          */
 191         vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
 192                         ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
 193         vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 194         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 195         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 196         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 197         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 198         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 199 }
 200
 201 #define INITIAL_PENDBASER_VALUE                                           \
 202         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 203         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 204         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 205
 206 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 207 {
 208         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 209
 210         /*
 211          * By forcing VMCR to zero, the GIC will restore the binary
 212          * points to their reset values. Anything else resets to zero
 213          * anyway.
 214          */
 215         vgic_v3->vgic_vmcr = 0;
 216         vgic_v3->vgic_elrsr = ~0;
 217
 218         /*
 219          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 220          * way, so we force SRE to 1 to demonstrate this to the guest.
 221          * Also, we don't support any form of IRQ/FIQ bypass.
 222          * This goes with the spec allowing the value to be RAO/WI.
 223          */
 224         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 225                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 226                                      ICC_SRE_EL1_DFB |
 227                                      ICC_SRE_EL1_SRE);
 228                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 229         } else {
 230                 vgic_v3->vgic_sre = 0;
 231         }
 232
 233         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 234                                            ICH_VTR_ID_BITS_MASK) >>
 235                                            ICH_VTR_ID_BITS_SHIFT;
 236         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 237                                             ICH_VTR_PRI_BITS_MASK) >>
 238                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 239
 240         /* Get the show on the road... */
 241         vgic_v3->vgic_hcr = ICH_HCR_EN;
 242 }
 243
 244 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
 245 {
 246         struct kvm_vcpu *vcpu;
 247         int byte_offset, bit_nr;
 248         gpa_t pendbase, ptr;
 249         bool status;
 250         u8 val;
 251         int ret;
 252
 253 retry:
 254         vcpu = irq->target_vcpu;
 255         if (!vcpu)
 256                 return 0;
 257
 258         pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 259
 260         byte_offset = irq->intid / BITS_PER_BYTE;
 261         bit_nr = irq->intid % BITS_PER_BYTE;
 262         ptr = pendbase + byte_offset;
 263
 264         ret = kvm_read_guest(kvm, ptr, &val, 1);
 265         if (ret)
 266                 return ret;
 267
 268         status = val & (1 << bit_nr);
 269
 270         spin_lock(&irq->irq_lock);
 271         if (irq->target_vcpu != vcpu) {
 272                 spin_unlock(&irq->irq_lock);
 273                 goto retry;
 274         }
 275         irq->pending_latch = status;
 276         vgic_queue_irq_unlock(vcpu->kvm, irq);
 277
 278         if (status) {
 279                 /* clear consumed data */
 280                 val &= ~(1 << bit_nr);
 281                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 282                 if (ret)
 283                         return ret;
 284         }
 285         return 0;
 286 }
 287
 288 /**
 289  * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 290  * kvm lock and all vcpu lock must be held
 291  */
 292 int vgic_v3_save_pending_tables(struct kvm *kvm)
 293 {
 294         struct vgic_dist *dist = &kvm->arch.vgic;
 295         int last_byte_offset = -1;
 296         struct vgic_irq *irq;
 297         int ret;
 298
 299         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 300                 int byte_offset, bit_nr;
 301                 struct kvm_vcpu *vcpu;
 302                 gpa_t pendbase, ptr;
 303                 bool stored;
 304                 u8 val;
 305
 306                 vcpu = irq->target_vcpu;
 307                 if (!vcpu)
 308                         continue;
 309
 310                 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 311
 312                 byte_offset = irq->intid / BITS_PER_BYTE;
 313                 bit_nr = irq->intid % BITS_PER_BYTE;
 314                 ptr = pendbase + byte_offset;
 315
 316                 if (byte_offset != last_byte_offset) {
 317                         ret = kvm_read_guest(kvm, ptr, &val, 1);
 318                         if (ret)
 319                                 return ret;
 320                         last_byte_offset = byte_offset;
 321                 }
 322
 323                 stored = val & (1U << bit_nr);
 324                 if (stored == irq->pending_latch)
 325                         continue;
 326
 327                 if (irq->pending_latch)
 328                         val |= 1 << bit_nr;
 329                 else
 330                         val &= ~(1 << bit_nr);
 331
 332                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 333                 if (ret)
 334                         return ret;
 335         }
 336         return 0;
 337 }
 338
 339 /*
 340  * Check for overlapping regions and for regions crossing the end of memory
 341  * for base addresses which have already been set.
 342  */
 343 bool vgic_v3_check_base(struct kvm *kvm)
 344 {
 345         struct vgic_dist *d = &kvm->arch.vgic;
 346         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 347
 348         redist_size *= atomic_read(&kvm->online_vcpus);
 349
 350         if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 351             d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 352                 return false;
 353
 354         if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
 355             d->vgic_redist_base + redist_size < d->vgic_redist_base)
 356                 return false;
 357
 358         /* Both base addresses must be set to check if they overlap */
 359         if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
 360             IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
 361                 return true;
 362
 363         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 364                 return true;
 365         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 366                 return true;
 367
 368         return false;
 369 }
 370
 371 int vgic_v3_map_resources(struct kvm *kvm)
 372 {
 373         int ret = 0;
 374         struct vgic_dist *dist = &kvm->arch.vgic;
 375
 376         if (vgic_ready(kvm))
 377                 goto out;
 378
 379         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 380             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 381                 kvm_err("Need to set vgic distributor addresses first\n");
 382                 ret = -ENXIO;
 383                 goto out;
 384         }
 385
 386         if (!vgic_v3_check_base(kvm)) {
 387                 kvm_err("VGIC redist and dist frames overlap\n");
 388                 ret = -EINVAL;
 389                 goto out;
 390         }
 391
 392         /*
 393          * For a VGICv3 we require the userland to explicitly initialize
 394          * the VGIC before we need to use it.
 395          */
 396         if (!vgic_initialized(kvm)) {
 397                 ret = -EBUSY;
 398                 goto out;
 399         }
 400
 401         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 402         if (ret) {
 403                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 404                 goto out;
 405         }
 406
 407         dist->ready = true;
 408
 409 out:
 410         return ret;
 411 }
 412
 413 /**
 414  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 415  * @node:       pointer to the DT node
 416  *
 417  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 418  */
 419 int vgic_v3_probe(const struct gic_kvm_info *info)
 420 {
 421         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 422         int ret;
 423
 424         /*
 425          * The ListRegs field is 5 bits, but there is a architectural
 426          * maximum of 16 list registers. Just ignore bit 4...
 427          */
 428         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 429         kvm_vgic_global_state.can_emulate_gicv2 = false;
 430         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 431
 432         if (!info->vcpu.start) {
 433                 kvm_info("GICv3: no GICV resource entry\n");
 434                 kvm_vgic_global_state.vcpu_base = 0;
 435         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 436                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 437                         (unsigned long long)info->vcpu.start);
 438                 kvm_vgic_global_state.vcpu_base = 0;
 439         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 440                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 441                         (unsigned long long)resource_size(&info->vcpu),
 442                         PAGE_SIZE);
 443                 kvm_vgic_global_state.vcpu_base = 0;
 444         } else {
 445                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 446                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 447                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 448                 if (ret) {
 449                         kvm_err("Cannot register GICv2 KVM device.\n");
 450                         return ret;
 451                 }
 452                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 453         }
 454         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 455         if (ret) {
 456                 kvm_err("Cannot register GICv3 KVM device.\n");
 457                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 458                 return ret;
 459         }
 460
 461         if (kvm_vgic_global_state.vcpu_base == 0)
 462                 kvm_info("disabling GICv2 emulation\n");
 463
 464         kvm_vgic_global_state.vctrl_base = NULL;
 465         kvm_vgic_global_state.type = VGIC_V3;
 466         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 467
 468         return 0;
 469 }
 470
 471 void vgic_v3_load(struct kvm_vcpu *vcpu)
 472 {
 473         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 474
 475         /*
 476          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 477          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 478          * VMCR_EL2 save/restore in the world switch.
 479          */
 480         if (likely(cpu_if->vgic_sre))
 481                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 482 }
 483
 484 void vgic_v3_put(struct kvm_vcpu *vcpu)
 485 {
 486         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 487
 488         if (likely(cpu_if->vgic_sre))
 489                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 490 }