sound/soc/zte/zx-i2s.c

   1 /*
   2  * Copyright (C) 2015 Linaro
   3  *
   4  * Author: Jun Nie <jun.nie@linaro.org>
   5  *
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/device.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include <sound/soc.h>
  18 #include <sound/soc-dai.h>
  19
  20 #include <sound/core.h>
  21 #include <sound/dmaengine_pcm.h>
  22 #include <sound/initval.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26
  27 #define ZX_I2S_PROCESS_CTRL     0x04
  28 #define ZX_I2S_TIMING_CTRL      0x08
  29 #define ZX_I2S_FIFO_CTRL        0x0C
  30 #define ZX_I2S_FIFO_STATUS      0x10
  31 #define ZX_I2S_INT_EN           0x14
  32 #define ZX_I2S_INT_STATUS       0x18
  33 #define ZX_I2S_DATA             0x1C
  34 #define ZX_I2S_FRAME_CNTR       0x20
  35
  36 #define I2S_DEAGULT_FIFO_THRES  (0x10)
  37 #define I2S_MAX_FIFO_THRES      (0x20)
  38
  39 #define ZX_I2S_PROCESS_TX_EN    (1 << 0)
  40 #define ZX_I2S_PROCESS_TX_DIS   (0 << 0)
  41 #define ZX_I2S_PROCESS_RX_EN    (1 << 1)
  42 #define ZX_I2S_PROCESS_RX_DIS   (0 << 1)
  43 #define ZX_I2S_PROCESS_I2S_EN   (1 << 2)
  44 #define ZX_I2S_PROCESS_I2S_DIS  (0 << 2)
  45
  46 #define ZX_I2S_TIMING_MAST              (1 << 0)
  47 #define ZX_I2S_TIMING_SLAVE             (0 << 0)
  48 #define ZX_I2S_TIMING_MS_MASK           (1 << 0)
  49 #define ZX_I2S_TIMING_LOOP              (1 << 1)
  50 #define ZX_I2S_TIMING_NOR               (0 << 1)
  51 #define ZX_I2S_TIMING_LOOP_MASK         (1 << 1)
  52 #define ZX_I2S_TIMING_PTNR              (1 << 2)
  53 #define ZX_I2S_TIMING_NTPR              (0 << 2)
  54 #define ZX_I2S_TIMING_PHASE_MASK        (1 << 2)
  55 #define ZX_I2S_TIMING_TDM               (1 << 3)
  56 #define ZX_I2S_TIMING_I2S               (0 << 3)
  57 #define ZX_I2S_TIMING_TIMING_MASK       (1 << 3)
  58 #define ZX_I2S_TIMING_LONG_SYNC         (1 << 4)
  59 #define ZX_I2S_TIMING_SHORT_SYNC        (0 << 4)
  60 #define ZX_I2S_TIMING_SYNC_MASK         (1 << 4)
  61 #define ZX_I2S_TIMING_TEAK_EN           (1 << 5)
  62 #define ZX_I2S_TIMING_TEAK_DIS          (0 << 5)
  63 #define ZX_I2S_TIMING_TEAK_MASK         (1 << 5)
  64 #define ZX_I2S_TIMING_STD_I2S           (0 << 6)
  65 #define ZX_I2S_TIMING_MSB_JUSTIF        (1 << 6)
  66 #define ZX_I2S_TIMING_LSB_JUSTIF        (2 << 6)
  67 #define ZX_I2S_TIMING_ALIGN_MASK        (3 << 6)
  68 #define ZX_I2S_TIMING_CHN_MASK          (7 << 8)
  69 #define ZX_I2S_TIMING_CHN(x)            ((x - 1) << 8)
  70 #define ZX_I2S_TIMING_LANE_MASK         (3 << 11)
  71 #define ZX_I2S_TIMING_LANE(x)           ((x - 1) << 11)
  72 #define ZX_I2S_TIMING_TSCFG_MASK        (7 << 13)
  73 #define ZX_I2S_TIMING_TSCFG(x)          (x << 13)
  74 #define ZX_I2S_TIMING_TS_WIDTH_MASK     (0x1f << 16)
  75 #define ZX_I2S_TIMING_TS_WIDTH(x)       ((x - 1) << 16)
  76 #define ZX_I2S_TIMING_DATA_SIZE_MASK    (0x1f << 21)
  77 #define ZX_I2S_TIMING_DATA_SIZE(x)      ((x - 1) << 21)
  78 #define ZX_I2S_TIMING_CFG_ERR_MASK      (1 << 31)
  79
  80 #define ZX_I2S_FIFO_CTRL_TX_RST         (1 << 0)
  81 #define ZX_I2S_FIFO_CTRL_TX_RST_MASK    (1 << 0)
  82 #define ZX_I2S_FIFO_CTRL_RX_RST         (1 << 1)
  83 #define ZX_I2S_FIFO_CTRL_RX_RST_MASK    (1 << 1)
  84 #define ZX_I2S_FIFO_CTRL_TX_DMA_EN      (1 << 4)
  85 #define ZX_I2S_FIFO_CTRL_TX_DMA_DIS     (0 << 4)
  86 #define ZX_I2S_FIFO_CTRL_TX_DMA_MASK    (1 << 4)
  87 #define ZX_I2S_FIFO_CTRL_RX_DMA_EN      (1 << 5)
  88 #define ZX_I2S_FIFO_CTRL_RX_DMA_DIS     (0 << 5)
  89 #define ZX_I2S_FIFO_CTRL_RX_DMA_MASK    (1 << 5)
  90 #define ZX_I2S_FIFO_CTRL_TX_THRES_MASK  (0x1F << 8)
  91 #define ZX_I2S_FIFO_CTRL_RX_THRES_MASK  (0x1F << 16)
  92
  93 #define CLK_RAT (32 * 4)
  94
  95 struct zx_i2s_info {
  96         struct snd_dmaengine_dai_dma_data       dma_playback;
  97         struct snd_dmaengine_dai_dma_data       dma_capture;
  98         struct clk                              *dai_wclk;
  99         struct clk                              *dai_pclk;
 100         void __iomem                            *reg_base;
 101         int                                     master;
 102         resource_size_t                         mapbase;
 103 };
 104
 105 static void zx_i2s_tx_en(void __iomem *base, bool on)
 106 {
 107         unsigned long val;
 108
 109         val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
 110         if (on)
 111                 val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
 112         else
 113                 val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
 114         writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
 115 }
 116
 117 static void zx_i2s_rx_en(void __iomem *base, bool on)
 118 {
 119         unsigned long val;
 120
 121         val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
 122         if (on)
 123                 val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
 124         else
 125                 val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
 126         writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
 127 }
 128
 129 static void zx_i2s_tx_dma_en(void __iomem *base, bool on)
 130 {
 131         unsigned long val;
 132
 133         val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
 134         val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
 135         if (on)
 136                 val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
 137         else
 138                 val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
 139         writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
 140 }
 141
 142 static void zx_i2s_rx_dma_en(void __iomem *base, bool on)
 143 {
 144         unsigned long val;
 145
 146         val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
 147         val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
 148         if (on)
 149                 val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
 150         else
 151                 val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
 152         writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
 153 }
 154
 155 #define ZX_I2S_RATES \
 156         (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
 157          SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 158          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000| \
 159          SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
 160
 161 #define ZX_I2S_FMTBIT \
 162         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
 163         SNDRV_PCM_FMTBIT_S32_LE)
 164
 165 static int zx_i2s_dai_probe(struct snd_soc_dai *dai)
 166 {
 167         struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
 168
 169         snd_soc_dai_set_drvdata(dai, zx_i2s);
 170         zx_i2s->dma_playback.addr = zx_i2s->mapbase + ZX_I2S_DATA;
 171         zx_i2s->dma_playback.maxburst = 16;
 172         zx_i2s->dma_capture.addr = zx_i2s->mapbase + ZX_I2S_DATA;
 173         zx_i2s->dma_capture.maxburst = 16;
 174         snd_soc_dai_init_dma_data(dai, &zx_i2s->dma_playback,
 175                                   &zx_i2s->dma_capture);
 176         return 0;
 177 }
 178
 179 static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 180 {
 181         struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 182         unsigned long val;
 183
 184         val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
 185         val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
 186                         ZX_I2S_TIMING_TEAK_MASK | ZX_I2S_TIMING_SYNC_MASK |
 187                         ZX_I2S_TIMING_MS_MASK);
 188
 189         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 190         case SND_SOC_DAIFMT_I2S:
 191                 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
 192                 break;
 193         case SND_SOC_DAIFMT_LEFT_J:
 194                 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
 195                 break;
 196         case SND_SOC_DAIFMT_RIGHT_J:
 197                 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
 198                 break;
 199         default:
 200                 dev_err(cpu_dai->dev, "Unknown i2s timeing\n");
 201                 return -EINVAL;
 202         }
 203
 204         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 205         case SND_SOC_DAIFMT_CBM_CFM:
 206                 i2s->master = 1;
 207                 val |= ZX_I2S_TIMING_MAST;
 208                 break;
 209         case SND_SOC_DAIFMT_CBS_CFS:
 210                 i2s->master = 0;
 211                 val |= ZX_I2S_TIMING_SLAVE;
 212                 break;
 213         default:
 214                 dev_err(cpu_dai->dev, "Unknown master/slave format\n");
 215                 return -EINVAL;
 216         }
 217
 218         writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
 219         return 0;
 220 }
 221
 222 static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
 223                             struct snd_pcm_hw_params *params,
 224                             struct snd_soc_dai *socdai)
 225 {
 226         struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
 227         struct snd_dmaengine_dai_dma_data *dma_data;
 228         unsigned int lane, ch_num, len, ret = 0;
 229         unsigned int ts_width = 32;
 230         unsigned long val;
 231         unsigned long chn_cfg;
 232
 233         dma_data = snd_soc_dai_get_dma_data(socdai, substream);
 234         dma_data->addr_width = ts_width >> 3;
 235
 236         val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
 237         val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
 238                 ZX_I2S_TIMING_LANE_MASK | ZX_I2S_TIMING_CHN_MASK |
 239                 ZX_I2S_TIMING_TSCFG_MASK);
 240
 241         switch (params_format(params)) {
 242         case SNDRV_PCM_FORMAT_S16_LE:
 243                 len = 16;
 244                 break;
 245         case SNDRV_PCM_FORMAT_S24_LE:
 246                 len = 24;
 247                 break;
 248         case SNDRV_PCM_FORMAT_S32_LE:
 249                 len = 32;
 250                 break;
 251         default:
 252                 dev_err(socdai->dev, "Unknown data format\n");
 253                 return -EINVAL;
 254         }
 255         val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
 256
 257         ch_num = params_channels(params);
 258         switch (ch_num) {
 259         case 1:
 260                 lane = 1;
 261                 chn_cfg = 2;
 262                 break;
 263         case 2:
 264         case 4:
 265         case 6:
 266         case 8:
 267                 lane = ch_num / 2;
 268                 chn_cfg = 3;
 269                 break;
 270         default:
 271                 dev_err(socdai->dev, "Not support channel num %d\n", ch_num);
 272                 return -EINVAL;
 273         }
 274         val |= ZX_I2S_TIMING_LANE(lane);
 275         val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
 276         val |= ZX_I2S_TIMING_CHN(ch_num);
 277         writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
 278
 279         if (i2s->master)
 280                 ret = clk_set_rate(i2s->dai_wclk,
 281                                 params_rate(params) * ch_num * CLK_RAT);
 282
 283         return ret;
 284 }
 285
 286 static int zx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 287                           struct snd_soc_dai *dai)
 288 {
 289         struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
 290         int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
 291         int ret = 0;
 292
 293         switch (cmd) {
 294         case SNDRV_PCM_TRIGGER_START:
 295                 if (capture)
 296                         zx_i2s_rx_dma_en(zx_i2s->reg_base, true);
 297                 else
 298                         zx_i2s_tx_dma_en(zx_i2s->reg_base, true);
 299         /* fall thru */
 300         case SNDRV_PCM_TRIGGER_RESUME:
 301         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 302                 if (capture)
 303                         zx_i2s_rx_en(zx_i2s->reg_base, true);
 304                 else
 305                         zx_i2s_tx_en(zx_i2s->reg_base, true);
 306                 break;
 307
 308         case SNDRV_PCM_TRIGGER_STOP:
 309                 if (capture)
 310                         zx_i2s_rx_dma_en(zx_i2s->reg_base, false);
 311                 else
 312                         zx_i2s_tx_dma_en(zx_i2s->reg_base, false);
 313         /* fall thru */
 314         case SNDRV_PCM_TRIGGER_SUSPEND:
 315         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 316                 if (capture)
 317                         zx_i2s_rx_en(zx_i2s->reg_base, false);
 318                 else
 319                         zx_i2s_tx_en(zx_i2s->reg_base, false);
 320                 break;
 321
 322         default:
 323                 ret = -EINVAL;
 324                 break;
 325         }
 326
 327         return ret;
 328 }
 329
 330 static int zx_i2s_startup(struct snd_pcm_substream *substream,
 331                           struct snd_soc_dai *dai)
 332 {
 333         struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
 334         int ret;
 335
 336         ret = clk_prepare_enable(zx_i2s->dai_wclk);
 337         if (ret)
 338                 return ret;
 339
 340         ret = clk_prepare_enable(zx_i2s->dai_pclk);
 341         if (ret) {
 342                 clk_disable_unprepare(zx_i2s->dai_wclk);
 343                 return ret;
 344         }
 345
 346         return ret;
 347 }
 348
 349 static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
 350                             struct snd_soc_dai *dai)
 351 {
 352         struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
 353
 354         clk_disable_unprepare(zx_i2s->dai_wclk);
 355         clk_disable_unprepare(zx_i2s->dai_pclk);
 356 }
 357
 358 static struct snd_soc_dai_ops zx_i2s_dai_ops = {
 359         .trigger        = zx_i2s_trigger,
 360         .hw_params      = zx_i2s_hw_params,
 361         .set_fmt        = zx_i2s_set_fmt,
 362         .startup        = zx_i2s_startup,
 363         .shutdown       = zx_i2s_shutdown,
 364 };
 365
 366 static const struct snd_soc_component_driver zx_i2s_component = {
 367         .name                   = "zx-i2s",
 368 };
 369
 370 static struct snd_soc_dai_driver zx_i2s_dai = {
 371         .name   = "zx-i2s-dai",
 372         .id     = 0,
 373         .probe  = zx_i2s_dai_probe,
 374         .playback   = {
 375                 .channels_min   = 1,
 376                 .channels_max   = 8,
 377                 .rates          = ZX_I2S_RATES,
 378                 .formats        = ZX_I2S_FMTBIT,
 379         },
 380         .capture = {
 381                 .channels_min   = 1,
 382                 .channels_max   = 2,
 383                 .rates          = ZX_I2S_RATES,
 384                 .formats        = ZX_I2S_FMTBIT,
 385         },
 386         .ops    = &zx_i2s_dai_ops,
 387 };
 388
 389 static int zx_i2s_probe(struct platform_device *pdev)
 390 {
 391         struct resource *res;
 392         struct zx_i2s_info *zx_i2s;
 393         int ret;
 394
 395         zx_i2s = devm_kzalloc(&pdev->dev, sizeof(*zx_i2s), GFP_KERNEL);
 396         if (!zx_i2s)
 397                 return -ENOMEM;
 398
 399         zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
 400         if (IS_ERR(zx_i2s->dai_wclk)) {
 401                 dev_err(&pdev->dev, "Fail to get wclk\n");
 402                 return PTR_ERR(zx_i2s->dai_wclk);
 403         }
 404
 405         zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
 406         if (IS_ERR(zx_i2s->dai_pclk)) {
 407                 dev_err(&pdev->dev, "Fail to get pclk\n");
 408                 return PTR_ERR(zx_i2s->dai_pclk);
 409         }
 410
 411         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 412         zx_i2s->mapbase = res->start;
 413         zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res);
 414         if (IS_ERR(zx_i2s->reg_base)) {
 415                 dev_err(&pdev->dev, "ioremap failed!\n");
 416                 return PTR_ERR(zx_i2s->reg_base);
 417         }
 418
 419         writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL);
 420         platform_set_drvdata(pdev, zx_i2s);
 421
 422         ret = devm_snd_soc_register_component(&pdev->dev, &zx_i2s_component,
 423                                               &zx_i2s_dai, 1);
 424         if (ret) {
 425                 dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
 426                 return ret;
 427         }
 428
 429         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 430         if (ret)
 431                 dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
 432
 433         return ret;
 434 }
 435
 436 static const struct of_device_id zx_i2s_dt_ids[] = {
 437         { .compatible = "zte,zx296702-i2s", },
 438         {}
 439 };
 440 MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
 441
 442 static struct platform_driver i2s_driver = {
 443         .probe = zx_i2s_probe,
 444         .driver = {
 445                 .name = "zx-i2s",
 446                 .of_match_table = zx_i2s_dt_ids,
 447         },
 448 };
 449
 450 module_platform_driver(i2s_driver);
 451
 452 MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
 453 MODULE_DESCRIPTION("ZTE I2S SoC DAI");
 454 MODULE_LICENSE("GPL");