sound/soc/sunxi/sun4i-i2s.c

   1 /*
   2  * Copyright (C) 2015 Andrea Venturi
   3  * Andrea Venturi <be17068@iperbole.bo.it>
   4  *
   5  * Copyright (C) 2016 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 #include <sound/dmaengine_pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27
  28 #define SUN4I_I2S_CTRL_REG              0x00
  29 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  30 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  31 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  32 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  33 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  34 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  35 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  36 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  37
  38 #define SUN4I_I2S_FMT0_REG              0x04
  39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  45 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  46 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  47 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  48 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  49 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  51 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  52 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  55
  56 #define SUN4I_I2S_FMT1_REG              0x08
  57 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  58 #define SUN4I_I2S_FIFO_RX_REG           0x10
  59
  60 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  67
  68 #define SUN4I_I2S_FIFO_STA_REG          0x18
  69
  70 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  73
  74 #define SUN4I_I2S_INT_STA_REG           0x20
  75
  76 #define SUN4I_I2S_CLK_DIV_REG           0x24
  77 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  82
  83 #define SUN4I_I2S_RX_CNT_REG            0x28
  84 #define SUN4I_I2S_TX_CNT_REG            0x2c
  85
  86 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  87 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  88
  89 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  91
  92 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  93 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  94
  95 /* Defines required for sun8i-h3 support */
  96 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  97 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  98
  99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
 101
 102 #define SUN8I_I2S_INT_STA_REG           0x0c
 103 #define SUN8I_I2S_FIFO_TX_REG           0x20
 104
 105 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 110
 111 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 112 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 12)
 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 115 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 117
 118 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 119 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 120
 121 /**
 122  * struct sun4i_i2s_quirks - Differences between SoC variants.
 123  *
 124  * @has_reset: SoC needs reset deasserted.
 125  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 126  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 127  * @has_chcfg: tx and rx slot number need to be set.
 128  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 129  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 130  * @reg_offset_txdata: offset of the tx fifo.
 131  * @sun4i_i2s_regmap: regmap config to use.
 132  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 133  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 134  * @fmt_offset: Value by which wss and sr needs to be adjusted.
 135  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 136  * @field_fmt_wss: regmap field to set word select size.
 137  * @field_fmt_sr: regmap field to set sample resolution.
 138  * @field_fmt_bclk: regmap field to set clk polarity.
 139  * @field_fmt_lrclk: regmap field to set frame polarity.
 140  * @field_fmt_mode: regmap field to set the operational mode.
 141  * @field_txchanmap: location of the tx channel mapping register.
 142  * @field_rxchanmap: location of the rx channel mapping register.
 143  * @field_txchansel: location of the tx channel select bit fields.
 144  * @field_rxchansel: location of the rx channel select bit fields.
 145  */
 146 struct sun4i_i2s_quirks {
 147         bool                            has_reset;
 148         bool                            has_slave_select_bit;
 149         bool                            has_fmt_set_lrck_period;
 150         bool                            has_chcfg;
 151         bool                            has_chsel_tx_chen;
 152         bool                            has_chsel_offset;
 153         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 154         const struct regmap_config      *sun4i_i2s_regmap;
 155         unsigned int                    mclk_offset;
 156         unsigned int                    bclk_offset;
 157         unsigned int                    fmt_offset;
 158
 159         /* Register fields for i2s */
 160         struct reg_field                field_clkdiv_mclk_en;
 161         struct reg_field                field_fmt_wss;
 162         struct reg_field                field_fmt_sr;
 163         struct reg_field                field_fmt_bclk;
 164         struct reg_field                field_fmt_lrclk;
 165         struct reg_field                field_fmt_mode;
 166         struct reg_field                field_txchanmap;
 167         struct reg_field                field_rxchanmap;
 168         struct reg_field                field_txchansel;
 169         struct reg_field                field_rxchansel;
 170 };
 171
 172 struct sun4i_i2s {
 173         struct clk      *bus_clk;
 174         struct clk      *mod_clk;
 175         struct regmap   *regmap;
 176         struct reset_control *rst;
 177
 178         unsigned int    mclk_freq;
 179
 180         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 181         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 182
 183         /* Register fields for i2s */
 184         struct regmap_field     *field_clkdiv_mclk_en;
 185         struct regmap_field     *field_fmt_wss;
 186         struct regmap_field     *field_fmt_sr;
 187         struct regmap_field     *field_fmt_bclk;
 188         struct regmap_field     *field_fmt_lrclk;
 189         struct regmap_field     *field_fmt_mode;
 190         struct regmap_field     *field_txchanmap;
 191         struct regmap_field     *field_rxchanmap;
 192         struct regmap_field     *field_txchansel;
 193         struct regmap_field     *field_rxchansel;
 194
 195         const struct sun4i_i2s_quirks   *variant;
 196 };
 197
 198 struct sun4i_i2s_clk_div {
 199         u8      div;
 200         u8      val;
 201 };
 202
 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 204         { .div = 2, .val = 0 },
 205         { .div = 4, .val = 1 },
 206         { .div = 6, .val = 2 },
 207         { .div = 8, .val = 3 },
 208         { .div = 12, .val = 4 },
 209         { .div = 16, .val = 5 },
 210         /* TODO - extend divide ratio supported by newer SoCs */
 211 };
 212
 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 214         { .div = 1, .val = 0 },
 215         { .div = 2, .val = 1 },
 216         { .div = 4, .val = 2 },
 217         { .div = 6, .val = 3 },
 218         { .div = 8, .val = 4 },
 219         { .div = 12, .val = 5 },
 220         { .div = 16, .val = 6 },
 221         { .div = 24, .val = 7 },
 222         /* TODO - extend divide ratio supported by newer SoCs */
 223 };
 224
 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 226                                   unsigned int oversample_rate,
 227                                   unsigned int word_size)
 228 {
 229         int div = oversample_rate / word_size / 2;
 230         int i;
 231
 232         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 233                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 234
 235                 if (bdiv->div == div)
 236                         return bdiv->val;
 237         }
 238
 239         return -EINVAL;
 240 }
 241
 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 243                                   unsigned int oversample_rate,
 244                                   unsigned int module_rate,
 245                                   unsigned int sampling_rate)
 246 {
 247         int div = module_rate / sampling_rate / oversample_rate;
 248         int i;
 249
 250         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 251                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 252
 253                 if (mdiv->div == div)
 254                         return mdiv->val;
 255         }
 256
 257         return -EINVAL;
 258 }
 259
 260 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 261 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 262 {
 263         int i;
 264
 265         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 266                 if (sun4i_i2s_oversample_rates[i] == oversample)
 267                         return true;
 268
 269         return false;
 270 }
 271
 272 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
 273                                   unsigned int rate,
 274                                   unsigned int word_size)
 275 {
 276         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 277         unsigned int oversample_rate, clk_rate;
 278         int bclk_div, mclk_div;
 279         int ret;
 280
 281         switch (rate) {
 282         case 176400:
 283         case 88200:
 284         case 44100:
 285         case 22050:
 286         case 11025:
 287                 clk_rate = 22579200;
 288                 break;
 289
 290         case 192000:
 291         case 128000:
 292         case 96000:
 293         case 64000:
 294         case 48000:
 295         case 32000:
 296         case 24000:
 297         case 16000:
 298         case 12000:
 299         case 8000:
 300                 clk_rate = 24576000;
 301                 break;
 302
 303         default:
 304                 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
 305                 return -EINVAL;
 306         }
 307
 308         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 309         if (ret)
 310                 return ret;
 311
 312         oversample_rate = i2s->mclk_freq / rate;
 313         if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
 314                 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
 315                         oversample_rate);
 316                 return -EINVAL;
 317         }
 318
 319         bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
 320                                           word_size);
 321         if (bclk_div < 0) {
 322                 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
 323                 return -EINVAL;
 324         }
 325
 326         mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
 327                                           clk_rate, rate);
 328         if (mclk_div < 0) {
 329                 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
 330                 return -EINVAL;
 331         }
 332
 333         /* Adjust the clock division values if needed */
 334         bclk_div += i2s->variant->bclk_offset;
 335         mclk_div += i2s->variant->mclk_offset;
 336
 337         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 338                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 339                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 340
 341         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 342
 343         /* Set sync period */
 344         if (i2s->variant->has_fmt_set_lrck_period)
 345                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 346                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 347                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 348
 349         return 0;
 350 }
 351
 352 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 353                                struct snd_pcm_hw_params *params,
 354                                struct snd_soc_dai *dai)
 355 {
 356         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 357         int sr, wss, channels;
 358         u32 width;
 359
 360         channels = params_channels(params);
 361         if (channels != 2) {
 362                 dev_err(dai->dev, "Unsupported number of channels: %d\n",
 363                         channels);
 364                 return -EINVAL;
 365         }
 366
 367         if (i2s->variant->has_chcfg) {
 368                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 369                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 370                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 371                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 372                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 373                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 374         }
 375
 376         /* Map the channels for playback and capture */
 377         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 378         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 379
 380         /* Configure the channels */
 381         regmap_field_write(i2s->field_txchansel,
 382                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 383
 384         regmap_field_write(i2s->field_rxchansel,
 385                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 386
 387         if (i2s->variant->has_chsel_tx_chen)
 388                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 389                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 390                                    SUN8I_I2S_TX_CHAN_EN(channels));
 391
 392         switch (params_physical_width(params)) {
 393         case 16:
 394                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 395                 break;
 396         default:
 397                 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
 398                         params_physical_width(params));
 399                 return -EINVAL;
 400         }
 401         i2s->playback_dma_data.addr_width = width;
 402
 403         switch (params_width(params)) {
 404         case 16:
 405                 sr = 0;
 406                 wss = 0;
 407                 break;
 408
 409         default:
 410                 dev_err(dai->dev, "Unsupported sample width: %d\n",
 411                         params_width(params));
 412                 return -EINVAL;
 413         }
 414
 415         regmap_field_write(i2s->field_fmt_wss,
 416                            wss + i2s->variant->fmt_offset);
 417         regmap_field_write(i2s->field_fmt_sr,
 418                            sr + i2s->variant->fmt_offset);
 419
 420         return sun4i_i2s_set_clk_rate(dai, params_rate(params),
 421                                       params_width(params));
 422 }
 423
 424 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 425 {
 426         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 427         u32 val;
 428         u32 offset = 0;
 429         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 430         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 431
 432         /* DAI Mode */
 433         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 434         case SND_SOC_DAIFMT_I2S:
 435                 val = SUN4I_I2S_FMT0_FMT_I2S;
 436                 offset = 1;
 437                 break;
 438         case SND_SOC_DAIFMT_LEFT_J:
 439                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 440                 break;
 441         case SND_SOC_DAIFMT_RIGHT_J:
 442                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 443                 break;
 444         default:
 445                 dev_err(dai->dev, "Unsupported format: %d\n",
 446                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 447                 return -EINVAL;
 448         }
 449
 450         if (i2s->variant->has_chsel_offset) {
 451                 /*
 452                  * offset being set indicates that we're connected to an i2s
 453                  * device, however offset is only used on the sun8i block and
 454                  * i2s shares the same setting with the LJ format. Increment
 455                  * val so that the bit to value to write is correct.
 456                  */
 457                 if (offset > 0)
 458                         val++;
 459                 /* blck offset determines whether i2s or LJ */
 460                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 461                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 462                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 463
 464                 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
 465                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 466                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 467         }
 468
 469         regmap_field_write(i2s->field_fmt_mode, val);
 470
 471         /* DAI clock polarity */
 472         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 473         case SND_SOC_DAIFMT_IB_IF:
 474                 /* Invert both clocks */
 475                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 476                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 477                 break;
 478         case SND_SOC_DAIFMT_IB_NF:
 479                 /* Invert bit clock */
 480                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 481                 break;
 482         case SND_SOC_DAIFMT_NB_IF:
 483                 /* Invert frame clock */
 484                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 485                 break;
 486         case SND_SOC_DAIFMT_NB_NF:
 487                 break;
 488         default:
 489                 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
 490                         fmt & SND_SOC_DAIFMT_INV_MASK);
 491                 return -EINVAL;
 492         }
 493
 494         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 495         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 496
 497         if (i2s->variant->has_slave_select_bit) {
 498                 /* DAI clock master masks */
 499                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 500                 case SND_SOC_DAIFMT_CBS_CFS:
 501                         /* BCLK and LRCLK master */
 502                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 503                         break;
 504                 case SND_SOC_DAIFMT_CBM_CFM:
 505                         /* BCLK and LRCLK slave */
 506                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 507                         break;
 508                 default:
 509                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 510                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 511                         return -EINVAL;
 512                 }
 513                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 514                                    SUN4I_I2S_CTRL_MODE_MASK,
 515                                    val);
 516         } else {
 517                 /*
 518                  * The newer i2s block does not have a slave select bit,
 519                  * instead the clk pins are configured as inputs.
 520                  */
 521                 /* DAI clock master masks */
 522                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 523                 case SND_SOC_DAIFMT_CBS_CFS:
 524                         /* BCLK and LRCLK master */
 525                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 526                                 SUN8I_I2S_CTRL_LRCK_OUT;
 527                         break;
 528                 case SND_SOC_DAIFMT_CBM_CFM:
 529                         /* BCLK and LRCLK slave */
 530                         val = 0;
 531                         break;
 532                 default:
 533                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 534                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 535                         return -EINVAL;
 536                 }
 537                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 538                                    SUN8I_I2S_CTRL_BCLK_OUT |
 539                                    SUN8I_I2S_CTRL_LRCK_OUT,
 540                                    val);
 541         }
 542
 543         /* Set significant bits in our FIFOs */
 544         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 545                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 546                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 547                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 548                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 549         return 0;
 550 }
 551
 552 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 553 {
 554         /* Flush RX FIFO */
 555         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 556                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 557                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 558
 559         /* Clear RX counter */
 560         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 561
 562         /* Enable RX Block */
 563         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 564                            SUN4I_I2S_CTRL_RX_EN,
 565                            SUN4I_I2S_CTRL_RX_EN);
 566
 567         /* Enable RX DRQ */
 568         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 569                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 570                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 571 }
 572
 573 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 574 {
 575         /* Flush TX FIFO */
 576         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 577                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 578                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 579
 580         /* Clear TX counter */
 581         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 582
 583         /* Enable TX Block */
 584         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 585                            SUN4I_I2S_CTRL_TX_EN,
 586                            SUN4I_I2S_CTRL_TX_EN);
 587
 588         /* Enable TX DRQ */
 589         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 590                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 591                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 592 }
 593
 594 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 595 {
 596         /* Disable RX Block */
 597         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 598                            SUN4I_I2S_CTRL_RX_EN,
 599                            0);
 600
 601         /* Disable RX DRQ */
 602         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 603                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 604                            0);
 605 }
 606
 607 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 608 {
 609         /* Disable TX Block */
 610         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 611                            SUN4I_I2S_CTRL_TX_EN,
 612                            0);
 613
 614         /* Disable TX DRQ */
 615         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 616                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 617                            0);
 618 }
 619
 620 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 621                              struct snd_soc_dai *dai)
 622 {
 623         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 624
 625         switch (cmd) {
 626         case SNDRV_PCM_TRIGGER_START:
 627         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 628         case SNDRV_PCM_TRIGGER_RESUME:
 629                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 630                         sun4i_i2s_start_playback(i2s);
 631                 else
 632                         sun4i_i2s_start_capture(i2s);
 633                 break;
 634
 635         case SNDRV_PCM_TRIGGER_STOP:
 636         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 637         case SNDRV_PCM_TRIGGER_SUSPEND:
 638                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 639                         sun4i_i2s_stop_playback(i2s);
 640                 else
 641                         sun4i_i2s_stop_capture(i2s);
 642                 break;
 643
 644         default:
 645                 return -EINVAL;
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 652                                 unsigned int freq, int dir)
 653 {
 654         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 655
 656         if (clk_id != 0)
 657                 return -EINVAL;
 658
 659         i2s->mclk_freq = freq;
 660
 661         return 0;
 662 }
 663
 664 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 665         .hw_params      = sun4i_i2s_hw_params,
 666         .set_fmt        = sun4i_i2s_set_fmt,
 667         .set_sysclk     = sun4i_i2s_set_sysclk,
 668         .trigger        = sun4i_i2s_trigger,
 669 };
 670
 671 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 672 {
 673         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 674
 675         snd_soc_dai_init_dma_data(dai,
 676                                   &i2s->playback_dma_data,
 677                                   &i2s->capture_dma_data);
 678
 679         snd_soc_dai_set_drvdata(dai, i2s);
 680
 681         return 0;
 682 }
 683
 684 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 685         .probe = sun4i_i2s_dai_probe,
 686         .capture = {
 687                 .stream_name = "Capture",
 688                 .channels_min = 2,
 689                 .channels_max = 2,
 690                 .rates = SNDRV_PCM_RATE_8000_192000,
 691                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 692         },
 693         .playback = {
 694                 .stream_name = "Playback",
 695                 .channels_min = 2,
 696                 .channels_max = 2,
 697                 .rates = SNDRV_PCM_RATE_8000_192000,
 698                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 699         },
 700         .ops = &sun4i_i2s_dai_ops,
 701         .symmetric_rates = 1,
 702 };
 703
 704 static const struct snd_soc_component_driver sun4i_i2s_component = {
 705         .name   = "sun4i-dai",
 706 };
 707
 708 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 709 {
 710         switch (reg) {
 711         case SUN4I_I2S_FIFO_TX_REG:
 712                 return false;
 713
 714         default:
 715                 return true;
 716         }
 717 }
 718
 719 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 720 {
 721         switch (reg) {
 722         case SUN4I_I2S_FIFO_RX_REG:
 723         case SUN4I_I2S_FIFO_STA_REG:
 724                 return false;
 725
 726         default:
 727                 return true;
 728         }
 729 }
 730
 731 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 732 {
 733         switch (reg) {
 734         case SUN4I_I2S_FIFO_RX_REG:
 735         case SUN4I_I2S_INT_STA_REG:
 736         case SUN4I_I2S_RX_CNT_REG:
 737         case SUN4I_I2S_TX_CNT_REG:
 738                 return true;
 739
 740         default:
 741                 return false;
 742         }
 743 }
 744
 745 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 746 {
 747         switch (reg) {
 748         case SUN8I_I2S_FIFO_TX_REG:
 749                 return false;
 750
 751         default:
 752                 return true;
 753         }
 754 }
 755
 756 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 757 {
 758         if (reg == SUN8I_I2S_INT_STA_REG)
 759                 return true;
 760         if (reg == SUN8I_I2S_FIFO_TX_REG)
 761                 return false;
 762
 763         return sun4i_i2s_volatile_reg(dev, reg);
 764 }
 765
 766 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 767         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 768         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 769         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 770         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 771         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 772         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 773         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 774         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 775         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 776         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 777 };
 778
 779 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 780         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 781         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 782         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 783         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 784         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 785         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 786         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 787         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 788         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 789         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 790         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 791 };
 792
 793 static const struct regmap_config sun4i_i2s_regmap_config = {
 794         .reg_bits       = 32,
 795         .reg_stride     = 4,
 796         .val_bits       = 32,
 797         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 798
 799         .cache_type     = REGCACHE_FLAT,
 800         .reg_defaults   = sun4i_i2s_reg_defaults,
 801         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 802         .writeable_reg  = sun4i_i2s_wr_reg,
 803         .readable_reg   = sun4i_i2s_rd_reg,
 804         .volatile_reg   = sun4i_i2s_volatile_reg,
 805 };
 806
 807 static const struct regmap_config sun8i_i2s_regmap_config = {
 808         .reg_bits       = 32,
 809         .reg_stride     = 4,
 810         .val_bits       = 32,
 811         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 812         .cache_type     = REGCACHE_FLAT,
 813         .reg_defaults   = sun8i_i2s_reg_defaults,
 814         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 815         .writeable_reg  = sun4i_i2s_wr_reg,
 816         .readable_reg   = sun8i_i2s_rd_reg,
 817         .volatile_reg   = sun8i_i2s_volatile_reg,
 818 };
 819
 820 static int sun4i_i2s_runtime_resume(struct device *dev)
 821 {
 822         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 823         int ret;
 824
 825         ret = clk_prepare_enable(i2s->bus_clk);
 826         if (ret) {
 827                 dev_err(dev, "Failed to enable bus clock\n");
 828                 return ret;
 829         }
 830
 831         regcache_cache_only(i2s->regmap, false);
 832         regcache_mark_dirty(i2s->regmap);
 833
 834         ret = regcache_sync(i2s->regmap);
 835         if (ret) {
 836                 dev_err(dev, "Failed to sync regmap cache\n");
 837                 goto err_disable_clk;
 838         }
 839
 840         /* Enable the whole hardware block */
 841         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 842                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 843
 844         /* Enable the first output line */
 845         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 846                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 847                            SUN4I_I2S_CTRL_SDO_EN(0));
 848
 849         ret = clk_prepare_enable(i2s->mod_clk);
 850         if (ret) {
 851                 dev_err(dev, "Failed to enable module clock\n");
 852                 goto err_disable_clk;
 853         }
 854
 855         return 0;
 856
 857 err_disable_clk:
 858         clk_disable_unprepare(i2s->bus_clk);
 859         return ret;
 860 }
 861
 862 static int sun4i_i2s_runtime_suspend(struct device *dev)
 863 {
 864         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 865
 866         clk_disable_unprepare(i2s->mod_clk);
 867
 868         /* Disable our output lines */
 869         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 870                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 871
 872         /* Disable the whole hardware block */
 873         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 874                            SUN4I_I2S_CTRL_GL_EN, 0);
 875
 876         regcache_cache_only(i2s->regmap, true);
 877
 878         clk_disable_unprepare(i2s->bus_clk);
 879
 880         return 0;
 881 }
 882
 883 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 884         .has_reset              = false,
 885         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 886         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 887         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 888         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 889         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 890         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 891         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 892         .has_slave_select_bit   = true,
 893         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 894         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 895         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 896         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 897         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 898 };
 899
 900 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 901         .has_reset              = true,
 902         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 903         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 904         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 905         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 906         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 907         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 908         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 909         .has_slave_select_bit   = true,
 910         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 911         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 912         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 913         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 914         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 915 };
 916
 917 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
 918         .has_reset              = true,
 919         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 920         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 921         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 922         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 923         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 924         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 925         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 926         .has_slave_select_bit   = true,
 927         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 928         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 929         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 930         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 931         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 932 };
 933
 934 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 935         .has_reset              = true,
 936         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 937         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 938         .mclk_offset            = 1,
 939         .bclk_offset            = 2,
 940         .fmt_offset             = 3,
 941         .has_fmt_set_lrck_period = true,
 942         .has_chcfg              = true,
 943         .has_chsel_tx_chen      = true,
 944         .has_chsel_offset       = true,
 945         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 946         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 947         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 948         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 949         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 950         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 951         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 952         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 953         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 954         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 955 };
 956
 957 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
 958         .has_reset              = true,
 959         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 960         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 961         .has_slave_select_bit   = true,
 962         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 963         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 964         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 965         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 966         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 967         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 968         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 969         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 970         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 971         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 972 };
 973
 974 static int sun4i_i2s_init_regmap_fields(struct device *dev,
 975                                         struct sun4i_i2s *i2s)
 976 {
 977         i2s->field_clkdiv_mclk_en =
 978                 devm_regmap_field_alloc(dev, i2s->regmap,
 979                                         i2s->variant->field_clkdiv_mclk_en);
 980         if (IS_ERR(i2s->field_clkdiv_mclk_en))
 981                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
 982
 983         i2s->field_fmt_wss =
 984                         devm_regmap_field_alloc(dev, i2s->regmap,
 985                                                 i2s->variant->field_fmt_wss);
 986         if (IS_ERR(i2s->field_fmt_wss))
 987                 return PTR_ERR(i2s->field_fmt_wss);
 988
 989         i2s->field_fmt_sr =
 990                         devm_regmap_field_alloc(dev, i2s->regmap,
 991                                                 i2s->variant->field_fmt_sr);
 992         if (IS_ERR(i2s->field_fmt_sr))
 993                 return PTR_ERR(i2s->field_fmt_sr);
 994
 995         i2s->field_fmt_bclk =
 996                         devm_regmap_field_alloc(dev, i2s->regmap,
 997                                                 i2s->variant->field_fmt_bclk);
 998         if (IS_ERR(i2s->field_fmt_bclk))
 999                 return PTR_ERR(i2s->field_fmt_bclk);
1000
1001         i2s->field_fmt_lrclk =
1002                         devm_regmap_field_alloc(dev, i2s->regmap,
1003                                                 i2s->variant->field_fmt_lrclk);
1004         if (IS_ERR(i2s->field_fmt_lrclk))
1005                 return PTR_ERR(i2s->field_fmt_lrclk);
1006
1007         i2s->field_fmt_mode =
1008                         devm_regmap_field_alloc(dev, i2s->regmap,
1009                                                 i2s->variant->field_fmt_mode);
1010         if (IS_ERR(i2s->field_fmt_mode))
1011                 return PTR_ERR(i2s->field_fmt_mode);
1012
1013         i2s->field_txchanmap =
1014                         devm_regmap_field_alloc(dev, i2s->regmap,
1015                                                 i2s->variant->field_txchanmap);
1016         if (IS_ERR(i2s->field_txchanmap))
1017                 return PTR_ERR(i2s->field_txchanmap);
1018
1019         i2s->field_rxchanmap =
1020                         devm_regmap_field_alloc(dev, i2s->regmap,
1021                                                 i2s->variant->field_rxchanmap);
1022         if (IS_ERR(i2s->field_rxchanmap))
1023                 return PTR_ERR(i2s->field_rxchanmap);
1024
1025         i2s->field_txchansel =
1026                         devm_regmap_field_alloc(dev, i2s->regmap,
1027                                                 i2s->variant->field_txchansel);
1028         if (IS_ERR(i2s->field_txchansel))
1029                 return PTR_ERR(i2s->field_txchansel);
1030
1031         i2s->field_rxchansel =
1032                         devm_regmap_field_alloc(dev, i2s->regmap,
1033                                                 i2s->variant->field_rxchansel);
1034         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1035 }
1036
1037 static int sun4i_i2s_probe(struct platform_device *pdev)
1038 {
1039         struct sun4i_i2s *i2s;
1040         struct resource *res;
1041         void __iomem *regs;
1042         int irq, ret;
1043
1044         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1045         if (!i2s)
1046                 return -ENOMEM;
1047         platform_set_drvdata(pdev, i2s);
1048
1049         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050         regs = devm_ioremap_resource(&pdev->dev, res);
1051         if (IS_ERR(regs))
1052                 return PTR_ERR(regs);
1053
1054         irq = platform_get_irq(pdev, 0);
1055         if (irq < 0) {
1056                 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1057                 return irq;
1058         }
1059
1060         i2s->variant = of_device_get_match_data(&pdev->dev);
1061         if (!i2s->variant) {
1062                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1063                 return -ENODEV;
1064         }
1065
1066         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1067         if (IS_ERR(i2s->bus_clk)) {
1068                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1069                 return PTR_ERR(i2s->bus_clk);
1070         }
1071
1072         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1073                                             i2s->variant->sun4i_i2s_regmap);
1074         if (IS_ERR(i2s->regmap)) {
1075                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1076                 return PTR_ERR(i2s->regmap);
1077         }
1078
1079         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1080         if (IS_ERR(i2s->mod_clk)) {
1081                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1082                 return PTR_ERR(i2s->mod_clk);
1083         }
1084
1085         if (i2s->variant->has_reset) {
1086                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1087                 if (IS_ERR(i2s->rst)) {
1088                         dev_err(&pdev->dev, "Failed to get reset control\n");
1089                         return PTR_ERR(i2s->rst);
1090                 }
1091         }
1092
1093         if (!IS_ERR(i2s->rst)) {
1094                 ret = reset_control_deassert(i2s->rst);
1095                 if (ret) {
1096                         dev_err(&pdev->dev,
1097                                 "Failed to deassert the reset control\n");
1098                         return -EINVAL;
1099                 }
1100         }
1101
1102         i2s->playback_dma_data.addr = res->start +
1103                                         i2s->variant->reg_offset_txdata;
1104         i2s->playback_dma_data.maxburst = 8;
1105
1106         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1107         i2s->capture_dma_data.maxburst = 8;
1108
1109         pm_runtime_enable(&pdev->dev);
1110         if (!pm_runtime_enabled(&pdev->dev)) {
1111                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1112                 if (ret)
1113                         goto err_pm_disable;
1114         }
1115
1116         ret = devm_snd_soc_register_component(&pdev->dev,
1117                                               &sun4i_i2s_component,
1118                                               &sun4i_i2s_dai, 1);
1119         if (ret) {
1120                 dev_err(&pdev->dev, "Could not register DAI\n");
1121                 goto err_suspend;
1122         }
1123
1124         ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1125         if (ret) {
1126                 dev_err(&pdev->dev, "Could not register PCM\n");
1127                 goto err_suspend;
1128         }
1129
1130         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1131         if (ret) {
1132                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1133                 goto err_suspend;
1134         }
1135
1136         return 0;
1137
1138 err_suspend:
1139         if (!pm_runtime_status_suspended(&pdev->dev))
1140                 sun4i_i2s_runtime_suspend(&pdev->dev);
1141 err_pm_disable:
1142         pm_runtime_disable(&pdev->dev);
1143         if (!IS_ERR(i2s->rst))
1144                 reset_control_assert(i2s->rst);
1145
1146         return ret;
1147 }
1148
1149 static int sun4i_i2s_remove(struct platform_device *pdev)
1150 {
1151         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1152
1153         snd_dmaengine_pcm_unregister(&pdev->dev);
1154
1155         pm_runtime_disable(&pdev->dev);
1156         if (!pm_runtime_status_suspended(&pdev->dev))
1157                 sun4i_i2s_runtime_suspend(&pdev->dev);
1158
1159         if (!IS_ERR(i2s->rst))
1160                 reset_control_assert(i2s->rst);
1161
1162         return 0;
1163 }
1164
1165 static const struct of_device_id sun4i_i2s_match[] = {
1166         {
1167                 .compatible = "allwinner,sun4i-a10-i2s",
1168                 .data = &sun4i_a10_i2s_quirks,
1169         },
1170         {
1171                 .compatible = "allwinner,sun6i-a31-i2s",
1172                 .data = &sun6i_a31_i2s_quirks,
1173         },
1174         {
1175                 .compatible = "allwinner,sun8i-a83t-i2s",
1176                 .data = &sun8i_a83t_i2s_quirks,
1177         },
1178         {
1179                 .compatible = "allwinner,sun8i-h3-i2s",
1180                 .data = &sun8i_h3_i2s_quirks,
1181         },
1182         {
1183                 .compatible = "allwinner,sun50i-a64-codec-i2s",
1184                 .data = &sun50i_a64_codec_i2s_quirks,
1185         },
1186         {}
1187 };
1188 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1189
1190 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1191         .runtime_resume         = sun4i_i2s_runtime_resume,
1192         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1193 };
1194
1195 static struct platform_driver sun4i_i2s_driver = {
1196         .probe  = sun4i_i2s_probe,
1197         .remove = sun4i_i2s_remove,
1198         .driver = {
1199                 .name           = "sun4i-i2s",
1200                 .of_match_table = sun4i_i2s_match,
1201                 .pm             = &sun4i_i2s_pm_ops,
1202         },
1203 };
1204 module_platform_driver(sun4i_i2s_driver);
1205
1206 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1207 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1208 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1209 MODULE_LICENSE("GPL");