sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25
  26 #define DRV_NAME "rockchip-i2s"
  27
  28 struct rk_i2s_pins {
  29         u32 reg_offset;
  30         u32 shift;
  31 };
  32
  33 struct rk_i2s_dev {
  34         struct device *dev;
  35
  36         struct clk *hclk;
  37         struct clk *mclk;
  38
  39         struct snd_dmaengine_dai_dma_data capture_dma_data;
  40         struct snd_dmaengine_dai_dma_data playback_dma_data;
  41
  42         struct regmap *regmap;
  43         struct regmap *grf;
  44
  45 /*
  46  * Used to indicate the tx/rx status.
  47  * I2S controller hopes to start the tx and rx together,
  48  * also to stop them when they are both try to stop.
  49 */
  50         bool tx_start;
  51         bool rx_start;
  52         bool is_master_mode;
  53         const struct rk_i2s_pins *pins;
  54 };
  55
  56 static int i2s_runtime_suspend(struct device *dev)
  57 {
  58         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  59
  60         regcache_cache_only(i2s->regmap, true);
  61         clk_disable_unprepare(i2s->mclk);
  62
  63         return 0;
  64 }
  65
  66 static int i2s_runtime_resume(struct device *dev)
  67 {
  68         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  69         int ret;
  70
  71         ret = clk_prepare_enable(i2s->mclk);
  72         if (ret) {
  73                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  74                 return ret;
  75         }
  76
  77         regcache_cache_only(i2s->regmap, false);
  78         regcache_mark_dirty(i2s->regmap);
  79
  80         ret = regcache_sync(i2s->regmap);
  81         if (ret)
  82                 clk_disable_unprepare(i2s->mclk);
  83
  84         return ret;
  85 }
  86
  87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  88 {
  89         return snd_soc_dai_get_drvdata(dai);
  90 }
  91
  92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  93 {
  94         unsigned int val = 0;
  95         int retry = 10;
  96
  97         if (on) {
  98                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  99                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 100
 101                 regmap_update_bits(i2s->regmap, I2S_XFER,
 102                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 104
 105                 i2s->tx_start = true;
 106         } else {
 107                 i2s->tx_start = false;
 108
 109                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 110                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 111
 112                 if (!i2s->rx_start) {
 113                         regmap_update_bits(i2s->regmap, I2S_XFER,
 114                                            I2S_XFER_TXS_START |
 115                                            I2S_XFER_RXS_START,
 116                                            I2S_XFER_TXS_STOP |
 117                                            I2S_XFER_RXS_STOP);
 118
 119                         udelay(150);
 120                         regmap_update_bits(i2s->regmap, I2S_CLR,
 121                                            I2S_CLR_TXC | I2S_CLR_RXC,
 122                                            I2S_CLR_TXC | I2S_CLR_RXC);
 123
 124                         regmap_read(i2s->regmap, I2S_CLR, &val);
 125
 126                         /* Should wait for clear operation to finish */
 127                         while (val) {
 128                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 129                                 retry--;
 130                                 if (!retry) {
 131                                         dev_warn(i2s->dev, "fail to clear\n");
 132                                         break;
 133                                 }
 134                         }
 135                 }
 136         }
 137 }
 138
 139 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 140 {
 141         unsigned int val = 0;
 142         int retry = 10;
 143
 144         if (on) {
 145                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 146                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 147
 148                 regmap_update_bits(i2s->regmap, I2S_XFER,
 149                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 150                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 151
 152                 i2s->rx_start = true;
 153         } else {
 154                 i2s->rx_start = false;
 155
 156                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 157                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 158
 159                 if (!i2s->tx_start) {
 160                         regmap_update_bits(i2s->regmap, I2S_XFER,
 161                                            I2S_XFER_TXS_START |
 162                                            I2S_XFER_RXS_START,
 163                                            I2S_XFER_TXS_STOP |
 164                                            I2S_XFER_RXS_STOP);
 165
 166                         udelay(150);
 167                         regmap_update_bits(i2s->regmap, I2S_CLR,
 168                                            I2S_CLR_TXC | I2S_CLR_RXC,
 169                                            I2S_CLR_TXC | I2S_CLR_RXC);
 170
 171                         regmap_read(i2s->regmap, I2S_CLR, &val);
 172
 173                         /* Should wait for clear operation to finish */
 174                         while (val) {
 175                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 176                                 retry--;
 177                                 if (!retry) {
 178                                         dev_warn(i2s->dev, "fail to clear\n");
 179                                         break;
 180                                 }
 181                         }
 182                 }
 183         }
 184 }
 185
 186 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 187                                 unsigned int fmt)
 188 {
 189         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 190         unsigned int mask = 0, val = 0;
 191
 192         mask = I2S_CKR_MSS_MASK;
 193         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 194         case SND_SOC_DAIFMT_CBS_CFS:
 195                 /* Set source clock in Master mode */
 196                 val = I2S_CKR_MSS_MASTER;
 197                 i2s->is_master_mode = true;
 198                 break;
 199         case SND_SOC_DAIFMT_CBM_CFM:
 200                 val = I2S_CKR_MSS_SLAVE;
 201                 i2s->is_master_mode = false;
 202                 break;
 203         default:
 204                 return -EINVAL;
 205         }
 206
 207         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 208
 209         mask = I2S_TXCR_IBM_MASK;
 210         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 211         case SND_SOC_DAIFMT_RIGHT_J:
 212                 val = I2S_TXCR_IBM_RSJM;
 213                 break;
 214         case SND_SOC_DAIFMT_LEFT_J:
 215                 val = I2S_TXCR_IBM_LSJM;
 216                 break;
 217         case SND_SOC_DAIFMT_I2S:
 218                 val = I2S_TXCR_IBM_NORMAL;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 225
 226         mask = I2S_RXCR_IBM_MASK;
 227         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 228         case SND_SOC_DAIFMT_RIGHT_J:
 229                 val = I2S_RXCR_IBM_RSJM;
 230                 break;
 231         case SND_SOC_DAIFMT_LEFT_J:
 232                 val = I2S_RXCR_IBM_LSJM;
 233                 break;
 234         case SND_SOC_DAIFMT_I2S:
 235                 val = I2S_RXCR_IBM_NORMAL;
 236                 break;
 237         default:
 238                 return -EINVAL;
 239         }
 240
 241         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 242
 243         return 0;
 244 }
 245
 246 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 247                                   struct snd_pcm_hw_params *params,
 248                                   struct snd_soc_dai *dai)
 249 {
 250         struct rk_i2s_dev *i2s = to_info(dai);
 251         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 252         unsigned int val = 0;
 253         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 254
 255         if (i2s->is_master_mode) {
 256                 mclk_rate = clk_get_rate(i2s->mclk);
 257                 bclk_rate = 2 * 32 * params_rate(params);
 258                 if (bclk_rate && mclk_rate % bclk_rate)
 259                         return -EINVAL;
 260
 261                 div_bclk = mclk_rate / bclk_rate;
 262                 div_lrck = bclk_rate / params_rate(params);
 263                 regmap_update_bits(i2s->regmap, I2S_CKR,
 264                                    I2S_CKR_MDIV_MASK,
 265                                    I2S_CKR_MDIV(div_bclk));
 266
 267                 regmap_update_bits(i2s->regmap, I2S_CKR,
 268                                    I2S_CKR_TSD_MASK |
 269                                    I2S_CKR_RSD_MASK,
 270                                    I2S_CKR_TSD(div_lrck) |
 271                                    I2S_CKR_RSD(div_lrck));
 272         }
 273
 274         switch (params_format(params)) {
 275         case SNDRV_PCM_FORMAT_S8:
 276                 val |= I2S_TXCR_VDW(8);
 277                 break;
 278         case SNDRV_PCM_FORMAT_S16_LE:
 279                 val |= I2S_TXCR_VDW(16);
 280                 break;
 281         case SNDRV_PCM_FORMAT_S20_3LE:
 282                 val |= I2S_TXCR_VDW(20);
 283                 break;
 284         case SNDRV_PCM_FORMAT_S24_LE:
 285                 val |= I2S_TXCR_VDW(24);
 286                 break;
 287         case SNDRV_PCM_FORMAT_S32_LE:
 288                 val |= I2S_TXCR_VDW(32);
 289                 break;
 290         default:
 291                 return -EINVAL;
 292         }
 293
 294         switch (params_channels(params)) {
 295         case 8:
 296                 val |= I2S_CHN_8;
 297                 break;
 298         case 6:
 299                 val |= I2S_CHN_6;
 300                 break;
 301         case 4:
 302                 val |= I2S_CHN_4;
 303                 break;
 304         case 2:
 305                 val |= I2S_CHN_2;
 306                 break;
 307         default:
 308                 dev_err(i2s->dev, "invalid channel: %d\n",
 309                         params_channels(params));
 310                 return -EINVAL;
 311         }
 312
 313         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 314                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 315                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 316                                    val);
 317         else
 318                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 319                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 320                                    val);
 321
 322         if (!IS_ERR(i2s->grf) && i2s->pins) {
 323                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 324                 val &= I2S_TXCR_CSR_MASK;
 325
 326                 switch (val) {
 327                 case I2S_CHN_4:
 328                         val = I2S_IO_4CH_OUT_6CH_IN;
 329                         break;
 330                 case I2S_CHN_6:
 331                         val = I2S_IO_6CH_OUT_4CH_IN;
 332                         break;
 333                 case I2S_CHN_8:
 334                         val = I2S_IO_8CH_OUT_2CH_IN;
 335                         break;
 336                 default:
 337                         val = I2S_IO_2CH_OUT_8CH_IN;
 338                         break;
 339                 }
 340
 341                 val <<= i2s->pins->shift;
 342                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 343                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 344         }
 345
 346         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 347                            I2S_DMACR_TDL(16));
 348         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 349                            I2S_DMACR_RDL(16));
 350
 351         val = I2S_CKR_TRCM_TXRX;
 352         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 353                 val = I2S_CKR_TRCM_TXONLY;
 354
 355         regmap_update_bits(i2s->regmap, I2S_CKR,
 356                            I2S_CKR_TRCM_MASK,
 357                            val);
 358         return 0;
 359 }
 360
 361 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 362                                 int cmd, struct snd_soc_dai *dai)
 363 {
 364         struct rk_i2s_dev *i2s = to_info(dai);
 365         int ret = 0;
 366
 367         switch (cmd) {
 368         case SNDRV_PCM_TRIGGER_START:
 369         case SNDRV_PCM_TRIGGER_RESUME:
 370         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 371                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 372                         rockchip_snd_rxctrl(i2s, 1);
 373                 else
 374                         rockchip_snd_txctrl(i2s, 1);
 375                 break;
 376         case SNDRV_PCM_TRIGGER_SUSPEND:
 377         case SNDRV_PCM_TRIGGER_STOP:
 378         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 379                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 380                         rockchip_snd_rxctrl(i2s, 0);
 381                 else
 382                         rockchip_snd_txctrl(i2s, 0);
 383                 break;
 384         default:
 385                 ret = -EINVAL;
 386                 break;
 387         }
 388
 389         return ret;
 390 }
 391
 392 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 393                                    unsigned int freq, int dir)
 394 {
 395         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 396         int ret;
 397
 398         ret = clk_set_rate(i2s->mclk, freq);
 399         if (ret)
 400                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 401
 402         return ret;
 403 }
 404
 405 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 406 {
 407         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 408
 409         dai->capture_dma_data = &i2s->capture_dma_data;
 410         dai->playback_dma_data = &i2s->playback_dma_data;
 411
 412         return 0;
 413 }
 414
 415 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 416         .hw_params = rockchip_i2s_hw_params,
 417         .set_sysclk = rockchip_i2s_set_sysclk,
 418         .set_fmt = rockchip_i2s_set_fmt,
 419         .trigger = rockchip_i2s_trigger,
 420 };
 421
 422 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 423         .probe = rockchip_i2s_dai_probe,
 424         .playback = {
 425                 .stream_name = "Playback",
 426                 .channels_min = 2,
 427                 .channels_max = 8,
 428                 .rates = SNDRV_PCM_RATE_8000_192000,
 429                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 430                             SNDRV_PCM_FMTBIT_S16_LE |
 431                             SNDRV_PCM_FMTBIT_S20_3LE |
 432                             SNDRV_PCM_FMTBIT_S24_LE |
 433                             SNDRV_PCM_FMTBIT_S32_LE),
 434         },
 435         .capture = {
 436                 .stream_name = "Capture",
 437                 .channels_min = 2,
 438                 .channels_max = 2,
 439                 .rates = SNDRV_PCM_RATE_8000_192000,
 440                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 441                             SNDRV_PCM_FMTBIT_S16_LE |
 442                             SNDRV_PCM_FMTBIT_S20_3LE |
 443                             SNDRV_PCM_FMTBIT_S24_LE |
 444                             SNDRV_PCM_FMTBIT_S32_LE),
 445         },
 446         .ops = &rockchip_i2s_dai_ops,
 447         .symmetric_rates = 1,
 448 };
 449
 450 static const struct snd_soc_component_driver rockchip_i2s_component = {
 451         .name = DRV_NAME,
 452 };
 453
 454 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 455 {
 456         switch (reg) {
 457         case I2S_TXCR:
 458         case I2S_RXCR:
 459         case I2S_CKR:
 460         case I2S_DMACR:
 461         case I2S_INTCR:
 462         case I2S_XFER:
 463         case I2S_CLR:
 464         case I2S_TXDR:
 465                 return true;
 466         default:
 467                 return false;
 468         }
 469 }
 470
 471 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 472 {
 473         switch (reg) {
 474         case I2S_TXCR:
 475         case I2S_RXCR:
 476         case I2S_CKR:
 477         case I2S_DMACR:
 478         case I2S_INTCR:
 479         case I2S_XFER:
 480         case I2S_CLR:
 481         case I2S_RXDR:
 482         case I2S_FIFOLR:
 483         case I2S_INTSR:
 484                 return true;
 485         default:
 486                 return false;
 487         }
 488 }
 489
 490 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 491 {
 492         switch (reg) {
 493         case I2S_INTSR:
 494         case I2S_CLR:
 495                 return true;
 496         default:
 497                 return false;
 498         }
 499 }
 500
 501 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 502 {
 503         switch (reg) {
 504         default:
 505                 return false;
 506         }
 507 }
 508
 509 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 510         {0x00, 0x0000000f},
 511         {0x04, 0x0000000f},
 512         {0x08, 0x00071f1f},
 513         {0x10, 0x001f0000},
 514         {0x14, 0x01f00000},
 515 };
 516
 517 static const struct regmap_config rockchip_i2s_regmap_config = {
 518         .reg_bits = 32,
 519         .reg_stride = 4,
 520         .val_bits = 32,
 521         .max_register = I2S_RXDR,
 522         .reg_defaults = rockchip_i2s_reg_defaults,
 523         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 524         .writeable_reg = rockchip_i2s_wr_reg,
 525         .readable_reg = rockchip_i2s_rd_reg,
 526         .volatile_reg = rockchip_i2s_volatile_reg,
 527         .precious_reg = rockchip_i2s_precious_reg,
 528         .cache_type = REGCACHE_FLAT,
 529 };
 530
 531 static const struct rk_i2s_pins rk3399_i2s_pins = {
 532         .reg_offset = 0xe220,
 533         .shift = 11,
 534 };
 535
 536 static const struct of_device_id rockchip_i2s_match[] = {
 537         { .compatible = "rockchip,rk3066-i2s", },
 538         { .compatible = "rockchip,rk3188-i2s", },
 539         { .compatible = "rockchip,rk3288-i2s", },
 540         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 541         {},
 542 };
 543
 544 static int rockchip_i2s_probe(struct platform_device *pdev)
 545 {
 546         struct device_node *node = pdev->dev.of_node;
 547         const struct of_device_id *of_id;
 548         struct rk_i2s_dev *i2s;
 549         struct snd_soc_dai_driver *soc_dai;
 550         struct resource *res;
 551         void __iomem *regs;
 552         int ret;
 553         int val;
 554
 555         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 556         if (!i2s) {
 557                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 558                 return -ENOMEM;
 559         }
 560
 561         i2s->dev = &pdev->dev;
 562
 563         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 564         if (!IS_ERR(i2s->grf)) {
 565                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 566                 if (!of_id || !of_id->data)
 567                         return -EINVAL;
 568
 569                 i2s->pins = of_id->data;
 570         }
 571
 572         /* try to prepare related clocks */
 573         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 574         if (IS_ERR(i2s->hclk)) {
 575                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 576                 return PTR_ERR(i2s->hclk);
 577         }
 578         ret = clk_prepare_enable(i2s->hclk);
 579         if (ret) {
 580                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 581                 return ret;
 582         }
 583
 584         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 585         if (IS_ERR(i2s->mclk)) {
 586                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 587                 return PTR_ERR(i2s->mclk);
 588         }
 589
 590         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 591         regs = devm_ioremap_resource(&pdev->dev, res);
 592         if (IS_ERR(regs))
 593                 return PTR_ERR(regs);
 594
 595         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 596                                             &rockchip_i2s_regmap_config);
 597         if (IS_ERR(i2s->regmap)) {
 598                 dev_err(&pdev->dev,
 599                         "Failed to initialise managed register map\n");
 600                 return PTR_ERR(i2s->regmap);
 601         }
 602
 603         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 604         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 605         i2s->playback_dma_data.maxburst = 4;
 606
 607         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 608         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 609         i2s->capture_dma_data.maxburst = 4;
 610
 611         dev_set_drvdata(&pdev->dev, i2s);
 612
 613         pm_runtime_enable(&pdev->dev);
 614         if (!pm_runtime_enabled(&pdev->dev)) {
 615                 ret = i2s_runtime_resume(&pdev->dev);
 616                 if (ret)
 617                         goto err_pm_disable;
 618         }
 619
 620         soc_dai = devm_kzalloc(&pdev->dev,
 621                                sizeof(*soc_dai), GFP_KERNEL);
 622         if (!soc_dai)
 623                 return -ENOMEM;
 624
 625         memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
 626         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 627                 if (val >= 2 && val <= 8)
 628                         soc_dai->playback.channels_max = val;
 629         }
 630
 631         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 632                 if (val >= 2 && val <= 8)
 633                         soc_dai->capture.channels_max = val;
 634         }
 635
 636         ret = devm_snd_soc_register_component(&pdev->dev,
 637                                               &rockchip_i2s_component,
 638                                               soc_dai, 1);
 639
 640         if (ret) {
 641                 dev_err(&pdev->dev, "Could not register DAI\n");
 642                 goto err_suspend;
 643         }
 644
 645         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 646         if (ret) {
 647                 dev_err(&pdev->dev, "Could not register PCM\n");
 648                 return ret;
 649         }
 650
 651         return 0;
 652
 653 err_suspend:
 654         if (!pm_runtime_status_suspended(&pdev->dev))
 655                 i2s_runtime_suspend(&pdev->dev);
 656 err_pm_disable:
 657         pm_runtime_disable(&pdev->dev);
 658
 659         return ret;
 660 }
 661
 662 static int rockchip_i2s_remove(struct platform_device *pdev)
 663 {
 664         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 665
 666         pm_runtime_disable(&pdev->dev);
 667         if (!pm_runtime_status_suspended(&pdev->dev))
 668                 i2s_runtime_suspend(&pdev->dev);
 669
 670         clk_disable_unprepare(i2s->mclk);
 671         clk_disable_unprepare(i2s->hclk);
 672
 673         return 0;
 674 }
 675
 676 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 677         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 678                            NULL)
 679 };
 680
 681 static struct platform_driver rockchip_i2s_driver = {
 682         .probe = rockchip_i2s_probe,
 683         .remove = rockchip_i2s_remove,
 684         .driver = {
 685                 .name = DRV_NAME,
 686                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 687                 .pm = &rockchip_i2s_pm_ops,
 688         },
 689 };
 690 module_platform_driver(rockchip_i2s_driver);
 691
 692 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 693 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 694 MODULE_LICENSE("GPL v2");
 695 MODULE_ALIAS("platform:" DRV_NAME);
 696 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);