sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25
  26 #define DRV_NAME "rockchip-i2s"
  27
  28 struct rk_i2s_pins {
  29         u32 reg_offset;
  30         u32 shift;
  31 };
  32
  33 struct rk_i2s_dev {
  34         struct device *dev;
  35
  36         struct clk *hclk;
  37         struct clk *mclk;
  38
  39         struct snd_dmaengine_dai_dma_data capture_dma_data;
  40         struct snd_dmaengine_dai_dma_data playback_dma_data;
  41
  42         struct regmap *regmap;
  43         struct regmap *grf;
  44
  45 /*
  46  * Used to indicate the tx/rx status.
  47  * I2S controller hopes to start the tx and rx together,
  48  * also to stop them when they are both try to stop.
  49 */
  50         bool tx_start;
  51         bool rx_start;
  52         bool is_master_mode;
  53         const struct rk_i2s_pins *pins;
  54 };
  55
  56 static int i2s_runtime_suspend(struct device *dev)
  57 {
  58         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  59
  60         regcache_cache_only(i2s->regmap, true);
  61         clk_disable_unprepare(i2s->mclk);
  62
  63         return 0;
  64 }
  65
  66 static int i2s_runtime_resume(struct device *dev)
  67 {
  68         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  69         int ret;
  70
  71         ret = clk_prepare_enable(i2s->mclk);
  72         if (ret) {
  73                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  74                 return ret;
  75         }
  76
  77         regcache_cache_only(i2s->regmap, false);
  78         regcache_mark_dirty(i2s->regmap);
  79
  80         ret = regcache_sync(i2s->regmap);
  81         if (ret)
  82                 clk_disable_unprepare(i2s->mclk);
  83
  84         return ret;
  85 }
  86
  87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  88 {
  89         return snd_soc_dai_get_drvdata(dai);
  90 }
  91
  92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  93 {
  94         unsigned int val = 0;
  95         int retry = 10;
  96
  97         if (on) {
  98                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  99                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 100
 101                 regmap_update_bits(i2s->regmap, I2S_XFER,
 102                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 104
 105                 i2s->tx_start = true;
 106         } else {
 107                 i2s->tx_start = false;
 108
 109                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 110                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 111
 112                 if (!i2s->rx_start) {
 113                         regmap_update_bits(i2s->regmap, I2S_XFER,
 114                                            I2S_XFER_TXS_START |
 115                                            I2S_XFER_RXS_START,
 116                                            I2S_XFER_TXS_STOP |
 117                                            I2S_XFER_RXS_STOP);
 118
 119                         regmap_update_bits(i2s->regmap, I2S_CLR,
 120                                            I2S_CLR_TXC | I2S_CLR_RXC,
 121                                            I2S_CLR_TXC | I2S_CLR_RXC);
 122
 123                         regmap_read(i2s->regmap, I2S_CLR, &val);
 124
 125                         /* Should wait for clear operation to finish */
 126                         while (val) {
 127                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 128                                 retry--;
 129                                 if (!retry) {
 130                                         dev_warn(i2s->dev, "fail to clear\n");
 131                                         break;
 132                                 }
 133                         }
 134                 }
 135         }
 136 }
 137
 138 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 139 {
 140         unsigned int val = 0;
 141         int retry = 10;
 142
 143         if (on) {
 144                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 145                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 146
 147                 regmap_update_bits(i2s->regmap, I2S_XFER,
 148                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 149                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 150
 151                 i2s->rx_start = true;
 152         } else {
 153                 i2s->rx_start = false;
 154
 155                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 156                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 157
 158                 if (!i2s->tx_start) {
 159                         regmap_update_bits(i2s->regmap, I2S_XFER,
 160                                            I2S_XFER_TXS_START |
 161                                            I2S_XFER_RXS_START,
 162                                            I2S_XFER_TXS_STOP |
 163                                            I2S_XFER_RXS_STOP);
 164
 165                         regmap_update_bits(i2s->regmap, I2S_CLR,
 166                                            I2S_CLR_TXC | I2S_CLR_RXC,
 167                                            I2S_CLR_TXC | I2S_CLR_RXC);
 168
 169                         regmap_read(i2s->regmap, I2S_CLR, &val);
 170
 171                         /* Should wait for clear operation to finish */
 172                         while (val) {
 173                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 174                                 retry--;
 175                                 if (!retry) {
 176                                         dev_warn(i2s->dev, "fail to clear\n");
 177                                         break;
 178                                 }
 179                         }
 180                 }
 181         }
 182 }
 183
 184 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 185                                 unsigned int fmt)
 186 {
 187         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 188         unsigned int mask = 0, val = 0;
 189
 190         mask = I2S_CKR_MSS_MASK;
 191         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 192         case SND_SOC_DAIFMT_CBS_CFS:
 193                 /* Set source clock in Master mode */
 194                 val = I2S_CKR_MSS_MASTER;
 195                 i2s->is_master_mode = true;
 196                 break;
 197         case SND_SOC_DAIFMT_CBM_CFM:
 198                 val = I2S_CKR_MSS_SLAVE;
 199                 i2s->is_master_mode = false;
 200                 break;
 201         default:
 202                 return -EINVAL;
 203         }
 204
 205         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 206
 207         mask = I2S_CKR_CKP_MASK;
 208         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 209         case SND_SOC_DAIFMT_NB_NF:
 210                 val = I2S_CKR_CKP_NEG;
 211                 break;
 212         case SND_SOC_DAIFMT_IB_NF:
 213                 val = I2S_CKR_CKP_POS;
 214                 break;
 215         default:
 216                 return -EINVAL;
 217         }
 218
 219         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 220
 221         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 222         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 223         case SND_SOC_DAIFMT_RIGHT_J:
 224                 val = I2S_TXCR_IBM_RSJM;
 225                 break;
 226         case SND_SOC_DAIFMT_LEFT_J:
 227                 val = I2S_TXCR_IBM_LSJM;
 228                 break;
 229         case SND_SOC_DAIFMT_I2S:
 230                 val = I2S_TXCR_IBM_NORMAL;
 231                 break;
 232         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 233                 val = I2S_TXCR_TFS_PCM;
 234                 break;
 235         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 236                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 237                 break;
 238         default:
 239                 return -EINVAL;
 240         }
 241
 242         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 243
 244         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 245         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 246         case SND_SOC_DAIFMT_RIGHT_J:
 247                 val = I2S_RXCR_IBM_RSJM;
 248                 break;
 249         case SND_SOC_DAIFMT_LEFT_J:
 250                 val = I2S_RXCR_IBM_LSJM;
 251                 break;
 252         case SND_SOC_DAIFMT_I2S:
 253                 val = I2S_RXCR_IBM_NORMAL;
 254                 break;
 255         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 256                 val = I2S_RXCR_TFS_PCM;
 257                 break;
 258         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 259                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 260                 break;
 261         default:
 262                 return -EINVAL;
 263         }
 264
 265         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 266
 267         return 0;
 268 }
 269
 270 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 271                                   struct snd_pcm_hw_params *params,
 272                                   struct snd_soc_dai *dai)
 273 {
 274         struct rk_i2s_dev *i2s = to_info(dai);
 275         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 276         unsigned int val = 0;
 277         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 278
 279         if (i2s->is_master_mode) {
 280                 mclk_rate = clk_get_rate(i2s->mclk);
 281                 bclk_rate = 2 * 32 * params_rate(params);
 282                 if (bclk_rate && mclk_rate % bclk_rate)
 283                         return -EINVAL;
 284
 285                 div_bclk = mclk_rate / bclk_rate;
 286                 div_lrck = bclk_rate / params_rate(params);
 287                 regmap_update_bits(i2s->regmap, I2S_CKR,
 288                                    I2S_CKR_MDIV_MASK,
 289                                    I2S_CKR_MDIV(div_bclk));
 290
 291                 regmap_update_bits(i2s->regmap, I2S_CKR,
 292                                    I2S_CKR_TSD_MASK |
 293                                    I2S_CKR_RSD_MASK,
 294                                    I2S_CKR_TSD(div_lrck) |
 295                                    I2S_CKR_RSD(div_lrck));
 296         }
 297
 298         switch (params_format(params)) {
 299         case SNDRV_PCM_FORMAT_S8:
 300                 val |= I2S_TXCR_VDW(8);
 301                 break;
 302         case SNDRV_PCM_FORMAT_S16_LE:
 303                 val |= I2S_TXCR_VDW(16);
 304                 break;
 305         case SNDRV_PCM_FORMAT_S20_3LE:
 306                 val |= I2S_TXCR_VDW(20);
 307                 break;
 308         case SNDRV_PCM_FORMAT_S24_LE:
 309                 val |= I2S_TXCR_VDW(24);
 310                 break;
 311         case SNDRV_PCM_FORMAT_S32_LE:
 312                 val |= I2S_TXCR_VDW(32);
 313                 break;
 314         default:
 315                 return -EINVAL;
 316         }
 317
 318         switch (params_channels(params)) {
 319         case 8:
 320                 val |= I2S_CHN_8;
 321                 break;
 322         case 6:
 323                 val |= I2S_CHN_6;
 324                 break;
 325         case 4:
 326                 val |= I2S_CHN_4;
 327                 break;
 328         case 2:
 329                 val |= I2S_CHN_2;
 330                 break;
 331         default:
 332                 dev_err(i2s->dev, "invalid channel: %d\n",
 333                         params_channels(params));
 334                 return -EINVAL;
 335         }
 336
 337         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 338                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 339                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 340                                    val);
 341         else
 342                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 343                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 344                                    val);
 345
 346         if (!IS_ERR(i2s->grf) && i2s->pins) {
 347                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 348                 val &= I2S_TXCR_CSR_MASK;
 349
 350                 switch (val) {
 351                 case I2S_CHN_4:
 352                         val = I2S_IO_4CH_OUT_6CH_IN;
 353                         break;
 354                 case I2S_CHN_6:
 355                         val = I2S_IO_6CH_OUT_4CH_IN;
 356                         break;
 357                 case I2S_CHN_8:
 358                         val = I2S_IO_8CH_OUT_2CH_IN;
 359                         break;
 360                 default:
 361                         val = I2S_IO_2CH_OUT_8CH_IN;
 362                         break;
 363                 }
 364
 365                 val <<= i2s->pins->shift;
 366                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 367                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 368         }
 369
 370         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 371                            I2S_DMACR_TDL(16));
 372         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 373                            I2S_DMACR_RDL(16));
 374
 375         val = I2S_CKR_TRCM_TXRX;
 376         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 377                 val = I2S_CKR_TRCM_TXONLY;
 378
 379         regmap_update_bits(i2s->regmap, I2S_CKR,
 380                            I2S_CKR_TRCM_MASK,
 381                            val);
 382         return 0;
 383 }
 384
 385 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 386                                 int cmd, struct snd_soc_dai *dai)
 387 {
 388         struct rk_i2s_dev *i2s = to_info(dai);
 389         int ret = 0;
 390
 391         switch (cmd) {
 392         case SNDRV_PCM_TRIGGER_START:
 393         case SNDRV_PCM_TRIGGER_RESUME:
 394         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 395                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 396                         rockchip_snd_rxctrl(i2s, 1);
 397                 else
 398                         rockchip_snd_txctrl(i2s, 1);
 399                 break;
 400         case SNDRV_PCM_TRIGGER_SUSPEND:
 401         case SNDRV_PCM_TRIGGER_STOP:
 402         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 403                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 404                         rockchip_snd_rxctrl(i2s, 0);
 405                 else
 406                         rockchip_snd_txctrl(i2s, 0);
 407                 break;
 408         default:
 409                 ret = -EINVAL;
 410                 break;
 411         }
 412
 413         return ret;
 414 }
 415
 416 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 417                                    unsigned int freq, int dir)
 418 {
 419         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 420         int ret;
 421
 422         ret = clk_set_rate(i2s->mclk, freq);
 423         if (ret)
 424                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 425
 426         return ret;
 427 }
 428
 429 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 430 {
 431         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 432
 433         dai->capture_dma_data = &i2s->capture_dma_data;
 434         dai->playback_dma_data = &i2s->playback_dma_data;
 435
 436         return 0;
 437 }
 438
 439 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 440         .hw_params = rockchip_i2s_hw_params,
 441         .set_sysclk = rockchip_i2s_set_sysclk,
 442         .set_fmt = rockchip_i2s_set_fmt,
 443         .trigger = rockchip_i2s_trigger,
 444 };
 445
 446 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 447         .probe = rockchip_i2s_dai_probe,
 448         .playback = {
 449                 .stream_name = "Playback",
 450                 .channels_min = 2,
 451                 .channels_max = 8,
 452                 .rates = SNDRV_PCM_RATE_8000_192000,
 453                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 454                             SNDRV_PCM_FMTBIT_S16_LE |
 455                             SNDRV_PCM_FMTBIT_S20_3LE |
 456                             SNDRV_PCM_FMTBIT_S24_LE |
 457                             SNDRV_PCM_FMTBIT_S32_LE),
 458         },
 459         .capture = {
 460                 .stream_name = "Capture",
 461                 .channels_min = 2,
 462                 .channels_max = 2,
 463                 .rates = SNDRV_PCM_RATE_8000_192000,
 464                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 465                             SNDRV_PCM_FMTBIT_S16_LE |
 466                             SNDRV_PCM_FMTBIT_S20_3LE |
 467                             SNDRV_PCM_FMTBIT_S24_LE |
 468                             SNDRV_PCM_FMTBIT_S32_LE),
 469         },
 470         .ops = &rockchip_i2s_dai_ops,
 471         .symmetric_rates = 1,
 472 };
 473
 474 static const struct snd_soc_component_driver rockchip_i2s_component = {
 475         .name = DRV_NAME,
 476 };
 477
 478 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 479 {
 480         switch (reg) {
 481         case I2S_TXCR:
 482         case I2S_RXCR:
 483         case I2S_CKR:
 484         case I2S_DMACR:
 485         case I2S_INTCR:
 486         case I2S_XFER:
 487         case I2S_CLR:
 488         case I2S_TXDR:
 489                 return true;
 490         default:
 491                 return false;
 492         }
 493 }
 494
 495 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 496 {
 497         switch (reg) {
 498         case I2S_TXCR:
 499         case I2S_RXCR:
 500         case I2S_CKR:
 501         case I2S_DMACR:
 502         case I2S_INTCR:
 503         case I2S_XFER:
 504         case I2S_CLR:
 505         case I2S_RXDR:
 506         case I2S_FIFOLR:
 507         case I2S_INTSR:
 508                 return true;
 509         default:
 510                 return false;
 511         }
 512 }
 513
 514 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 515 {
 516         switch (reg) {
 517         case I2S_INTSR:
 518         case I2S_CLR:
 519                 return true;
 520         default:
 521                 return false;
 522         }
 523 }
 524
 525 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 526 {
 527         switch (reg) {
 528         default:
 529                 return false;
 530         }
 531 }
 532
 533 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 534         {0x00, 0x0000000f},
 535         {0x04, 0x0000000f},
 536         {0x08, 0x00071f1f},
 537         {0x10, 0x001f0000},
 538         {0x14, 0x01f00000},
 539 };
 540
 541 static const struct regmap_config rockchip_i2s_regmap_config = {
 542         .reg_bits = 32,
 543         .reg_stride = 4,
 544         .val_bits = 32,
 545         .max_register = I2S_RXDR,
 546         .reg_defaults = rockchip_i2s_reg_defaults,
 547         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 548         .writeable_reg = rockchip_i2s_wr_reg,
 549         .readable_reg = rockchip_i2s_rd_reg,
 550         .volatile_reg = rockchip_i2s_volatile_reg,
 551         .precious_reg = rockchip_i2s_precious_reg,
 552         .cache_type = REGCACHE_FLAT,
 553 };
 554
 555 static const struct rk_i2s_pins rk3399_i2s_pins = {
 556         .reg_offset = 0xe220,
 557         .shift = 11,
 558 };
 559
 560 static const struct of_device_id rockchip_i2s_match[] = {
 561         { .compatible = "rockchip,rk3066-i2s", },
 562         { .compatible = "rockchip,rk3188-i2s", },
 563         { .compatible = "rockchip,rk3288-i2s", },
 564         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 565         {},
 566 };
 567
 568 static int rockchip_i2s_probe(struct platform_device *pdev)
 569 {
 570         struct device_node *node = pdev->dev.of_node;
 571         const struct of_device_id *of_id;
 572         struct rk_i2s_dev *i2s;
 573         struct snd_soc_dai_driver *soc_dai;
 574         struct resource *res;
 575         void __iomem *regs;
 576         int ret;
 577         int val;
 578
 579         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 580         if (!i2s) {
 581                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 582                 return -ENOMEM;
 583         }
 584
 585         i2s->dev = &pdev->dev;
 586
 587         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 588         if (!IS_ERR(i2s->grf)) {
 589                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 590                 if (!of_id || !of_id->data)
 591                         return -EINVAL;
 592
 593                 i2s->pins = of_id->data;
 594         }
 595
 596         /* try to prepare related clocks */
 597         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 598         if (IS_ERR(i2s->hclk)) {
 599                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 600                 return PTR_ERR(i2s->hclk);
 601         }
 602         ret = clk_prepare_enable(i2s->hclk);
 603         if (ret) {
 604                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 605                 return ret;
 606         }
 607
 608         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 609         if (IS_ERR(i2s->mclk)) {
 610                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 611                 return PTR_ERR(i2s->mclk);
 612         }
 613
 614         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 615         regs = devm_ioremap_resource(&pdev->dev, res);
 616         if (IS_ERR(regs))
 617                 return PTR_ERR(regs);
 618
 619         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 620                                             &rockchip_i2s_regmap_config);
 621         if (IS_ERR(i2s->regmap)) {
 622                 dev_err(&pdev->dev,
 623                         "Failed to initialise managed register map\n");
 624                 return PTR_ERR(i2s->regmap);
 625         }
 626
 627         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 628         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 629         i2s->playback_dma_data.maxburst = 4;
 630
 631         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 632         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 633         i2s->capture_dma_data.maxburst = 4;
 634
 635         dev_set_drvdata(&pdev->dev, i2s);
 636
 637         pm_runtime_enable(&pdev->dev);
 638         if (!pm_runtime_enabled(&pdev->dev)) {
 639                 ret = i2s_runtime_resume(&pdev->dev);
 640                 if (ret)
 641                         goto err_pm_disable;
 642         }
 643
 644         soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai
 645                                sizeof(*soc_dai), GFP_KERNEL);
 646         if (!soc_dai) {
 647                 err = -ENOMEM;
 648                 goto err_pm_disable;
 649         }
 650
 651         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 652                 if (val >= 2 && val <= 8)
 653                         soc_dai->playback.channels_max = val;
 654         }
 655
 656         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 657                 if (val >= 2 && val <= 8)
 658                         soc_dai->capture.channels_max = val;
 659         }
 660
 661         ret = devm_snd_soc_register_component(&pdev->dev,
 662                                               &rockchip_i2s_component,
 663                                               soc_dai, 1);
 664
 665         if (ret) {
 666                 dev_err(&pdev->dev, "Could not register DAI\n");
 667                 goto err_suspend;
 668         }
 669
 670         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 671         if (ret) {
 672                 dev_err(&pdev->dev, "Could not register PCM\n");
 673                 return ret;
 674         }
 675
 676         return 0;
 677
 678 err_suspend:
 679         if (!pm_runtime_status_suspended(&pdev->dev))
 680                 i2s_runtime_suspend(&pdev->dev);
 681 err_pm_disable:
 682         pm_runtime_disable(&pdev->dev);
 683
 684         return ret;
 685 }
 686
 687 static int rockchip_i2s_remove(struct platform_device *pdev)
 688 {
 689         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 690
 691         pm_runtime_disable(&pdev->dev);
 692         if (!pm_runtime_status_suspended(&pdev->dev))
 693                 i2s_runtime_suspend(&pdev->dev);
 694
 695         clk_disable_unprepare(i2s->mclk);
 696         clk_disable_unprepare(i2s->hclk);
 697
 698         return 0;
 699 }
 700
 701 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 702         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 703                            NULL)
 704 };
 705
 706 static struct platform_driver rockchip_i2s_driver = {
 707         .probe = rockchip_i2s_probe,
 708         .remove = rockchip_i2s_remove,
 709         .driver = {
 710                 .name = DRV_NAME,
 711                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 712                 .pm = &rockchip_i2s_pm_ops,
 713         },
 714 };
 715 module_platform_driver(rockchip_i2s_driver);
 716
 717 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 718 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 719 MODULE_LICENSE("GPL v2");
 720 MODULE_ALIAS("platform:" DRV_NAME);
 721 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);