sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25
  26 #define DRV_NAME "rockchip-i2s"
  27
  28 struct rk_i2s_pins {
  29         u32 reg_offset;
  30         u32 shift;
  31 };
  32
  33 struct rk_i2s_dev {
  34         struct device *dev;
  35
  36         struct clk *hclk;
  37         struct clk *mclk;
  38
  39         struct snd_dmaengine_dai_dma_data capture_dma_data;
  40         struct snd_dmaengine_dai_dma_data playback_dma_data;
  41
  42         struct regmap *regmap;
  43         struct regmap *grf;
  44
  45 /*
  46  * Used to indicate the tx/rx status.
  47  * I2S controller hopes to start the tx and rx together,
  48  * also to stop them when they are both try to stop.
  49 */
  50         bool tx_start;
  51         bool rx_start;
  52         bool is_master_mode;
  53         const struct rk_i2s_pins *pins;
  54 };
  55
  56 static int i2s_runtime_suspend(struct device *dev)
  57 {
  58         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  59
  60         regcache_cache_only(i2s->regmap, true);
  61         clk_disable_unprepare(i2s->mclk);
  62
  63         return 0;
  64 }
  65
  66 static int i2s_runtime_resume(struct device *dev)
  67 {
  68         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  69         int ret;
  70
  71         ret = clk_prepare_enable(i2s->mclk);
  72         if (ret) {
  73                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  74                 return ret;
  75         }
  76
  77         regcache_cache_only(i2s->regmap, false);
  78         regcache_mark_dirty(i2s->regmap);
  79
  80         ret = regcache_sync(i2s->regmap);
  81         if (ret)
  82                 clk_disable_unprepare(i2s->mclk);
  83
  84         return ret;
  85 }
  86
  87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  88 {
  89         return snd_soc_dai_get_drvdata(dai);
  90 }
  91
  92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  93 {
  94         unsigned int val = 0;
  95         int retry = 10;
  96
  97         if (on) {
  98                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  99                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 100
 101                 regmap_update_bits(i2s->regmap, I2S_XFER,
 102                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 104
 105                 i2s->tx_start = true;
 106         } else {
 107                 i2s->tx_start = false;
 108
 109                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 110                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 111
 112                 if (!i2s->rx_start) {
 113                         regmap_update_bits(i2s->regmap, I2S_XFER,
 114                                            I2S_XFER_TXS_START |
 115                                            I2S_XFER_RXS_START,
 116                                            I2S_XFER_TXS_STOP |
 117                                            I2S_XFER_RXS_STOP);
 118
 119                         udelay(150);
 120                         regmap_update_bits(i2s->regmap, I2S_CLR,
 121                                            I2S_CLR_TXC | I2S_CLR_RXC,
 122                                            I2S_CLR_TXC | I2S_CLR_RXC);
 123
 124                         regmap_read(i2s->regmap, I2S_CLR, &val);
 125
 126                         /* Should wait for clear operation to finish */
 127                         while (val) {
 128                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 129                                 retry--;
 130                                 if (!retry) {
 131                                         dev_warn(i2s->dev, "fail to clear\n");
 132                                         break;
 133                                 }
 134                         }
 135                 }
 136         }
 137 }
 138
 139 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 140 {
 141         unsigned int val = 0;
 142         int retry = 10;
 143
 144         if (on) {
 145                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 146                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 147
 148                 regmap_update_bits(i2s->regmap, I2S_XFER,
 149                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 150                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 151
 152                 i2s->rx_start = true;
 153         } else {
 154                 i2s->rx_start = false;
 155
 156                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 157                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 158
 159                 if (!i2s->tx_start) {
 160                         regmap_update_bits(i2s->regmap, I2S_XFER,
 161                                            I2S_XFER_TXS_START |
 162                                            I2S_XFER_RXS_START,
 163                                            I2S_XFER_TXS_STOP |
 164                                            I2S_XFER_RXS_STOP);
 165
 166                         udelay(150);
 167                         regmap_update_bits(i2s->regmap, I2S_CLR,
 168                                            I2S_CLR_TXC | I2S_CLR_RXC,
 169                                            I2S_CLR_TXC | I2S_CLR_RXC);
 170
 171                         regmap_read(i2s->regmap, I2S_CLR, &val);
 172
 173                         /* Should wait for clear operation to finish */
 174                         while (val) {
 175                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 176                                 retry--;
 177                                 if (!retry) {
 178                                         dev_warn(i2s->dev, "fail to clear\n");
 179                                         break;
 180                                 }
 181                         }
 182                 }
 183         }
 184 }
 185
 186 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 187                                 unsigned int fmt)
 188 {
 189         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 190         unsigned int mask = 0, val = 0;
 191
 192         mask = I2S_CKR_MSS_MASK;
 193         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 194         case SND_SOC_DAIFMT_CBS_CFS:
 195                 /* Set source clock in Master mode */
 196                 val = I2S_CKR_MSS_MASTER;
 197                 i2s->is_master_mode = true;
 198                 break;
 199         case SND_SOC_DAIFMT_CBM_CFM:
 200                 val = I2S_CKR_MSS_SLAVE;
 201                 i2s->is_master_mode = false;
 202                 break;
 203         default:
 204                 return -EINVAL;
 205         }
 206
 207         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 208
 209         mask = I2S_CKR_CKP_MASK;
 210         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 211         case SND_SOC_DAIFMT_NB_NF:
 212                 val = I2S_CKR_CKP_NEG;
 213                 break;
 214         case SND_SOC_DAIFMT_IB_NF:
 215                 val = I2S_CKR_CKP_POS;
 216                 break;
 217         default:
 218                 return -EINVAL;
 219         }
 220
 221         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 222
 223         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 224         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 225         case SND_SOC_DAIFMT_RIGHT_J:
 226                 val = I2S_TXCR_IBM_RSJM;
 227                 break;
 228         case SND_SOC_DAIFMT_LEFT_J:
 229                 val = I2S_TXCR_IBM_LSJM;
 230                 break;
 231         case SND_SOC_DAIFMT_I2S:
 232                 val = I2S_TXCR_IBM_NORMAL;
 233                 break;
 234         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 235                 val = I2S_TXCR_TFS_PCM;
 236                 break;
 237         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 238                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 239                 break;
 240         default:
 241                 return -EINVAL;
 242         }
 243
 244         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 245
 246         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 247         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 248         case SND_SOC_DAIFMT_RIGHT_J:
 249                 val = I2S_RXCR_IBM_RSJM;
 250                 break;
 251         case SND_SOC_DAIFMT_LEFT_J:
 252                 val = I2S_RXCR_IBM_LSJM;
 253                 break;
 254         case SND_SOC_DAIFMT_I2S:
 255                 val = I2S_RXCR_IBM_NORMAL;
 256                 break;
 257         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 258                 val = I2S_RXCR_TFS_PCM;
 259                 break;
 260         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 261                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 262                 break;
 263         default:
 264                 return -EINVAL;
 265         }
 266
 267         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 268
 269         return 0;
 270 }
 271
 272 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 273                                   struct snd_pcm_hw_params *params,
 274                                   struct snd_soc_dai *dai)
 275 {
 276         struct rk_i2s_dev *i2s = to_info(dai);
 277         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 278         unsigned int val = 0;
 279         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 280
 281         if (i2s->is_master_mode) {
 282                 mclk_rate = clk_get_rate(i2s->mclk);
 283                 bclk_rate = 2 * 32 * params_rate(params);
 284                 if (bclk_rate && mclk_rate % bclk_rate)
 285                         return -EINVAL;
 286
 287                 div_bclk = mclk_rate / bclk_rate;
 288                 div_lrck = bclk_rate / params_rate(params);
 289                 regmap_update_bits(i2s->regmap, I2S_CKR,
 290                                    I2S_CKR_MDIV_MASK,
 291                                    I2S_CKR_MDIV(div_bclk));
 292
 293                 regmap_update_bits(i2s->regmap, I2S_CKR,
 294                                    I2S_CKR_TSD_MASK |
 295                                    I2S_CKR_RSD_MASK,
 296                                    I2S_CKR_TSD(div_lrck) |
 297                                    I2S_CKR_RSD(div_lrck));
 298         }
 299
 300         switch (params_format(params)) {
 301         case SNDRV_PCM_FORMAT_S8:
 302                 val |= I2S_TXCR_VDW(8);
 303                 break;
 304         case SNDRV_PCM_FORMAT_S16_LE:
 305                 val |= I2S_TXCR_VDW(16);
 306                 break;
 307         case SNDRV_PCM_FORMAT_S20_3LE:
 308                 val |= I2S_TXCR_VDW(20);
 309                 break;
 310         case SNDRV_PCM_FORMAT_S24_LE:
 311                 val |= I2S_TXCR_VDW(24);
 312                 break;
 313         case SNDRV_PCM_FORMAT_S32_LE:
 314                 val |= I2S_TXCR_VDW(32);
 315                 break;
 316         default:
 317                 return -EINVAL;
 318         }
 319
 320         switch (params_channels(params)) {
 321         case 8:
 322                 val |= I2S_CHN_8;
 323                 break;
 324         case 6:
 325                 val |= I2S_CHN_6;
 326                 break;
 327         case 4:
 328                 val |= I2S_CHN_4;
 329                 break;
 330         case 2:
 331                 val |= I2S_CHN_2;
 332                 break;
 333         default:
 334                 dev_err(i2s->dev, "invalid channel: %d\n",
 335                         params_channels(params));
 336                 return -EINVAL;
 337         }
 338
 339         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 340                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 341                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 342                                    val);
 343         else
 344                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 345                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 346                                    val);
 347
 348         if (!IS_ERR(i2s->grf) && i2s->pins) {
 349                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 350                 val &= I2S_TXCR_CSR_MASK;
 351
 352                 switch (val) {
 353                 case I2S_CHN_4:
 354                         val = I2S_IO_4CH_OUT_6CH_IN;
 355                         break;
 356                 case I2S_CHN_6:
 357                         val = I2S_IO_6CH_OUT_4CH_IN;
 358                         break;
 359                 case I2S_CHN_8:
 360                         val = I2S_IO_8CH_OUT_2CH_IN;
 361                         break;
 362                 default:
 363                         val = I2S_IO_2CH_OUT_8CH_IN;
 364                         break;
 365                 }
 366
 367                 val <<= i2s->pins->shift;
 368                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 369                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 370         }
 371
 372         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 373                            I2S_DMACR_TDL(16));
 374         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 375                            I2S_DMACR_RDL(16));
 376
 377         val = I2S_CKR_TRCM_TXRX;
 378         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 379                 val = I2S_CKR_TRCM_TXONLY;
 380
 381         regmap_update_bits(i2s->regmap, I2S_CKR,
 382                            I2S_CKR_TRCM_MASK,
 383                            val);
 384         return 0;
 385 }
 386
 387 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 388                                 int cmd, struct snd_soc_dai *dai)
 389 {
 390         struct rk_i2s_dev *i2s = to_info(dai);
 391         int ret = 0;
 392
 393         switch (cmd) {
 394         case SNDRV_PCM_TRIGGER_START:
 395         case SNDRV_PCM_TRIGGER_RESUME:
 396         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 397                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 398                         rockchip_snd_rxctrl(i2s, 1);
 399                 else
 400                         rockchip_snd_txctrl(i2s, 1);
 401                 break;
 402         case SNDRV_PCM_TRIGGER_SUSPEND:
 403         case SNDRV_PCM_TRIGGER_STOP:
 404         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 405                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 406                         rockchip_snd_rxctrl(i2s, 0);
 407                 else
 408                         rockchip_snd_txctrl(i2s, 0);
 409                 break;
 410         default:
 411                 ret = -EINVAL;
 412                 break;
 413         }
 414
 415         return ret;
 416 }
 417
 418 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 419                                    unsigned int freq, int dir)
 420 {
 421         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 422         int ret;
 423
 424         ret = clk_set_rate(i2s->mclk, freq);
 425         if (ret)
 426                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 427
 428         return ret;
 429 }
 430
 431 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 432 {
 433         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 434
 435         dai->capture_dma_data = &i2s->capture_dma_data;
 436         dai->playback_dma_data = &i2s->playback_dma_data;
 437
 438         return 0;
 439 }
 440
 441 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 442         .hw_params = rockchip_i2s_hw_params,
 443         .set_sysclk = rockchip_i2s_set_sysclk,
 444         .set_fmt = rockchip_i2s_set_fmt,
 445         .trigger = rockchip_i2s_trigger,
 446 };
 447
 448 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 449         .probe = rockchip_i2s_dai_probe,
 450         .playback = {
 451                 .stream_name = "Playback",
 452                 .channels_min = 2,
 453                 .channels_max = 8,
 454                 .rates = SNDRV_PCM_RATE_8000_192000,
 455                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 456                             SNDRV_PCM_FMTBIT_S16_LE |
 457                             SNDRV_PCM_FMTBIT_S20_3LE |
 458                             SNDRV_PCM_FMTBIT_S24_LE |
 459                             SNDRV_PCM_FMTBIT_S32_LE),
 460         },
 461         .capture = {
 462                 .stream_name = "Capture",
 463                 .channels_min = 2,
 464                 .channels_max = 2,
 465                 .rates = SNDRV_PCM_RATE_8000_192000,
 466                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 467                             SNDRV_PCM_FMTBIT_S16_LE |
 468                             SNDRV_PCM_FMTBIT_S20_3LE |
 469                             SNDRV_PCM_FMTBIT_S24_LE |
 470                             SNDRV_PCM_FMTBIT_S32_LE),
 471         },
 472         .ops = &rockchip_i2s_dai_ops,
 473         .symmetric_rates = 1,
 474 };
 475
 476 static const struct snd_soc_component_driver rockchip_i2s_component = {
 477         .name = DRV_NAME,
 478 };
 479
 480 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 481 {
 482         switch (reg) {
 483         case I2S_TXCR:
 484         case I2S_RXCR:
 485         case I2S_CKR:
 486         case I2S_DMACR:
 487         case I2S_INTCR:
 488         case I2S_XFER:
 489         case I2S_CLR:
 490         case I2S_TXDR:
 491                 return true;
 492         default:
 493                 return false;
 494         }
 495 }
 496
 497 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 498 {
 499         switch (reg) {
 500         case I2S_TXCR:
 501         case I2S_RXCR:
 502         case I2S_CKR:
 503         case I2S_DMACR:
 504         case I2S_INTCR:
 505         case I2S_XFER:
 506         case I2S_CLR:
 507         case I2S_RXDR:
 508         case I2S_FIFOLR:
 509         case I2S_INTSR:
 510                 return true;
 511         default:
 512                 return false;
 513         }
 514 }
 515
 516 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 517 {
 518         switch (reg) {
 519         case I2S_INTSR:
 520         case I2S_CLR:
 521                 return true;
 522         default:
 523                 return false;
 524         }
 525 }
 526
 527 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 528 {
 529         switch (reg) {
 530         default:
 531                 return false;
 532         }
 533 }
 534
 535 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 536         {0x00, 0x0000000f},
 537         {0x04, 0x0000000f},
 538         {0x08, 0x00071f1f},
 539         {0x10, 0x001f0000},
 540         {0x14, 0x01f00000},
 541 };
 542
 543 static const struct regmap_config rockchip_i2s_regmap_config = {
 544         .reg_bits = 32,
 545         .reg_stride = 4,
 546         .val_bits = 32,
 547         .max_register = I2S_RXDR,
 548         .reg_defaults = rockchip_i2s_reg_defaults,
 549         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 550         .writeable_reg = rockchip_i2s_wr_reg,
 551         .readable_reg = rockchip_i2s_rd_reg,
 552         .volatile_reg = rockchip_i2s_volatile_reg,
 553         .precious_reg = rockchip_i2s_precious_reg,
 554         .cache_type = REGCACHE_FLAT,
 555 };
 556
 557 static const struct rk_i2s_pins rk3399_i2s_pins = {
 558         .reg_offset = 0xe220,
 559         .shift = 11,
 560 };
 561
 562 static const struct of_device_id rockchip_i2s_match[] = {
 563         { .compatible = "rockchip,rk3066-i2s", },
 564         { .compatible = "rockchip,rk3188-i2s", },
 565         { .compatible = "rockchip,rk3288-i2s", },
 566         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 567         {},
 568 };
 569
 570 static int rockchip_i2s_probe(struct platform_device *pdev)
 571 {
 572         struct device_node *node = pdev->dev.of_node;
 573         const struct of_device_id *of_id;
 574         struct rk_i2s_dev *i2s;
 575         struct snd_soc_dai_driver *soc_dai;
 576         struct resource *res;
 577         void __iomem *regs;
 578         int ret;
 579         int val;
 580
 581         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 582         if (!i2s) {
 583                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 584                 return -ENOMEM;
 585         }
 586
 587         i2s->dev = &pdev->dev;
 588
 589         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 590         if (!IS_ERR(i2s->grf)) {
 591                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 592                 if (!of_id || !of_id->data)
 593                         return -EINVAL;
 594
 595                 i2s->pins = of_id->data;
 596         }
 597
 598         /* try to prepare related clocks */
 599         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 600         if (IS_ERR(i2s->hclk)) {
 601                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 602                 return PTR_ERR(i2s->hclk);
 603         }
 604         ret = clk_prepare_enable(i2s->hclk);
 605         if (ret) {
 606                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 607                 return ret;
 608         }
 609
 610         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 611         if (IS_ERR(i2s->mclk)) {
 612                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 613                 return PTR_ERR(i2s->mclk);
 614         }
 615
 616         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 617         regs = devm_ioremap_resource(&pdev->dev, res);
 618         if (IS_ERR(regs))
 619                 return PTR_ERR(regs);
 620
 621         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 622                                             &rockchip_i2s_regmap_config);
 623         if (IS_ERR(i2s->regmap)) {
 624                 dev_err(&pdev->dev,
 625                         "Failed to initialise managed register map\n");
 626                 return PTR_ERR(i2s->regmap);
 627         }
 628
 629         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 630         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 631         i2s->playback_dma_data.maxburst = 4;
 632
 633         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 634         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 635         i2s->capture_dma_data.maxburst = 4;
 636
 637         dev_set_drvdata(&pdev->dev, i2s);
 638
 639         pm_runtime_enable(&pdev->dev);
 640         if (!pm_runtime_enabled(&pdev->dev)) {
 641                 ret = i2s_runtime_resume(&pdev->dev);
 642                 if (ret)
 643                         goto err_pm_disable;
 644         }
 645
 646         soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
 647                                sizeof(*soc_dai), GFP_KERNEL);
 648         if (!soc_dai) {
 649                 ret = -ENOMEM;
 650                 goto err_pm_disable;
 651         }
 652
 653         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 654                 if (val >= 2 && val <= 8)
 655                         soc_dai->playback.channels_max = val;
 656         }
 657
 658         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 659                 if (val >= 2 && val <= 8)
 660                         soc_dai->capture.channels_max = val;
 661         }
 662
 663         ret = devm_snd_soc_register_component(&pdev->dev,
 664                                               &rockchip_i2s_component,
 665                                               soc_dai, 1);
 666
 667         if (ret) {
 668                 dev_err(&pdev->dev, "Could not register DAI\n");
 669                 goto err_suspend;
 670         }
 671
 672         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 673         if (ret) {
 674                 dev_err(&pdev->dev, "Could not register PCM\n");
 675                 return ret;
 676         }
 677
 678         return 0;
 679
 680 err_suspend:
 681         if (!pm_runtime_status_suspended(&pdev->dev))
 682                 i2s_runtime_suspend(&pdev->dev);
 683 err_pm_disable:
 684         pm_runtime_disable(&pdev->dev);
 685
 686         return ret;
 687 }
 688
 689 static int rockchip_i2s_remove(struct platform_device *pdev)
 690 {
 691         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 692
 693         pm_runtime_disable(&pdev->dev);
 694         if (!pm_runtime_status_suspended(&pdev->dev))
 695                 i2s_runtime_suspend(&pdev->dev);
 696
 697         clk_disable_unprepare(i2s->mclk);
 698         clk_disable_unprepare(i2s->hclk);
 699
 700         return 0;
 701 }
 702
 703 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 704         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 705                            NULL)
 706 };
 707
 708 static struct platform_driver rockchip_i2s_driver = {
 709         .probe = rockchip_i2s_probe,
 710         .remove = rockchip_i2s_remove,
 711         .driver = {
 712                 .name = DRV_NAME,
 713                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 714                 .pm = &rockchip_i2s_pm_ops,
 715         },
 716 };
 717 module_platform_driver(rockchip_i2s_driver);
 718
 719 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 720 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 721 MODULE_LICENSE("GPL v2");
 722 MODULE_ALIAS("platform:" DRV_NAME);
 723 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);