2 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
16 #include <linux/dma-mapping.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <sound/pcm_params.h>
22 #include <linux/regmap.h>
23 #include <sound/soc.h>
24 #include "lpass-lpaif-reg.h"
27 struct lpass_pcm_data {
32 #define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
33 #define LPASS_PLATFORM_PERIODS 2
35 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
36 .info = SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_MMAP_VALID |
38 SNDRV_PCM_INFO_INTERLEAVED |
39 SNDRV_PCM_INFO_PAUSE |
40 SNDRV_PCM_INFO_RESUME,
41 .formats = SNDRV_PCM_FMTBIT_S16 |
42 SNDRV_PCM_FMTBIT_S24 |
44 .rates = SNDRV_PCM_RATE_8000_192000,
49 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
50 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
51 LPASS_PLATFORM_PERIODS,
52 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
53 LPASS_PLATFORM_PERIODS,
54 .periods_min = LPASS_PLATFORM_PERIODS,
55 .periods_max = LPASS_PLATFORM_PERIODS,
59 static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
61 struct snd_pcm_runtime *runtime = substream->runtime;
62 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
63 struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
64 struct lpass_data *drvdata =
65 snd_soc_platform_get_drvdata(soc_runtime->platform);
66 struct lpass_variant *v = drvdata->variant;
67 int ret, dma_ch, dir = substream->stream;
68 struct lpass_pcm_data *data;
70 data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
74 data->i2s_port = cpu_dai->driver->id;
75 runtime->private_data = data;
78 if (v->alloc_dma_channel)
79 dma_ch = v->alloc_dma_channel(drvdata, dir);
86 drvdata->substream[dma_ch] = substream;
88 ret = regmap_write(drvdata->lpaif_map,
89 LPAIF_DMACTL_REG(v, dma_ch, dir), 0);
91 dev_err(soc_runtime->dev,
92 "error writing to rdmactl reg: %d\n", ret);
96 data->dma_ch = dma_ch;
98 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
100 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
102 ret = snd_pcm_hw_constraint_integer(runtime,
103 SNDRV_PCM_HW_PARAM_PERIODS);
105 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
110 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
115 static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream)
117 struct snd_pcm_runtime *runtime = substream->runtime;
118 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
119 struct lpass_data *drvdata =
120 snd_soc_platform_get_drvdata(soc_runtime->platform);
121 struct lpass_variant *v = drvdata->variant;
122 struct lpass_pcm_data *data;
124 data = runtime->private_data;
125 v = drvdata->variant;
126 drvdata->substream[data->dma_ch] = NULL;
127 if (v->free_dma_channel)
128 v->free_dma_channel(drvdata, data->dma_ch);
133 static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
134 struct snd_pcm_hw_params *params)
136 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
137 struct lpass_data *drvdata =
138 snd_soc_platform_get_drvdata(soc_runtime->platform);
139 struct snd_pcm_runtime *rt = substream->runtime;
140 struct lpass_pcm_data *pcm_data = rt->private_data;
141 struct lpass_variant *v = drvdata->variant;
142 snd_pcm_format_t format = params_format(params);
143 unsigned int channels = params_channels(params);
145 int ch, dir = substream->stream;
147 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
149 ch = pcm_data->dma_ch;
151 bitwidth = snd_pcm_format_width(format);
153 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
158 regval = LPAIF_DMACTL_BURSTEN_INCR4 |
159 LPAIF_DMACTL_AUDINTF(dma_port) |
160 LPAIF_DMACTL_FIFOWM_8;
167 regval |= LPAIF_DMACTL_WPSCNT_ONE;
170 regval |= LPAIF_DMACTL_WPSCNT_TWO;
173 regval |= LPAIF_DMACTL_WPSCNT_THREE;
176 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
179 dev_err(soc_runtime->dev,
180 "invalid PCM config given: bw=%d, ch=%u\n",
189 regval |= LPAIF_DMACTL_WPSCNT_ONE;
192 regval |= LPAIF_DMACTL_WPSCNT_TWO;
195 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
198 regval |= LPAIF_DMACTL_WPSCNT_SIX;
201 regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
204 dev_err(soc_runtime->dev,
205 "invalid PCM config given: bw=%d, ch=%u\n",
211 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
216 ret = regmap_write(drvdata->lpaif_map,
217 LPAIF_DMACTL_REG(v, ch, dir), regval);
219 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
227 static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
229 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
230 struct lpass_data *drvdata =
231 snd_soc_platform_get_drvdata(soc_runtime->platform);
232 struct snd_pcm_runtime *rt = substream->runtime;
233 struct lpass_pcm_data *pcm_data = rt->private_data;
234 struct lpass_variant *v = drvdata->variant;
238 reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream);
239 ret = regmap_write(drvdata->lpaif_map, reg, 0);
241 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
247 static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
249 struct snd_pcm_runtime *runtime = substream->runtime;
250 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
251 struct lpass_data *drvdata =
252 snd_soc_platform_get_drvdata(soc_runtime->platform);
253 struct snd_pcm_runtime *rt = substream->runtime;
254 struct lpass_pcm_data *pcm_data = rt->private_data;
255 struct lpass_variant *v = drvdata->variant;
256 int ret, ch, dir = substream->stream;
258 ch = pcm_data->dma_ch;
260 ret = regmap_write(drvdata->lpaif_map,
261 LPAIF_DMABASE_REG(v, ch, dir),
264 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
269 ret = regmap_write(drvdata->lpaif_map,
270 LPAIF_DMABUFF_REG(v, ch, dir),
271 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
273 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
278 ret = regmap_write(drvdata->lpaif_map,
279 LPAIF_DMAPER_REG(v, ch, dir),
280 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
282 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
287 ret = regmap_update_bits(drvdata->lpaif_map,
288 LPAIF_DMACTL_REG(v, ch, dir),
289 LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
291 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
299 static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
302 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
303 struct lpass_data *drvdata =
304 snd_soc_platform_get_drvdata(soc_runtime->platform);
305 struct snd_pcm_runtime *rt = substream->runtime;
306 struct lpass_pcm_data *pcm_data = rt->private_data;
307 struct lpass_variant *v = drvdata->variant;
308 int ret, ch, dir = substream->stream;
310 ch = pcm_data->dma_ch;
313 case SNDRV_PCM_TRIGGER_START:
314 case SNDRV_PCM_TRIGGER_RESUME:
315 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
316 /* clear status before enabling interrupts */
317 ret = regmap_write(drvdata->lpaif_map,
318 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
321 dev_err(soc_runtime->dev,
322 "error writing to irqclear reg: %d\n", ret);
326 ret = regmap_update_bits(drvdata->lpaif_map,
327 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
331 dev_err(soc_runtime->dev,
332 "error writing to irqen reg: %d\n", ret);
336 ret = regmap_update_bits(drvdata->lpaif_map,
337 LPAIF_DMACTL_REG(v, ch, dir),
338 LPAIF_DMACTL_ENABLE_MASK,
339 LPAIF_DMACTL_ENABLE_ON);
341 dev_err(soc_runtime->dev,
342 "error writing to rdmactl reg: %d\n", ret);
346 case SNDRV_PCM_TRIGGER_STOP:
347 case SNDRV_PCM_TRIGGER_SUSPEND:
348 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
349 ret = regmap_update_bits(drvdata->lpaif_map,
350 LPAIF_DMACTL_REG(v, ch, dir),
351 LPAIF_DMACTL_ENABLE_MASK,
352 LPAIF_DMACTL_ENABLE_OFF);
354 dev_err(soc_runtime->dev,
355 "error writing to rdmactl reg: %d\n", ret);
359 ret = regmap_update_bits(drvdata->lpaif_map,
360 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
361 LPAIF_IRQ_ALL(ch), 0);
363 dev_err(soc_runtime->dev,
364 "error writing to irqen reg: %d\n", ret);
373 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
374 struct snd_pcm_substream *substream)
376 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
377 struct lpass_data *drvdata =
378 snd_soc_platform_get_drvdata(soc_runtime->platform);
379 struct snd_pcm_runtime *rt = substream->runtime;
380 struct lpass_pcm_data *pcm_data = rt->private_data;
381 struct lpass_variant *v = drvdata->variant;
382 unsigned int base_addr, curr_addr;
383 int ret, ch, dir = substream->stream;
385 ch = pcm_data->dma_ch;
387 ret = regmap_read(drvdata->lpaif_map,
388 LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
390 dev_err(soc_runtime->dev,
391 "error reading from rdmabase reg: %d\n", ret);
395 ret = regmap_read(drvdata->lpaif_map,
396 LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
398 dev_err(soc_runtime->dev,
399 "error reading from rdmacurr reg: %d\n", ret);
403 return bytes_to_frames(substream->runtime, curr_addr - base_addr);
406 static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
407 struct vm_area_struct *vma)
409 struct snd_pcm_runtime *runtime = substream->runtime;
411 return dma_mmap_coherent(substream->pcm->card->dev, vma,
412 runtime->dma_area, runtime->dma_addr,
416 static const struct snd_pcm_ops lpass_platform_pcm_ops = {
417 .open = lpass_platform_pcmops_open,
418 .close = lpass_platform_pcmops_close,
419 .ioctl = snd_pcm_lib_ioctl,
420 .hw_params = lpass_platform_pcmops_hw_params,
421 .hw_free = lpass_platform_pcmops_hw_free,
422 .prepare = lpass_platform_pcmops_prepare,
423 .trigger = lpass_platform_pcmops_trigger,
424 .pointer = lpass_platform_pcmops_pointer,
425 .mmap = lpass_platform_pcmops_mmap,
428 static irqreturn_t lpass_dma_interrupt_handler(
429 struct snd_pcm_substream *substream,
430 struct lpass_data *drvdata,
431 int chan, u32 interrupts)
433 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
434 struct lpass_variant *v = drvdata->variant;
435 irqreturn_t ret = IRQ_NONE;
438 if (interrupts & LPAIF_IRQ_PER(chan)) {
439 rv = regmap_write(drvdata->lpaif_map,
440 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
441 LPAIF_IRQ_PER(chan));
443 dev_err(soc_runtime->dev,
444 "error writing to irqclear reg: %d\n", rv);
447 snd_pcm_period_elapsed(substream);
451 if (interrupts & LPAIF_IRQ_XRUN(chan)) {
452 rv = regmap_write(drvdata->lpaif_map,
453 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
454 LPAIF_IRQ_XRUN(chan));
456 dev_err(soc_runtime->dev,
457 "error writing to irqclear reg: %d\n", rv);
460 dev_warn(soc_runtime->dev, "xrun warning\n");
461 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
465 if (interrupts & LPAIF_IRQ_ERR(chan)) {
466 rv = regmap_write(drvdata->lpaif_map,
467 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
468 LPAIF_IRQ_ERR(chan));
470 dev_err(soc_runtime->dev,
471 "error writing to irqclear reg: %d\n", rv);
474 dev_err(soc_runtime->dev, "bus access error\n");
475 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
482 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
484 struct lpass_data *drvdata = data;
485 struct lpass_variant *v = drvdata->variant;
489 rv = regmap_read(drvdata->lpaif_map,
490 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
492 pr_err("error reading from irqstat reg: %d\n", rv);
496 /* Handle per channel interrupts */
497 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
498 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
499 rv = lpass_dma_interrupt_handler(
500 drvdata->substream[chan],
501 drvdata, chan, irqs);
502 if (rv != IRQ_HANDLED)
510 static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
512 struct snd_pcm *pcm = soc_runtime->pcm;
513 struct snd_pcm_substream *psubstream, *csubstream;
515 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
517 psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
519 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
520 soc_runtime->platform->dev,
521 size, &psubstream->dma_buffer);
523 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
528 csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
530 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
531 soc_runtime->platform->dev,
532 size, &csubstream->dma_buffer);
534 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
536 snd_dma_free_pages(&psubstream->dma_buffer);
545 static void lpass_platform_pcm_free(struct snd_pcm *pcm)
547 struct snd_pcm_substream *substream;
550 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
551 substream = pcm->streams[i].substream;
553 snd_dma_free_pages(&substream->dma_buffer);
554 substream->dma_buffer.area = NULL;
555 substream->dma_buffer.addr = 0;
560 static const struct snd_soc_platform_driver lpass_platform_driver = {
561 .pcm_new = lpass_platform_pcm_new,
562 .pcm_free = lpass_platform_pcm_free,
563 .ops = &lpass_platform_pcm_ops,
566 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
568 struct lpass_data *drvdata = platform_get_drvdata(pdev);
569 struct lpass_variant *v = drvdata->variant;
572 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
573 if (drvdata->lpaif_irq < 0) {
574 dev_err(&pdev->dev, "error getting irq handle: %d\n",
579 /* ensure audio hardware is disabled */
580 ret = regmap_write(drvdata->lpaif_map,
581 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
583 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
587 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
588 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
589 "lpass-irq-lpaif", drvdata);
591 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
596 return devm_snd_soc_register_platform(&pdev->dev,
597 &lpass_platform_driver);
599 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
601 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
602 MODULE_LICENSE("GPL v2");