2 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
16 #include <linux/dma-mapping.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <sound/pcm_params.h>
22 #include <linux/regmap.h>
23 #include <sound/soc.h>
24 #include "lpass-lpaif-reg.h"
27 struct lpass_pcm_data {
33 #define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
34 #define LPASS_PLATFORM_PERIODS 2
36 static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
37 .info = SNDRV_PCM_INFO_MMAP |
38 SNDRV_PCM_INFO_MMAP_VALID |
39 SNDRV_PCM_INFO_INTERLEAVED |
40 SNDRV_PCM_INFO_PAUSE |
41 SNDRV_PCM_INFO_RESUME,
42 .formats = SNDRV_PCM_FMTBIT_S16 |
43 SNDRV_PCM_FMTBIT_S24 |
45 .rates = SNDRV_PCM_RATE_8000_192000,
50 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
51 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
52 LPASS_PLATFORM_PERIODS,
53 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
54 LPASS_PLATFORM_PERIODS,
55 .periods_min = LPASS_PLATFORM_PERIODS,
56 .periods_max = LPASS_PLATFORM_PERIODS,
60 static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
62 struct snd_pcm_runtime *runtime = substream->runtime;
63 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
64 struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
65 struct lpass_data *drvdata =
66 snd_soc_platform_get_drvdata(soc_runtime->platform);
67 struct lpass_variant *v = drvdata->variant;
68 int ret, dma_ch, dir = substream->stream;
69 struct lpass_pcm_data *data;
71 data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
75 data->i2s_port = cpu_dai->driver->id;
76 runtime->private_data = data;
79 if (v->alloc_dma_channel)
80 dma_ch = v->alloc_dma_channel(drvdata, dir);
84 drvdata->substream[dma_ch] = substream;
86 ret = regmap_write(drvdata->lpaif_map,
87 LPAIF_DMACTL_REG(v, dma_ch, dir), 0);
89 dev_err(soc_runtime->dev,
90 "%s() error writing to rdmactl reg: %d\n",
95 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
96 data->rdma_ch = dma_ch;
98 data->wrdma_ch = dma_ch;
100 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
102 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
104 ret = snd_pcm_hw_constraint_integer(runtime,
105 SNDRV_PCM_HW_PARAM_PERIODS);
107 dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
112 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
117 static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream)
119 struct snd_pcm_runtime *runtime = substream->runtime;
120 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
121 struct lpass_data *drvdata =
122 snd_soc_platform_get_drvdata(soc_runtime->platform);
123 struct lpass_variant *v = drvdata->variant;
124 struct lpass_pcm_data *data;
125 int dma_ch, dir = substream->stream;
127 data = runtime->private_data;
128 v = drvdata->variant;
130 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
131 dma_ch = data->rdma_ch;
133 dma_ch = data->wrdma_ch;
135 drvdata->substream[dma_ch] = NULL;
137 if (v->free_dma_channel)
138 v->free_dma_channel(drvdata, dma_ch);
143 static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
144 struct snd_pcm_hw_params *params)
146 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
147 struct lpass_data *drvdata =
148 snd_soc_platform_get_drvdata(soc_runtime->platform);
149 struct snd_pcm_runtime *rt = substream->runtime;
150 struct lpass_pcm_data *pcm_data = rt->private_data;
151 struct lpass_variant *v = drvdata->variant;
152 snd_pcm_format_t format = params_format(params);
153 unsigned int channels = params_channels(params);
155 int ch, dir = substream->stream;
157 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
159 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
160 ch = pcm_data->rdma_ch;
162 ch = pcm_data->wrdma_ch;
164 bitwidth = snd_pcm_format_width(format);
166 dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
171 regval = LPAIF_DMACTL_BURSTEN_INCR4 |
172 LPAIF_DMACTL_AUDINTF(dma_port) |
173 LPAIF_DMACTL_FIFOWM_8;
180 regval |= LPAIF_DMACTL_WPSCNT_ONE;
183 regval |= LPAIF_DMACTL_WPSCNT_TWO;
186 regval |= LPAIF_DMACTL_WPSCNT_THREE;
189 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
192 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
193 __func__, bitwidth, channels);
201 regval |= LPAIF_DMACTL_WPSCNT_ONE;
204 regval |= LPAIF_DMACTL_WPSCNT_TWO;
207 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
210 regval |= LPAIF_DMACTL_WPSCNT_SIX;
213 regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
216 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
217 __func__, bitwidth, channels);
222 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
223 __func__, bitwidth, channels);
227 ret = regmap_write(drvdata->lpaif_map,
228 LPAIF_DMACTL_REG(v, ch, dir), regval);
230 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
238 static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
240 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
241 struct lpass_data *drvdata =
242 snd_soc_platform_get_drvdata(soc_runtime->platform);
243 struct snd_pcm_runtime *rt = substream->runtime;
244 struct lpass_pcm_data *pcm_data = rt->private_data;
245 struct lpass_variant *v = drvdata->variant;
249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
250 reg = LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch);
252 reg = LPAIF_WRDMACTL_REG(v, pcm_data->wrdma_ch);
254 ret = regmap_write(drvdata->lpaif_map, reg, 0);
256 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
262 static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
264 struct snd_pcm_runtime *runtime = substream->runtime;
265 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
266 struct lpass_data *drvdata =
267 snd_soc_platform_get_drvdata(soc_runtime->platform);
268 struct snd_pcm_runtime *rt = substream->runtime;
269 struct lpass_pcm_data *pcm_data = rt->private_data;
270 struct lpass_variant *v = drvdata->variant;
271 int ret, ch, dir = substream->stream;
273 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
274 ch = pcm_data->rdma_ch;
276 ch = pcm_data->wrdma_ch;
278 ret = regmap_write(drvdata->lpaif_map,
279 LPAIF_DMABASE_REG(v, ch, dir),
282 dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
287 ret = regmap_write(drvdata->lpaif_map,
288 LPAIF_DMABUFF_REG(v, ch, dir),
289 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
291 dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
296 ret = regmap_write(drvdata->lpaif_map,
297 LPAIF_DMAPER_REG(v, ch, dir),
298 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
300 dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
305 ret = regmap_update_bits(drvdata->lpaif_map,
306 LPAIF_DMACTL_REG(v, ch, dir),
307 LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
309 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
317 static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
320 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
321 struct lpass_data *drvdata =
322 snd_soc_platform_get_drvdata(soc_runtime->platform);
323 struct snd_pcm_runtime *rt = substream->runtime;
324 struct lpass_pcm_data *pcm_data = rt->private_data;
325 struct lpass_variant *v = drvdata->variant;
326 int ret, ch, dir = substream->stream;
328 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
329 ch = pcm_data->rdma_ch;
331 ch = pcm_data->wrdma_ch;
334 case SNDRV_PCM_TRIGGER_START:
335 case SNDRV_PCM_TRIGGER_RESUME:
336 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
337 /* clear status before enabling interrupts */
338 ret = regmap_write(drvdata->lpaif_map,
339 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
342 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
347 ret = regmap_update_bits(drvdata->lpaif_map,
348 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
352 dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
357 ret = regmap_update_bits(drvdata->lpaif_map,
358 LPAIF_DMACTL_REG(v, ch, dir),
359 LPAIF_DMACTL_ENABLE_MASK,
360 LPAIF_DMACTL_ENABLE_ON);
362 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
367 case SNDRV_PCM_TRIGGER_STOP:
368 case SNDRV_PCM_TRIGGER_SUSPEND:
369 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
370 ret = regmap_update_bits(drvdata->lpaif_map,
371 LPAIF_DMACTL_REG(v, ch, dir),
372 LPAIF_DMACTL_ENABLE_MASK,
373 LPAIF_DMACTL_ENABLE_OFF);
375 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
380 ret = regmap_update_bits(drvdata->lpaif_map,
381 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
382 LPAIF_IRQ_ALL(ch), 0);
384 dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
394 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
395 struct snd_pcm_substream *substream)
397 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
398 struct lpass_data *drvdata =
399 snd_soc_platform_get_drvdata(soc_runtime->platform);
400 struct snd_pcm_runtime *rt = substream->runtime;
401 struct lpass_pcm_data *pcm_data = rt->private_data;
402 struct lpass_variant *v = drvdata->variant;
403 unsigned int base_addr, curr_addr;
404 int ret, ch, dir = substream->stream;
406 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
407 ch = pcm_data->rdma_ch;
409 ch = pcm_data->wrdma_ch;
411 ret = regmap_read(drvdata->lpaif_map,
412 LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
414 dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
419 ret = regmap_read(drvdata->lpaif_map,
420 LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
422 dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
427 return bytes_to_frames(substream->runtime, curr_addr - base_addr);
430 static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
431 struct vm_area_struct *vma)
433 struct snd_pcm_runtime *runtime = substream->runtime;
435 return dma_mmap_coherent(substream->pcm->card->dev, vma,
436 runtime->dma_area, runtime->dma_addr,
440 static const struct snd_pcm_ops lpass_platform_pcm_ops = {
441 .open = lpass_platform_pcmops_open,
442 .close = lpass_platform_pcmops_close,
443 .ioctl = snd_pcm_lib_ioctl,
444 .hw_params = lpass_platform_pcmops_hw_params,
445 .hw_free = lpass_platform_pcmops_hw_free,
446 .prepare = lpass_platform_pcmops_prepare,
447 .trigger = lpass_platform_pcmops_trigger,
448 .pointer = lpass_platform_pcmops_pointer,
449 .mmap = lpass_platform_pcmops_mmap,
452 static irqreturn_t lpass_dma_interrupt_handler(
453 struct snd_pcm_substream *substream,
454 struct lpass_data *drvdata,
455 int chan, u32 interrupts)
457 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
458 struct lpass_variant *v = drvdata->variant;
459 irqreturn_t ret = IRQ_NONE;
462 if (interrupts & LPAIF_IRQ_PER(chan)) {
463 rv = regmap_write(drvdata->lpaif_map,
464 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
465 LPAIF_IRQ_PER(chan));
467 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
471 snd_pcm_period_elapsed(substream);
475 if (interrupts & LPAIF_IRQ_XRUN(chan)) {
476 rv = regmap_write(drvdata->lpaif_map,
477 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
478 LPAIF_IRQ_XRUN(chan));
480 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
484 dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
485 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
489 if (interrupts & LPAIF_IRQ_ERR(chan)) {
490 rv = regmap_write(drvdata->lpaif_map,
491 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
492 LPAIF_IRQ_ERR(chan));
494 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
498 dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
499 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
506 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
508 struct lpass_data *drvdata = data;
509 struct lpass_variant *v = drvdata->variant;
513 rv = regmap_read(drvdata->lpaif_map,
514 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
516 pr_err("%s() error reading from irqstat reg: %d\n",
521 /* Handle per channel interrupts */
522 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
523 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
524 rv = lpass_dma_interrupt_handler(
525 drvdata->substream[chan],
526 drvdata, chan, irqs);
527 if (rv != IRQ_HANDLED)
535 static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
537 struct snd_pcm *pcm = soc_runtime->pcm;
538 struct snd_pcm_substream *psubstream, *csubstream;
540 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
542 psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
544 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
545 soc_runtime->platform->dev,
546 size, &psubstream->dma_buffer);
548 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
553 csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
555 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
556 soc_runtime->platform->dev,
557 size, &csubstream->dma_buffer);
559 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
561 snd_dma_free_pages(&psubstream->dma_buffer);
570 static void lpass_platform_pcm_free(struct snd_pcm *pcm)
572 struct snd_pcm_substream *substream;
575 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
576 substream = pcm->streams[i].substream;
578 snd_dma_free_pages(&substream->dma_buffer);
579 substream->dma_buffer.area = NULL;
580 substream->dma_buffer.addr = 0;
585 static struct snd_soc_platform_driver lpass_platform_driver = {
586 .pcm_new = lpass_platform_pcm_new,
587 .pcm_free = lpass_platform_pcm_free,
588 .ops = &lpass_platform_pcm_ops,
591 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
593 struct lpass_data *drvdata = platform_get_drvdata(pdev);
594 struct lpass_variant *v = drvdata->variant;
597 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
598 if (drvdata->lpaif_irq < 0) {
599 dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
600 __func__, drvdata->lpaif_irq);
604 /* ensure audio hardware is disabled */
605 ret = regmap_write(drvdata->lpaif_map,
606 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
608 dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
613 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
614 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
615 "lpass-irq-lpaif", drvdata);
617 dev_err(&pdev->dev, "%s() irq request failed: %d\n",
623 return devm_snd_soc_register_platform(&pdev->dev,
624 &lpass_platform_driver);
626 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
628 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
629 MODULE_LICENSE("GPL v2");