Merge branch 'fix/asoc' into topic/asoc
[sfrench/cifs-2.6.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21  * 02110-1301 USA
22  *
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33
34 #include <mach/control.h>
35 #include <mach/dma.h>
36 #include <mach/mcbsp.h>
37 #include "omap-mcbsp.h"
38 #include "omap-pcm.h"
39
40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
41
42 struct omap_mcbsp_data {
43         unsigned int                    bus_id;
44         struct omap_mcbsp_reg_cfg       regs;
45         unsigned int                    fmt;
46         /*
47          * Flags indicating is the bus already activated and configured by
48          * another substream
49          */
50         int                             active;
51         int                             configured;
52 };
53
54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
55
56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
57
58 /*
59  * Stream DMA parameters. DMA request line and port address are set runtime
60  * since they are different between OMAP1 and later OMAPs
61  */
62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63
64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
65 static const int omap1_dma_reqs[][2] = {
66         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
67         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
68         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 };
70 static const unsigned long omap1_mcbsp_port[][2] = {
71         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
72           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
73         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
74           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
75         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
76           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
77 };
78 #else
79 static const int omap1_dma_reqs[][2] = {};
80 static const unsigned long omap1_mcbsp_port[][2] = {};
81 #endif
82
83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
84 static const int omap24xx_dma_reqs[][2] = {
85         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
86         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
88         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
89         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
90         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
91 #endif
92 };
93 #else
94 static const int omap24xx_dma_reqs[][2] = {};
95 #endif
96
97 #if defined(CONFIG_ARCH_OMAP2420)
98 static const unsigned long omap2420_mcbsp_port[][2] = {
99         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
100           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
101         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
102           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
103 };
104 #else
105 static const unsigned long omap2420_mcbsp_port[][2] = {};
106 #endif
107
108 #if defined(CONFIG_ARCH_OMAP2430)
109 static const unsigned long omap2430_mcbsp_port[][2] = {
110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
114         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
115           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
116         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
117           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
118         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
119           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
120 };
121 #else
122 static const unsigned long omap2430_mcbsp_port[][2] = {};
123 #endif
124
125 #if defined(CONFIG_ARCH_OMAP34XX)
126 static const unsigned long omap34xx_mcbsp_port[][2] = {
127         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
128           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
129         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
130           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
131         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
132           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
133         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
134           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
135         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
136           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
137 };
138 #else
139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
140 #endif
141
142 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
143                                   struct snd_soc_dai *dai)
144 {
145         struct snd_soc_pcm_runtime *rtd = substream->private_data;
146         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
147         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
148         int err = 0;
149
150         if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
151                 /*
152                  * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
153                  * Set constraint for minimum buffer size to the same than FIFO
154                  * size in order to avoid underruns in playback startup because
155                  * HW is keeping the DMA request active until FIFO is filled.
156                  */
157                 snd_pcm_hw_constraint_minmax(substream->runtime,
158                         SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
159         }
160
161         if (!cpu_dai->active)
162                 err = omap_mcbsp_request(mcbsp_data->bus_id);
163
164         return err;
165 }
166
167 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
168                                     struct snd_soc_dai *dai)
169 {
170         struct snd_soc_pcm_runtime *rtd = substream->private_data;
171         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
172         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
173
174         if (!cpu_dai->active) {
175                 omap_mcbsp_free(mcbsp_data->bus_id);
176                 mcbsp_data->configured = 0;
177         }
178 }
179
180 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
181                                   struct snd_soc_dai *dai)
182 {
183         struct snd_soc_pcm_runtime *rtd = substream->private_data;
184         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
185         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
186         int err = 0;
187
188         switch (cmd) {
189         case SNDRV_PCM_TRIGGER_START:
190         case SNDRV_PCM_TRIGGER_RESUME:
191         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
192                 if (!mcbsp_data->active++)
193                         omap_mcbsp_start(mcbsp_data->bus_id);
194                 break;
195
196         case SNDRV_PCM_TRIGGER_STOP:
197         case SNDRV_PCM_TRIGGER_SUSPEND:
198         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
199                 if (!--mcbsp_data->active)
200                         omap_mcbsp_stop(mcbsp_data->bus_id);
201                 break;
202         default:
203                 err = -EINVAL;
204         }
205
206         return err;
207 }
208
209 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
210                                     struct snd_pcm_hw_params *params,
211                                     struct snd_soc_dai *dai)
212 {
213         struct snd_soc_pcm_runtime *rtd = substream->private_data;
214         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
215         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
216         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
217         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
218         int wlen, channels, wpf;
219         unsigned long port;
220         unsigned int format;
221
222         if (cpu_class_is_omap1()) {
223                 dma = omap1_dma_reqs[bus_id][substream->stream];
224                 port = omap1_mcbsp_port[bus_id][substream->stream];
225         } else if (cpu_is_omap2420()) {
226                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
227                 port = omap2420_mcbsp_port[bus_id][substream->stream];
228         } else if (cpu_is_omap2430()) {
229                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
230                 port = omap2430_mcbsp_port[bus_id][substream->stream];
231         } else if (cpu_is_omap343x()) {
232                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
233                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
234         } else {
235                 return -ENODEV;
236         }
237         omap_mcbsp_dai_dma_params[id][substream->stream].name =
238                 substream->stream ? "Audio Capture" : "Audio Playback";
239         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
240         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
241         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
242
243         if (mcbsp_data->configured) {
244                 /* McBSP already configured by another stream */
245                 return 0;
246         }
247
248         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
249         wpf = channels = params_channels(params);
250         switch (channels) {
251         case 2:
252                 if (format == SND_SOC_DAIFMT_I2S) {
253                         /* Use dual-phase frames */
254                         regs->rcr2      |= RPHASE;
255                         regs->xcr2      |= XPHASE;
256                         /* Set 1 word per (McBSP) frame for phase1 and phase2 */
257                         wpf--;
258                         regs->rcr2      |= RFRLEN2(wpf - 1);
259                         regs->xcr2      |= XFRLEN2(wpf - 1);
260                 }
261         case 1:
262         case 4:
263                 /* Set word per (McBSP) frame for phase1 */
264                 regs->rcr1      |= RFRLEN1(wpf - 1);
265                 regs->xcr1      |= XFRLEN1(wpf - 1);
266                 break;
267         default:
268                 /* Unsupported number of channels */
269                 return -EINVAL;
270         }
271
272         switch (params_format(params)) {
273         case SNDRV_PCM_FORMAT_S16_LE:
274                 /* Set word lengths */
275                 wlen = 16;
276                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
277                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
278                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
279                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
280                 break;
281         default:
282                 /* Unsupported PCM format */
283                 return -EINVAL;
284         }
285
286         /* Set FS period and length in terms of bit clock periods */
287         switch (format) {
288         case SND_SOC_DAIFMT_I2S:
289                 regs->srgr2     |= FPER(wlen * channels - 1);
290                 regs->srgr1     |= FWID(wlen - 1);
291                 break;
292         case SND_SOC_DAIFMT_DSP_A:
293         case SND_SOC_DAIFMT_DSP_B:
294                 regs->srgr2     |= FPER(wlen * channels - 1);
295                 regs->srgr1     |= FWID(0);
296                 break;
297         }
298
299         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
300         mcbsp_data->configured = 1;
301
302         return 0;
303 }
304
305 /*
306  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
307  * cache is initialized here
308  */
309 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310                                       unsigned int fmt)
311 {
312         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
313         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
314         unsigned int temp_fmt = fmt;
315
316         if (mcbsp_data->configured)
317                 return 0;
318
319         mcbsp_data->fmt = fmt;
320         memset(regs, 0, sizeof(*regs));
321         /* Generic McBSP register settings */
322         regs->spcr2     |= XINTM(3) | FREE;
323         regs->spcr1     |= RINTM(3);
324         regs->rcr2      |= RFIG;
325         regs->xcr2      |= XFIG;
326         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
327                 regs->xccr = DXENDLY(1) | XDMAEN;
328                 regs->rccr = RFULL_CYCLE | RDMAEN;
329         }
330
331         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
332         case SND_SOC_DAIFMT_I2S:
333                 /* 1-bit data delay */
334                 regs->rcr2      |= RDATDLY(1);
335                 regs->xcr2      |= XDATDLY(1);
336                 break;
337         case SND_SOC_DAIFMT_DSP_A:
338                 /* 1-bit data delay */
339                 regs->rcr2      |= RDATDLY(1);
340                 regs->xcr2      |= XDATDLY(1);
341                 /* Invert FS polarity configuration */
342                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
343                 break;
344         case SND_SOC_DAIFMT_DSP_B:
345                 /* 0-bit data delay */
346                 regs->rcr2      |= RDATDLY(0);
347                 regs->xcr2      |= XDATDLY(0);
348                 /* Invert FS polarity configuration */
349                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
350                 break;
351         default:
352                 /* Unsupported data format */
353                 return -EINVAL;
354         }
355
356         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
357         case SND_SOC_DAIFMT_CBS_CFS:
358                 /* McBSP master. Set FS and bit clocks as outputs */
359                 regs->pcr0      |= FSXM | FSRM |
360                                    CLKXM | CLKRM;
361                 /* Sample rate generator drives the FS */
362                 regs->srgr2     |= FSGM;
363                 break;
364         case SND_SOC_DAIFMT_CBM_CFM:
365                 /* McBSP slave */
366                 break;
367         default:
368                 /* Unsupported master/slave configuration */
369                 return -EINVAL;
370         }
371
372         /* Set bit clock (CLKX/CLKR) and FS polarities */
373         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
374         case SND_SOC_DAIFMT_NB_NF:
375                 /*
376                  * Normal BCLK + FS.
377                  * FS active low. TX data driven on falling edge of bit clock
378                  * and RX data sampled on rising edge of bit clock.
379                  */
380                 regs->pcr0      |= FSXP | FSRP |
381                                    CLKXP | CLKRP;
382                 break;
383         case SND_SOC_DAIFMT_NB_IF:
384                 regs->pcr0      |= CLKXP | CLKRP;
385                 break;
386         case SND_SOC_DAIFMT_IB_NF:
387                 regs->pcr0      |= FSXP | FSRP;
388                 break;
389         case SND_SOC_DAIFMT_IB_IF:
390                 break;
391         default:
392                 return -EINVAL;
393         }
394
395         return 0;
396 }
397
398 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
399                                      int div_id, int div)
400 {
401         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
402         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
403
404         if (div_id != OMAP_MCBSP_CLKGDV)
405                 return -ENODEV;
406
407         regs->srgr1     |= CLKGDV(div - 1);
408
409         return 0;
410 }
411
412 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
413                                        int clk_id)
414 {
415         int sel_bit;
416         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
417
418         if (cpu_class_is_omap1()) {
419                 /* OMAP1's can use only external source clock */
420                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
421                         return -EINVAL;
422                 else
423                         return 0;
424         }
425
426         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
427                 return -EINVAL;
428
429         if (cpu_is_omap343x())
430                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
431
432         switch (mcbsp_data->bus_id) {
433         case 0:
434                 reg = OMAP2_CONTROL_DEVCONF0;
435                 sel_bit = 2;
436                 break;
437         case 1:
438                 reg = OMAP2_CONTROL_DEVCONF0;
439                 sel_bit = 6;
440                 break;
441         case 2:
442                 reg = reg_devconf1;
443                 sel_bit = 0;
444                 break;
445         case 3:
446                 reg = reg_devconf1;
447                 sel_bit = 2;
448                 break;
449         case 4:
450                 reg = reg_devconf1;
451                 sel_bit = 4;
452                 break;
453         default:
454                 return -EINVAL;
455         }
456
457         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
458                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
459         else
460                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
461
462         return 0;
463 }
464
465 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
466                                          int clk_id, unsigned int freq,
467                                          int dir)
468 {
469         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
470         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
471         int err = 0;
472
473         switch (clk_id) {
474         case OMAP_MCBSP_SYSCLK_CLK:
475                 regs->srgr2     |= CLKSM;
476                 break;
477         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
478         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
479                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
480                 break;
481
482         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
483                 regs->srgr2     |= CLKSM;
484         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
485                 regs->pcr0      |= SCLKME;
486                 break;
487         default:
488                 err = -ENODEV;
489         }
490
491         return err;
492 }
493
494 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
495         .startup        = omap_mcbsp_dai_startup,
496         .shutdown       = omap_mcbsp_dai_shutdown,
497         .trigger        = omap_mcbsp_dai_trigger,
498         .hw_params      = omap_mcbsp_dai_hw_params,
499         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
500         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
501         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
502 };
503
504 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
505 {                                                               \
506         .name = "omap-mcbsp-dai-"#link_id,                      \
507         .id = (link_id),                                        \
508         .playback = {                                           \
509                 .channels_min = 1,                              \
510                 .channels_max = 4,                              \
511                 .rates = OMAP_MCBSP_RATES,                      \
512                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
513         },                                                      \
514         .capture = {                                            \
515                 .channels_min = 1,                              \
516                 .channels_max = 4,                              \
517                 .rates = OMAP_MCBSP_RATES,                      \
518                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
519         },                                                      \
520         .ops = &omap_mcbsp_dai_ops,                             \
521         .private_data = &mcbsp_data[(link_id)].bus_id,          \
522 }
523
524 struct snd_soc_dai omap_mcbsp_dai[] = {
525         OMAP_MCBSP_DAI_BUILDER(0),
526         OMAP_MCBSP_DAI_BUILDER(1),
527 #if NUM_LINKS >= 3
528         OMAP_MCBSP_DAI_BUILDER(2),
529 #endif
530 #if NUM_LINKS == 5
531         OMAP_MCBSP_DAI_BUILDER(3),
532         OMAP_MCBSP_DAI_BUILDER(4),
533 #endif
534 };
535
536 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
537
538 static int __init snd_omap_mcbsp_init(void)
539 {
540         return snd_soc_register_dais(omap_mcbsp_dai,
541                                      ARRAY_SIZE(omap_mcbsp_dai));
542 }
543 module_init(snd_omap_mcbsp_init);
544
545 static void __exit snd_omap_mcbsp_exit(void)
546 {
547         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
548 }
549 module_exit(snd_omap_mcbsp_exit);
550
551 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
552 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
553 MODULE_LICENSE("GPL");