2 * skl_topology.h - Intel HDA Platform topology header file
4 * Copyright (C) 2014-15 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 #ifndef __SKL_TOPOLOGY_H__
22 #define __SKL_TOPOLOGY_H__
24 #include <linux/types.h>
26 #include <sound/hdaudio_ext.h>
27 #include <sound/soc.h>
29 #include "skl-tplg-interface.h"
31 #define BITS_PER_BYTE 8
32 #define MAX_TS_GROUPS 8
33 #define MAX_DMIC_TS_GROUPS 4
34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
36 /* Maximum number of coefficients up down mixer module */
37 #define UP_DOWN_MIXER_MAX_COEFF 6
39 #define MODULE_MAX_IN_PINS 8
40 #define MODULE_MAX_OUT_PINS 8
42 enum skl_channel_index {
44 SKL_CHANNEL_RIGHT = 1,
45 SKL_CHANNEL_CENTER = 2,
46 SKL_CHANNEL_LEFT_SURROUND = 3,
47 SKL_CHANNEL_CENTER_SURROUND = 3,
48 SKL_CHANNEL_RIGHT_SURROUND = 4,
50 SKL_CHANNEL_INVALID = 0xF,
75 SKL_FS_128000 = 128000,
76 SKL_FS_176400 = 176400,
77 SKL_FS_192000 = 192000,
81 enum skl_widget_type {
82 SKL_WIDGET_VMIXER = 1,
88 struct skl_audio_data_format {
89 enum skl_s_freq s_freq;
90 enum skl_bitdepth bit_depth;
92 enum skl_ch_cfg ch_cfg;
93 enum skl_interleaving interleaving;
94 u8 number_of_channels;
100 struct skl_base_cfg {
105 struct skl_audio_data_format audio_fmt;
108 struct skl_cpr_gtw_cfg {
112 /* not mandatory; required only for DMIC/I2S */
116 struct skl_dma_control {
123 struct skl_base_cfg base_cfg;
124 struct skl_audio_data_format out_fmt;
125 u32 cpr_feature_mask;
126 struct skl_cpr_gtw_cfg gtw_cfg;
130 struct skl_src_module_cfg {
131 struct skl_base_cfg base_cfg;
132 enum skl_s_freq src_cfg;
135 struct notification_mask {
140 struct skl_up_down_mixer_cfg {
141 struct skl_base_cfg base_cfg;
142 enum skl_ch_cfg out_ch_cfg;
143 /* This should be set to 1 if user coefficients are required */
145 /* Pass the user coeff in this array */
146 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
149 struct skl_algo_cfg {
150 struct skl_base_cfg base_cfg;
154 struct skl_base_outfmt_cfg {
155 struct skl_base_cfg base_cfg;
156 struct skl_audio_data_format out_fmt;
160 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
161 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
162 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
163 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
164 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
165 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
166 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
167 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
168 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
171 union skl_ssp_dma_node {
174 u8 time_slot_index:4;
179 union skl_connector_node_id {
188 struct skl_module_fmt {
194 u32 interleaving_style;
199 struct skl_module_cfg;
201 struct skl_mod_inst_map {
206 struct skl_kpb_params {
208 struct skl_mod_inst_map map[0];
211 struct skl_module_inst_id {
217 enum skl_module_pin_state {
219 SKL_PIN_BIND_DONE = 1,
222 struct skl_module_pin {
223 struct skl_module_inst_id id;
226 enum skl_module_pin_state pin_state;
227 struct skl_module_cfg *tgt_mcfg;
230 struct skl_specific_cfg {
237 enum skl_pipe_state {
238 SKL_PIPE_INVALID = 0,
239 SKL_PIPE_CREATED = 1,
241 SKL_PIPE_STARTED = 3,
245 struct skl_pipe_module {
246 struct snd_soc_dapm_widget *w;
247 struct list_head node;
250 struct skl_pipe_params {
257 snd_pcm_format_t format;
260 unsigned int host_bps;
261 unsigned int link_bps;
270 struct skl_pipe_params *p_params;
271 enum skl_pipe_state state;
272 struct list_head w_list;
276 enum skl_module_state {
277 SKL_MODULE_UNINIT = 0,
278 SKL_MODULE_LOADED = 1,
279 SKL_MODULE_INIT_DONE = 2,
280 SKL_MODULE_BIND_DONE = 3,
281 SKL_MODULE_UNLOADED = 4,
284 enum d0i3_capability {
286 SKL_D0I3_STREAMING = 1,
287 SKL_D0I3_NON_STREAMING = 2,
290 struct skl_module_cfg {
292 struct skl_module_inst_id id;
294 bool homogenous_inputs;
295 bool homogenous_outputs;
296 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
297 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
316 enum d0i3_capability d0i3_caps;
317 struct skl_module_pin *m_in_pin;
318 struct skl_module_pin *m_out_pin;
319 enum skl_module_type m_type;
320 enum skl_hw_conn_type hw_conn_type;
321 enum skl_module_state m_state;
322 struct skl_pipe *pipe;
323 struct skl_specific_cfg formats_config;
326 struct skl_algo_data {
334 struct skl_pipeline {
335 struct skl_pipe *pipe;
336 struct list_head node;
339 struct skl_module_deferred_bind {
340 struct skl_module_cfg *src;
341 struct skl_module_cfg *dst;
342 struct list_head node;
345 static inline struct skl *get_skl_ctx(struct device *dev)
347 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
349 return ebus_to_skl(ebus);
352 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
353 struct skl_pipe_params *params);
354 int skl_dsp_set_dma_control(struct skl_sst *ctx,
355 struct skl_module_cfg *mconfig);
356 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
357 struct skl_pipe_params *params, int stream);
358 int skl_tplg_init(struct snd_soc_platform *platform,
359 struct hdac_ext_bus *ebus);
360 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
361 struct snd_soc_dai *dai, int stream);
362 int skl_tplg_update_pipe_params(struct device *dev,
363 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
365 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
366 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
368 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
370 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
372 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
374 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
376 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
378 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
380 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
382 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
383 *src_module, struct skl_module_cfg *dst_module);
385 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
386 *src_module, struct skl_module_cfg *dst_module);
388 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
389 u32 param_id, struct skl_module_cfg *mcfg);
390 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
391 u32 param_id, struct skl_module_cfg *mcfg);
393 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
395 enum skl_bitdepth skl_get_bit_depth(int params);
396 int skl_pcm_host_dma_prepare(struct device *dev,
397 struct skl_pipe_params *params);
398 int skl_pcm_link_dma_prepare(struct device *dev,
399 struct skl_pipe_params *params);