sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/hdaudio.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc.h>
  19 #include "skl.h"
  20 #include "skl-topology.h"
  21 #include "skl-sst-dsp.h"
  22 #include "skl-sst-ipc.h"
  23
  24 #define HDA_MONO 1
  25 #define HDA_STEREO 2
  26 #define HDA_QUAD 4
  27 #define HDA_MAX 8
  28
  29 static const struct snd_pcm_hardware azx_pcm_hw = {
  30         .info =                 (SNDRV_PCM_INFO_MMAP |
  31                                  SNDRV_PCM_INFO_INTERLEAVED |
  32                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  33                                  SNDRV_PCM_INFO_MMAP_VALID |
  34                                  SNDRV_PCM_INFO_PAUSE |
  35                                  SNDRV_PCM_INFO_RESUME |
  36                                  SNDRV_PCM_INFO_SYNC_START |
  37                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  38                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  39                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  40         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  41                                 SNDRV_PCM_FMTBIT_S32_LE |
  42                                 SNDRV_PCM_FMTBIT_S24_LE,
  43         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  44                                 SNDRV_PCM_RATE_8000,
  45         .rate_min =             8000,
  46         .rate_max =             48000,
  47         .channels_min =         1,
  48         .channels_max =         8,
  49         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  50         .period_bytes_min =     128,
  51         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  52         .periods_min =          2,
  53         .periods_max =          AZX_MAX_FRAG,
  54         .fifo_size =            0,
  55 };
  56
  57 static inline
  58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  59 {
  60         return substream->runtime->private_data;
  61 }
  62
  63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  64 {
  65         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  66         struct hdac_stream *hstream = hdac_stream(stream);
  67         struct hdac_bus *bus = hstream->bus;
  68         return bus;
  69 }
  70
  71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  72                                  struct snd_pcm_substream *substream,
  73                                  size_t size)
  74 {
  75         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  76
  77         hdac_stream(stream)->bufsize = 0;
  78         hdac_stream(stream)->period_bytes = 0;
  79         hdac_stream(stream)->format_val = 0;
  80
  81         return 0;
  82 }
  83
  84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  85                                  struct snd_pcm_runtime *runtime)
  86 {
  87         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  88
  89         /* avoid wrap-around with wall-clock */
  90         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  91                                      20, 178000000);
  92 }
  93
  94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  95 {
  96         if (bus->ppcap)
  97                 return HDAC_EXT_STREAM_TYPE_HOST;
  98         else
  99                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 100 }
 101
 102 /*
 103  * check if the stream opened is marked as ignore_suspend by machine, if so
 104  * then enable suspend_active refcount
 105  *
 106  * The count supend_active does not need lock as it is used in open/close
 107  * and suspend context
 108  */
 109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 110                                          struct snd_soc_dai *dai, bool enable)
 111 {
 112         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 113         struct snd_soc_dapm_widget *w;
 114         struct skl_dev *skl = bus_to_skl(bus);
 115
 116         w = snd_soc_dai_get_widget(dai, substream->stream);
 117
 118         if (w->ignore_suspend && enable)
 119                 skl->supend_active++;
 120         else if (w->ignore_suspend && !enable)
 121                 skl->supend_active--;
 122 }
 123
 124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dev);
 127         unsigned int format_val;
 128         struct hdac_stream *hstream;
 129         struct hdac_ext_stream *stream;
 130         unsigned int bits;
 131         int err;
 132
 133         hstream = snd_hdac_get_stream(bus, params->stream,
 134                                         params->host_dma_id + 1);
 135         if (!hstream)
 136                 return -EINVAL;
 137
 138         stream = stream_to_hdac_ext_stream(hstream);
 139         snd_hdac_ext_stream_decouple(bus, stream, true);
 140
 141         bits = snd_hdac_stream_format_bits(params->format, SNDRV_PCM_SUBFORMAT_STD,
 142                                            params->host_bps);
 143         format_val = snd_hdac_stream_format(params->ch, bits, params->s_freq);
 144
 145         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 146                 format_val, params->s_freq, params->ch, params->format);
 147
 148         snd_hdac_stream_reset(hdac_stream(stream));
 149         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 150         if (err < 0)
 151                 return err;
 152
 153         err = snd_hdac_ext_host_stream_setup(stream, false);
 154         if (err < 0)
 155                 return err;
 156
 157         hdac_stream(stream)->prepared = 1;
 158
 159         return 0;
 160 }
 161
 162 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 163 {
 164         struct hdac_bus *bus = dev_get_drvdata(dev);
 165         unsigned int format_val;
 166         struct hdac_stream *hstream;
 167         struct hdac_ext_stream *stream;
 168         struct hdac_ext_link *link;
 169         unsigned char stream_tag;
 170         unsigned int bits;
 171
 172         hstream = snd_hdac_get_stream(bus, params->stream,
 173                                         params->link_dma_id + 1);
 174         if (!hstream)
 175                 return -EINVAL;
 176
 177         stream = stream_to_hdac_ext_stream(hstream);
 178         snd_hdac_ext_stream_decouple(bus, stream, true);
 179
 180         bits = snd_hdac_stream_format_bits(params->format, SNDRV_PCM_SUBFORMAT_STD,
 181                                            params->link_bps);
 182         format_val = snd_hdac_stream_format(params->ch, bits, params->s_freq);
 183
 184         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 185                 format_val, params->s_freq, params->ch, params->format);
 186
 187         snd_hdac_ext_stream_reset(stream);
 188
 189         snd_hdac_ext_stream_setup(stream, format_val);
 190
 191         stream_tag = hstream->stream_tag;
 192         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 193                 list_for_each_entry(link, &bus->hlink_list, list) {
 194                         if (link->index == params->link_index)
 195                                 snd_hdac_ext_bus_link_set_stream_id(link,
 196                                                                     stream_tag);
 197                 }
 198         }
 199
 200         stream->link_prepared = 1;
 201
 202         return 0;
 203 }
 204
 205 static int skl_pcm_open(struct snd_pcm_substream *substream,
 206                 struct snd_soc_dai *dai)
 207 {
 208         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 209         struct hdac_ext_stream *stream;
 210         struct snd_pcm_runtime *runtime = substream->runtime;
 211         struct skl_dma_params *dma_params;
 212         struct skl_dev *skl = get_skl_ctx(dai->dev);
 213         struct skl_module_cfg *mconfig;
 214
 215         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 216
 217         stream = snd_hdac_ext_stream_assign(bus, substream,
 218                                         skl_get_host_stream_type(bus));
 219         if (stream == NULL)
 220                 return -EBUSY;
 221
 222         skl_set_pcm_constrains(bus, runtime);
 223
 224         /*
 225          * disable WALLCLOCK timestamps for capture streams
 226          * until we figure out how to handle digital inputs
 227          */
 228         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 229                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 230                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 231         }
 232
 233         runtime->private_data = stream;
 234
 235         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 236         if (!dma_params)
 237                 return -ENOMEM;
 238
 239         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 240         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 241
 242         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 243                                  dma_params->stream_tag);
 244         skl_set_suspend_active(substream, dai, true);
 245         snd_pcm_set_sync(substream);
 246
 247         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 248         if (!mconfig) {
 249                 kfree(dma_params);
 250                 return -EINVAL;
 251         }
 252
 253         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 254
 255         return 0;
 256 }
 257
 258 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 259                 struct snd_soc_dai *dai)
 260 {
 261         struct skl_dev *skl = get_skl_ctx(dai->dev);
 262         struct skl_module_cfg *mconfig;
 263         int ret;
 264
 265         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 266
 267         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 268
 269         /*
 270          * In case of XRUN recovery or in the case when the application
 271          * calls prepare another time, reset the FW pipe to clean state
 272          */
 273         if (mconfig &&
 274                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 275                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 276                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 277
 278                 ret = skl_reset_pipe(skl, mconfig->pipe);
 279
 280                 if (ret < 0)
 281                         return ret;
 282
 283                 ret = skl_pcm_host_dma_prepare(dai->dev,
 284                                         mconfig->pipe->p_params);
 285                 if (ret < 0)
 286                         return ret;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 293                                 struct snd_pcm_hw_params *params,
 294                                 struct snd_soc_dai *dai)
 295 {
 296         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 297         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 298         struct snd_pcm_runtime *runtime = substream->runtime;
 299         struct skl_pipe_params p_params = {0};
 300         struct skl_module_cfg *m_cfg;
 301         int ret, dma_id;
 302
 303         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 304         ret = skl_substream_alloc_pages(bus, substream,
 305                                           params_buffer_bytes(params));
 306         if (ret < 0)
 307                 return ret;
 308
 309         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 310                         runtime->rate, runtime->channels, runtime->format);
 311
 312         dma_id = hdac_stream(stream)->stream_tag - 1;
 313         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 314
 315         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 316         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 317         p_params.ch = params_channels(params);
 318         p_params.s_freq = params_rate(params);
 319         p_params.host_dma_id = dma_id;
 320         p_params.stream = substream->stream;
 321         p_params.format = params_format(params);
 322         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 323                 p_params.host_bps = dai->driver->playback.sig_bits;
 324         else
 325                 p_params.host_bps = dai->driver->capture.sig_bits;
 326
 327
 328         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 329         if (m_cfg)
 330                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 331
 332         return 0;
 333 }
 334
 335 static void skl_pcm_close(struct snd_pcm_substream *substream,
 336                 struct snd_soc_dai *dai)
 337 {
 338         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 339         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 340         struct skl_dma_params *dma_params = NULL;
 341         struct skl_dev *skl = bus_to_skl(bus);
 342         struct skl_module_cfg *mconfig;
 343
 344         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 345
 346         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 347
 348         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 349         /*
 350          * now we should set this to NULL as we are freeing by the
 351          * dma_params
 352          */
 353         snd_soc_dai_set_dma_data(dai, substream, NULL);
 354         skl_set_suspend_active(substream, dai, false);
 355
 356         /*
 357          * check if close is for "Reference Pin" and set back the
 358          * CGCTL.MISCBDCGE if disabled by driver
 359          */
 360         if (!strncmp(dai->name, "Reference Pin", 13) &&
 361                         skl->miscbdcg_disabled) {
 362                 skl->enable_miscbdcge(dai->dev, true);
 363                 skl->miscbdcg_disabled = false;
 364         }
 365
 366         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 367         if (mconfig)
 368                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 369
 370         kfree(dma_params);
 371 }
 372
 373 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 374                 struct snd_soc_dai *dai)
 375 {
 376         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 377         struct skl_dev *skl = get_skl_ctx(dai->dev);
 378         struct skl_module_cfg *mconfig;
 379         int ret;
 380
 381         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 382
 383         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 384
 385         if (mconfig) {
 386                 ret = skl_reset_pipe(skl, mconfig->pipe);
 387                 if (ret < 0)
 388                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 389                                                 __func__, ret);
 390         }
 391
 392         snd_hdac_stream_cleanup(hdac_stream(stream));
 393         hdac_stream(stream)->prepared = 0;
 394
 395         return 0;
 396 }
 397
 398 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 399                                 struct snd_pcm_hw_params *params,
 400                                 struct snd_soc_dai *dai)
 401 {
 402         struct skl_pipe_params p_params = {0};
 403
 404         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 405         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 406         p_params.ch = params_channels(params);
 407         p_params.s_freq = params_rate(params);
 408         p_params.stream = substream->stream;
 409
 410         return skl_tplg_be_update_params(dai, &p_params);
 411 }
 412
 413 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 414                 int cmd)
 415 {
 416         struct hdac_bus *bus = get_bus_ctx(substream);
 417         struct hdac_ext_stream *stream;
 418         int start;
 419         unsigned long cookie;
 420         struct hdac_stream *hstr;
 421
 422         stream = get_hdac_ext_stream(substream);
 423         hstr = hdac_stream(stream);
 424
 425         if (!hstr->prepared)
 426                 return -EPIPE;
 427
 428         switch (cmd) {
 429         case SNDRV_PCM_TRIGGER_START:
 430         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 431         case SNDRV_PCM_TRIGGER_RESUME:
 432                 start = 1;
 433                 break;
 434
 435         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 436         case SNDRV_PCM_TRIGGER_SUSPEND:
 437         case SNDRV_PCM_TRIGGER_STOP:
 438                 start = 0;
 439                 break;
 440
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         spin_lock_irqsave(&bus->reg_lock, cookie);
 446
 447         if (start) {
 448                 snd_hdac_stream_start(hdac_stream(stream));
 449                 snd_hdac_stream_timecounter_init(hstr, 0);
 450         } else {
 451                 snd_hdac_stream_stop(hdac_stream(stream));
 452         }
 453
 454         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 455
 456         return 0;
 457 }
 458
 459 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 460                 struct snd_soc_dai *dai)
 461 {
 462         struct skl_dev *skl = get_skl_ctx(dai->dev);
 463         struct skl_module_cfg *mconfig;
 464         struct hdac_bus *bus = get_bus_ctx(substream);
 465         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 466         struct hdac_stream *hstream = hdac_stream(stream);
 467         struct snd_soc_dapm_widget *w;
 468         int ret;
 469
 470         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 471         if (!mconfig)
 472                 return -EIO;
 473
 474         w = snd_soc_dai_get_widget(dai, substream->stream);
 475
 476         switch (cmd) {
 477         case SNDRV_PCM_TRIGGER_RESUME:
 478                 if (!w->ignore_suspend) {
 479                         /*
 480                          * enable DMA Resume enable bit for the stream, set the
 481                          * dpib & lpib position to resume before starting the
 482                          * DMA
 483                          */
 484                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 485                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 486                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 487                 }
 488                 fallthrough;
 489
 490         case SNDRV_PCM_TRIGGER_START:
 491         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 492                 /*
 493                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 494                  * there are no underrun/overrun in the case when the FE
 495                  * pipeline is started but there is a delay in starting the
 496                  * DMA channel on the host.
 497                  */
 498                 ret = skl_decoupled_trigger(substream, cmd);
 499                 if (ret < 0)
 500                         return ret;
 501                 return skl_run_pipe(skl, mconfig->pipe);
 502
 503         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 504         case SNDRV_PCM_TRIGGER_SUSPEND:
 505         case SNDRV_PCM_TRIGGER_STOP:
 506                 /*
 507                  * Stop FE Pipe first and stop DMA. This is to make sure that
 508                  * there are no underrun/overrun in the case if there is a delay
 509                  * between the two operations.
 510                  */
 511                 ret = skl_stop_pipe(skl, mconfig->pipe);
 512                 if (ret < 0)
 513                         return ret;
 514
 515                 ret = skl_decoupled_trigger(substream, cmd);
 516                 if (ret < 0)
 517                         return ret;
 518
 519                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 520                         /* save the dpib and lpib positions */
 521                         hstream->dpib = readl(bus->remap_addr +
 522                                         AZX_REG_VS_SDXDPIB_XBASE +
 523                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 524                                         hstream->index));
 525
 526                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 527
 528                         snd_hdac_ext_stream_decouple(bus, stream, false);
 529                 }
 530                 break;
 531
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         return 0;
 537 }
 538
 539
 540 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 541                                 struct snd_pcm_hw_params *params,
 542                                 struct snd_soc_dai *dai)
 543 {
 544         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 545         struct hdac_ext_stream *link_dev;
 546         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 547         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
 548         struct skl_pipe_params p_params = {0};
 549         struct hdac_ext_link *link;
 550         int stream_tag;
 551
 552         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 553                                         HDAC_EXT_STREAM_TYPE_LINK);
 554         if (!link_dev)
 555                 return -EBUSY;
 556
 557         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 558
 559         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 560         if (!link)
 561                 return -EINVAL;
 562
 563         stream_tag = hdac_stream(link_dev)->stream_tag;
 564
 565         /* set the hdac_stream in the codec dai */
 566         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 567
 568         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 569         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 570         p_params.ch = params_channels(params);
 571         p_params.s_freq = params_rate(params);
 572         p_params.stream = substream->stream;
 573         p_params.link_dma_id = stream_tag - 1;
 574         p_params.link_index = link->index;
 575         p_params.format = params_format(params);
 576
 577         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 578                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 579         else
 580                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 581
 582         return skl_tplg_be_update_params(dai, &p_params);
 583 }
 584
 585 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 586                 struct snd_soc_dai *dai)
 587 {
 588         struct skl_dev *skl = get_skl_ctx(dai->dev);
 589         struct skl_module_cfg *mconfig = NULL;
 590
 591         /* In case of XRUN recovery, reset the FW pipe to clean state */
 592         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 593         if (mconfig && !mconfig->pipe->passthru &&
 594                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 595                 skl_reset_pipe(skl, mconfig->pipe);
 596
 597         return 0;
 598 }
 599
 600 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 601         int cmd, struct snd_soc_dai *dai)
 602 {
 603         struct hdac_ext_stream *link_dev =
 604                                 snd_soc_dai_get_dma_data(dai, substream);
 605         struct hdac_bus *bus = get_bus_ctx(substream);
 606         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 607
 608         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 609         switch (cmd) {
 610         case SNDRV_PCM_TRIGGER_RESUME:
 611         case SNDRV_PCM_TRIGGER_START:
 612         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 613                 snd_hdac_ext_stream_start(link_dev);
 614                 break;
 615
 616         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 617         case SNDRV_PCM_TRIGGER_SUSPEND:
 618         case SNDRV_PCM_TRIGGER_STOP:
 619                 snd_hdac_ext_stream_clear(link_dev);
 620                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 621                         snd_hdac_ext_stream_decouple(bus, stream, false);
 622                 break;
 623
 624         default:
 625                 return -EINVAL;
 626         }
 627         return 0;
 628 }
 629
 630 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 631                 struct snd_soc_dai *dai)
 632 {
 633         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 634         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 635         struct hdac_ext_stream *link_dev =
 636                                 snd_soc_dai_get_dma_data(dai, substream);
 637         struct hdac_ext_link *link;
 638         unsigned char stream_tag;
 639
 640         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 641
 642         link_dev->link_prepared = 0;
 643
 644         link = snd_hdac_ext_bus_get_hlink_by_name(bus, snd_soc_rtd_to_codec(rtd, 0)->component->name);
 645         if (!link)
 646                 return -EINVAL;
 647
 648         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 649                 stream_tag = hdac_stream(link_dev)->stream_tag;
 650                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 651         }
 652
 653         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 654         return 0;
 655 }
 656
 657 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 658         .startup = skl_pcm_open,
 659         .shutdown = skl_pcm_close,
 660         .prepare = skl_pcm_prepare,
 661         .hw_params = skl_pcm_hw_params,
 662         .hw_free = skl_pcm_hw_free,
 663         .trigger = skl_pcm_trigger,
 664 };
 665
 666 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 667         .hw_params = skl_be_hw_params,
 668 };
 669
 670 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 671         .hw_params = skl_be_hw_params,
 672 };
 673
 674 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 675         .prepare = skl_link_pcm_prepare,
 676         .hw_params = skl_link_hw_params,
 677         .hw_free = skl_link_hw_free,
 678         .trigger = skl_link_pcm_trigger,
 679 };
 680
 681 static struct snd_soc_dai_driver skl_fe_dai[] = {
 682 {
 683         .name = "System Pin",
 684         .ops = &skl_pcm_dai_ops,
 685         .playback = {
 686                 .stream_name = "System Playback",
 687                 .channels_min = HDA_MONO,
 688                 .channels_max = HDA_STEREO,
 689                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 690                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 691                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 692                 .sig_bits = 32,
 693         },
 694         .capture = {
 695                 .stream_name = "System Capture",
 696                 .channels_min = HDA_MONO,
 697                 .channels_max = HDA_STEREO,
 698                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 699                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 700                 .sig_bits = 32,
 701         },
 702 },
 703 {
 704         .name = "System Pin2",
 705         .ops = &skl_pcm_dai_ops,
 706         .playback = {
 707                 .stream_name = "Headset Playback",
 708                 .channels_min = HDA_MONO,
 709                 .channels_max = HDA_STEREO,
 710                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 711                         SNDRV_PCM_RATE_8000,
 712                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 713                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 714         },
 715 },
 716 {
 717         .name = "Echoref Pin",
 718         .ops = &skl_pcm_dai_ops,
 719         .capture = {
 720                 .stream_name = "Echoreference Capture",
 721                 .channels_min = HDA_STEREO,
 722                 .channels_max = HDA_STEREO,
 723                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 724                         SNDRV_PCM_RATE_8000,
 725                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 726                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 727         },
 728 },
 729 {
 730         .name = "Reference Pin",
 731         .ops = &skl_pcm_dai_ops,
 732         .capture = {
 733                 .stream_name = "Reference Capture",
 734                 .channels_min = HDA_MONO,
 735                 .channels_max = HDA_QUAD,
 736                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 737                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 738                 .sig_bits = 32,
 739         },
 740 },
 741 {
 742         .name = "Deepbuffer Pin",
 743         .ops = &skl_pcm_dai_ops,
 744         .playback = {
 745                 .stream_name = "Deepbuffer Playback",
 746                 .channels_min = HDA_STEREO,
 747                 .channels_max = HDA_STEREO,
 748                 .rates = SNDRV_PCM_RATE_48000,
 749                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 750                 .sig_bits = 32,
 751         },
 752 },
 753 {
 754         .name = "LowLatency Pin",
 755         .ops = &skl_pcm_dai_ops,
 756         .playback = {
 757                 .stream_name = "Low Latency Playback",
 758                 .channels_min = HDA_STEREO,
 759                 .channels_max = HDA_STEREO,
 760                 .rates = SNDRV_PCM_RATE_48000,
 761                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 762                 .sig_bits = 32,
 763         },
 764 },
 765 {
 766         .name = "DMIC Pin",
 767         .ops = &skl_pcm_dai_ops,
 768         .capture = {
 769                 .stream_name = "DMIC Capture",
 770                 .channels_min = HDA_MONO,
 771                 .channels_max = HDA_QUAD,
 772                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 773                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 774                 .sig_bits = 32,
 775         },
 776 },
 777 {
 778         .name = "HDMI1 Pin",
 779         .ops = &skl_pcm_dai_ops,
 780         .playback = {
 781                 .stream_name = "HDMI1 Playback",
 782                 .channels_min = HDA_STEREO,
 783                 .channels_max = 8,
 784                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 785                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 786                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 787                         SNDRV_PCM_RATE_192000,
 788                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 789                         SNDRV_PCM_FMTBIT_S32_LE,
 790                 .sig_bits = 32,
 791         },
 792 },
 793 {
 794         .name = "HDMI2 Pin",
 795         .ops = &skl_pcm_dai_ops,
 796         .playback = {
 797                 .stream_name = "HDMI2 Playback",
 798                 .channels_min = HDA_STEREO,
 799                 .channels_max = 8,
 800                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 801                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 802                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 803                         SNDRV_PCM_RATE_192000,
 804                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 805                         SNDRV_PCM_FMTBIT_S32_LE,
 806                 .sig_bits = 32,
 807         },
 808 },
 809 {
 810         .name = "HDMI3 Pin",
 811         .ops = &skl_pcm_dai_ops,
 812         .playback = {
 813                 .stream_name = "HDMI3 Playback",
 814                 .channels_min = HDA_STEREO,
 815                 .channels_max = 8,
 816                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 817                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 818                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 819                         SNDRV_PCM_RATE_192000,
 820                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 821                         SNDRV_PCM_FMTBIT_S32_LE,
 822                 .sig_bits = 32,
 823         },
 824 },
 825 };
 826
 827 /* BE CPU  Dais */
 828 static struct snd_soc_dai_driver skl_platform_dai[] = {
 829 {
 830         .name = "SSP0 Pin",
 831         .ops = &skl_be_ssp_dai_ops,
 832         .playback = {
 833                 .stream_name = "ssp0 Tx",
 834                 .channels_min = HDA_STEREO,
 835                 .channels_max = HDA_STEREO,
 836                 .rates = SNDRV_PCM_RATE_48000,
 837                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 838         },
 839         .capture = {
 840                 .stream_name = "ssp0 Rx",
 841                 .channels_min = HDA_STEREO,
 842                 .channels_max = HDA_STEREO,
 843                 .rates = SNDRV_PCM_RATE_48000,
 844                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 845         },
 846 },
 847 {
 848         .name = "SSP1 Pin",
 849         .ops = &skl_be_ssp_dai_ops,
 850         .playback = {
 851                 .stream_name = "ssp1 Tx",
 852                 .channels_min = HDA_STEREO,
 853                 .channels_max = HDA_STEREO,
 854                 .rates = SNDRV_PCM_RATE_48000,
 855                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 856         },
 857         .capture = {
 858                 .stream_name = "ssp1 Rx",
 859                 .channels_min = HDA_STEREO,
 860                 .channels_max = HDA_STEREO,
 861                 .rates = SNDRV_PCM_RATE_48000,
 862                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 863         },
 864 },
 865 {
 866         .name = "SSP2 Pin",
 867         .ops = &skl_be_ssp_dai_ops,
 868         .playback = {
 869                 .stream_name = "ssp2 Tx",
 870                 .channels_min = HDA_STEREO,
 871                 .channels_max = HDA_STEREO,
 872                 .rates = SNDRV_PCM_RATE_48000,
 873                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 874         },
 875         .capture = {
 876                 .stream_name = "ssp2 Rx",
 877                 .channels_min = HDA_STEREO,
 878                 .channels_max = HDA_STEREO,
 879                 .rates = SNDRV_PCM_RATE_48000,
 880                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 881         },
 882 },
 883 {
 884         .name = "SSP3 Pin",
 885         .ops = &skl_be_ssp_dai_ops,
 886         .playback = {
 887                 .stream_name = "ssp3 Tx",
 888                 .channels_min = HDA_STEREO,
 889                 .channels_max = HDA_STEREO,
 890                 .rates = SNDRV_PCM_RATE_48000,
 891                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 892         },
 893         .capture = {
 894                 .stream_name = "ssp3 Rx",
 895                 .channels_min = HDA_STEREO,
 896                 .channels_max = HDA_STEREO,
 897                 .rates = SNDRV_PCM_RATE_48000,
 898                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 899         },
 900 },
 901 {
 902         .name = "SSP4 Pin",
 903         .ops = &skl_be_ssp_dai_ops,
 904         .playback = {
 905                 .stream_name = "ssp4 Tx",
 906                 .channels_min = HDA_STEREO,
 907                 .channels_max = HDA_STEREO,
 908                 .rates = SNDRV_PCM_RATE_48000,
 909                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 910         },
 911         .capture = {
 912                 .stream_name = "ssp4 Rx",
 913                 .channels_min = HDA_STEREO,
 914                 .channels_max = HDA_STEREO,
 915                 .rates = SNDRV_PCM_RATE_48000,
 916                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 917         },
 918 },
 919 {
 920         .name = "SSP5 Pin",
 921         .ops = &skl_be_ssp_dai_ops,
 922         .playback = {
 923                 .stream_name = "ssp5 Tx",
 924                 .channels_min = HDA_STEREO,
 925                 .channels_max = HDA_STEREO,
 926                 .rates = SNDRV_PCM_RATE_48000,
 927                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 928         },
 929         .capture = {
 930                 .stream_name = "ssp5 Rx",
 931                 .channels_min = HDA_STEREO,
 932                 .channels_max = HDA_STEREO,
 933                 .rates = SNDRV_PCM_RATE_48000,
 934                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 935         },
 936 },
 937 {
 938         .name = "iDisp1 Pin",
 939         .ops = &skl_link_dai_ops,
 940         .playback = {
 941                 .stream_name = "iDisp1 Tx",
 942                 .channels_min = HDA_STEREO,
 943                 .channels_max = 8,
 944                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 945                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 946                         SNDRV_PCM_FMTBIT_S24_LE,
 947         },
 948 },
 949 {
 950         .name = "iDisp2 Pin",
 951         .ops = &skl_link_dai_ops,
 952         .playback = {
 953                 .stream_name = "iDisp2 Tx",
 954                 .channels_min = HDA_STEREO,
 955                 .channels_max = 8,
 956                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 957                         SNDRV_PCM_RATE_48000,
 958                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 959                         SNDRV_PCM_FMTBIT_S24_LE,
 960         },
 961 },
 962 {
 963         .name = "iDisp3 Pin",
 964         .ops = &skl_link_dai_ops,
 965         .playback = {
 966                 .stream_name = "iDisp3 Tx",
 967                 .channels_min = HDA_STEREO,
 968                 .channels_max = 8,
 969                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 970                         SNDRV_PCM_RATE_48000,
 971                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 972                         SNDRV_PCM_FMTBIT_S24_LE,
 973         },
 974 },
 975 {
 976         .name = "DMIC01 Pin",
 977         .ops = &skl_dmic_dai_ops,
 978         .capture = {
 979                 .stream_name = "DMIC01 Rx",
 980                 .channels_min = HDA_MONO,
 981                 .channels_max = HDA_QUAD,
 982                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 983                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 984         },
 985 },
 986 {
 987         .name = "DMIC16k Pin",
 988         .ops = &skl_dmic_dai_ops,
 989         .capture = {
 990                 .stream_name = "DMIC16k Rx",
 991                 .channels_min = HDA_MONO,
 992                 .channels_max = HDA_QUAD,
 993                 .rates = SNDRV_PCM_RATE_16000,
 994                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 995         },
 996 },
 997 {
 998         .name = "Analog CPU DAI",
 999         .ops = &skl_link_dai_ops,
1000         .playback = {
1001                 .stream_name = "Analog CPU Playback",
1002                 .channels_min = HDA_MONO,
1003                 .channels_max = HDA_MAX,
1004                 .rates = SNDRV_PCM_RATE_8000_192000,
1005                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1006                         SNDRV_PCM_FMTBIT_S32_LE,
1007         },
1008         .capture = {
1009                 .stream_name = "Analog CPU Capture",
1010                 .channels_min = HDA_MONO,
1011                 .channels_max = HDA_MAX,
1012                 .rates = SNDRV_PCM_RATE_8000_192000,
1013                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1014                         SNDRV_PCM_FMTBIT_S32_LE,
1015         },
1016 },
1017 {
1018         .name = "Alt Analog CPU DAI",
1019         .ops = &skl_link_dai_ops,
1020         .playback = {
1021                 .stream_name = "Alt Analog CPU Playback",
1022                 .channels_min = HDA_MONO,
1023                 .channels_max = HDA_MAX,
1024                 .rates = SNDRV_PCM_RATE_8000_192000,
1025                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1026                         SNDRV_PCM_FMTBIT_S32_LE,
1027         },
1028         .capture = {
1029                 .stream_name = "Alt Analog CPU Capture",
1030                 .channels_min = HDA_MONO,
1031                 .channels_max = HDA_MAX,
1032                 .rates = SNDRV_PCM_RATE_8000_192000,
1033                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1034                         SNDRV_PCM_FMTBIT_S32_LE,
1035         },
1036 },
1037 {
1038         .name = "Digital CPU DAI",
1039         .ops = &skl_link_dai_ops,
1040         .playback = {
1041                 .stream_name = "Digital CPU Playback",
1042                 .channels_min = HDA_MONO,
1043                 .channels_max = HDA_MAX,
1044                 .rates = SNDRV_PCM_RATE_8000_192000,
1045                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1046                         SNDRV_PCM_FMTBIT_S32_LE,
1047         },
1048         .capture = {
1049                 .stream_name = "Digital CPU Capture",
1050                 .channels_min = HDA_MONO,
1051                 .channels_max = HDA_MAX,
1052                 .rates = SNDRV_PCM_RATE_8000_192000,
1053                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1054                         SNDRV_PCM_FMTBIT_S32_LE,
1055         },
1056 },
1057 };
1058
1059 int skl_dai_load(struct snd_soc_component *cmp, int index,
1060                         struct snd_soc_dai_driver *dai_drv,
1061                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1062 {
1063         dai_drv->ops = &skl_pcm_dai_ops;
1064
1065         return 0;
1066 }
1067
1068 static int skl_platform_soc_open(struct snd_soc_component *component,
1069                                  struct snd_pcm_substream *substream)
1070 {
1071         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1072         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1073
1074         dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1075                                         dai_link->cpus->dai_name);
1076
1077         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1078
1079         return 0;
1080 }
1081
1082 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1083                                         int cmd)
1084 {
1085         struct hdac_bus *bus = get_bus_ctx(substream);
1086         struct hdac_ext_stream *stream;
1087         struct snd_pcm_substream *s;
1088         bool start;
1089         int sbits = 0;
1090         unsigned long cookie;
1091         struct hdac_stream *hstr;
1092
1093         stream = get_hdac_ext_stream(substream);
1094         hstr = hdac_stream(stream);
1095
1096         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1097
1098         if (!hstr->prepared)
1099                 return -EPIPE;
1100
1101         switch (cmd) {
1102         case SNDRV_PCM_TRIGGER_START:
1103         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1104         case SNDRV_PCM_TRIGGER_RESUME:
1105                 start = true;
1106                 break;
1107
1108         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1109         case SNDRV_PCM_TRIGGER_SUSPEND:
1110         case SNDRV_PCM_TRIGGER_STOP:
1111                 start = false;
1112                 break;
1113
1114         default:
1115                 return -EINVAL;
1116         }
1117
1118         snd_pcm_group_for_each_entry(s, substream) {
1119                 if (s->pcm->card != substream->pcm->card)
1120                         continue;
1121                 stream = get_hdac_ext_stream(s);
1122                 sbits |= 1 << hdac_stream(stream)->index;
1123                 snd_pcm_trigger_done(s, substream);
1124         }
1125
1126         spin_lock_irqsave(&bus->reg_lock, cookie);
1127
1128         /* first, set SYNC bits of corresponding streams */
1129         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1130
1131         snd_pcm_group_for_each_entry(s, substream) {
1132                 if (s->pcm->card != substream->pcm->card)
1133                         continue;
1134                 stream = get_hdac_ext_stream(s);
1135                 if (start)
1136                         snd_hdac_stream_start(hdac_stream(stream));
1137                 else
1138                         snd_hdac_stream_stop(hdac_stream(stream));
1139         }
1140         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1141
1142         snd_hdac_stream_sync(hstr, start, sbits);
1143
1144         spin_lock_irqsave(&bus->reg_lock, cookie);
1145
1146         /* reset SYNC bits */
1147         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1148         if (start)
1149                 snd_hdac_stream_timecounter_init(hstr, sbits);
1150         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1151
1152         return 0;
1153 }
1154
1155 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1156                                     struct snd_pcm_substream *substream,
1157                                     int cmd)
1158 {
1159         struct hdac_bus *bus = get_bus_ctx(substream);
1160
1161         if (!bus->ppcap)
1162                 return skl_coupled_trigger(substream, cmd);
1163
1164         return 0;
1165 }
1166
1167 static snd_pcm_uframes_t skl_platform_soc_pointer(
1168         struct snd_soc_component *component,
1169         struct snd_pcm_substream *substream)
1170 {
1171         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1172         struct hdac_bus *bus = get_bus_ctx(substream);
1173         unsigned int pos;
1174
1175         /*
1176          * Use DPIB for Playback stream as the periodic DMA Position-in-
1177          * Buffer Writes may be scheduled at the same time or later than
1178          * the MSI and does not guarantee to reflect the Position of the
1179          * last buffer that was transferred. Whereas DPIB register in
1180          * HAD space reflects the actual data that is transferred.
1181          * Use the position buffer for capture, as DPIB write gets
1182          * completed earlier than the actual data written to the DDR.
1183          *
1184          * For capture stream following workaround is required to fix the
1185          * incorrect position reporting.
1186          *
1187          * 1. Wait for 20us before reading the DMA position in buffer once
1188          * the interrupt is generated for stream completion as update happens
1189          * on the HDA frame boundary i.e. 20.833uSec.
1190          * 2. Read DPIB register to flush the DMA position value. This dummy
1191          * read is required to flush DMA position value.
1192          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1193          * or greater than period boundary.
1194          */
1195
1196         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1197                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1198                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1199                                 hdac_stream(hstream)->index));
1200         } else {
1201                 udelay(20);
1202                 readl(bus->remap_addr +
1203                                 AZX_REG_VS_SDXDPIB_XBASE +
1204                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1205                                  hdac_stream(hstream)->index));
1206                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1207         }
1208
1209         if (pos >= hdac_stream(hstream)->bufsize)
1210                 pos = 0;
1211
1212         return bytes_to_frames(substream->runtime, pos);
1213 }
1214
1215 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1216                                 u64 nsec)
1217 {
1218         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1219         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
1220         u64 codec_frames, codec_nsecs;
1221
1222         if (!codec_dai->driver->ops->delay)
1223                 return nsec;
1224
1225         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1226         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1227                               substream->runtime->rate);
1228
1229         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1230                 return nsec + codec_nsecs;
1231
1232         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1233 }
1234
1235 static int skl_platform_soc_get_time_info(
1236                         struct snd_soc_component *component,
1237                         struct snd_pcm_substream *substream,
1238                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1239                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1240                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1241 {
1242         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1243         struct hdac_stream *hstr = hdac_stream(sstream);
1244         u64 nsec;
1245
1246         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1247                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1248
1249                 snd_pcm_gettime(substream->runtime, system_ts);
1250
1251                 nsec = timecounter_read(&hstr->tc);
1252                 if (audio_tstamp_config->report_delay)
1253                         nsec = skl_adjust_codec_delay(substream, nsec);
1254
1255                 *audio_ts = ns_to_timespec64(nsec);
1256
1257                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1258                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1259                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1260
1261         } else {
1262                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1263         }
1264
1265         return 0;
1266 }
1267
1268 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1269
1270 static int skl_platform_soc_new(struct snd_soc_component *component,
1271                                 struct snd_soc_pcm_runtime *rtd)
1272 {
1273         struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1274         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1275         struct snd_pcm *pcm = rtd->pcm;
1276         unsigned int size;
1277         struct skl_dev *skl = bus_to_skl(bus);
1278
1279         if (dai->driver->playback.channels_min ||
1280                 dai->driver->capture.channels_min) {
1281                 /* buffer pre-allocation */
1282                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1283                 if (size > MAX_PREALLOC_SIZE)
1284                         size = MAX_PREALLOC_SIZE;
1285                 snd_pcm_set_managed_buffer_all(pcm,
1286                                                SNDRV_DMA_TYPE_DEV_SG,
1287                                                &skl->pci->dev,
1288                                                size, MAX_PREALLOC_SIZE);
1289         }
1290
1291         return 0;
1292 }
1293
1294 static int skl_get_module_info(struct skl_dev *skl,
1295                 struct skl_module_cfg *mconfig)
1296 {
1297         struct skl_module_inst_id *pin_id;
1298         guid_t *uuid_mod, *uuid_tplg;
1299         struct skl_module *skl_module;
1300         struct uuid_module *module;
1301         int i, ret = -EIO;
1302
1303         uuid_mod = (guid_t *)mconfig->guid;
1304
1305         if (list_empty(&skl->uuid_list)) {
1306                 dev_err(skl->dev, "Module list is empty\n");
1307                 return -EIO;
1308         }
1309
1310         for (i = 0; i < skl->nr_modules; i++) {
1311                 skl_module = skl->modules[i];
1312                 uuid_tplg = &skl_module->uuid;
1313                 if (guid_equal(uuid_mod, uuid_tplg)) {
1314                         mconfig->module = skl_module;
1315                         ret = 0;
1316                         break;
1317                 }
1318         }
1319
1320         if (skl->nr_modules && ret)
1321                 return ret;
1322
1323         ret = -EIO;
1324         list_for_each_entry(module, &skl->uuid_list, list) {
1325                 if (guid_equal(uuid_mod, &module->uuid)) {
1326                         mconfig->id.module_id = module->id;
1327                         mconfig->module->loadable = module->is_loadable;
1328                         ret = 0;
1329                 }
1330
1331                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1332                         pin_id = &mconfig->m_in_pin[i].id;
1333                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1334                                 pin_id->module_id = module->id;
1335                 }
1336
1337                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1338                         pin_id = &mconfig->m_out_pin[i].id;
1339                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1340                                 pin_id->module_id = module->id;
1341                 }
1342         }
1343
1344         return ret;
1345 }
1346
1347 static int skl_populate_modules(struct skl_dev *skl)
1348 {
1349         struct skl_pipeline *p;
1350         struct skl_pipe_module *m;
1351         struct snd_soc_dapm_widget *w;
1352         struct skl_module_cfg *mconfig;
1353         int ret = 0;
1354
1355         list_for_each_entry(p, &skl->ppl_list, node) {
1356                 list_for_each_entry(m, &p->pipe->w_list, node) {
1357                         w = m->w;
1358                         mconfig = w->priv;
1359
1360                         ret = skl_get_module_info(skl, mconfig);
1361                         if (ret < 0) {
1362                                 dev_err(skl->dev,
1363                                         "query module info failed\n");
1364                                 return ret;
1365                         }
1366
1367                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1368                 }
1369         }
1370
1371         return ret;
1372 }
1373
1374 static int skl_platform_soc_probe(struct snd_soc_component *component)
1375 {
1376         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1377         struct skl_dev *skl = bus_to_skl(bus);
1378         const struct skl_dsp_ops *ops;
1379         int ret;
1380
1381         ret = pm_runtime_resume_and_get(component->dev);
1382         if (ret < 0 && ret != -EACCES)
1383                 return ret;
1384
1385         if (bus->ppcap) {
1386                 skl->component = component;
1387
1388                 /* init debugfs */
1389                 skl->debugfs = skl_debugfs_init(skl);
1390
1391                 ret = skl_tplg_init(component, bus);
1392                 if (ret < 0) {
1393                         dev_err(component->dev, "Failed to init topology!\n");
1394                         return ret;
1395                 }
1396
1397                 /* load the firmwares, since all is set */
1398                 ops = skl_get_dsp_ops(skl->pci->device);
1399                 if (!ops)
1400                         return -EIO;
1401
1402                 /*
1403                  * Disable dynamic clock and power gating during firmware
1404                  * and library download
1405                  */
1406                 skl->enable_miscbdcge(component->dev, false);
1407                 skl->clock_power_gating(component->dev, false);
1408
1409                 ret = ops->init_fw(component->dev, skl);
1410                 skl->enable_miscbdcge(component->dev, true);
1411                 skl->clock_power_gating(component->dev, true);
1412                 if (ret < 0) {
1413                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1414                         return ret;
1415                 }
1416                 skl_populate_modules(skl);
1417                 skl->update_d0i3c = skl_update_d0i3c;
1418
1419                 if (skl->cfg.astate_cfg != NULL) {
1420                         skl_dsp_set_astate_cfg(skl,
1421                                         skl->cfg.astate_cfg->count,
1422                                         skl->cfg.astate_cfg);
1423                 }
1424         }
1425         pm_runtime_mark_last_busy(component->dev);
1426         pm_runtime_put_autosuspend(component->dev);
1427
1428         return 0;
1429 }
1430
1431 static void skl_platform_soc_remove(struct snd_soc_component *component)
1432 {
1433         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1434         struct skl_dev *skl = bus_to_skl(bus);
1435
1436         skl_tplg_exit(component, bus);
1437
1438         skl_debugfs_exit(skl);
1439 }
1440
1441 static const struct snd_soc_component_driver skl_component  = {
1442         .name           = "pcm",
1443         .probe          = skl_platform_soc_probe,
1444         .remove         = skl_platform_soc_remove,
1445         .open           = skl_platform_soc_open,
1446         .trigger        = skl_platform_soc_trigger,
1447         .pointer        = skl_platform_soc_pointer,
1448         .get_time_info  = skl_platform_soc_get_time_info,
1449         .pcm_construct  = skl_platform_soc_new,
1450         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1451 };
1452
1453 int skl_platform_register(struct device *dev)
1454 {
1455         int ret;
1456         struct snd_soc_dai_driver *dais;
1457         int num_dais = ARRAY_SIZE(skl_platform_dai);
1458         struct hdac_bus *bus = dev_get_drvdata(dev);
1459         struct skl_dev *skl = bus_to_skl(bus);
1460
1461         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1462                             GFP_KERNEL);
1463         if (!skl->dais) {
1464                 ret = -ENOMEM;
1465                 goto err;
1466         }
1467
1468         if (!skl->use_tplg_pcm) {
1469                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1470                                 sizeof(skl_platform_dai), GFP_KERNEL);
1471                 if (!dais) {
1472                         kfree(skl->dais);
1473                         ret = -ENOMEM;
1474                         goto err;
1475                 }
1476
1477                 skl->dais = dais;
1478                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1479                        sizeof(skl_fe_dai));
1480                 num_dais += ARRAY_SIZE(skl_fe_dai);
1481         }
1482
1483         ret = devm_snd_soc_register_component(dev, &skl_component,
1484                                          skl->dais, num_dais);
1485         if (ret) {
1486                 kfree(skl->dais);
1487                 dev_err(dev, "soc component registration failed %d\n", ret);
1488         }
1489 err:
1490         return ret;
1491 }
1492
1493 int skl_platform_unregister(struct device *dev)
1494 {
1495         struct hdac_bus *bus = dev_get_drvdata(dev);
1496         struct skl_dev *skl = bus_to_skl(bus);
1497         struct skl_module_deferred_bind *modules, *tmp;
1498
1499         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1500                 list_del(&modules->node);
1501                 kfree(modules);
1502         }
1503
1504         kfree(skl->dais);
1505
1506         return 0;
1507 }