sound/soc/intel/skylake/skl-pcm.c

   1 /*
   2  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   3  *
   4  *  Copyright (C) 2014-2015 Intel Corp
   5  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   6  *
   7  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; version 2 of the License.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but
  14  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  *  General Public License for more details.
  17  *
  18  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  19  *
  20  */
  21
  22 #include <linux/pci.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/delay.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include "skl.h"
  28 #include "skl-topology.h"
  29 #include "skl-sst-dsp.h"
  30 #include "skl-sst-ipc.h"
  31
  32 #define HDA_MONO 1
  33 #define HDA_STEREO 2
  34 #define HDA_QUAD 4
  35
  36 static const struct snd_pcm_hardware azx_pcm_hw = {
  37         .info =                 (SNDRV_PCM_INFO_MMAP |
  38                                  SNDRV_PCM_INFO_INTERLEAVED |
  39                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  40                                  SNDRV_PCM_INFO_MMAP_VALID |
  41                                  SNDRV_PCM_INFO_PAUSE |
  42                                  SNDRV_PCM_INFO_RESUME |
  43                                  SNDRV_PCM_INFO_SYNC_START |
  44                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  45                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  46                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  47         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  48                                 SNDRV_PCM_FMTBIT_S32_LE |
  49                                 SNDRV_PCM_FMTBIT_S24_LE,
  50         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  51                                 SNDRV_PCM_RATE_8000,
  52         .rate_min =             8000,
  53         .rate_max =             48000,
  54         .channels_min =         1,
  55         .channels_max =         8,
  56         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  57         .period_bytes_min =     128,
  58         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  59         .periods_min =          2,
  60         .periods_max =          AZX_MAX_FRAG,
  61         .fifo_size =            0,
  62 };
  63
  64 static inline
  65 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  66 {
  67         return substream->runtime->private_data;
  68 }
  69
  70 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  71 {
  72         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  73         struct hdac_stream *hstream = hdac_stream(stream);
  74         struct hdac_bus *bus = hstream->bus;
  75
  76         return hbus_to_ebus(bus);
  77 }
  78
  79 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
  80                                  struct snd_pcm_substream *substream,
  81                                  size_t size)
  82 {
  83         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  84
  85         hdac_stream(stream)->bufsize = 0;
  86         hdac_stream(stream)->period_bytes = 0;
  87         hdac_stream(stream)->format_val = 0;
  88
  89         return snd_pcm_lib_malloc_pages(substream, size);
  90 }
  91
  92 static int skl_substream_free_pages(struct hdac_bus *bus,
  93                                 struct snd_pcm_substream *substream)
  94 {
  95         return snd_pcm_lib_free_pages(substream);
  96 }
  97
  98 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
  99                                  struct snd_pcm_runtime *runtime)
 100 {
 101         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 102
 103         /* avoid wrap-around with wall-clock */
 104         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 105                                      20, 178000000);
 106 }
 107
 108 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
 109 {
 110         if ((ebus_to_hbus(ebus))->ppcap)
 111                 return HDAC_EXT_STREAM_TYPE_HOST;
 112         else
 113                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 114 }
 115
 116 /*
 117  * check if the stream opened is marked as ignore_suspend by machine, if so
 118  * then enable suspend_active refcount
 119  *
 120  * The count supend_active does not need lock as it is used in open/close
 121  * and suspend context
 122  */
 123 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 124                                          struct snd_soc_dai *dai, bool enable)
 125 {
 126         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 127         struct snd_soc_dapm_widget *w;
 128         struct skl *skl = ebus_to_skl(ebus);
 129
 130         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 131                 w = dai->playback_widget;
 132         else
 133                 w = dai->capture_widget;
 134
 135         if (w->ignore_suspend && enable)
 136                 skl->supend_active++;
 137         else if (w->ignore_suspend && !enable)
 138                 skl->supend_active--;
 139 }
 140
 141 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 142 {
 143         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
 144         struct hdac_bus *bus = ebus_to_hbus(ebus);
 145         unsigned int format_val;
 146         struct hdac_stream *hstream;
 147         struct hdac_ext_stream *stream;
 148         int err;
 149
 150         hstream = snd_hdac_get_stream(bus, params->stream,
 151                                         params->host_dma_id + 1);
 152         if (!hstream)
 153                 return -EINVAL;
 154
 155         stream = stream_to_hdac_ext_stream(hstream);
 156         snd_hdac_ext_stream_decouple(ebus, stream, true);
 157
 158         format_val = snd_hdac_calc_stream_format(params->s_freq,
 159                         params->ch, params->format, params->host_bps, 0);
 160
 161         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 162                 format_val, params->s_freq, params->ch, params->format);
 163
 164         snd_hdac_stream_reset(hdac_stream(stream));
 165         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 166         if (err < 0)
 167                 return err;
 168
 169         err = snd_hdac_stream_setup(hdac_stream(stream));
 170         if (err < 0)
 171                 return err;
 172
 173         hdac_stream(stream)->prepared = 1;
 174
 175         return 0;
 176 }
 177
 178 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 179 {
 180         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
 181         struct hdac_bus *bus = ebus_to_hbus(ebus);
 182         unsigned int format_val;
 183         struct hdac_stream *hstream;
 184         struct hdac_ext_stream *stream;
 185         struct hdac_ext_link *link;
 186
 187         hstream = snd_hdac_get_stream(bus, params->stream,
 188                                         params->link_dma_id + 1);
 189         if (!hstream)
 190                 return -EINVAL;
 191
 192         stream = stream_to_hdac_ext_stream(hstream);
 193         snd_hdac_ext_stream_decouple(ebus, stream, true);
 194         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 195                                         params->format, params->link_bps, 0);
 196
 197         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 198                 format_val, params->s_freq, params->ch, params->format);
 199
 200         snd_hdac_ext_link_stream_reset(stream);
 201
 202         snd_hdac_ext_link_stream_setup(stream, format_val);
 203
 204         list_for_each_entry(link, &ebus->hlink_list, list) {
 205                 if (link->index == params->link_index)
 206                         snd_hdac_ext_link_set_stream_id(link,
 207                                         hstream->stream_tag);
 208         }
 209
 210         stream->link_prepared = 1;
 211
 212         return 0;
 213 }
 214
 215 static int skl_pcm_open(struct snd_pcm_substream *substream,
 216                 struct snd_soc_dai *dai)
 217 {
 218         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 219         struct hdac_ext_stream *stream;
 220         struct snd_pcm_runtime *runtime = substream->runtime;
 221         struct skl_dma_params *dma_params;
 222         struct skl *skl = get_skl_ctx(dai->dev);
 223         struct skl_module_cfg *mconfig;
 224
 225         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 226
 227         stream = snd_hdac_ext_stream_assign(ebus, substream,
 228                                         skl_get_host_stream_type(ebus));
 229         if (stream == NULL)
 230                 return -EBUSY;
 231
 232         skl_set_pcm_constrains(ebus, runtime);
 233
 234         /*
 235          * disable WALLCLOCK timestamps for capture streams
 236          * until we figure out how to handle digital inputs
 237          */
 238         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 239                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 240                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 241         }
 242
 243         runtime->private_data = stream;
 244
 245         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 246         if (!dma_params)
 247                 return -ENOMEM;
 248
 249         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 250         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 251
 252         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 253                                  dma_params->stream_tag);
 254         skl_set_suspend_active(substream, dai, true);
 255         snd_pcm_set_sync(substream);
 256
 257         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 258         if (!mconfig)
 259                 return -EINVAL;
 260
 261         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 262
 263         return 0;
 264 }
 265
 266 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 267                 struct snd_soc_dai *dai)
 268 {
 269         struct skl *skl = get_skl_ctx(dai->dev);
 270         struct skl_module_cfg *mconfig;
 271
 272         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 273
 274         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 275
 276         /* In case of XRUN recovery, reset the FW pipe to clean state */
 277         if (mconfig && (substream->runtime->status->state ==
 278                                         SNDRV_PCM_STATE_XRUN))
 279                 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
 280
 281         return 0;
 282 }
 283
 284 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 285                                 struct snd_pcm_hw_params *params,
 286                                 struct snd_soc_dai *dai)
 287 {
 288         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 289         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 290         struct snd_pcm_runtime *runtime = substream->runtime;
 291         struct skl_pipe_params p_params = {0};
 292         struct skl_module_cfg *m_cfg;
 293         int ret, dma_id;
 294
 295         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 296         ret = skl_substream_alloc_pages(ebus, substream,
 297                                           params_buffer_bytes(params));
 298         if (ret < 0)
 299                 return ret;
 300
 301         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 302                         runtime->rate, runtime->channels, runtime->format);
 303
 304         dma_id = hdac_stream(stream)->stream_tag - 1;
 305         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 306
 307         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 308         p_params.ch = params_channels(params);
 309         p_params.s_freq = params_rate(params);
 310         p_params.host_dma_id = dma_id;
 311         p_params.stream = substream->stream;
 312         p_params.format = params_format(params);
 313         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 314                 p_params.host_bps = dai->driver->playback.sig_bits;
 315         else
 316                 p_params.host_bps = dai->driver->capture.sig_bits;
 317
 318
 319         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 320         if (m_cfg)
 321                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 322
 323         return 0;
 324 }
 325
 326 static void skl_pcm_close(struct snd_pcm_substream *substream,
 327                 struct snd_soc_dai *dai)
 328 {
 329         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 330         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 331         struct skl_dma_params *dma_params = NULL;
 332         struct skl *skl = ebus_to_skl(ebus);
 333         struct skl_module_cfg *mconfig;
 334
 335         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 336
 337         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
 338
 339         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 340         /*
 341          * now we should set this to NULL as we are freeing by the
 342          * dma_params
 343          */
 344         snd_soc_dai_set_dma_data(dai, substream, NULL);
 345         skl_set_suspend_active(substream, dai, false);
 346
 347         /*
 348          * check if close is for "Reference Pin" and set back the
 349          * CGCTL.MISCBDCGE if disabled by driver
 350          */
 351         if (!strncmp(dai->name, "Reference Pin", 13) &&
 352                         skl->skl_sst->miscbdcg_disabled) {
 353                 skl->skl_sst->enable_miscbdcge(dai->dev, true);
 354                 skl->skl_sst->miscbdcg_disabled = false;
 355         }
 356
 357         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 358         if (mconfig)
 359                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 360
 361         kfree(dma_params);
 362 }
 363
 364 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 365                 struct snd_soc_dai *dai)
 366 {
 367         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 368         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 369
 370         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 371
 372         snd_hdac_stream_cleanup(hdac_stream(stream));
 373         hdac_stream(stream)->prepared = 0;
 374
 375         return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
 376 }
 377
 378 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 379                                 struct snd_pcm_hw_params *params,
 380                                 struct snd_soc_dai *dai)
 381 {
 382         struct skl_pipe_params p_params = {0};
 383
 384         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 385         p_params.ch = params_channels(params);
 386         p_params.s_freq = params_rate(params);
 387         p_params.stream = substream->stream;
 388
 389         return skl_tplg_be_update_params(dai, &p_params);
 390 }
 391
 392 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 393                 int cmd)
 394 {
 395         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
 396         struct hdac_bus *bus = ebus_to_hbus(ebus);
 397         struct hdac_ext_stream *stream;
 398         int start;
 399         unsigned long cookie;
 400         struct hdac_stream *hstr;
 401
 402         stream = get_hdac_ext_stream(substream);
 403         hstr = hdac_stream(stream);
 404
 405         if (!hstr->prepared)
 406                 return -EPIPE;
 407
 408         switch (cmd) {
 409         case SNDRV_PCM_TRIGGER_START:
 410         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 411         case SNDRV_PCM_TRIGGER_RESUME:
 412                 start = 1;
 413                 break;
 414
 415         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 416         case SNDRV_PCM_TRIGGER_SUSPEND:
 417         case SNDRV_PCM_TRIGGER_STOP:
 418                 start = 0;
 419                 break;
 420
 421         default:
 422                 return -EINVAL;
 423         }
 424
 425         spin_lock_irqsave(&bus->reg_lock, cookie);
 426
 427         if (start) {
 428                 snd_hdac_stream_start(hdac_stream(stream), true);
 429                 snd_hdac_stream_timecounter_init(hstr, 0);
 430         } else {
 431                 snd_hdac_stream_stop(hdac_stream(stream));
 432         }
 433
 434         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 435
 436         return 0;
 437 }
 438
 439 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 440                 struct snd_soc_dai *dai)
 441 {
 442         struct skl *skl = get_skl_ctx(dai->dev);
 443         struct skl_sst *ctx = skl->skl_sst;
 444         struct skl_module_cfg *mconfig;
 445         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
 446         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 447         struct snd_soc_dapm_widget *w;
 448         int ret;
 449
 450         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 451         if (!mconfig)
 452                 return -EIO;
 453
 454         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 455                 w = dai->playback_widget;
 456         else
 457                 w = dai->capture_widget;
 458
 459         switch (cmd) {
 460         case SNDRV_PCM_TRIGGER_RESUME:
 461                 if (!w->ignore_suspend) {
 462                         /*
 463                          * enable DMA Resume enable bit for the stream, set the
 464                          * dpib & lpib position to resume before starting the
 465                          * DMA
 466                          */
 467                         snd_hdac_ext_stream_drsm_enable(ebus, true,
 468                                                 hdac_stream(stream)->index);
 469                         snd_hdac_ext_stream_set_dpibr(ebus, stream,
 470                                                         stream->lpib);
 471                         snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
 472                 }
 473
 474         case SNDRV_PCM_TRIGGER_START:
 475         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 476                 /*
 477                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 478                  * there are no underrun/overrun in the case when the FE
 479                  * pipeline is started but there is a delay in starting the
 480                  * DMA channel on the host.
 481                  */
 482                 ret = skl_decoupled_trigger(substream, cmd);
 483                 if (ret < 0)
 484                         return ret;
 485                 return skl_run_pipe(ctx, mconfig->pipe);
 486                 break;
 487
 488         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 489         case SNDRV_PCM_TRIGGER_SUSPEND:
 490         case SNDRV_PCM_TRIGGER_STOP:
 491                 /*
 492                  * Stop FE Pipe first and stop DMA. This is to make sure that
 493                  * there are no underrun/overrun in the case if there is a delay
 494                  * between the two operations.
 495                  */
 496                 ret = skl_stop_pipe(ctx, mconfig->pipe);
 497                 if (ret < 0)
 498                         return ret;
 499
 500                 ret = skl_decoupled_trigger(substream, cmd);
 501                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 502                         /* save the dpib and lpib positions */
 503                         stream->dpib = readl(ebus->bus.remap_addr +
 504                                         AZX_REG_VS_SDXDPIB_XBASE +
 505                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 506                                         hdac_stream(stream)->index));
 507
 508                         stream->lpib = snd_hdac_stream_get_pos_lpib(
 509                                                         hdac_stream(stream));
 510                         snd_hdac_ext_stream_decouple(ebus, stream, false);
 511                 }
 512                 break;
 513
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 522                                 struct snd_pcm_hw_params *params,
 523                                 struct snd_soc_dai *dai)
 524 {
 525         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 526         struct hdac_ext_stream *link_dev;
 527         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 528         struct snd_soc_dai *codec_dai = rtd->codec_dai;
 529         struct skl_pipe_params p_params = {0};
 530         struct hdac_ext_link *link;
 531         int stream_tag;
 532
 533         link_dev = snd_hdac_ext_stream_assign(ebus, substream,
 534                                         HDAC_EXT_STREAM_TYPE_LINK);
 535         if (!link_dev)
 536                 return -EBUSY;
 537
 538         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 539
 540         link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
 541         if (!link)
 542                 return -EINVAL;
 543
 544         stream_tag = hdac_stream(link_dev)->stream_tag;
 545
 546         /* set the stream tag in the codec dai dma params  */
 547         snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
 548
 549         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 550         p_params.ch = params_channels(params);
 551         p_params.s_freq = params_rate(params);
 552         p_params.stream = substream->stream;
 553         p_params.link_dma_id = stream_tag - 1;
 554         p_params.link_index = link->index;
 555         p_params.format = params_format(params);
 556
 557         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 558                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 559         else
 560                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 561
 562         return skl_tplg_be_update_params(dai, &p_params);
 563 }
 564
 565 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 566                 struct snd_soc_dai *dai)
 567 {
 568         struct skl *skl = get_skl_ctx(dai->dev);
 569         struct skl_module_cfg *mconfig = NULL;
 570
 571         /* In case of XRUN recovery, reset the FW pipe to clean state */
 572         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 573         if (mconfig && !mconfig->pipe->passthru &&
 574                 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
 575                 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
 576
 577         return 0;
 578 }
 579
 580 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 581         int cmd, struct snd_soc_dai *dai)
 582 {
 583         struct hdac_ext_stream *link_dev =
 584                                 snd_soc_dai_get_dma_data(dai, substream);
 585         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
 586         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 587
 588         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 589         switch (cmd) {
 590         case SNDRV_PCM_TRIGGER_RESUME:
 591         case SNDRV_PCM_TRIGGER_START:
 592         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 593                 snd_hdac_ext_link_stream_start(link_dev);
 594                 break;
 595
 596         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 597         case SNDRV_PCM_TRIGGER_SUSPEND:
 598         case SNDRV_PCM_TRIGGER_STOP:
 599                 snd_hdac_ext_link_stream_clear(link_dev);
 600                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 601                         snd_hdac_ext_stream_decouple(ebus, stream, false);
 602                 break;
 603
 604         default:
 605                 return -EINVAL;
 606         }
 607         return 0;
 608 }
 609
 610 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 611                 struct snd_soc_dai *dai)
 612 {
 613         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 614         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 615         struct hdac_ext_stream *link_dev =
 616                                 snd_soc_dai_get_dma_data(dai, substream);
 617         struct hdac_ext_link *link;
 618
 619         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 620
 621         link_dev->link_prepared = 0;
 622
 623         link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
 624         if (!link)
 625                 return -EINVAL;
 626
 627         snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
 628         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 629         return 0;
 630 }
 631
 632 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 633         .startup = skl_pcm_open,
 634         .shutdown = skl_pcm_close,
 635         .prepare = skl_pcm_prepare,
 636         .hw_params = skl_pcm_hw_params,
 637         .hw_free = skl_pcm_hw_free,
 638         .trigger = skl_pcm_trigger,
 639 };
 640
 641 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 642         .hw_params = skl_be_hw_params,
 643 };
 644
 645 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 646         .hw_params = skl_be_hw_params,
 647 };
 648
 649 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 650         .prepare = skl_link_pcm_prepare,
 651         .hw_params = skl_link_hw_params,
 652         .hw_free = skl_link_hw_free,
 653         .trigger = skl_link_pcm_trigger,
 654 };
 655
 656 static struct snd_soc_dai_driver skl_fe_dai[] = {
 657 {
 658         .name = "System Pin",
 659         .ops = &skl_pcm_dai_ops,
 660         .playback = {
 661                 .stream_name = "System Playback",
 662                 .channels_min = HDA_MONO,
 663                 .channels_max = HDA_STEREO,
 664                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 665                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 666                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 667                 .sig_bits = 32,
 668         },
 669         .capture = {
 670                 .stream_name = "System Capture",
 671                 .channels_min = HDA_MONO,
 672                 .channels_max = HDA_STEREO,
 673                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 674                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 675                 .sig_bits = 32,
 676         },
 677 },
 678 {
 679         .name = "System Pin2",
 680         .ops = &skl_pcm_dai_ops,
 681         .playback = {
 682                 .stream_name = "Headset Playback",
 683                 .channels_min = HDA_MONO,
 684                 .channels_max = HDA_STEREO,
 685                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 686                         SNDRV_PCM_RATE_8000,
 687                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 688                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 689         },
 690 },
 691 {
 692         .name = "Echoref Pin",
 693         .ops = &skl_pcm_dai_ops,
 694         .capture = {
 695                 .stream_name = "Echoreference Capture",
 696                 .channels_min = HDA_STEREO,
 697                 .channels_max = HDA_STEREO,
 698                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 699                         SNDRV_PCM_RATE_8000,
 700                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 701                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 702         },
 703 },
 704 {
 705         .name = "Reference Pin",
 706         .ops = &skl_pcm_dai_ops,
 707         .capture = {
 708                 .stream_name = "Reference Capture",
 709                 .channels_min = HDA_MONO,
 710                 .channels_max = HDA_QUAD,
 711                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 712                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 713                 .sig_bits = 32,
 714         },
 715 },
 716 {
 717         .name = "Deepbuffer Pin",
 718         .ops = &skl_pcm_dai_ops,
 719         .playback = {
 720                 .stream_name = "Deepbuffer Playback",
 721                 .channels_min = HDA_STEREO,
 722                 .channels_max = HDA_STEREO,
 723                 .rates = SNDRV_PCM_RATE_48000,
 724                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 725                 .sig_bits = 32,
 726         },
 727 },
 728 {
 729         .name = "LowLatency Pin",
 730         .ops = &skl_pcm_dai_ops,
 731         .playback = {
 732                 .stream_name = "Low Latency Playback",
 733                 .channels_min = HDA_STEREO,
 734                 .channels_max = HDA_STEREO,
 735                 .rates = SNDRV_PCM_RATE_48000,
 736                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 737                 .sig_bits = 32,
 738         },
 739 },
 740 {
 741         .name = "DMIC Pin",
 742         .ops = &skl_pcm_dai_ops,
 743         .capture = {
 744                 .stream_name = "DMIC Capture",
 745                 .channels_min = HDA_MONO,
 746                 .channels_max = HDA_QUAD,
 747                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 748                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 749                 .sig_bits = 32,
 750         },
 751 },
 752 {
 753         .name = "HDMI1 Pin",
 754         .ops = &skl_pcm_dai_ops,
 755         .playback = {
 756                 .stream_name = "HDMI1 Playback",
 757                 .channels_min = HDA_STEREO,
 758                 .channels_max = 8,
 759                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 760                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 761                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 762                         SNDRV_PCM_RATE_192000,
 763                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 764                         SNDRV_PCM_FMTBIT_S32_LE,
 765                 .sig_bits = 32,
 766         },
 767 },
 768 {
 769         .name = "HDMI2 Pin",
 770         .ops = &skl_pcm_dai_ops,
 771         .playback = {
 772                 .stream_name = "HDMI2 Playback",
 773                 .channels_min = HDA_STEREO,
 774                 .channels_max = 8,
 775                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 776                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 777                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 778                         SNDRV_PCM_RATE_192000,
 779                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 780                         SNDRV_PCM_FMTBIT_S32_LE,
 781                 .sig_bits = 32,
 782         },
 783 },
 784 {
 785         .name = "HDMI3 Pin",
 786         .ops = &skl_pcm_dai_ops,
 787         .playback = {
 788                 .stream_name = "HDMI3 Playback",
 789                 .channels_min = HDA_STEREO,
 790                 .channels_max = 8,
 791                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 792                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 793                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 794                         SNDRV_PCM_RATE_192000,
 795                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 796                         SNDRV_PCM_FMTBIT_S32_LE,
 797                 .sig_bits = 32,
 798         },
 799 },
 800 };
 801
 802 /* BE CPU  Dais */
 803 static struct snd_soc_dai_driver skl_platform_dai[] = {
 804 {
 805         .name = "SSP0 Pin",
 806         .ops = &skl_be_ssp_dai_ops,
 807         .playback = {
 808                 .stream_name = "ssp0 Tx",
 809                 .channels_min = HDA_STEREO,
 810                 .channels_max = HDA_STEREO,
 811                 .rates = SNDRV_PCM_RATE_48000,
 812                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 813         },
 814         .capture = {
 815                 .stream_name = "ssp0 Rx",
 816                 .channels_min = HDA_STEREO,
 817                 .channels_max = HDA_STEREO,
 818                 .rates = SNDRV_PCM_RATE_48000,
 819                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 820         },
 821 },
 822 {
 823         .name = "SSP1 Pin",
 824         .ops = &skl_be_ssp_dai_ops,
 825         .playback = {
 826                 .stream_name = "ssp1 Tx",
 827                 .channels_min = HDA_STEREO,
 828                 .channels_max = HDA_STEREO,
 829                 .rates = SNDRV_PCM_RATE_48000,
 830                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 831         },
 832         .capture = {
 833                 .stream_name = "ssp1 Rx",
 834                 .channels_min = HDA_STEREO,
 835                 .channels_max = HDA_STEREO,
 836                 .rates = SNDRV_PCM_RATE_48000,
 837                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 838         },
 839 },
 840 {
 841         .name = "SSP2 Pin",
 842         .ops = &skl_be_ssp_dai_ops,
 843         .playback = {
 844                 .stream_name = "ssp2 Tx",
 845                 .channels_min = HDA_STEREO,
 846                 .channels_max = HDA_STEREO,
 847                 .rates = SNDRV_PCM_RATE_48000,
 848                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 849         },
 850         .capture = {
 851                 .stream_name = "ssp2 Rx",
 852                 .channels_min = HDA_STEREO,
 853                 .channels_max = HDA_STEREO,
 854                 .rates = SNDRV_PCM_RATE_48000,
 855                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 856         },
 857 },
 858 {
 859         .name = "SSP3 Pin",
 860         .ops = &skl_be_ssp_dai_ops,
 861         .playback = {
 862                 .stream_name = "ssp3 Tx",
 863                 .channels_min = HDA_STEREO,
 864                 .channels_max = HDA_STEREO,
 865                 .rates = SNDRV_PCM_RATE_48000,
 866                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 867         },
 868         .capture = {
 869                 .stream_name = "ssp3 Rx",
 870                 .channels_min = HDA_STEREO,
 871                 .channels_max = HDA_STEREO,
 872                 .rates = SNDRV_PCM_RATE_48000,
 873                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 874         },
 875 },
 876 {
 877         .name = "SSP4 Pin",
 878         .ops = &skl_be_ssp_dai_ops,
 879         .playback = {
 880                 .stream_name = "ssp4 Tx",
 881                 .channels_min = HDA_STEREO,
 882                 .channels_max = HDA_STEREO,
 883                 .rates = SNDRV_PCM_RATE_48000,
 884                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 885         },
 886         .capture = {
 887                 .stream_name = "ssp4 Rx",
 888                 .channels_min = HDA_STEREO,
 889                 .channels_max = HDA_STEREO,
 890                 .rates = SNDRV_PCM_RATE_48000,
 891                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 892         },
 893 },
 894 {
 895         .name = "SSP5 Pin",
 896         .ops = &skl_be_ssp_dai_ops,
 897         .playback = {
 898                 .stream_name = "ssp5 Tx",
 899                 .channels_min = HDA_STEREO,
 900                 .channels_max = HDA_STEREO,
 901                 .rates = SNDRV_PCM_RATE_48000,
 902                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 903         },
 904         .capture = {
 905                 .stream_name = "ssp5 Rx",
 906                 .channels_min = HDA_STEREO,
 907                 .channels_max = HDA_STEREO,
 908                 .rates = SNDRV_PCM_RATE_48000,
 909                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 910         },
 911 },
 912 {
 913         .name = "iDisp1 Pin",
 914         .ops = &skl_link_dai_ops,
 915         .playback = {
 916                 .stream_name = "iDisp1 Tx",
 917                 .channels_min = HDA_STEREO,
 918                 .channels_max = 8,
 919                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 920                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 921                         SNDRV_PCM_FMTBIT_S24_LE,
 922         },
 923 },
 924 {
 925         .name = "iDisp2 Pin",
 926         .ops = &skl_link_dai_ops,
 927         .playback = {
 928                 .stream_name = "iDisp2 Tx",
 929                 .channels_min = HDA_STEREO,
 930                 .channels_max = 8,
 931                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 932                         SNDRV_PCM_RATE_48000,
 933                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 934                         SNDRV_PCM_FMTBIT_S24_LE,
 935         },
 936 },
 937 {
 938         .name = "iDisp3 Pin",
 939         .ops = &skl_link_dai_ops,
 940         .playback = {
 941                 .stream_name = "iDisp3 Tx",
 942                 .channels_min = HDA_STEREO,
 943                 .channels_max = 8,
 944                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 945                         SNDRV_PCM_RATE_48000,
 946                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 947                         SNDRV_PCM_FMTBIT_S24_LE,
 948         },
 949 },
 950 {
 951         .name = "DMIC01 Pin",
 952         .ops = &skl_dmic_dai_ops,
 953         .capture = {
 954                 .stream_name = "DMIC01 Rx",
 955                 .channels_min = HDA_MONO,
 956                 .channels_max = HDA_QUAD,
 957                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 958                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 959         },
 960 },
 961 {
 962         .name = "HD-Codec Pin",
 963         .ops = &skl_link_dai_ops,
 964         .playback = {
 965                 .stream_name = "HD-Codec Tx",
 966                 .channels_min = HDA_STEREO,
 967                 .channels_max = HDA_STEREO,
 968                 .rates = SNDRV_PCM_RATE_48000,
 969                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 970         },
 971         .capture = {
 972                 .stream_name = "HD-Codec Rx",
 973                 .channels_min = HDA_STEREO,
 974                 .channels_max = HDA_STEREO,
 975                 .rates = SNDRV_PCM_RATE_48000,
 976                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 977         },
 978 },
 979 };
 980
 981 int skl_dai_load(struct snd_soc_component *cmp,
 982                  struct snd_soc_dai_driver *pcm_dai)
 983 {
 984         pcm_dai->ops = &skl_pcm_dai_ops;
 985
 986         return 0;
 987 }
 988
 989 static int skl_platform_open(struct snd_pcm_substream *substream)
 990 {
 991         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 992         struct snd_soc_dai_link *dai_link = rtd->dai_link;
 993
 994         dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
 995                                         dai_link->cpu_dai_name);
 996
 997         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
 998
 999         return 0;
1000 }
1001
1002 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1003                                         int cmd)
1004 {
1005         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1006         struct hdac_bus *bus = ebus_to_hbus(ebus);
1007         struct hdac_ext_stream *stream;
1008         struct snd_pcm_substream *s;
1009         bool start;
1010         int sbits = 0;
1011         unsigned long cookie;
1012         struct hdac_stream *hstr;
1013
1014         stream = get_hdac_ext_stream(substream);
1015         hstr = hdac_stream(stream);
1016
1017         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1018
1019         if (!hstr->prepared)
1020                 return -EPIPE;
1021
1022         switch (cmd) {
1023         case SNDRV_PCM_TRIGGER_START:
1024         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1025         case SNDRV_PCM_TRIGGER_RESUME:
1026                 start = true;
1027                 break;
1028
1029         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1030         case SNDRV_PCM_TRIGGER_SUSPEND:
1031         case SNDRV_PCM_TRIGGER_STOP:
1032                 start = false;
1033                 break;
1034
1035         default:
1036                 return -EINVAL;
1037         }
1038
1039         snd_pcm_group_for_each_entry(s, substream) {
1040                 if (s->pcm->card != substream->pcm->card)
1041                         continue;
1042                 stream = get_hdac_ext_stream(s);
1043                 sbits |= 1 << hdac_stream(stream)->index;
1044                 snd_pcm_trigger_done(s, substream);
1045         }
1046
1047         spin_lock_irqsave(&bus->reg_lock, cookie);
1048
1049         /* first, set SYNC bits of corresponding streams */
1050         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1051
1052         snd_pcm_group_for_each_entry(s, substream) {
1053                 if (s->pcm->card != substream->pcm->card)
1054                         continue;
1055                 stream = get_hdac_ext_stream(s);
1056                 if (start)
1057                         snd_hdac_stream_start(hdac_stream(stream), true);
1058                 else
1059                         snd_hdac_stream_stop(hdac_stream(stream));
1060         }
1061         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1062
1063         snd_hdac_stream_sync(hstr, start, sbits);
1064
1065         spin_lock_irqsave(&bus->reg_lock, cookie);
1066
1067         /* reset SYNC bits */
1068         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1069         if (start)
1070                 snd_hdac_stream_timecounter_init(hstr, sbits);
1071         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1072
1073         return 0;
1074 }
1075
1076 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1077                                         int cmd)
1078 {
1079         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1080
1081         if (!(ebus_to_hbus(ebus))->ppcap)
1082                 return skl_coupled_trigger(substream, cmd);
1083
1084         return 0;
1085 }
1086
1087 static snd_pcm_uframes_t skl_platform_pcm_pointer
1088                         (struct snd_pcm_substream *substream)
1089 {
1090         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1091         struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1092         unsigned int pos;
1093
1094         /*
1095          * Use DPIB for Playback stream as the periodic DMA Position-in-
1096          * Buffer Writes may be scheduled at the same time or later than
1097          * the MSI and does not guarantee to reflect the Position of the
1098          * last buffer that was transferred. Whereas DPIB register in
1099          * HAD space reflects the actual data that is transferred.
1100          * Use the position buffer for capture, as DPIB write gets
1101          * completed earlier than the actual data written to the DDR.
1102          *
1103          * For capture stream following workaround is required to fix the
1104          * incorrect position reporting.
1105          *
1106          * 1. Wait for 20us before reading the DMA position in buffer once
1107          * the interrupt is generated for stream completion as update happens
1108          * on the HDA frame boundary i.e. 20.833uSec.
1109          * 2. Read DPIB register to flush the DMA position value. This dummy
1110          * read is required to flush DMA position value.
1111          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1112          * or greater than period boundary.
1113          */
1114
1115         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1116                 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1117                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1118                                 hdac_stream(hstream)->index));
1119         } else {
1120                 udelay(20);
1121                 readl(ebus->bus.remap_addr +
1122                                 AZX_REG_VS_SDXDPIB_XBASE +
1123                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1124                                  hdac_stream(hstream)->index));
1125                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1126         }
1127
1128         if (pos >= hdac_stream(hstream)->bufsize)
1129                 pos = 0;
1130
1131         return bytes_to_frames(substream->runtime, pos);
1132 }
1133
1134 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1135                                 u64 nsec)
1136 {
1137         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1138         struct snd_soc_dai *codec_dai = rtd->codec_dai;
1139         u64 codec_frames, codec_nsecs;
1140
1141         if (!codec_dai->driver->ops->delay)
1142                 return nsec;
1143
1144         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1145         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1146                               substream->runtime->rate);
1147
1148         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1149                 return nsec + codec_nsecs;
1150
1151         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1152 }
1153
1154 static int skl_get_time_info(struct snd_pcm_substream *substream,
1155                         struct timespec *system_ts, struct timespec *audio_ts,
1156                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1157                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1158 {
1159         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1160         struct hdac_stream *hstr = hdac_stream(sstream);
1161         u64 nsec;
1162
1163         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1164                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1165
1166                 snd_pcm_gettime(substream->runtime, system_ts);
1167
1168                 nsec = timecounter_read(&hstr->tc);
1169                 nsec = div_u64(nsec, 3); /* can be optimized */
1170                 if (audio_tstamp_config->report_delay)
1171                         nsec = skl_adjust_codec_delay(substream, nsec);
1172
1173                 *audio_ts = ns_to_timespec(nsec);
1174
1175                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1176                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1177                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1178
1179         } else {
1180                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static const struct snd_pcm_ops skl_platform_ops = {
1187         .open = skl_platform_open,
1188         .ioctl = snd_pcm_lib_ioctl,
1189         .trigger = skl_platform_pcm_trigger,
1190         .pointer = skl_platform_pcm_pointer,
1191         .get_time_info =  skl_get_time_info,
1192         .mmap = snd_pcm_lib_default_mmap,
1193         .page = snd_pcm_sgbuf_ops_page,
1194 };
1195
1196 static void skl_pcm_free(struct snd_pcm *pcm)
1197 {
1198         snd_pcm_lib_preallocate_free_for_all(pcm);
1199 }
1200
1201 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1202
1203 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1204 {
1205         struct snd_soc_dai *dai = rtd->cpu_dai;
1206         struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1207         struct snd_pcm *pcm = rtd->pcm;
1208         unsigned int size;
1209         int retval = 0;
1210         struct skl *skl = ebus_to_skl(ebus);
1211
1212         if (dai->driver->playback.channels_min ||
1213                 dai->driver->capture.channels_min) {
1214                 /* buffer pre-allocation */
1215                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1216                 if (size > MAX_PREALLOC_SIZE)
1217                         size = MAX_PREALLOC_SIZE;
1218                 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1219                                                 SNDRV_DMA_TYPE_DEV_SG,
1220                                                 snd_dma_pci_data(skl->pci),
1221                                                 size, MAX_PREALLOC_SIZE);
1222                 if (retval) {
1223                         dev_err(dai->dev, "dma buffer allocation fail\n");
1224                         return retval;
1225                 }
1226         }
1227
1228         return retval;
1229 }
1230
1231 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig)
1232 {
1233         struct skl_sst *ctx = skl->skl_sst;
1234         struct skl_module_inst_id *pin_id;
1235         uuid_le *uuid_mod, *uuid_tplg;
1236         struct skl_module *skl_module;
1237         struct uuid_module *module;
1238         int i, ret = -EIO;
1239
1240         uuid_mod = (uuid_le *)mconfig->guid;
1241
1242         if (list_empty(&ctx->uuid_list)) {
1243                 dev_err(ctx->dev, "Module list is empty\n");
1244                 return -EIO;
1245         }
1246
1247         list_for_each_entry(module, &ctx->uuid_list, list) {
1248                 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) {
1249                         mconfig->id.module_id = module->id;
1250                         if (mconfig->module)
1251                                 mconfig->module->loadable = module->is_loadable;
1252                         ret = 0;
1253                         break;
1254                 }
1255         }
1256
1257         if (ret)
1258                 return ret;
1259
1260         uuid_mod = &module->uuid;
1261         ret = -EIO;
1262         for (i = 0; i < skl->nr_modules; i++) {
1263                 skl_module = skl->modules[i];
1264                 uuid_tplg = &skl_module->uuid;
1265                 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) {
1266                         mconfig->module = skl_module;
1267                         ret = 0;
1268                         break;
1269                 }
1270         }
1271         if (skl->nr_modules && ret)
1272                 return ret;
1273
1274         list_for_each_entry(module, &ctx->uuid_list, list) {
1275                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1276                         pin_id = &mconfig->m_in_pin[i].id;
1277                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1278                                 pin_id->module_id = module->id;
1279                 }
1280
1281                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1282                         pin_id = &mconfig->m_out_pin[i].id;
1283                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1284                                 pin_id->module_id = module->id;
1285                 }
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int skl_populate_modules(struct skl *skl)
1292 {
1293         struct skl_pipeline *p;
1294         struct skl_pipe_module *m;
1295         struct snd_soc_dapm_widget *w;
1296         struct skl_module_cfg *mconfig;
1297         int ret = 0;
1298
1299         list_for_each_entry(p, &skl->ppl_list, node) {
1300                 list_for_each_entry(m, &p->pipe->w_list, node) {
1301                         w = m->w;
1302                         mconfig = w->priv;
1303
1304                         ret = skl_get_module_info(skl, mconfig);
1305                         if (ret < 0) {
1306                                 dev_err(skl->skl_sst->dev,
1307                                         "query module info failed\n");
1308                                 return ret;
1309                         }
1310                 }
1311         }
1312
1313         return ret;
1314 }
1315
1316 static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1317 {
1318         struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1319         struct skl *skl = ebus_to_skl(ebus);
1320         const struct skl_dsp_ops *ops;
1321         int ret;
1322
1323         pm_runtime_get_sync(platform->dev);
1324         if ((ebus_to_hbus(ebus))->ppcap) {
1325                 skl->platform = platform;
1326
1327                 /* init debugfs */
1328                 skl->debugfs = skl_debugfs_init(skl);
1329
1330                 ret = skl_tplg_init(platform, ebus);
1331                 if (ret < 0) {
1332                         dev_err(platform->dev, "Failed to init topology!\n");
1333                         return ret;
1334                 }
1335
1336                 /* load the firmwares, since all is set */
1337                 ops = skl_get_dsp_ops(skl->pci->device);
1338                 if (!ops)
1339                         return -EIO;
1340
1341                 if (skl->skl_sst->is_first_boot == false) {
1342                         dev_err(platform->dev, "DSP reports first boot done!!!\n");
1343                         return -EIO;
1344                 }
1345
1346                 ret = ops->init_fw(platform->dev, skl->skl_sst);
1347                 if (ret < 0) {
1348                         dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);
1349                         return ret;
1350                 }
1351                 skl_populate_modules(skl);
1352                 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1353                 skl_dsp_enable_notification(skl->skl_sst, false);
1354         }
1355         pm_runtime_mark_last_busy(platform->dev);
1356         pm_runtime_put_autosuspend(platform->dev);
1357
1358         return 0;
1359 }
1360 static const struct snd_soc_platform_driver skl_platform_drv  = {
1361         .probe          = skl_platform_soc_probe,
1362         .ops            = &skl_platform_ops,
1363         .pcm_new        = skl_pcm_new,
1364         .pcm_free       = skl_pcm_free,
1365 };
1366
1367 static const struct snd_soc_component_driver skl_component = {
1368         .name           = "pcm",
1369 };
1370
1371 int skl_platform_register(struct device *dev)
1372 {
1373         int ret;
1374         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1375         struct skl *skl = ebus_to_skl(ebus);
1376         struct snd_soc_dai_driver *dais;
1377         int num_dais = ARRAY_SIZE(skl_platform_dai);
1378
1379         INIT_LIST_HEAD(&skl->ppl_list);
1380         INIT_LIST_HEAD(&skl->bind_list);
1381
1382         ret = snd_soc_register_platform(dev, &skl_platform_drv);
1383         if (ret) {
1384                 dev_err(dev, "soc platform registration failed %d\n", ret);
1385                 return ret;
1386         }
1387
1388         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1389                             GFP_KERNEL);
1390         if (!skl->dais) {
1391                 ret = -ENOMEM;
1392                 goto err;
1393         }
1394
1395         if (!skl->use_tplg_pcm) {
1396                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1397                                 sizeof(skl_platform_dai), GFP_KERNEL);
1398                 if (!dais) {
1399                         ret = -ENOMEM;
1400                         goto err;
1401                 }
1402
1403                 skl->dais = dais;
1404                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1405                        sizeof(skl_fe_dai));
1406                 num_dais += ARRAY_SIZE(skl_fe_dai);
1407         }
1408
1409         ret = snd_soc_register_component(dev, &skl_component,
1410                                          skl->dais, num_dais);
1411         if (ret) {
1412                 dev_err(dev, "soc component registration failed %d\n", ret);
1413                 goto err;
1414         }
1415
1416         return 0;
1417 err:
1418         snd_soc_unregister_platform(dev);
1419         return ret;
1420
1421 }
1422
1423 int skl_platform_unregister(struct device *dev)
1424 {
1425         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1426         struct skl *skl = ebus_to_skl(ebus);
1427         struct skl_module_deferred_bind *modules, *tmp;
1428
1429         if (!list_empty(&skl->bind_list)) {
1430                 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1431                         list_del(&modules->node);
1432                         kfree(modules);
1433                 }
1434         }
1435
1436         snd_soc_unregister_component(dev);
1437         snd_soc_unregister_platform(dev);
1438         kfree(skl->dais);
1439
1440         return 0;
1441 }