Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/hdmi', 'asoc/topic/hisi...
[sfrench/cifs-2.6.git] / sound / soc / hisilicon / hi6210-i2s.c
1 /*
2  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
3  *
4  * Copyright (C) 2015 Linaro, Ltd
5  * Author: Andy Green <andy.green@linaro.org>
6  *
7  * This program is free software: you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation, version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * This driver only deals with S2 interface (BT)
17  */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/jiffies.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/dmaengine_pcm.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33 #include <linux/interrupt.h>
34 #include <linux/reset.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/mfd/syscon.h>
38 #include <linux/reset-controller.h>
39 #include <linux/clk.h>
40
41 #include "hi6210-i2s.h"
42
43 struct hi6210_i2s {
44         struct device *dev;
45         struct reset_control *rc;
46         struct clk *clk[8];
47         int clocks;
48         struct snd_soc_dai_driver dai;
49         void __iomem *base;
50         struct regmap *sysctrl;
51         phys_addr_t base_phys;
52         struct snd_dmaengine_dai_dma_data dma_data[2];
53         int clk_rate;
54         spinlock_t lock;
55         int rate;
56         int format;
57         u8 bits;
58         u8 channels;
59         u8 id;
60         u8 channel_length;
61         u8 use;
62         u32 master:1;
63         u32 status:1;
64 };
65
66 #define SC_PERIPH_CLKEN1        0x210
67 #define SC_PERIPH_CLKDIS1       0x214
68
69 #define SC_PERIPH_CLKEN3        0x230
70 #define SC_PERIPH_CLKDIS3       0x234
71
72 #define SC_PERIPH_CLKEN12       0x270
73 #define SC_PERIPH_CLKDIS12      0x274
74
75 #define SC_PERIPH_RSTEN1        0x310
76 #define SC_PERIPH_RSTDIS1       0x314
77 #define SC_PERIPH_RSTSTAT1      0x318
78
79 #define SC_PERIPH_RSTEN2        0x320
80 #define SC_PERIPH_RSTDIS2       0x324
81 #define SC_PERIPH_RSTSTAT2      0x328
82
83 #define SOC_PMCTRL_BBPPLLALIAS  0x48
84
85 enum {
86         CLK_DACODEC,
87         CLK_I2S_BASE,
88 };
89
90 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
91 {
92         writel(val, i2s->base + reg);
93 }
94
95 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
96 {
97         return readl(i2s->base + reg);
98 }
99
100 static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
101                               struct snd_soc_dai *cpu_dai)
102 {
103         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
104         int ret, n;
105         u32 val;
106
107         /* deassert reset on ABB */
108         regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
109         if (val & BIT(4))
110                 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
111
112         for (n = 0; n < i2s->clocks; n++) {
113                 ret = clk_prepare_enable(i2s->clk[n]);
114                 if (ret) {
115                         while (n--)
116                                 clk_disable_unprepare(i2s->clk[n]);
117                         return ret;
118                 }
119         }
120
121         ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
122         if (ret) {
123                 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
124                         __func__, ret);
125                 return ret;
126         }
127
128         /* enable clock before frequency division */
129         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
130
131         /* enable codec working clock / == "codec bus clock" */
132         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
133
134         /* deassert reset on codec / interface clock / working clock */
135         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
136         regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
137
138         /* not interested in i2s irqs */
139         val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
140         val |= 0x3f;
141         hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
142
143
144         /* reset the stereo downlink fifo */
145         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
146         val |= (BIT(5) | BIT(4));
147         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
148
149         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
150         val &= ~(BIT(5) | BIT(4));
151         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
152
153
154         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
155         val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
156                         HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
157         val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
158         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
159
160         val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
161         /* mux 11/12 = APB not i2s */
162         val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
163         /* BT R ch  0 = mixer op of DACR ch */
164         val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
165         val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
166
167         val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
168         /* BT L ch = 1 = mux 7 = "mixer output of DACL */
169         val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
170         hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
171
172         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
173         val |= HII2S_SW_RST_N__SW_RST_N;
174         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
175
176         return 0;
177 }
178
179 static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
180                                 struct snd_soc_dai *cpu_dai)
181 {
182         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
183         int n;
184
185         for (n = 0; n < i2s->clocks; n++)
186                 clk_disable_unprepare(i2s->clk[n]);
187
188         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
189 }
190
191 static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
192 {
193         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
194         u32 val;
195
196         spin_lock(&i2s->lock);
197         if (on) {
198                 /* enable S2 TX */
199                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
200                 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
201                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
202         } else {
203                 /* disable S2 TX */
204                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
205                 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
206                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
207         }
208         spin_unlock(&i2s->lock);
209 }
210
211 static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
212 {
213         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
214         u32 val;
215
216         spin_lock(&i2s->lock);
217         if (on) {
218                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
219                 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
220                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
221         } else {
222                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
223                 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
224                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
225         }
226         spin_unlock(&i2s->lock);
227 }
228
229 static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
230 {
231         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
232
233         /*
234          * We don't actually set the hardware until the hw_params
235          * call, but we need to validate the user input here.
236          */
237         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
238         case SND_SOC_DAIFMT_CBM_CFM:
239         case SND_SOC_DAIFMT_CBS_CFS:
240                 break;
241         default:
242                 return -EINVAL;
243         }
244
245         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
246         case SND_SOC_DAIFMT_I2S:
247         case SND_SOC_DAIFMT_LEFT_J:
248         case SND_SOC_DAIFMT_RIGHT_J:
249                 break;
250         default:
251                 return -EINVAL;
252         }
253
254         i2s->format = fmt;
255         i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
256                       SND_SOC_DAIFMT_CBS_CFS;
257
258         return 0;
259 }
260
261 static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
262                             struct snd_pcm_hw_params *params,
263                             struct snd_soc_dai *cpu_dai)
264 {
265         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
266         u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
267         u32 val;
268         struct snd_dmaengine_dai_dma_data *dma_data;
269
270         switch (params_format(params)) {
271         case SNDRV_PCM_FORMAT_U16_LE:
272                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
273                 /* fallthru */
274         case SNDRV_PCM_FORMAT_S16_LE:
275                 bits = HII2S_BITS_16;
276                 break;
277         case SNDRV_PCM_FORMAT_U24_LE:
278                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
279                 /* fallthru */
280         case SNDRV_PCM_FORMAT_S24_LE:
281                 bits = HII2S_BITS_24;
282                 break;
283         default:
284                 dev_err(cpu_dai->dev, "Bad format\n");
285                 return -EINVAL;
286         }
287
288
289         switch (params_rate(params)) {
290         case 8000:
291                 rate = HII2S_FS_RATE_8KHZ;
292                 break;
293         case 16000:
294                 rate = HII2S_FS_RATE_16KHZ;
295                 break;
296         case 32000:
297                 rate = HII2S_FS_RATE_32KHZ;
298                 break;
299         case 48000:
300                 rate = HII2S_FS_RATE_48KHZ;
301                 break;
302         case 96000:
303                 rate = HII2S_FS_RATE_96KHZ;
304                 break;
305         case 192000:
306                 rate = HII2S_FS_RATE_192KHZ;
307                 break;
308         default:
309                 dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
310                 return -EINVAL;
311         }
312
313         if (!(params_channels(params))) {
314                 dev_err(cpu_dai->dev, "Bad channels\n");
315                 return -EINVAL;
316         }
317
318         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
319
320         switch (bits) {
321         case HII2S_BITS_24:
322                 i2s->bits = 32;
323                 dma_data->addr_width = 3;
324                 break;
325         default:
326                 i2s->bits = 16;
327                 dma_data->addr_width = 2;
328                 break;
329         }
330         i2s->rate = params_rate(params);
331         i2s->channels = params_channels(params);
332         i2s->channel_length = i2s->channels * i2s->bits;
333
334         val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
335         val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
336                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
337                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
338                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
339                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
340                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
341                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
342                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
343         val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
344                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
345                 (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
346                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
347         hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
348
349
350         val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
351         val |= (BIT(19) | BIT(18) | BIT(17) |
352                 HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
353                 HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
354                 HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
355                 HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
356                 HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
357         hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
358
359
360         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
361         val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
362                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
363                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
364                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
365                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
366                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
367         val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
368                 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
369         hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
370
371
372         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
373         val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
374                  HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
375         hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
376
377         val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
378         val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
379                  HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
380                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
381                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
382         hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
383
384
385         switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
386         case SND_SOC_DAIFMT_CBM_CFM:
387                 i2s->master = false;
388                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
389                 val |= HII2S_I2S_CFG__S2_MST_SLV;
390                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
391                 break;
392         case SND_SOC_DAIFMT_CBS_CFS:
393                 i2s->master = true;
394                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
395                 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
396                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
397                 break;
398         default:
399                 WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
400                 return -EINVAL;
401         }
402
403         switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
404         case SND_SOC_DAIFMT_I2S:
405                 fmt = HII2S_FORMAT_I2S;
406                 break;
407         case SND_SOC_DAIFMT_LEFT_J:
408                 fmt = HII2S_FORMAT_LEFT_JUST;
409                 break;
410         case SND_SOC_DAIFMT_RIGHT_J:
411                 fmt = HII2S_FORMAT_RIGHT_JUST;
412                 break;
413         default:
414                 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
415                 return -EINVAL;
416         }
417
418         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
419         val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
420                         HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
421         val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
422         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
423
424
425         val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
426         val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
427                         HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
428         hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
429
430         dma_data->maxburst = 2;
431
432         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
433                 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
434         else
435                 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
436
437         switch (i2s->channels) {
438         case 1:
439                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
440                 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
441                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
442                 break;
443         default:
444                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
445                 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
446                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
447                 break;
448         }
449
450         /* clear loopback, set signed type and word length */
451         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
452         val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
453         val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
454                         HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
455         val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
456                         HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
457         val |= signed_data;
458         val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
459         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
460
461
462         if (!i2s->master)
463                 return 0;
464
465         /* set DAC and related units to correct rate */
466         val = hi6210_read_reg(i2s, HII2S_FS_CFG);
467         val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
468         val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
469         val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
470                                         HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
471         val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
472                                         HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
473         val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
474         val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
475         val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
476         val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
477         hi6210_write_reg(i2s, HII2S_FS_CFG, val);
478
479         return 0;
480 }
481
482 static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
483                           struct snd_soc_dai *cpu_dai)
484 {
485         pr_debug("%s\n", __func__);
486         switch (cmd) {
487         case SNDRV_PCM_TRIGGER_START:
488         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
489                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
490                         hi6210_i2s_rxctrl(cpu_dai, 1);
491                 else
492                         hi6210_i2s_txctrl(cpu_dai, 1);
493                 break;
494         case SNDRV_PCM_TRIGGER_STOP:
495         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
496                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
497                         hi6210_i2s_rxctrl(cpu_dai, 0);
498                 else
499                         hi6210_i2s_txctrl(cpu_dai, 0);
500                 break;
501         default:
502                 dev_err(cpu_dai->dev, "uknown cmd\n");
503                 return -EINVAL;
504         }
505         return 0;
506 }
507
508 static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
509 {
510         struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
511
512         snd_soc_dai_init_dma_data(dai,
513                                   &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
514                                   &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
515
516         return 0;
517 }
518
519
520 static struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
521         .trigger        = hi6210_i2s_trigger,
522         .hw_params      = hi6210_i2s_hw_params,
523         .set_fmt        = hi6210_i2s_set_fmt,
524         .startup        = hi6210_i2s_startup,
525         .shutdown       = hi6210_i2s_shutdown,
526 };
527
528 static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
529         .probe          = hi6210_i2s_dai_probe,
530         .playback = {
531                 .channels_min = 2,
532                 .channels_max = 2,
533                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
534                            SNDRV_PCM_FMTBIT_U16_LE,
535                 .rates = SNDRV_PCM_RATE_48000,
536         },
537         .capture = {
538                 .channels_min = 2,
539                 .channels_max = 2,
540                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
541                            SNDRV_PCM_FMTBIT_U16_LE,
542                 .rates = SNDRV_PCM_RATE_48000,
543         },
544         .ops = &hi6210_i2s_dai_ops,
545 };
546
547 static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
548         .name = "hi6210_i2s-i2s",
549 };
550
551 static int hi6210_i2s_probe(struct platform_device *pdev)
552 {
553         struct device_node *node = pdev->dev.of_node;
554         struct device *dev = &pdev->dev;
555         struct hi6210_i2s *i2s;
556         struct resource *res;
557         int ret;
558
559         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
560         if (!i2s)
561                 return -ENOMEM;
562
563         i2s->dev = dev;
564         spin_lock_init(&i2s->lock);
565
566         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
567         i2s->base = devm_ioremap_resource(dev, res);
568         if (IS_ERR(i2s->base))
569                 return PTR_ERR(i2s->base);
570
571         i2s->base_phys = (phys_addr_t)res->start;
572         i2s->dai = hi6210_i2s_dai_init;
573
574         dev_set_drvdata(&pdev->dev, i2s);
575
576         i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
577                                                 "hisilicon,sysctrl-syscon");
578         if (IS_ERR(i2s->sysctrl))
579                 return PTR_ERR(i2s->sysctrl);
580
581         i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
582         if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
583                 return PTR_ERR(i2s->clk[CLK_DACODEC]);
584         i2s->clocks++;
585
586         i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
587         if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
588                 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
589         i2s->clocks++;
590
591         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
592         if (ret)
593                 return ret;
594
595         ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
596                                          &i2s->dai, 1);
597         return ret;
598 }
599
600 static const struct of_device_id hi6210_i2s_dt_ids[] = {
601         { .compatible = "hisilicon,hi6210-i2s" },
602         { /* sentinel */ }
603 };
604
605 MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
606
607 static struct platform_driver hi6210_i2s_driver = {
608         .probe = hi6210_i2s_probe,
609         .driver = {
610                 .name = "hi6210_i2s",
611                 .of_match_table = hi6210_i2s_dt_ids,
612         },
613 };
614
615 module_platform_driver(hi6210_i2s_driver);
616
617 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
618 MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
619 MODULE_LICENSE("GPL");