ASoC: dwc: Unmask I2S interrupts only for enabled channels
[sfrench/cifs-2.6.git] / sound / soc / dwc / designware_i2s.c
1 /*
2  * ALSA SoC Synopsys I2S Audio Layer
3  *
4  * sound/soc/dwc/designware_i2s.c
5  *
6  * Copyright (C) 2010 ST Microelectronics
7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/pm_runtime.h>
22 #include <sound/designware_i2s.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/dmaengine_pcm.h>
27
28 /* common register for all channel */
29 #define IER             0x000
30 #define IRER            0x004
31 #define ITER            0x008
32 #define CER             0x00C
33 #define CCR             0x010
34 #define RXFFR           0x014
35 #define TXFFR           0x018
36
37 /* I2STxRxRegisters for all channels */
38 #define LRBR_LTHR(x)    (0x40 * x + 0x020)
39 #define RRBR_RTHR(x)    (0x40 * x + 0x024)
40 #define RER(x)          (0x40 * x + 0x028)
41 #define TER(x)          (0x40 * x + 0x02C)
42 #define RCR(x)          (0x40 * x + 0x030)
43 #define TCR(x)          (0x40 * x + 0x034)
44 #define ISR(x)          (0x40 * x + 0x038)
45 #define IMR(x)          (0x40 * x + 0x03C)
46 #define ROR(x)          (0x40 * x + 0x040)
47 #define TOR(x)          (0x40 * x + 0x044)
48 #define RFCR(x)         (0x40 * x + 0x048)
49 #define TFCR(x)         (0x40 * x + 0x04C)
50 #define RFF(x)          (0x40 * x + 0x050)
51 #define TFF(x)          (0x40 * x + 0x054)
52
53 /* I2SCOMPRegisters */
54 #define I2S_COMP_PARAM_2        0x01F0
55 #define I2S_COMP_PARAM_1        0x01F4
56 #define I2S_COMP_VERSION        0x01F8
57 #define I2S_COMP_TYPE           0x01FC
58
59 /*
60  * Component parameter register fields - define the I2S block's
61  * configuration.
62  */
63 #define COMP1_TX_WORDSIZE_3(r)  (((r) & GENMASK(27, 25)) >> 25)
64 #define COMP1_TX_WORDSIZE_2(r)  (((r) & GENMASK(24, 22)) >> 22)
65 #define COMP1_TX_WORDSIZE_1(r)  (((r) & GENMASK(21, 19)) >> 19)
66 #define COMP1_TX_WORDSIZE_0(r)  (((r) & GENMASK(18, 16)) >> 16)
67 #define COMP1_TX_CHANNELS(r)    (((r) & GENMASK(10, 9)) >> 9)
68 #define COMP1_RX_CHANNELS(r)    (((r) & GENMASK(8, 7)) >> 7)
69 #define COMP1_RX_ENABLED(r)     (((r) & BIT(6)) >> 6)
70 #define COMP1_TX_ENABLED(r)     (((r) & BIT(5)) >> 5)
71 #define COMP1_MODE_EN(r)        (((r) & BIT(4)) >> 4)
72 #define COMP1_FIFO_DEPTH_GLOBAL(r)      (((r) & GENMASK(3, 2)) >> 2)
73 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
74
75 #define COMP2_RX_WORDSIZE_3(r)  (((r) & GENMASK(12, 10)) >> 10)
76 #define COMP2_RX_WORDSIZE_2(r)  (((r) & GENMASK(9, 7)) >> 7)
77 #define COMP2_RX_WORDSIZE_1(r)  (((r) & GENMASK(5, 3)) >> 3)
78 #define COMP2_RX_WORDSIZE_0(r)  (((r) & GENMASK(2, 0)) >> 0)
79
80 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
81 #define COMP_MAX_WORDSIZE       (1 << 3)
82 #define COMP_MAX_DATA_WIDTH     (1 << 2)
83
84 #define MAX_CHANNEL_NUM         8
85 #define MIN_CHANNEL_NUM         2
86
87 union dw_i2s_snd_dma_data {
88         struct i2s_dma_data pd;
89         struct snd_dmaengine_dai_dma_data dt;
90 };
91
92 struct dw_i2s_dev {
93         void __iomem *i2s_base;
94         struct clk *clk;
95         int active;
96         unsigned int capability;
97         unsigned int quirks;
98         unsigned int i2s_reg_comp1;
99         unsigned int i2s_reg_comp2;
100         struct device *dev;
101         u32 ccr;
102         u32 xfer_resolution;
103
104         /* data related to DMA transfers b/w i2s and DMAC */
105         union dw_i2s_snd_dma_data play_dma_data;
106         union dw_i2s_snd_dma_data capture_dma_data;
107         struct i2s_clk_config_data config;
108         int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
109 };
110
111 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
112 {
113         writel(val, io_base + reg);
114 }
115
116 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
117 {
118         return readl(io_base + reg);
119 }
120
121 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
122 {
123         u32 i = 0;
124
125         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
126                 for (i = 0; i < 4; i++)
127                         i2s_write_reg(dev->i2s_base, TER(i), 0);
128         } else {
129                 for (i = 0; i < 4; i++)
130                         i2s_write_reg(dev->i2s_base, RER(i), 0);
131         }
132 }
133
134 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
135 {
136         u32 i = 0;
137
138         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
139                 for (i = 0; i < 4; i++)
140                         i2s_read_reg(dev->i2s_base, TOR(i));
141         } else {
142                 for (i = 0; i < 4; i++)
143                         i2s_read_reg(dev->i2s_base, ROR(i));
144         }
145 }
146
147 static void i2s_start(struct dw_i2s_dev *dev,
148                       struct snd_pcm_substream *substream)
149 {
150         struct i2s_clk_config_data *config = &dev->config;
151         u32 i, irq;
152         i2s_write_reg(dev->i2s_base, IER, 1);
153
154         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
155                 for (i = 0; i < (config->chan_nr / 2); i++) {
156                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
157                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
158                 }
159                 i2s_write_reg(dev->i2s_base, ITER, 1);
160         } else {
161                 for (i = 0; i < (config->chan_nr / 2); i++) {
162                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
163                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
164                 }
165                 i2s_write_reg(dev->i2s_base, IRER, 1);
166         }
167
168         i2s_write_reg(dev->i2s_base, CER, 1);
169 }
170
171 static void i2s_stop(struct dw_i2s_dev *dev,
172                 struct snd_pcm_substream *substream)
173 {
174         u32 i = 0, irq;
175
176         i2s_clear_irqs(dev, substream->stream);
177         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
178                 i2s_write_reg(dev->i2s_base, ITER, 0);
179
180                 for (i = 0; i < 4; i++) {
181                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
182                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
183                 }
184         } else {
185                 i2s_write_reg(dev->i2s_base, IRER, 0);
186
187                 for (i = 0; i < 4; i++) {
188                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
189                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
190                 }
191         }
192
193         if (!dev->active) {
194                 i2s_write_reg(dev->i2s_base, CER, 0);
195                 i2s_write_reg(dev->i2s_base, IER, 0);
196         }
197 }
198
199 static int dw_i2s_startup(struct snd_pcm_substream *substream,
200                 struct snd_soc_dai *cpu_dai)
201 {
202         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
203         union dw_i2s_snd_dma_data *dma_data = NULL;
204
205         if (!(dev->capability & DWC_I2S_RECORD) &&
206                         (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
207                 return -EINVAL;
208
209         if (!(dev->capability & DWC_I2S_PLAY) &&
210                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
211                 return -EINVAL;
212
213         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
214                 dma_data = &dev->play_dma_data;
215         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
216                 dma_data = &dev->capture_dma_data;
217
218         snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
219
220         return 0;
221 }
222
223 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
224 {
225         u32 ch_reg, irq;
226         struct i2s_clk_config_data *config = &dev->config;
227
228
229         i2s_disable_channels(dev, stream);
230
231         for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
232                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
233                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
234                                       dev->xfer_resolution);
235                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
236                         irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
237                         i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
238                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
239                 } else {
240                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
241                                       dev->xfer_resolution);
242                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
243                         irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
244                         i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
245                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
246                 }
247
248         }
249 }
250
251 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
252                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
253 {
254         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
255         struct i2s_clk_config_data *config = &dev->config;
256         int ret;
257
258         switch (params_format(params)) {
259         case SNDRV_PCM_FORMAT_S16_LE:
260                 config->data_width = 16;
261                 dev->ccr = 0x00;
262                 dev->xfer_resolution = 0x02;
263                 break;
264
265         case SNDRV_PCM_FORMAT_S24_LE:
266                 config->data_width = 24;
267                 dev->ccr = 0x08;
268                 dev->xfer_resolution = 0x04;
269                 break;
270
271         case SNDRV_PCM_FORMAT_S32_LE:
272                 config->data_width = 32;
273                 dev->ccr = 0x10;
274                 dev->xfer_resolution = 0x05;
275                 break;
276
277         default:
278                 dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
279                 return -EINVAL;
280         }
281
282         config->chan_nr = params_channels(params);
283
284         switch (config->chan_nr) {
285         case EIGHT_CHANNEL_SUPPORT:
286         case SIX_CHANNEL_SUPPORT:
287         case FOUR_CHANNEL_SUPPORT:
288         case TWO_CHANNEL_SUPPORT:
289                 break;
290         default:
291                 dev_err(dev->dev, "channel not supported\n");
292                 return -EINVAL;
293         }
294
295         dw_i2s_config(dev, substream->stream);
296
297         i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
298
299         config->sample_rate = params_rate(params);
300
301         if (dev->capability & DW_I2S_MASTER) {
302                 if (dev->i2s_clk_cfg) {
303                         ret = dev->i2s_clk_cfg(config);
304                         if (ret < 0) {
305                                 dev_err(dev->dev, "runtime audio clk config fail\n");
306                                 return ret;
307                         }
308                 } else {
309                         u32 bitclk = config->sample_rate *
310                                         config->data_width * 2;
311
312                         ret = clk_set_rate(dev->clk, bitclk);
313                         if (ret) {
314                                 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
315                                         ret);
316                                 return ret;
317                         }
318                 }
319         }
320         return 0;
321 }
322
323 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
324                 struct snd_soc_dai *dai)
325 {
326         snd_soc_dai_set_dma_data(dai, substream, NULL);
327 }
328
329 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
330                           struct snd_soc_dai *dai)
331 {
332         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
333
334         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
335                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
336         else
337                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
338
339         return 0;
340 }
341
342 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
343                 int cmd, struct snd_soc_dai *dai)
344 {
345         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
346         int ret = 0;
347
348         switch (cmd) {
349         case SNDRV_PCM_TRIGGER_START:
350         case SNDRV_PCM_TRIGGER_RESUME:
351         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
352                 dev->active++;
353                 i2s_start(dev, substream);
354                 break;
355
356         case SNDRV_PCM_TRIGGER_STOP:
357         case SNDRV_PCM_TRIGGER_SUSPEND:
358         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
359                 dev->active--;
360                 i2s_stop(dev, substream);
361                 break;
362         default:
363                 ret = -EINVAL;
364                 break;
365         }
366         return ret;
367 }
368
369 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
370 {
371         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
372         int ret = 0;
373
374         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
375         case SND_SOC_DAIFMT_CBM_CFM:
376                 if (dev->capability & DW_I2S_SLAVE)
377                         ret = 0;
378                 else
379                         ret = -EINVAL;
380                 break;
381         case SND_SOC_DAIFMT_CBS_CFS:
382                 if (dev->capability & DW_I2S_MASTER)
383                         ret = 0;
384                 else
385                         ret = -EINVAL;
386                 break;
387         case SND_SOC_DAIFMT_CBM_CFS:
388         case SND_SOC_DAIFMT_CBS_CFM:
389                 ret = -EINVAL;
390                 break;
391         default:
392                 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
393                 ret = -EINVAL;
394                 break;
395         }
396         return ret;
397 }
398
399 static struct snd_soc_dai_ops dw_i2s_dai_ops = {
400         .startup        = dw_i2s_startup,
401         .shutdown       = dw_i2s_shutdown,
402         .hw_params      = dw_i2s_hw_params,
403         .prepare        = dw_i2s_prepare,
404         .trigger        = dw_i2s_trigger,
405         .set_fmt        = dw_i2s_set_fmt,
406 };
407
408 static const struct snd_soc_component_driver dw_i2s_component = {
409         .name           = "dw-i2s",
410 };
411
412 #ifdef CONFIG_PM
413 static int dw_i2s_runtime_suspend(struct device *dev)
414 {
415         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
416
417         if (dw_dev->capability & DW_I2S_MASTER)
418                 clk_disable(dw_dev->clk);
419         return 0;
420 }
421
422 static int dw_i2s_runtime_resume(struct device *dev)
423 {
424         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
425
426         if (dw_dev->capability & DW_I2S_MASTER)
427                 clk_enable(dw_dev->clk);
428         return 0;
429 }
430
431 static int dw_i2s_suspend(struct snd_soc_dai *dai)
432 {
433         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
434
435         if (dev->capability & DW_I2S_MASTER)
436                 clk_disable(dev->clk);
437         return 0;
438 }
439
440 static int dw_i2s_resume(struct snd_soc_dai *dai)
441 {
442         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
443
444         if (dev->capability & DW_I2S_MASTER)
445                 clk_enable(dev->clk);
446
447         if (dai->playback_active)
448                 dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK);
449         if (dai->capture_active)
450                 dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE);
451         return 0;
452 }
453
454 #else
455 #define dw_i2s_suspend  NULL
456 #define dw_i2s_resume   NULL
457 #endif
458
459 /*
460  * The following tables allow a direct lookup of various parameters
461  * defined in the I2S block's configuration in terms of sound system
462  * parameters.  Each table is sized to the number of entries possible
463  * according to the number of configuration bits describing an I2S
464  * block parameter.
465  */
466
467 /* Maximum bit resolution of a channel - not uniformly spaced */
468 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
469         12, 16, 20, 24, 32, 0, 0, 0
470 };
471
472 /* Width of (DMA) bus */
473 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
474         DMA_SLAVE_BUSWIDTH_1_BYTE,
475         DMA_SLAVE_BUSWIDTH_2_BYTES,
476         DMA_SLAVE_BUSWIDTH_4_BYTES,
477         DMA_SLAVE_BUSWIDTH_UNDEFINED
478 };
479
480 /* PCM format to support channel resolution */
481 static const u32 formats[COMP_MAX_WORDSIZE] = {
482         SNDRV_PCM_FMTBIT_S16_LE,
483         SNDRV_PCM_FMTBIT_S16_LE,
484         SNDRV_PCM_FMTBIT_S24_LE,
485         SNDRV_PCM_FMTBIT_S24_LE,
486         SNDRV_PCM_FMTBIT_S32_LE,
487         0,
488         0,
489         0
490 };
491
492 static int dw_configure_dai(struct dw_i2s_dev *dev,
493                                    struct snd_soc_dai_driver *dw_i2s_dai,
494                                    unsigned int rates)
495 {
496         /*
497          * Read component parameter registers to extract
498          * the I2S block's configuration.
499          */
500         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
501         u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
502         u32 idx;
503
504         if (dev->capability & DWC_I2S_RECORD &&
505                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
506                 comp1 = comp1 & ~BIT(5);
507
508         if (COMP1_TX_ENABLED(comp1)) {
509                 dev_dbg(dev->dev, " designware: play supported\n");
510                 idx = COMP1_TX_WORDSIZE_0(comp1);
511                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
512                         return -EINVAL;
513                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
514                 dw_i2s_dai->playback.channels_max =
515                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
516                 dw_i2s_dai->playback.formats = formats[idx];
517                 dw_i2s_dai->playback.rates = rates;
518         }
519
520         if (COMP1_RX_ENABLED(comp1)) {
521                 dev_dbg(dev->dev, "designware: record supported\n");
522                 idx = COMP2_RX_WORDSIZE_0(comp2);
523                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
524                         return -EINVAL;
525                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
526                 dw_i2s_dai->capture.channels_max =
527                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
528                 dw_i2s_dai->capture.formats = formats[idx];
529                 dw_i2s_dai->capture.rates = rates;
530         }
531
532         if (COMP1_MODE_EN(comp1)) {
533                 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
534                 dev->capability |= DW_I2S_MASTER;
535         } else {
536                 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
537                 dev->capability |= DW_I2S_SLAVE;
538         }
539
540         return 0;
541 }
542
543 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
544                                    struct snd_soc_dai_driver *dw_i2s_dai,
545                                    struct resource *res,
546                                    const struct i2s_platform_data *pdata)
547 {
548         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
549         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
550         int ret;
551
552         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
553                 return -EINVAL;
554
555         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
556         if (ret < 0)
557                 return ret;
558
559         /* Set DMA slaves info */
560         dev->play_dma_data.pd.data = pdata->play_dma_data;
561         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
562         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
563         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
564         dev->play_dma_data.pd.max_burst = 16;
565         dev->capture_dma_data.pd.max_burst = 16;
566         dev->play_dma_data.pd.addr_width = bus_widths[idx];
567         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
568         dev->play_dma_data.pd.filter = pdata->filter;
569         dev->capture_dma_data.pd.filter = pdata->filter;
570
571         return 0;
572 }
573
574 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
575                                    struct snd_soc_dai_driver *dw_i2s_dai,
576                                    struct resource *res)
577 {
578         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
579         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
580         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
581         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
582         u32 idx2;
583         int ret;
584
585         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
586                 return -EINVAL;
587
588         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
589         if (ret < 0)
590                 return ret;
591
592         if (COMP1_TX_ENABLED(comp1)) {
593                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
594
595                 dev->capability |= DWC_I2S_PLAY;
596                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
597                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
598                 dev->play_dma_data.dt.chan_name = "TX";
599                 dev->play_dma_data.dt.fifo_size = fifo_depth *
600                         (fifo_width[idx2]) >> 8;
601                 dev->play_dma_data.dt.maxburst = 16;
602         }
603         if (COMP1_RX_ENABLED(comp1)) {
604                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
605
606                 dev->capability |= DWC_I2S_RECORD;
607                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
608                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
609                 dev->capture_dma_data.dt.chan_name = "RX";
610                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
611                         (fifo_width[idx2] >> 8);
612                 dev->capture_dma_data.dt.maxburst = 16;
613         }
614
615         return 0;
616
617 }
618
619 static int dw_i2s_probe(struct platform_device *pdev)
620 {
621         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
622         struct dw_i2s_dev *dev;
623         struct resource *res;
624         int ret;
625         struct snd_soc_dai_driver *dw_i2s_dai;
626         const char *clk_id;
627
628         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
629         if (!dev) {
630                 dev_warn(&pdev->dev, "kzalloc fail\n");
631                 return -ENOMEM;
632         }
633
634         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
635         if (!dw_i2s_dai)
636                 return -ENOMEM;
637
638         dw_i2s_dai->ops = &dw_i2s_dai_ops;
639         dw_i2s_dai->suspend = dw_i2s_suspend;
640         dw_i2s_dai->resume = dw_i2s_resume;
641
642         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
643         dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
644         if (IS_ERR(dev->i2s_base))
645                 return PTR_ERR(dev->i2s_base);
646
647         dev->dev = &pdev->dev;
648
649         dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
650         dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
651         if (pdata) {
652                 dev->capability = pdata->cap;
653                 clk_id = NULL;
654                 dev->quirks = pdata->quirks;
655                 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
656                         dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
657                         dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
658                 }
659                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
660         } else {
661                 clk_id = "i2sclk";
662                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
663         }
664         if (ret < 0)
665                 return ret;
666
667         if (dev->capability & DW_I2S_MASTER) {
668                 if (pdata) {
669                         dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
670                         if (!dev->i2s_clk_cfg) {
671                                 dev_err(&pdev->dev, "no clock configure method\n");
672                                 return -ENODEV;
673                         }
674                 }
675                 dev->clk = devm_clk_get(&pdev->dev, clk_id);
676
677                 if (IS_ERR(dev->clk))
678                         return PTR_ERR(dev->clk);
679
680                 ret = clk_prepare_enable(dev->clk);
681                 if (ret < 0)
682                         return ret;
683         }
684
685         dev_set_drvdata(&pdev->dev, dev);
686         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
687                                          dw_i2s_dai, 1);
688         if (ret != 0) {
689                 dev_err(&pdev->dev, "not able to register dai\n");
690                 goto err_clk_disable;
691         }
692
693         if (!pdata) {
694                 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
695                 if (ret) {
696                         dev_err(&pdev->dev,
697                                 "Could not register PCM: %d\n", ret);
698                         goto err_clk_disable;
699                 }
700         }
701         pm_runtime_enable(&pdev->dev);
702         return 0;
703
704 err_clk_disable:
705         if (dev->capability & DW_I2S_MASTER)
706                 clk_disable_unprepare(dev->clk);
707         return ret;
708 }
709
710 static int dw_i2s_remove(struct platform_device *pdev)
711 {
712         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
713
714         if (dev->capability & DW_I2S_MASTER)
715                 clk_disable_unprepare(dev->clk);
716
717         pm_runtime_disable(&pdev->dev);
718         return 0;
719 }
720
721 #ifdef CONFIG_OF
722 static const struct of_device_id dw_i2s_of_match[] = {
723         { .compatible = "snps,designware-i2s",   },
724         {},
725 };
726
727 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
728 #endif
729
730 static const struct dev_pm_ops dwc_pm_ops = {
731         SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
732 };
733
734 static struct platform_driver dw_i2s_driver = {
735         .probe          = dw_i2s_probe,
736         .remove         = dw_i2s_remove,
737         .driver         = {
738                 .name   = "designware-i2s",
739                 .of_match_table = of_match_ptr(dw_i2s_of_match),
740                 .pm = &dwc_pm_ops,
741         },
742 };
743
744 module_platform_driver(dw_i2s_driver);
745
746 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
747 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
748 MODULE_LICENSE("GPL");
749 MODULE_ALIAS("platform:designware_i2s");