2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <linux/debugfs.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/jack.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
37 #define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39 #define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48 #define ADSP1_CONTROL_1 0x00
49 #define ADSP1_CONTROL_2 0x02
50 #define ADSP1_CONTROL_3 0x03
51 #define ADSP1_CONTROL_4 0x04
52 #define ADSP1_CONTROL_5 0x06
53 #define ADSP1_CONTROL_6 0x07
54 #define ADSP1_CONTROL_7 0x08
55 #define ADSP1_CONTROL_8 0x09
56 #define ADSP1_CONTROL_9 0x0A
57 #define ADSP1_CONTROL_10 0x0B
58 #define ADSP1_CONTROL_11 0x0C
59 #define ADSP1_CONTROL_12 0x0D
60 #define ADSP1_CONTROL_13 0x0F
61 #define ADSP1_CONTROL_14 0x10
62 #define ADSP1_CONTROL_15 0x11
63 #define ADSP1_CONTROL_16 0x12
64 #define ADSP1_CONTROL_17 0x13
65 #define ADSP1_CONTROL_18 0x14
66 #define ADSP1_CONTROL_19 0x16
67 #define ADSP1_CONTROL_20 0x17
68 #define ADSP1_CONTROL_21 0x18
69 #define ADSP1_CONTROL_22 0x1A
70 #define ADSP1_CONTROL_23 0x1B
71 #define ADSP1_CONTROL_24 0x1C
72 #define ADSP1_CONTROL_25 0x1E
73 #define ADSP1_CONTROL_26 0x20
74 #define ADSP1_CONTROL_27 0x21
75 #define ADSP1_CONTROL_28 0x22
76 #define ADSP1_CONTROL_29 0x23
77 #define ADSP1_CONTROL_30 0x24
78 #define ADSP1_CONTROL_31 0x26
83 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
91 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103 #define ADSP1_START 0x0001 /* DSP1_START */
104 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
105 #define ADSP1_START_SHIFT 0 /* DSP1_START */
106 #define ADSP1_START_WIDTH 1 /* DSP1_START */
111 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
115 #define ADSP2_CONTROL 0x0
116 #define ADSP2_CLOCKING 0x1
117 #define ADSP2V2_CLOCKING 0x2
118 #define ADSP2_STATUS1 0x4
119 #define ADSP2_WDMA_CONFIG_1 0x30
120 #define ADSP2_WDMA_CONFIG_2 0x31
121 #define ADSP2V2_WDMA_CONFIG_2 0x32
122 #define ADSP2_RDMA_CONFIG_1 0x34
124 #define ADSP2_SCRATCH0 0x40
125 #define ADSP2_SCRATCH1 0x41
126 #define ADSP2_SCRATCH2 0x42
127 #define ADSP2_SCRATCH3 0x43
129 #define ADSP2V2_SCRATCH0_1 0x40
130 #define ADSP2V2_SCRATCH2_3 0x42
136 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
137 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
138 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
139 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
140 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
141 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
142 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
143 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
144 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
145 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
146 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
147 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
148 #define ADSP2_START 0x0001 /* DSP1_START */
149 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
150 #define ADSP2_START_SHIFT 0 /* DSP1_START */
151 #define ADSP2_START_WIDTH 1 /* DSP1_START */
156 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
157 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
158 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
163 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
164 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
165 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
167 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
168 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
169 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
174 #define ADSP2_RAM_RDY 0x0001
175 #define ADSP2_RAM_RDY_MASK 0x0001
176 #define ADSP2_RAM_RDY_SHIFT 0
177 #define ADSP2_RAM_RDY_WIDTH 1
182 #define ADSP2_LOCK_CODE_0 0x5555
183 #define ADSP2_LOCK_CODE_1 0xAAAA
185 #define ADSP2_WATCHDOG 0x0A
186 #define ADSP2_BUS_ERR_ADDR 0x52
187 #define ADSP2_REGION_LOCK_STATUS 0x64
188 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
189 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
190 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
191 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
192 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
193 #define ADSP2_LOCK_REGION_CTRL 0x7A
194 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
196 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
197 #define ADSP2_SLAVE_ERR_MASK 0x4000
198 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
199 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
200 #define ADSP2_CTRL_ERR_EINT 0x0001
202 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
203 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
204 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
205 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
206 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
208 #define ADSP2_LOCK_REGION_SHIFT 16
210 #define ADSP_MAX_STD_CTRL_SIZE 512
212 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
213 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
214 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
215 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
218 * Event control messages
220 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
223 struct list_head list;
227 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
228 struct list_head *list)
230 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
235 buf->buf = vmalloc(len);
240 memcpy(buf->buf, src, len);
243 list_add_tail(&buf->list, list);
248 static void wm_adsp_buf_free(struct list_head *list)
250 while (!list_empty(list)) {
251 struct wm_adsp_buf *buf = list_first_entry(list,
254 list_del(&buf->list);
260 #define WM_ADSP_FW_MBC_VSS 0
261 #define WM_ADSP_FW_HIFI 1
262 #define WM_ADSP_FW_TX 2
263 #define WM_ADSP_FW_TX_SPK 3
264 #define WM_ADSP_FW_RX 4
265 #define WM_ADSP_FW_RX_ANC 5
266 #define WM_ADSP_FW_CTRL 6
267 #define WM_ADSP_FW_ASR 7
268 #define WM_ADSP_FW_TRACE 8
269 #define WM_ADSP_FW_SPK_PROT 9
270 #define WM_ADSP_FW_MISC 10
272 #define WM_ADSP_NUM_FW 11
274 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
275 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
276 [WM_ADSP_FW_HIFI] = "MasterHiFi",
277 [WM_ADSP_FW_TX] = "Tx",
278 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
279 [WM_ADSP_FW_RX] = "Rx",
280 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
281 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
282 [WM_ADSP_FW_ASR] = "ASR Assist",
283 [WM_ADSP_FW_TRACE] = "Dbg Trace",
284 [WM_ADSP_FW_SPK_PROT] = "Protection",
285 [WM_ADSP_FW_MISC] = "Misc",
288 struct wm_adsp_system_config_xm_hdr {
294 __be32 dma_buffer_size;
297 __be32 build_job_name[3];
298 __be32 build_job_number;
301 struct wm_adsp_alg_xm_struct {
307 __be32 high_water_mark;
308 __be32 low_water_mark;
309 __be64 smoothed_power;
312 struct wm_adsp_buffer {
313 __be32 X_buf_base; /* XM base addr of first X area */
314 __be32 X_buf_size; /* Size of 1st X area in words */
315 __be32 X_buf_base2; /* XM base addr of 2nd X area */
316 __be32 X_buf_brk; /* Total X size in words */
317 __be32 Y_buf_base; /* YM base addr of Y area */
318 __be32 wrap; /* Total size X and Y in words */
319 __be32 high_water_mark; /* Point at which IRQ is asserted */
320 __be32 irq_count; /* bits 1-31 count IRQ assertions */
321 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
322 __be32 next_write_index; /* word index of next write */
323 __be32 next_read_index; /* word index of next read */
324 __be32 error; /* error if any */
325 __be32 oldest_block_index; /* word index of oldest surviving */
326 __be32 requested_rewind; /* how many blocks rewind was done */
327 __be32 reserved_space; /* internal */
328 __be32 min_free; /* min free space since stream start */
329 __be32 blocks_written[2]; /* total blocks written (64 bit) */
330 __be32 words_written[2]; /* total words written (64 bit) */
333 struct wm_adsp_compr;
335 struct wm_adsp_compr_buf {
337 struct wm_adsp_compr *compr;
339 struct wm_adsp_buffer_region *regions;
348 struct wm_adsp_compr {
350 struct wm_adsp_compr_buf *buf;
352 struct snd_compr_stream *stream;
353 struct snd_compressed_buffer size;
356 unsigned int copied_total;
358 unsigned int sample_rate;
361 #define WM_ADSP_DATA_WORD_SIZE 3
363 #define WM_ADSP_MIN_FRAGMENTS 1
364 #define WM_ADSP_MAX_FRAGMENTS 256
365 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
366 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
368 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
370 #define HOST_BUFFER_FIELD(field) \
371 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
373 #define ALG_XM_FIELD(field) \
374 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
376 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
377 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
379 struct wm_adsp_buffer_region {
381 unsigned int cumulative_size;
382 unsigned int mem_type;
383 unsigned int base_addr;
386 struct wm_adsp_buffer_region_def {
387 unsigned int mem_type;
388 unsigned int base_offset;
389 unsigned int size_offset;
392 static const struct wm_adsp_buffer_region_def default_regions[] = {
394 .mem_type = WMFW_ADSP2_XM,
395 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
396 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
399 .mem_type = WMFW_ADSP2_XM,
400 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
401 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
404 .mem_type = WMFW_ADSP2_YM,
405 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
406 .size_offset = HOST_BUFFER_FIELD(wrap),
410 struct wm_adsp_fw_caps {
412 struct snd_codec_desc desc;
414 const struct wm_adsp_buffer_region_def *region_defs;
417 static const struct wm_adsp_fw_caps ctrl_caps[] = {
419 .id = SND_AUDIOCODEC_BESPOKE,
422 .sample_rates = { 16000 },
423 .num_sample_rates = 1,
424 .formats = SNDRV_PCM_FMTBIT_S16_LE,
426 .num_regions = ARRAY_SIZE(default_regions),
427 .region_defs = default_regions,
431 static const struct wm_adsp_fw_caps trace_caps[] = {
433 .id = SND_AUDIOCODEC_BESPOKE,
437 4000, 8000, 11025, 12000, 16000, 22050,
438 24000, 32000, 44100, 48000, 64000, 88200,
439 96000, 176400, 192000
441 .num_sample_rates = 15,
442 .formats = SNDRV_PCM_FMTBIT_S16_LE,
444 .num_regions = ARRAY_SIZE(default_regions),
445 .region_defs = default_regions,
449 static const struct {
453 const struct wm_adsp_fw_caps *caps;
455 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
456 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
457 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
458 [WM_ADSP_FW_TX] = { .file = "tx" },
459 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
460 [WM_ADSP_FW_RX] = { .file = "rx" },
461 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
462 [WM_ADSP_FW_CTRL] = {
464 .compr_direction = SND_COMPRESS_CAPTURE,
465 .num_caps = ARRAY_SIZE(ctrl_caps),
467 .voice_trigger = true,
469 [WM_ADSP_FW_ASR] = { .file = "asr" },
470 [WM_ADSP_FW_TRACE] = {
472 .compr_direction = SND_COMPRESS_CAPTURE,
473 .num_caps = ARRAY_SIZE(trace_caps),
476 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
477 [WM_ADSP_FW_MISC] = { .file = "misc" },
480 struct wm_coeff_ctl_ops {
481 int (*xget)(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol);
483 int (*xput)(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol);
485 int (*xinfo)(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_info *uinfo);
489 struct wm_coeff_ctl {
492 struct wm_adsp_alg_region alg_region;
493 struct wm_coeff_ctl_ops ops;
495 unsigned int enabled:1;
496 struct list_head list;
501 struct soc_bytes_ext bytes_ext;
506 static const char *wm_adsp_mem_region_name(unsigned int type)
524 #ifdef CONFIG_DEBUG_FS
525 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
527 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
529 kfree(dsp->wmfw_file_name);
530 dsp->wmfw_file_name = tmp;
533 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
535 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
537 kfree(dsp->bin_file_name);
538 dsp->bin_file_name = tmp;
541 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
543 kfree(dsp->wmfw_file_name);
544 kfree(dsp->bin_file_name);
545 dsp->wmfw_file_name = NULL;
546 dsp->bin_file_name = NULL;
549 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
550 char __user *user_buf,
551 size_t count, loff_t *ppos)
553 struct wm_adsp *dsp = file->private_data;
556 mutex_lock(&dsp->pwr_lock);
558 if (!dsp->wmfw_file_name || !dsp->booted)
561 ret = simple_read_from_buffer(user_buf, count, ppos,
563 strlen(dsp->wmfw_file_name));
565 mutex_unlock(&dsp->pwr_lock);
569 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
570 char __user *user_buf,
571 size_t count, loff_t *ppos)
573 struct wm_adsp *dsp = file->private_data;
576 mutex_lock(&dsp->pwr_lock);
578 if (!dsp->bin_file_name || !dsp->booted)
581 ret = simple_read_from_buffer(user_buf, count, ppos,
583 strlen(dsp->bin_file_name));
585 mutex_unlock(&dsp->pwr_lock);
589 static const struct {
591 const struct file_operations fops;
592 } wm_adsp_debugfs_fops[] = {
594 .name = "wmfw_file_name",
597 .read = wm_adsp_debugfs_wmfw_read,
601 .name = "bin_file_name",
604 .read = wm_adsp_debugfs_bin_read,
609 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
610 struct snd_soc_codec *codec)
612 struct dentry *root = NULL;
616 if (!codec->component.debugfs_root) {
617 adsp_err(dsp, "No codec debugfs root\n");
621 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
625 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
626 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
632 if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
635 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
638 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
641 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
642 &dsp->fw_id_version))
645 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
646 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
648 &wm_adsp_debugfs_fops[i].fops))
652 dsp->debugfs_root = root;
656 debugfs_remove_recursive(root);
657 adsp_err(dsp, "Failed to create debugfs\n");
660 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
662 wm_adsp_debugfs_clear(dsp);
663 debugfs_remove_recursive(dsp->debugfs_root);
666 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
667 struct snd_soc_codec *codec)
671 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
675 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
680 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
685 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
690 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
691 struct snd_ctl_elem_value *ucontrol)
693 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
694 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
695 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
697 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
702 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
703 struct snd_ctl_elem_value *ucontrol)
705 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
706 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
707 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
710 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
713 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
716 mutex_lock(&dsp[e->shift_l].pwr_lock);
718 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
721 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
723 mutex_unlock(&dsp[e->shift_l].pwr_lock);
728 static const struct soc_enum wm_adsp_fw_enum[] = {
729 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
730 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
731 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
732 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
733 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
734 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
735 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
738 const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
739 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
740 wm_adsp_fw_get, wm_adsp_fw_put),
741 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
742 wm_adsp_fw_get, wm_adsp_fw_put),
743 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
744 wm_adsp_fw_get, wm_adsp_fw_put),
745 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
746 wm_adsp_fw_get, wm_adsp_fw_put),
747 SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4],
748 wm_adsp_fw_get, wm_adsp_fw_put),
749 SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5],
750 wm_adsp_fw_get, wm_adsp_fw_put),
751 SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6],
752 wm_adsp_fw_get, wm_adsp_fw_put),
754 EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
756 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
761 for (i = 0; i < dsp->num_mems; i++)
762 if (dsp->mem[i].type == type)
768 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
775 return mem->base + (offset * 3);
777 return mem->base + (offset * 2);
779 return mem->base + (offset * 2);
781 return mem->base + (offset * 2);
783 return mem->base + (offset * 2);
785 WARN(1, "Unknown memory region type");
790 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
795 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
796 scratch, sizeof(scratch));
798 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
802 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
803 be16_to_cpu(scratch[0]),
804 be16_to_cpu(scratch[1]),
805 be16_to_cpu(scratch[2]),
806 be16_to_cpu(scratch[3]));
809 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
814 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
815 scratch, sizeof(scratch));
818 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
822 scratch[0] = be32_to_cpu(scratch[0]);
823 scratch[1] = be32_to_cpu(scratch[1]);
825 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
832 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
834 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
837 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
839 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
840 struct wm_adsp *dsp = ctl->dsp;
841 const struct wm_adsp_region *mem;
843 mem = wm_adsp_find_region(dsp, alg_region->type);
845 adsp_err(dsp, "No base for region %x\n",
850 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
855 static int wm_coeff_info(struct snd_kcontrol *kctl,
856 struct snd_ctl_elem_info *uinfo)
858 struct soc_bytes_ext *bytes_ext =
859 (struct soc_bytes_ext *)kctl->private_value;
860 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
863 case WMFW_CTL_TYPE_ACKED:
864 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
865 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
866 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
867 uinfo->value.integer.step = 1;
871 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
872 uinfo->count = ctl->len;
879 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
880 unsigned int event_id)
882 struct wm_adsp *dsp = ctl->dsp;
883 u32 val = cpu_to_be32(event_id);
887 ret = wm_coeff_base_reg(ctl, ®);
891 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
892 event_id, ctl->alg_region.alg,
893 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
895 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
897 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
902 * Poll for ack, we initially poll at ~1ms intervals for firmwares
903 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
904 * to ack instantly so we do the first 1ms delay before reading the
905 * control to avoid a pointless bus transaction
907 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
909 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
910 usleep_range(1000, 2000);
914 usleep_range(10000, 20000);
919 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
921 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
926 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
931 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
932 reg, ctl->alg_region.alg,
933 wm_adsp_mem_region_name(ctl->alg_region.type),
939 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
940 const void *buf, size_t len)
942 struct wm_adsp *dsp = ctl->dsp;
947 ret = wm_coeff_base_reg(ctl, ®);
951 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
955 ret = regmap_raw_write(dsp->regmap, reg, scratch,
958 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
963 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
970 static int wm_coeff_put(struct snd_kcontrol *kctl,
971 struct snd_ctl_elem_value *ucontrol)
973 struct soc_bytes_ext *bytes_ext =
974 (struct soc_bytes_ext *)kctl->private_value;
975 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
976 char *p = ucontrol->value.bytes.data;
979 mutex_lock(&ctl->dsp->pwr_lock);
981 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
984 memcpy(ctl->cache, p, ctl->len);
987 if (ctl->enabled && ctl->dsp->running)
988 ret = wm_coeff_write_control(ctl, p, ctl->len);
990 mutex_unlock(&ctl->dsp->pwr_lock);
995 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
996 const unsigned int __user *bytes, unsigned int size)
998 struct soc_bytes_ext *bytes_ext =
999 (struct soc_bytes_ext *)kctl->private_value;
1000 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1003 mutex_lock(&ctl->dsp->pwr_lock);
1005 if (copy_from_user(ctl->cache, bytes, size)) {
1009 if (ctl->enabled && ctl->dsp->running)
1010 ret = wm_coeff_write_control(ctl, ctl->cache, size);
1011 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1015 mutex_unlock(&ctl->dsp->pwr_lock);
1020 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1021 struct snd_ctl_elem_value *ucontrol)
1023 struct soc_bytes_ext *bytes_ext =
1024 (struct soc_bytes_ext *)kctl->private_value;
1025 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1026 unsigned int val = ucontrol->value.integer.value[0];
1030 return 0; /* 0 means no event */
1032 mutex_lock(&ctl->dsp->pwr_lock);
1034 if (ctl->enabled && ctl->dsp->running)
1035 ret = wm_coeff_write_acked_control(ctl, val);
1039 mutex_unlock(&ctl->dsp->pwr_lock);
1044 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1045 void *buf, size_t len)
1047 struct wm_adsp *dsp = ctl->dsp;
1052 ret = wm_coeff_base_reg(ctl, ®);
1056 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1060 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1062 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1067 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1069 memcpy(buf, scratch, len);
1075 static int wm_coeff_get(struct snd_kcontrol *kctl,
1076 struct snd_ctl_elem_value *ucontrol)
1078 struct soc_bytes_ext *bytes_ext =
1079 (struct soc_bytes_ext *)kctl->private_value;
1080 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1081 char *p = ucontrol->value.bytes.data;
1084 mutex_lock(&ctl->dsp->pwr_lock);
1086 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1087 if (ctl->enabled && ctl->dsp->running)
1088 ret = wm_coeff_read_control(ctl, p, ctl->len);
1092 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1093 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1095 memcpy(p, ctl->cache, ctl->len);
1098 mutex_unlock(&ctl->dsp->pwr_lock);
1103 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1104 unsigned int __user *bytes, unsigned int size)
1106 struct soc_bytes_ext *bytes_ext =
1107 (struct soc_bytes_ext *)kctl->private_value;
1108 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1111 mutex_lock(&ctl->dsp->pwr_lock);
1113 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1114 if (ctl->enabled && ctl->dsp->running)
1115 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1119 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1120 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1123 if (!ret && copy_to_user(bytes, ctl->cache, size))
1126 mutex_unlock(&ctl->dsp->pwr_lock);
1131 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1132 struct snd_ctl_elem_value *ucontrol)
1135 * Although it's not useful to read an acked control, we must satisfy
1136 * user-side assumptions that all controls are readable and that a
1137 * write of the same value should be filtered out (it's valid to send
1138 * the same event number again to the firmware). We therefore return 0,
1139 * meaning "no event" so valid event numbers will always be a change
1141 ucontrol->value.integer.value[0] = 0;
1146 struct wmfw_ctl_work {
1147 struct wm_adsp *dsp;
1148 struct wm_coeff_ctl *ctl;
1149 struct work_struct work;
1152 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1154 unsigned int out, rd, wr, vol;
1156 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1157 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1158 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1159 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1161 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1163 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1164 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1165 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1171 if (in & WMFW_CTL_FLAG_READABLE)
1173 if (in & WMFW_CTL_FLAG_WRITEABLE)
1175 if (in & WMFW_CTL_FLAG_VOLATILE)
1178 out |= rd | wr | vol;
1184 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1186 struct snd_kcontrol_new *kcontrol;
1189 if (!ctl || !ctl->name)
1192 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1196 kcontrol->name = ctl->name;
1197 kcontrol->info = wm_coeff_info;
1198 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1199 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1200 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1201 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1203 switch (ctl->type) {
1204 case WMFW_CTL_TYPE_ACKED:
1205 kcontrol->get = wm_coeff_get_acked;
1206 kcontrol->put = wm_coeff_put_acked;
1209 kcontrol->get = wm_coeff_get;
1210 kcontrol->put = wm_coeff_put;
1212 ctl->bytes_ext.max = ctl->len;
1213 ctl->bytes_ext.get = wm_coeff_tlv_get;
1214 ctl->bytes_ext.put = wm_coeff_tlv_put;
1218 ret = snd_soc_add_codec_controls(dsp->codec, kcontrol, 1);
1231 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1233 struct wm_coeff_ctl *ctl;
1236 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1237 if (!ctl->enabled || ctl->set)
1239 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1242 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1250 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1252 struct wm_coeff_ctl *ctl;
1255 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1258 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1259 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1268 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1271 struct wm_coeff_ctl *ctl;
1274 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1275 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1281 ret = wm_coeff_write_acked_control(ctl, event);
1284 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1285 event, ctl->alg_region.alg, ret);
1289 static void wm_adsp_ctl_work(struct work_struct *work)
1291 struct wmfw_ctl_work *ctl_work = container_of(work,
1292 struct wmfw_ctl_work,
1295 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1299 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1306 static int wm_adsp_create_control(struct wm_adsp *dsp,
1307 const struct wm_adsp_alg_region *alg_region,
1308 unsigned int offset, unsigned int len,
1309 const char *subname, unsigned int subname_len,
1310 unsigned int flags, unsigned int type)
1312 struct wm_coeff_ctl *ctl;
1313 struct wmfw_ctl_work *ctl_work;
1314 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1315 const char *region_name;
1318 region_name = wm_adsp_mem_region_name(alg_region->type);
1320 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1324 switch (dsp->fw_ver) {
1327 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1328 dsp->num, region_name, alg_region->alg);
1331 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1332 "DSP%d%c %.12s %x", dsp->num, *region_name,
1333 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1335 /* Truncate the subname from the start if it is too long */
1337 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1340 if (subname_len > avail)
1341 skip = subname_len - avail;
1343 snprintf(name + ret,
1344 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1345 subname_len - skip, subname + skip);
1350 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1351 if (!strcmp(ctl->name, name)) {
1358 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1361 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1362 ctl->alg_region = *alg_region;
1363 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1370 ctl->ops.xget = wm_coeff_get;
1371 ctl->ops.xput = wm_coeff_put;
1376 ctl->offset = offset;
1378 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1384 list_add(&ctl->list, &dsp->ctl_list);
1386 if (flags & WMFW_CTL_FLAG_SYS)
1389 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1395 ctl_work->dsp = dsp;
1396 ctl_work->ctl = ctl;
1397 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1398 schedule_work(&ctl_work->work);
1412 struct wm_coeff_parsed_alg {
1419 struct wm_coeff_parsed_coeff {
1429 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1438 length = le16_to_cpu(*((__le16 *)*pos));
1445 *str = *pos + bytes;
1447 *pos += ((length + bytes) + 3) & ~0x03;
1452 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1458 val = le16_to_cpu(*((__le16 *)*pos));
1461 val = le32_to_cpu(*((__le32 *)*pos));
1472 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1473 struct wm_coeff_parsed_alg *blk)
1475 const struct wmfw_adsp_alg_data *raw;
1477 switch (dsp->fw_ver) {
1480 raw = (const struct wmfw_adsp_alg_data *)*data;
1483 blk->id = le32_to_cpu(raw->id);
1484 blk->name = raw->name;
1485 blk->name_len = strlen(raw->name);
1486 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1489 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1490 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1492 wm_coeff_parse_string(sizeof(u16), data, NULL);
1493 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1497 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1498 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1499 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1502 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1503 struct wm_coeff_parsed_coeff *blk)
1505 const struct wmfw_adsp_coeff_data *raw;
1509 switch (dsp->fw_ver) {
1512 raw = (const struct wmfw_adsp_coeff_data *)*data;
1513 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1515 blk->offset = le16_to_cpu(raw->hdr.offset);
1516 blk->mem_type = le16_to_cpu(raw->hdr.type);
1517 blk->name = raw->name;
1518 blk->name_len = strlen(raw->name);
1519 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1520 blk->flags = le16_to_cpu(raw->flags);
1521 blk->len = le32_to_cpu(raw->len);
1525 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1526 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1527 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1528 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1530 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1531 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1532 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1533 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1534 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1536 *data = *data + sizeof(raw->hdr) + length;
1540 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1541 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1542 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1543 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1544 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1545 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1548 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1549 const struct wm_coeff_parsed_coeff *coeff_blk,
1550 unsigned int f_required,
1551 unsigned int f_illegal)
1553 if ((coeff_blk->flags & f_illegal) ||
1554 ((coeff_blk->flags & f_required) != f_required)) {
1555 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1556 coeff_blk->flags, coeff_blk->ctl_type);
1563 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1564 const struct wmfw_region *region)
1566 struct wm_adsp_alg_region alg_region = {};
1567 struct wm_coeff_parsed_alg alg_blk;
1568 struct wm_coeff_parsed_coeff coeff_blk;
1569 const u8 *data = region->data;
1572 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1573 for (i = 0; i < alg_blk.ncoeff; i++) {
1574 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1576 switch (coeff_blk.ctl_type) {
1577 case SNDRV_CTL_ELEM_TYPE_BYTES:
1579 case WMFW_CTL_TYPE_ACKED:
1580 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1581 continue; /* ignore */
1583 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1584 WMFW_CTL_FLAG_VOLATILE |
1585 WMFW_CTL_FLAG_WRITEABLE |
1586 WMFW_CTL_FLAG_READABLE,
1591 case WMFW_CTL_TYPE_HOSTEVENT:
1592 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1594 WMFW_CTL_FLAG_VOLATILE |
1595 WMFW_CTL_FLAG_WRITEABLE |
1596 WMFW_CTL_FLAG_READABLE,
1602 adsp_err(dsp, "Unknown control type: %d\n",
1603 coeff_blk.ctl_type);
1607 alg_region.type = coeff_blk.mem_type;
1608 alg_region.alg = alg_blk.id;
1610 ret = wm_adsp_create_control(dsp, &alg_region,
1616 coeff_blk.ctl_type);
1618 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1619 coeff_blk.name_len, coeff_blk.name, ret);
1625 static int wm_adsp_load(struct wm_adsp *dsp)
1627 LIST_HEAD(buf_list);
1628 const struct firmware *firmware;
1629 struct regmap *regmap = dsp->regmap;
1630 unsigned int pos = 0;
1631 const struct wmfw_header *header;
1632 const struct wmfw_adsp1_sizes *adsp1_sizes;
1633 const struct wmfw_adsp2_sizes *adsp2_sizes;
1634 const struct wmfw_footer *footer;
1635 const struct wmfw_region *region;
1636 const struct wm_adsp_region *mem;
1637 const char *region_name;
1638 char *file, *text = NULL;
1639 struct wm_adsp_buf *buf;
1642 int ret, offset, type, sizes;
1644 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1648 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1649 wm_adsp_fw[dsp->fw].file);
1650 file[PAGE_SIZE - 1] = '\0';
1652 ret = request_firmware(&firmware, file, dsp->dev);
1654 adsp_err(dsp, "Failed to request '%s'\n", file);
1659 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1660 if (pos >= firmware->size) {
1661 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1662 file, firmware->size);
1666 header = (void *)&firmware->data[0];
1668 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1669 adsp_err(dsp, "%s: invalid magic\n", file);
1673 switch (header->ver) {
1675 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1682 adsp_err(dsp, "%s: unknown file format %d\n",
1687 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1688 dsp->fw_ver = header->ver;
1690 if (header->core != dsp->type) {
1691 adsp_err(dsp, "%s: invalid core %d != %d\n",
1692 file, header->core, dsp->type);
1696 switch (dsp->type) {
1698 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1699 adsp1_sizes = (void *)&(header[1]);
1700 footer = (void *)&(adsp1_sizes[1]);
1701 sizes = sizeof(*adsp1_sizes);
1703 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1704 file, le32_to_cpu(adsp1_sizes->dm),
1705 le32_to_cpu(adsp1_sizes->pm),
1706 le32_to_cpu(adsp1_sizes->zm));
1710 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1711 adsp2_sizes = (void *)&(header[1]);
1712 footer = (void *)&(adsp2_sizes[1]);
1713 sizes = sizeof(*adsp2_sizes);
1715 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1716 file, le32_to_cpu(adsp2_sizes->xm),
1717 le32_to_cpu(adsp2_sizes->ym),
1718 le32_to_cpu(adsp2_sizes->pm),
1719 le32_to_cpu(adsp2_sizes->zm));
1723 WARN(1, "Unknown DSP type");
1727 if (le32_to_cpu(header->len) != sizeof(*header) +
1728 sizes + sizeof(*footer)) {
1729 adsp_err(dsp, "%s: unexpected header length %d\n",
1730 file, le32_to_cpu(header->len));
1734 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1735 le64_to_cpu(footer->timestamp));
1737 while (pos < firmware->size &&
1738 pos - firmware->size > sizeof(*region)) {
1739 region = (void *)&(firmware->data[pos]);
1740 region_name = "Unknown";
1743 offset = le32_to_cpu(region->offset) & 0xffffff;
1744 type = be32_to_cpu(region->type) & 0xff;
1745 mem = wm_adsp_find_region(dsp, type);
1748 case WMFW_NAME_TEXT:
1749 region_name = "Firmware name";
1750 text = kzalloc(le32_to_cpu(region->len) + 1,
1753 case WMFW_ALGORITHM_DATA:
1754 region_name = "Algorithm";
1755 ret = wm_adsp_parse_coeff(dsp, region);
1759 case WMFW_INFO_TEXT:
1760 region_name = "Information";
1761 text = kzalloc(le32_to_cpu(region->len) + 1,
1765 region_name = "Absolute";
1773 region_name = wm_adsp_mem_region_name(type);
1774 reg = wm_adsp_region_to_reg(mem, offset);
1778 "%s.%d: Unknown region type %x at %d(%x)\n",
1779 file, regions, type, pos, pos);
1783 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1784 regions, le32_to_cpu(region->len), offset,
1787 if ((pos + le32_to_cpu(region->len) + sizeof(*region)) >
1790 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1791 file, regions, region_name,
1792 le32_to_cpu(region->len), firmware->size);
1798 memcpy(text, region->data, le32_to_cpu(region->len));
1799 adsp_info(dsp, "%s: %s\n", file, text);
1805 buf = wm_adsp_buf_alloc(region->data,
1806 le32_to_cpu(region->len),
1809 adsp_err(dsp, "Out of memory\n");
1814 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1815 le32_to_cpu(region->len));
1818 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1820 le32_to_cpu(region->len), offset,
1826 pos += le32_to_cpu(region->len) + sizeof(*region);
1830 ret = regmap_async_complete(regmap);
1832 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1836 if (pos > firmware->size)
1837 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1838 file, regions, pos - firmware->size);
1840 wm_adsp_debugfs_save_wmfwname(dsp, file);
1843 regmap_async_complete(regmap);
1844 wm_adsp_buf_free(&buf_list);
1845 release_firmware(firmware);
1853 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1854 const struct wm_adsp_alg_region *alg_region)
1856 struct wm_coeff_ctl *ctl;
1858 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1859 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1860 alg_region->alg == ctl->alg_region.alg &&
1861 alg_region->type == ctl->alg_region.type) {
1862 ctl->alg_region.base = alg_region->base;
1867 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1868 unsigned int pos, unsigned int len)
1875 adsp_err(dsp, "No algorithms\n");
1876 return ERR_PTR(-EINVAL);
1879 if (n_algs > 1024) {
1880 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1881 return ERR_PTR(-EINVAL);
1884 /* Read the terminator first to validate the length */
1885 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1887 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1889 return ERR_PTR(ret);
1892 if (be32_to_cpu(val) != 0xbedead)
1893 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1894 pos + len, be32_to_cpu(val));
1896 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1898 return ERR_PTR(-ENOMEM);
1900 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1902 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
1904 return ERR_PTR(ret);
1910 static struct wm_adsp_alg_region *
1911 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1913 struct wm_adsp_alg_region *alg_region;
1915 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1916 if (id == alg_region->alg && type == alg_region->type)
1923 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1924 int type, __be32 id,
1927 struct wm_adsp_alg_region *alg_region;
1929 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1931 return ERR_PTR(-ENOMEM);
1933 alg_region->type = type;
1934 alg_region->alg = be32_to_cpu(id);
1935 alg_region->base = be32_to_cpu(base);
1937 list_add_tail(&alg_region->list, &dsp->alg_regions);
1939 if (dsp->fw_ver > 0)
1940 wm_adsp_ctl_fixup_base(dsp, alg_region);
1945 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1947 struct wm_adsp_alg_region *alg_region;
1949 while (!list_empty(&dsp->alg_regions)) {
1950 alg_region = list_first_entry(&dsp->alg_regions,
1951 struct wm_adsp_alg_region,
1953 list_del(&alg_region->list);
1958 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1960 struct wmfw_adsp1_id_hdr adsp1_id;
1961 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1962 struct wm_adsp_alg_region *alg_region;
1963 const struct wm_adsp_region *mem;
1964 unsigned int pos, len;
1968 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1972 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1975 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1980 n_algs = be32_to_cpu(adsp1_id.n_algs);
1981 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1982 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1984 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1985 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1986 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
1989 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1990 adsp1_id.fw.id, adsp1_id.zm);
1991 if (IS_ERR(alg_region))
1992 return PTR_ERR(alg_region);
1994 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1995 adsp1_id.fw.id, adsp1_id.dm);
1996 if (IS_ERR(alg_region))
1997 return PTR_ERR(alg_region);
1999 pos = sizeof(adsp1_id) / 2;
2000 len = (sizeof(*adsp1_alg) * n_algs) / 2;
2002 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
2003 if (IS_ERR(adsp1_alg))
2004 return PTR_ERR(adsp1_alg);
2006 for (i = 0; i < n_algs; i++) {
2007 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2008 i, be32_to_cpu(adsp1_alg[i].alg.id),
2009 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2010 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2011 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2012 be32_to_cpu(adsp1_alg[i].dm),
2013 be32_to_cpu(adsp1_alg[i].zm));
2015 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2016 adsp1_alg[i].alg.id,
2018 if (IS_ERR(alg_region)) {
2019 ret = PTR_ERR(alg_region);
2022 if (dsp->fw_ver == 0) {
2023 if (i + 1 < n_algs) {
2024 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2025 len -= be32_to_cpu(adsp1_alg[i].dm);
2027 wm_adsp_create_control(dsp, alg_region, 0,
2029 SNDRV_CTL_ELEM_TYPE_BYTES);
2031 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2032 be32_to_cpu(adsp1_alg[i].alg.id));
2036 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2037 adsp1_alg[i].alg.id,
2039 if (IS_ERR(alg_region)) {
2040 ret = PTR_ERR(alg_region);
2043 if (dsp->fw_ver == 0) {
2044 if (i + 1 < n_algs) {
2045 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2046 len -= be32_to_cpu(adsp1_alg[i].zm);
2048 wm_adsp_create_control(dsp, alg_region, 0,
2050 SNDRV_CTL_ELEM_TYPE_BYTES);
2052 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2053 be32_to_cpu(adsp1_alg[i].alg.id));
2063 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2065 struct wmfw_adsp2_id_hdr adsp2_id;
2066 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2067 struct wm_adsp_alg_region *alg_region;
2068 const struct wm_adsp_region *mem;
2069 unsigned int pos, len;
2073 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2077 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2080 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2085 n_algs = be32_to_cpu(adsp2_id.n_algs);
2086 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
2087 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
2088 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2090 (dsp->fw_id_version & 0xff0000) >> 16,
2091 (dsp->fw_id_version & 0xff00) >> 8,
2092 dsp->fw_id_version & 0xff,
2095 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2096 adsp2_id.fw.id, adsp2_id.xm);
2097 if (IS_ERR(alg_region))
2098 return PTR_ERR(alg_region);
2100 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2101 adsp2_id.fw.id, adsp2_id.ym);
2102 if (IS_ERR(alg_region))
2103 return PTR_ERR(alg_region);
2105 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2106 adsp2_id.fw.id, adsp2_id.zm);
2107 if (IS_ERR(alg_region))
2108 return PTR_ERR(alg_region);
2110 pos = sizeof(adsp2_id) / 2;
2111 len = (sizeof(*adsp2_alg) * n_algs) / 2;
2113 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
2114 if (IS_ERR(adsp2_alg))
2115 return PTR_ERR(adsp2_alg);
2117 for (i = 0; i < n_algs; i++) {
2119 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2120 i, be32_to_cpu(adsp2_alg[i].alg.id),
2121 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2122 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2123 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2124 be32_to_cpu(adsp2_alg[i].xm),
2125 be32_to_cpu(adsp2_alg[i].ym),
2126 be32_to_cpu(adsp2_alg[i].zm));
2128 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2129 adsp2_alg[i].alg.id,
2131 if (IS_ERR(alg_region)) {
2132 ret = PTR_ERR(alg_region);
2135 if (dsp->fw_ver == 0) {
2136 if (i + 1 < n_algs) {
2137 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2138 len -= be32_to_cpu(adsp2_alg[i].xm);
2140 wm_adsp_create_control(dsp, alg_region, 0,
2142 SNDRV_CTL_ELEM_TYPE_BYTES);
2144 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2145 be32_to_cpu(adsp2_alg[i].alg.id));
2149 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2150 adsp2_alg[i].alg.id,
2152 if (IS_ERR(alg_region)) {
2153 ret = PTR_ERR(alg_region);
2156 if (dsp->fw_ver == 0) {
2157 if (i + 1 < n_algs) {
2158 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2159 len -= be32_to_cpu(adsp2_alg[i].ym);
2161 wm_adsp_create_control(dsp, alg_region, 0,
2163 SNDRV_CTL_ELEM_TYPE_BYTES);
2165 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2166 be32_to_cpu(adsp2_alg[i].alg.id));
2170 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2171 adsp2_alg[i].alg.id,
2173 if (IS_ERR(alg_region)) {
2174 ret = PTR_ERR(alg_region);
2177 if (dsp->fw_ver == 0) {
2178 if (i + 1 < n_algs) {
2179 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2180 len -= be32_to_cpu(adsp2_alg[i].zm);
2182 wm_adsp_create_control(dsp, alg_region, 0,
2184 SNDRV_CTL_ELEM_TYPE_BYTES);
2186 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2187 be32_to_cpu(adsp2_alg[i].alg.id));
2197 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2199 LIST_HEAD(buf_list);
2200 struct regmap *regmap = dsp->regmap;
2201 struct wmfw_coeff_hdr *hdr;
2202 struct wmfw_coeff_item *blk;
2203 const struct firmware *firmware;
2204 const struct wm_adsp_region *mem;
2205 struct wm_adsp_alg_region *alg_region;
2206 const char *region_name;
2207 int ret, pos, blocks, type, offset, reg;
2209 struct wm_adsp_buf *buf;
2211 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2215 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2216 wm_adsp_fw[dsp->fw].file);
2217 file[PAGE_SIZE - 1] = '\0';
2219 ret = request_firmware(&firmware, file, dsp->dev);
2221 adsp_warn(dsp, "Failed to request '%s'\n", file);
2227 if (sizeof(*hdr) >= firmware->size) {
2228 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2229 file, firmware->size);
2233 hdr = (void *)&firmware->data[0];
2234 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2235 adsp_err(dsp, "%s: invalid magic\n", file);
2239 switch (be32_to_cpu(hdr->rev) & 0xff) {
2243 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2244 file, be32_to_cpu(hdr->rev) & 0xff);
2249 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2250 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2251 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2252 le32_to_cpu(hdr->ver) & 0xff);
2254 pos = le32_to_cpu(hdr->len);
2257 while (pos < firmware->size &&
2258 pos - firmware->size > sizeof(*blk)) {
2259 blk = (void *)(&firmware->data[pos]);
2261 type = le16_to_cpu(blk->type);
2262 offset = le16_to_cpu(blk->offset);
2264 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2265 file, blocks, le32_to_cpu(blk->id),
2266 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2267 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2268 le32_to_cpu(blk->ver) & 0xff);
2269 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2270 file, blocks, le32_to_cpu(blk->len), offset, type);
2273 region_name = "Unknown";
2275 case (WMFW_NAME_TEXT << 8):
2276 case (WMFW_INFO_TEXT << 8):
2278 case (WMFW_ABSOLUTE << 8):
2280 * Old files may use this for global
2283 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2285 region_name = "global coefficients";
2286 mem = wm_adsp_find_region(dsp, type);
2288 adsp_err(dsp, "No ZM\n");
2291 reg = wm_adsp_region_to_reg(mem, 0);
2294 region_name = "register";
2303 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2304 file, blocks, le32_to_cpu(blk->len),
2305 type, le32_to_cpu(blk->id));
2307 mem = wm_adsp_find_region(dsp, type);
2309 adsp_err(dsp, "No base for region %x\n", type);
2313 alg_region = wm_adsp_find_alg_region(dsp, type,
2314 le32_to_cpu(blk->id));
2316 reg = alg_region->base;
2317 reg = wm_adsp_region_to_reg(mem, reg);
2320 adsp_err(dsp, "No %x for algorithm %x\n",
2321 type, le32_to_cpu(blk->id));
2326 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2327 file, blocks, type, pos);
2332 if ((pos + le32_to_cpu(blk->len) + sizeof(*blk)) >
2335 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2336 file, blocks, region_name,
2337 le32_to_cpu(blk->len),
2343 buf = wm_adsp_buf_alloc(blk->data,
2344 le32_to_cpu(blk->len),
2347 adsp_err(dsp, "Out of memory\n");
2352 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2353 file, blocks, le32_to_cpu(blk->len),
2355 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2356 le32_to_cpu(blk->len));
2359 "%s.%d: Failed to write to %x in %s: %d\n",
2360 file, blocks, reg, region_name, ret);
2364 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2368 ret = regmap_async_complete(regmap);
2370 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2372 if (pos > firmware->size)
2373 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2374 file, blocks, pos - firmware->size);
2376 wm_adsp_debugfs_save_binname(dsp, file);
2379 regmap_async_complete(regmap);
2380 release_firmware(firmware);
2381 wm_adsp_buf_free(&buf_list);
2387 int wm_adsp1_init(struct wm_adsp *dsp)
2389 INIT_LIST_HEAD(&dsp->alg_regions);
2391 mutex_init(&dsp->pwr_lock);
2395 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2397 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2398 struct snd_kcontrol *kcontrol,
2401 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2402 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2403 struct wm_adsp *dsp = &dsps[w->shift];
2404 struct wm_coeff_ctl *ctl;
2410 mutex_lock(&dsp->pwr_lock);
2413 case SND_SOC_DAPM_POST_PMU:
2414 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2415 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2418 * For simplicity set the DSP clock rate to be the
2419 * SYSCLK rate rather than making it configurable.
2421 if (dsp->sysclk_reg) {
2422 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2424 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2429 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2431 ret = regmap_update_bits(dsp->regmap,
2432 dsp->base + ADSP1_CONTROL_31,
2433 ADSP1_CLK_SEL_MASK, val);
2435 adsp_err(dsp, "Failed to set clock rate: %d\n",
2441 ret = wm_adsp_load(dsp);
2445 ret = wm_adsp1_setup_algs(dsp);
2449 ret = wm_adsp_load_coeff(dsp);
2453 /* Initialize caches for enabled and unset controls */
2454 ret = wm_coeff_init_control_caches(dsp);
2458 /* Sync set controls */
2459 ret = wm_coeff_sync_controls(dsp);
2465 /* Start the core running */
2466 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2467 ADSP1_CORE_ENA | ADSP1_START,
2468 ADSP1_CORE_ENA | ADSP1_START);
2470 dsp->running = true;
2473 case SND_SOC_DAPM_PRE_PMD:
2474 dsp->running = false;
2475 dsp->booted = false;
2478 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2479 ADSP1_CORE_ENA | ADSP1_START, 0);
2481 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2482 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2484 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2487 list_for_each_entry(ctl, &dsp->ctl_list, list)
2491 wm_adsp_free_alg_regions(dsp);
2498 mutex_unlock(&dsp->pwr_lock);
2503 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2506 mutex_unlock(&dsp->pwr_lock);
2510 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2512 static int wm_adsp2_ena(struct wm_adsp *dsp)
2519 ret = regmap_update_bits_async(dsp->regmap,
2520 dsp->base + ADSP2_CONTROL,
2521 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2529 /* Wait for the RAM to start, should be near instantaneous */
2530 for (count = 0; count < 10; ++count) {
2531 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2535 if (val & ADSP2_RAM_RDY)
2538 usleep_range(250, 500);
2541 if (!(val & ADSP2_RAM_RDY)) {
2542 adsp_err(dsp, "Failed to start DSP RAM\n");
2546 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2551 static void wm_adsp2_boot_work(struct work_struct *work)
2553 struct wm_adsp *dsp = container_of(work,
2558 mutex_lock(&dsp->pwr_lock);
2560 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2561 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2565 ret = wm_adsp2_ena(dsp);
2569 ret = wm_adsp_load(dsp);
2573 ret = wm_adsp2_setup_algs(dsp);
2577 ret = wm_adsp_load_coeff(dsp);
2581 /* Initialize caches for enabled and unset controls */
2582 ret = wm_coeff_init_control_caches(dsp);
2588 /* Turn DSP back off until we are ready to run */
2589 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2600 mutex_unlock(&dsp->pwr_lock);
2605 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2606 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2608 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2611 mutex_unlock(&dsp->pwr_lock);
2614 static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2620 ret = regmap_update_bits_async(dsp->regmap,
2621 dsp->base + ADSP2_CLOCKING,
2623 freq << ADSP2_CLK_SEL_SHIFT);
2625 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2630 /* clock is handled by parent codec driver */
2635 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2636 struct snd_ctl_elem_value *ucontrol)
2638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2639 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
2641 ucontrol->value.integer.value[0] = dsp->preloaded;
2645 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2647 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2648 struct snd_ctl_elem_value *ucontrol)
2650 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2651 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
2652 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2653 struct soc_mixer_control *mc =
2654 (struct soc_mixer_control *)kcontrol->private_value;
2657 snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", mc->shift);
2659 dsp->preloaded = ucontrol->value.integer.value[0];
2661 if (ucontrol->value.integer.value[0])
2662 snd_soc_dapm_force_enable_pin(dapm, preload);
2664 snd_soc_dapm_disable_pin(dapm, preload);
2666 snd_soc_dapm_sync(dapm);
2670 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2672 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2679 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2680 ADSP2_WDT_ENA_MASK, 0);
2684 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2685 struct snd_kcontrol *kcontrol, int event,
2688 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2689 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2690 struct wm_adsp *dsp = &dsps[w->shift];
2691 struct wm_coeff_ctl *ctl;
2694 case SND_SOC_DAPM_PRE_PMU:
2695 wm_adsp2_set_dspclk(dsp, freq);
2696 queue_work(system_unbound_wq, &dsp->boot_work);
2698 case SND_SOC_DAPM_PRE_PMD:
2699 mutex_lock(&dsp->pwr_lock);
2701 wm_adsp_debugfs_clear(dsp);
2704 dsp->fw_id_version = 0;
2706 dsp->booted = false;
2708 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2711 list_for_each_entry(ctl, &dsp->ctl_list, list)
2714 wm_adsp_free_alg_regions(dsp);
2716 mutex_unlock(&dsp->pwr_lock);
2718 adsp_dbg(dsp, "Shutdown complete\n");
2726 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2728 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2729 struct snd_kcontrol *kcontrol, int event)
2731 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2732 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2733 struct wm_adsp *dsp = &dsps[w->shift];
2737 case SND_SOC_DAPM_POST_PMU:
2738 flush_work(&dsp->boot_work);
2740 mutex_lock(&dsp->pwr_lock);
2747 ret = wm_adsp2_ena(dsp);
2751 /* Sync set controls */
2752 ret = wm_coeff_sync_controls(dsp);
2756 wm_adsp2_lock(dsp, dsp->lock_regions);
2758 ret = regmap_update_bits(dsp->regmap,
2759 dsp->base + ADSP2_CONTROL,
2760 ADSP2_CORE_ENA | ADSP2_START,
2761 ADSP2_CORE_ENA | ADSP2_START);
2765 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
2766 ret = wm_adsp_buffer_init(dsp);
2771 dsp->running = true;
2773 mutex_unlock(&dsp->pwr_lock);
2777 case SND_SOC_DAPM_PRE_PMD:
2778 /* Tell the firmware to cleanup */
2779 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2781 wm_adsp_stop_watchdog(dsp);
2783 /* Log firmware state, it can be useful for analysis */
2786 wm_adsp2_show_fw_status(dsp);
2789 wm_adsp2v2_show_fw_status(dsp);
2793 mutex_lock(&dsp->pwr_lock);
2795 dsp->running = false;
2797 regmap_update_bits(dsp->regmap,
2798 dsp->base + ADSP2_CONTROL,
2799 ADSP2_CORE_ENA | ADSP2_START, 0);
2801 /* Make sure DMAs are quiesced */
2804 regmap_write(dsp->regmap,
2805 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2806 regmap_write(dsp->regmap,
2807 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2808 regmap_write(dsp->regmap,
2809 dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2811 regmap_update_bits(dsp->regmap,
2812 dsp->base + ADSP2_CONTROL,
2816 regmap_write(dsp->regmap,
2817 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2818 regmap_write(dsp->regmap,
2819 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2820 regmap_write(dsp->regmap,
2821 dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2825 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2826 wm_adsp_buffer_free(dsp);
2828 mutex_unlock(&dsp->pwr_lock);
2830 adsp_dbg(dsp, "Execution stopped\n");
2839 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2840 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2841 mutex_unlock(&dsp->pwr_lock);
2844 EXPORT_SYMBOL_GPL(wm_adsp2_event);
2846 int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2848 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2851 snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num);
2852 snd_soc_dapm_disable_pin(dapm, preload);
2854 wm_adsp2_init_debugfs(dsp, codec);
2858 return snd_soc_add_codec_controls(codec,
2859 &wm_adsp_fw_controls[dsp->num - 1],
2862 EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2864 int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2866 wm_adsp2_cleanup_debugfs(dsp);
2870 EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2872 int wm_adsp2_init(struct wm_adsp *dsp)
2879 * Disable the DSP memory by default when in reset for a small
2882 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2886 "Failed to clear memory retention: %d\n", ret);
2894 INIT_LIST_HEAD(&dsp->alg_regions);
2895 INIT_LIST_HEAD(&dsp->ctl_list);
2896 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
2898 mutex_init(&dsp->pwr_lock);
2902 EXPORT_SYMBOL_GPL(wm_adsp2_init);
2904 void wm_adsp2_remove(struct wm_adsp *dsp)
2906 struct wm_coeff_ctl *ctl;
2908 while (!list_empty(&dsp->ctl_list)) {
2909 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2911 list_del(&ctl->list);
2912 wm_adsp_free_ctl_blk(ctl);
2915 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2917 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2919 return compr->buf != NULL;
2922 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2925 * Note this will be more complex once each DSP can support multiple
2928 if (!compr->dsp->buffer)
2931 compr->buf = compr->dsp->buffer;
2932 compr->buf->compr = compr;
2937 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2942 /* Wake the poll so it can see buffer is no longer attached */
2944 snd_compr_fragment_elapsed(compr->stream);
2946 if (wm_adsp_compr_attached(compr)) {
2947 compr->buf->compr = NULL;
2952 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2954 struct wm_adsp_compr *compr;
2957 mutex_lock(&dsp->pwr_lock);
2959 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2960 adsp_err(dsp, "Firmware does not support compressed API\n");
2965 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2966 adsp_err(dsp, "Firmware does not support stream direction\n");
2972 /* It is expect this limitation will be removed in future */
2973 adsp_err(dsp, "Only a single stream supported per DSP\n");
2978 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2985 compr->stream = stream;
2989 stream->runtime->private_data = compr;
2992 mutex_unlock(&dsp->pwr_lock);
2996 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2998 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3000 struct wm_adsp_compr *compr = stream->runtime->private_data;
3001 struct wm_adsp *dsp = compr->dsp;
3003 mutex_lock(&dsp->pwr_lock);
3005 wm_adsp_compr_detach(compr);
3008 kfree(compr->raw_buf);
3011 mutex_unlock(&dsp->pwr_lock);
3015 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3017 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3018 struct snd_compr_params *params)
3020 struct wm_adsp_compr *compr = stream->runtime->private_data;
3021 struct wm_adsp *dsp = compr->dsp;
3022 const struct wm_adsp_fw_caps *caps;
3023 const struct snd_codec_desc *desc;
3026 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3027 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3028 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3029 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3030 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3031 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
3032 params->buffer.fragment_size,
3033 params->buffer.fragments);
3038 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3039 caps = &wm_adsp_fw[dsp->fw].caps[i];
3042 if (caps->id != params->codec.id)
3045 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3046 if (desc->max_ch < params->codec.ch_out)
3049 if (desc->max_ch < params->codec.ch_in)
3053 if (!(desc->formats & (1 << params->codec.format)))
3056 for (j = 0; j < desc->num_sample_rates; ++j)
3057 if (desc->sample_rates[j] == params->codec.sample_rate)
3061 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3062 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3063 params->codec.sample_rate, params->codec.format);
3067 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3069 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3072 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3073 struct snd_compr_params *params)
3075 struct wm_adsp_compr *compr = stream->runtime->private_data;
3079 ret = wm_adsp_compr_check_params(stream, params);
3083 compr->size = params->buffer;
3085 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
3086 compr->size.fragment_size, compr->size.fragments);
3088 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3089 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3090 if (!compr->raw_buf)
3093 compr->sample_rate = params->codec.sample_rate;
3097 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3099 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3100 struct snd_compr_caps *caps)
3102 struct wm_adsp_compr *compr = stream->runtime->private_data;
3103 int fw = compr->dsp->fw;
3106 if (wm_adsp_fw[fw].caps) {
3107 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3108 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3110 caps->num_codecs = i;
3111 caps->direction = wm_adsp_fw[fw].compr_direction;
3113 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3114 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3115 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3116 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3121 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3123 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3124 unsigned int mem_addr,
3125 unsigned int num_words, u32 *data)
3127 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3128 unsigned int i, reg;
3134 reg = wm_adsp_region_to_reg(mem, mem_addr);
3136 ret = regmap_raw_read(dsp->regmap, reg, data,
3137 sizeof(*data) * num_words);
3141 for (i = 0; i < num_words; ++i)
3142 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3147 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3148 unsigned int mem_addr, u32 *data)
3150 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3153 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3154 unsigned int mem_addr, u32 data)
3156 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3162 reg = wm_adsp_region_to_reg(mem, mem_addr);
3164 data = cpu_to_be32(data & 0x00ffffffu);
3166 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3169 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3170 unsigned int field_offset, u32 *data)
3172 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
3173 buf->host_buf_ptr + field_offset, data);
3176 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3177 unsigned int field_offset, u32 data)
3179 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
3180 buf->host_buf_ptr + field_offset, data);
3183 static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
3185 struct wm_adsp_alg_region *alg_region;
3186 struct wm_adsp *dsp = buf->dsp;
3187 u32 xmalg, addr, magic;
3190 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3191 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3193 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3194 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3198 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3201 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3202 for (i = 0; i < 5; ++i) {
3203 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3204 &buf->host_buf_ptr);
3208 if (buf->host_buf_ptr)
3211 usleep_range(1000, 2000);
3214 if (!buf->host_buf_ptr)
3217 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3222 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3224 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3225 struct wm_adsp_buffer_region *region;
3229 for (i = 0; i < caps->num_regions; ++i) {
3230 region = &buf->regions[i];
3232 region->offset = offset;
3233 region->mem_type = caps->region_defs[i].mem_type;
3235 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3236 ®ion->base_addr);
3240 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3245 region->cumulative_size = offset;
3248 "region=%d type=%d base=%04x off=%04x size=%04x\n",
3249 i, region->mem_type, region->base_addr,
3250 region->offset, region->cumulative_size);
3256 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3258 struct wm_adsp_compr_buf *buf;
3261 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3266 buf->read_index = -1;
3267 buf->irq_count = 0xFFFFFFFF;
3269 ret = wm_adsp_buffer_locate(buf);
3271 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
3275 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
3276 sizeof(*buf->regions), GFP_KERNEL);
3277 if (!buf->regions) {
3282 ret = wm_adsp_buffer_populate(buf);
3284 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
3293 kfree(buf->regions);
3299 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3302 wm_adsp_compr_detach(dsp->buffer->compr);
3304 kfree(dsp->buffer->regions);
3313 int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3315 struct wm_adsp_compr *compr = stream->runtime->private_data;
3316 struct wm_adsp *dsp = compr->dsp;
3319 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3321 mutex_lock(&dsp->pwr_lock);
3324 case SNDRV_PCM_TRIGGER_START:
3325 if (wm_adsp_compr_attached(compr))
3328 ret = wm_adsp_compr_attach(compr);
3330 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3335 /* Trigger the IRQ at one fragment of data */
3336 ret = wm_adsp_buffer_write(compr->buf,
3337 HOST_BUFFER_FIELD(high_water_mark),
3338 wm_adsp_compr_frag_words(compr));
3340 adsp_err(dsp, "Failed to set high water mark: %d\n",
3345 case SNDRV_PCM_TRIGGER_STOP:
3352 mutex_unlock(&dsp->pwr_lock);
3356 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3358 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3360 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3362 return buf->regions[last_region].cumulative_size;
3365 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3367 u32 next_read_index, next_write_index;
3368 int write_index, read_index, avail;
3371 /* Only sync read index if we haven't already read a valid index */
3372 if (buf->read_index < 0) {
3373 ret = wm_adsp_buffer_read(buf,
3374 HOST_BUFFER_FIELD(next_read_index),
3379 read_index = sign_extend32(next_read_index, 23);
3381 if (read_index < 0) {
3382 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3386 buf->read_index = read_index;
3389 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3394 write_index = sign_extend32(next_write_index, 23);
3396 avail = write_index - buf->read_index;
3398 avail += wm_adsp_buffer_size(buf);
3400 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
3401 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
3408 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3412 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3414 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3417 if (buf->error != 0) {
3418 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3425 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3427 struct wm_adsp_compr_buf *buf;
3428 struct wm_adsp_compr *compr;
3431 mutex_lock(&dsp->pwr_lock);
3441 adsp_dbg(dsp, "Handling buffer IRQ\n");
3443 ret = wm_adsp_buffer_get_error(buf);
3445 goto out_notify; /* Wake poll to report error */
3447 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3450 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3454 ret = wm_adsp_buffer_update_avail(buf);
3456 adsp_err(dsp, "Error reading avail: %d\n", ret);
3460 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3461 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3464 if (compr && compr->stream)
3465 snd_compr_fragment_elapsed(compr->stream);
3468 mutex_unlock(&dsp->pwr_lock);
3472 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3474 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3476 if (buf->irq_count & 0x01)
3479 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3482 buf->irq_count |= 0x01;
3484 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3488 int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3489 struct snd_compr_tstamp *tstamp)
3491 struct wm_adsp_compr *compr = stream->runtime->private_data;
3492 struct wm_adsp *dsp = compr->dsp;
3493 struct wm_adsp_compr_buf *buf;
3496 adsp_dbg(dsp, "Pointer request\n");
3498 mutex_lock(&dsp->pwr_lock);
3502 if (!compr->buf || compr->buf->error) {
3503 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
3508 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3509 ret = wm_adsp_buffer_update_avail(buf);
3511 adsp_err(dsp, "Error reading avail: %d\n", ret);
3516 * If we really have less than 1 fragment available tell the
3517 * DSP to inform us once a whole fragment is available.
3519 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3520 ret = wm_adsp_buffer_get_error(buf);
3522 if (compr->buf->error)
3523 snd_compr_stop_error(stream,
3524 SNDRV_PCM_STATE_XRUN);
3528 ret = wm_adsp_buffer_reenable_irq(buf);
3531 "Failed to re-enable buffer IRQ: %d\n",
3538 tstamp->copied_total = compr->copied_total;
3539 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
3540 tstamp->sampling_rate = compr->sample_rate;
3543 mutex_unlock(&dsp->pwr_lock);
3547 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3549 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3551 struct wm_adsp_compr_buf *buf = compr->buf;
3552 u8 *pack_in = (u8 *)compr->raw_buf;
3553 u8 *pack_out = (u8 *)compr->raw_buf;
3554 unsigned int adsp_addr;
3555 int mem_type, nwords, max_read;
3558 /* Calculate read parameters */
3559 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3560 if (buf->read_index < buf->regions[i].cumulative_size)
3563 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3566 mem_type = buf->regions[i].mem_type;
3567 adsp_addr = buf->regions[i].base_addr +
3568 (buf->read_index - buf->regions[i].offset);
3570 max_read = wm_adsp_compr_frag_words(compr);
3571 nwords = buf->regions[i].cumulative_size - buf->read_index;
3573 if (nwords > target)
3575 if (nwords > buf->avail)
3576 nwords = buf->avail;
3577 if (nwords > max_read)
3582 /* Read data from DSP */
3583 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3584 nwords, compr->raw_buf);
3588 /* Remove the padding bytes from the data read from the DSP */
3589 for (i = 0; i < nwords; i++) {
3590 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3591 *pack_out++ = *pack_in++;
3593 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3596 /* update read index to account for words read */
3597 buf->read_index += nwords;
3598 if (buf->read_index == wm_adsp_buffer_size(buf))
3599 buf->read_index = 0;
3601 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3606 /* update avail to account for words read */
3607 buf->avail -= nwords;
3612 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3613 char __user *buf, size_t count)
3615 struct wm_adsp *dsp = compr->dsp;
3619 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3621 if (!compr->buf || compr->buf->error) {
3622 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
3626 count /= WM_ADSP_DATA_WORD_SIZE;
3629 nwords = wm_adsp_buffer_capture_block(compr, count);
3631 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3635 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3637 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3639 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3640 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3647 } while (nwords > 0 && count > 0);
3649 compr->copied_total += ntotal;
3654 int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3657 struct wm_adsp_compr *compr = stream->runtime->private_data;
3658 struct wm_adsp *dsp = compr->dsp;
3661 mutex_lock(&dsp->pwr_lock);
3663 if (stream->direction == SND_COMPRESS_CAPTURE)
3664 ret = wm_adsp_compr_read(compr, buf, count);
3668 mutex_unlock(&dsp->pwr_lock);
3672 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3674 int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
3676 struct regmap *regmap = dsp->regmap;
3677 unsigned int code0, code1, lock_reg;
3679 if (!(lock_regions & WM_ADSP2_REGION_ALL))
3682 lock_regions &= WM_ADSP2_REGION_ALL;
3683 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
3685 while (lock_regions) {
3687 if (lock_regions & BIT(0)) {
3688 code0 = ADSP2_LOCK_CODE_0;
3689 code1 = ADSP2_LOCK_CODE_1;
3691 if (lock_regions & BIT(1)) {
3692 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
3693 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
3695 regmap_write(regmap, lock_reg, code0);
3696 regmap_write(regmap, lock_reg, code1);
3703 EXPORT_SYMBOL_GPL(wm_adsp2_lock);
3705 irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
3708 struct regmap *regmap = dsp->regmap;
3711 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
3714 "Failed to read Region Lock Ctrl register: %d\n", ret);
3718 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
3719 adsp_err(dsp, "watchdog timeout error\n");
3720 wm_adsp_stop_watchdog(dsp);
3723 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
3724 if (val & ADSP2_SLAVE_ERR_MASK)
3725 adsp_err(dsp, "bus error: slave error\n");
3727 adsp_err(dsp, "bus error: region lock error\n");
3729 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
3732 "Failed to read Bus Err Addr register: %d\n",
3737 adsp_err(dsp, "bus error address = 0x%x\n",
3738 val & ADSP2_BUS_ERR_ADDR_MASK);
3740 ret = regmap_read(regmap,
3741 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3745 "Failed to read Pmem Xmem Err Addr register: %d\n",
3750 adsp_err(dsp, "xmem error address = 0x%x\n",
3751 val & ADSP2_XMEM_ERR_ADDR_MASK);
3752 adsp_err(dsp, "pmem error address = 0x%x\n",
3753 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3754 ADSP2_PMEM_ERR_ADDR_SHIFT);
3757 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3758 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3762 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
3764 MODULE_LICENSE("GPL v2");