2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5665.h>
38 #define RT5665_NUM_SUPPLIES 3
40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
75 static const struct reg_default rt5665_reg[] = {
466 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
491 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
890 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
899 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900 static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
910 /* Interface data select */
911 static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
915 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
918 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
921 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
924 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
927 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
930 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
933 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
936 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
939 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
942 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
945 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
948 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
951 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
954 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
957 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
960 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
963 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
966 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
969 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
972 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
975 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
978 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
981 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
984 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
987 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
990 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
993 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
996 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
999 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1015 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1045 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1125 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127 static int rt5665_button_detect(struct snd_soc_codec *codec)
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1138 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1143 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1144 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1145 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1146 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1147 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1148 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1149 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1151 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1152 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1153 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1154 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1155 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1156 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1161 * rt5665_headset_detect - Detect headset.
1162 * @codec: SoC audio codec device.
1163 * @jack_insert: Jack insert or not.
1165 * Detect whether is headset or not when jack inserted.
1167 * Returns detect status.
1169 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1171 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1172 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1173 unsigned int sar_hs_type, val;
1176 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1177 snd_soc_dapm_sync(dapm);
1179 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1182 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1184 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1189 usleep_range(10000, 15000);
1190 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1195 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1197 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1198 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1199 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1201 usleep_range(10000, 15000);
1203 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1204 RT5665_SAR_IL_CMD_4) & 0x7ff;
1206 sar_hs_type = rt5665->pdata.sar_hs_type ?
1207 rt5665->pdata.sar_hs_type : 729;
1209 if (rt5665->sar_adc_value > sar_hs_type) {
1210 rt5665->jack_type = SND_JACK_HEADSET;
1211 rt5665_enable_push_button_irq(codec, true);
1213 rt5665->jack_type = SND_JACK_HEADPHONE;
1214 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1216 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1218 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1219 snd_soc_dapm_sync(dapm);
1222 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1223 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1224 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1225 snd_soc_dapm_sync(dapm);
1226 if (rt5665->jack_type == SND_JACK_HEADSET)
1227 rt5665_enable_push_button_irq(codec, false);
1228 rt5665->jack_type = 0;
1231 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1232 return rt5665->jack_type;
1235 static irqreturn_t rt5665_irq(int irq, void *data)
1237 struct rt5665_priv *rt5665 = data;
1239 mod_delayed_work(system_power_efficient_wq,
1240 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1245 static void rt5665_jd_check_handler(struct work_struct *work)
1247 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1248 jd_check_work.work);
1250 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1252 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1254 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1256 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1257 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1259 schedule_delayed_work(&rt5665->jd_check_work, 500);
1263 static int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1264 struct snd_soc_jack *hs_jack, void *data)
1266 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1268 switch (rt5665->pdata.jd_src) {
1270 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1271 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1272 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1274 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1275 RT5665_PWR_JD1, RT5665_PWR_JD1);
1276 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1279 case RT5665_JD_NULL:
1283 dev_warn(codec->dev, "Wrong JD source\n");
1287 rt5665->hs_jack = hs_jack;
1292 static void rt5665_jack_detect_handler(struct work_struct *work)
1294 struct rt5665_priv *rt5665 =
1295 container_of(work, struct rt5665_priv, jack_detect_work.work);
1298 while (!rt5665->codec) {
1299 pr_debug("%s codec = null\n", __func__);
1300 usleep_range(10000, 15000);
1303 while (!rt5665->codec->component.card->instantiated) {
1304 pr_debug("%s\n", __func__);
1305 usleep_range(10000, 15000);
1308 mutex_lock(&rt5665->calibrate_mutex);
1310 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1313 if (rt5665->jack_type == 0) {
1314 /* jack was out, report jack type */
1316 rt5665_headset_detect(rt5665->codec, 1);
1318 /* jack is already in, report button event */
1319 rt5665->jack_type = SND_JACK_HEADSET;
1320 btn_type = rt5665_button_detect(rt5665->codec);
1322 * rt5665 can report three kinds of button behavior,
1323 * one click, double click and hold. However,
1324 * currently we will report button pressed/released
1325 * event. So all the three button behaviors are
1326 * treated as button pressed.
1332 rt5665->jack_type |= SND_JACK_BTN_0;
1337 rt5665->jack_type |= SND_JACK_BTN_1;
1342 rt5665->jack_type |= SND_JACK_BTN_2;
1347 rt5665->jack_type |= SND_JACK_BTN_3;
1349 case 0x0000: /* unpressed */
1353 dev_err(rt5665->codec->dev,
1354 "Unexpected button code 0x%04x\n",
1361 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1364 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1366 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1367 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1369 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1370 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1371 schedule_delayed_work(&rt5665->jd_check_work, 0);
1373 cancel_delayed_work_sync(&rt5665->jd_check_work);
1375 mutex_unlock(&rt5665->calibrate_mutex);
1378 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1379 /* Headphone Output Volume */
1380 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1381 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1382 rt5665_hp_vol_put, hp_vol_tlv),
1384 /* Mono Output Volume */
1385 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1386 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1387 rt5665_mono_vol_put, mono_vol_tlv),
1390 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1391 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1393 /* DAC Digital Volume */
1394 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1395 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1396 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1397 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1398 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1399 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1401 /* IN1/IN2/IN3/IN4 Volume */
1402 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1403 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1404 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1405 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1406 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1407 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1408 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1409 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1410 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1411 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1413 /* INL/INR Volume Control */
1414 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1415 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1417 /* ADC Digital Volume Control */
1418 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1419 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1420 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1421 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1422 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1423 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1424 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1425 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1426 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1427 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1428 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1429 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1431 /* ADC Boost Volume Control */
1432 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1433 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1436 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1437 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1440 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1441 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1446 * set_dmic_clk - Set parameter of dmic.
1449 * @kcontrol: The kcontrol of this widget.
1452 * Choose dmic clock between 1MHz and 3MHz.
1453 * It is better for clock to approximate 3MHz.
1455 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1456 struct snd_kcontrol *kcontrol, int event)
1458 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1459 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1460 int pd, idx = -EINVAL;
1462 pd = rl6231_get_pre_div(rt5665->regmap,
1463 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1464 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1467 dev_err(codec->dev, "Failed to set DMIC clock\n");
1469 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1470 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1475 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1476 struct snd_kcontrol *kcontrol, int event)
1478 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1481 case SND_SOC_DAPM_PRE_PMU:
1482 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1483 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1484 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1486 case SND_SOC_DAPM_POST_PMD:
1487 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1488 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1489 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1498 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1499 struct snd_soc_dapm_widget *sink)
1502 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1504 val = snd_soc_read(codec, RT5665_GLB_CLK);
1505 val &= RT5665_SCLK_SRC_MASK;
1506 if (val == RT5665_SCLK_SRC_PLL1)
1512 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1513 struct snd_soc_dapm_widget *sink)
1515 unsigned int reg, shift, val;
1516 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1519 case RT5665_ADC_MONO_R_ASRC_SFT:
1520 reg = RT5665_ASRC_3;
1521 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1523 case RT5665_ADC_MONO_L_ASRC_SFT:
1524 reg = RT5665_ASRC_3;
1525 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1527 case RT5665_ADC_STO1_ASRC_SFT:
1528 reg = RT5665_ASRC_3;
1529 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1531 case RT5665_ADC_STO2_ASRC_SFT:
1532 reg = RT5665_ASRC_3;
1533 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1535 case RT5665_DAC_MONO_R_ASRC_SFT:
1536 reg = RT5665_ASRC_2;
1537 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1539 case RT5665_DAC_MONO_L_ASRC_SFT:
1540 reg = RT5665_ASRC_2;
1541 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1543 case RT5665_DAC_STO1_ASRC_SFT:
1544 reg = RT5665_ASRC_2;
1545 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1547 case RT5665_DAC_STO2_ASRC_SFT:
1548 reg = RT5665_ASRC_2;
1549 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1555 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1557 case RT5665_CLK_SEL_I2S1_ASRC:
1558 case RT5665_CLK_SEL_I2S2_ASRC:
1559 case RT5665_CLK_SEL_I2S3_ASRC:
1560 /* I2S_Pre_Div1 should be 1 in asrc mode */
1561 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1562 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1571 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1572 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1573 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1574 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1575 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1578 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1579 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1580 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1581 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1582 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1585 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1586 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1587 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1588 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1589 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1592 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1593 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1594 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1595 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1596 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1599 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1600 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1601 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1603 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1606 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1607 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1608 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1609 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1610 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1613 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1614 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1615 RT5665_M_ADCMIX_L_SFT, 1, 1),
1616 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1617 RT5665_M_DAC1_L_SFT, 1, 1),
1620 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1621 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1622 RT5665_M_ADCMIX_R_SFT, 1, 1),
1623 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1624 RT5665_M_DAC1_R_SFT, 1, 1),
1627 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1628 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1629 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1630 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1631 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1632 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1633 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1634 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1635 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1638 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1639 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1640 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1641 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1642 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1643 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1644 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1645 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1646 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1649 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1650 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1651 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1652 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1653 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1654 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1655 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1658 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1659 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1660 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1661 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1662 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1663 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1664 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1667 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1668 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1669 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1670 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1671 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1672 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1673 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1674 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1675 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1678 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1679 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1680 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1681 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1682 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1683 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1684 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1685 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1686 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1689 /* Analog Input Mixer */
1690 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1691 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1692 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1694 RT5665_M_INL_RM1_L_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1696 RT5665_M_INR_RM1_L_SFT, 1, 1),
1697 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1698 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1700 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1701 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1702 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1703 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1704 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1707 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1708 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1709 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1711 RT5665_M_INR_RM1_R_SFT, 1, 1),
1712 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1713 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1714 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1715 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1717 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1719 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1722 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1723 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1724 RT5665_M_INL_RM2_L_SFT, 1, 1),
1725 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1726 RT5665_M_INR_RM2_L_SFT, 1, 1),
1727 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1728 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1729 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1730 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1732 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1734 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1736 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1739 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1740 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1741 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1742 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1743 RT5665_M_INL_RM2_R_SFT, 1, 1),
1744 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1745 RT5665_M_INR_RM2_R_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1747 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1749 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1751 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1753 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1756 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1757 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1758 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1760 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1761 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1762 RT5665_M_BST1_MM_SFT, 1, 1),
1763 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1764 RT5665_M_BST2_MM_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1766 RT5665_M_BST3_MM_SFT, 1, 1),
1769 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1770 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1771 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1772 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1773 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1774 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1775 RT5665_M_BST1_OM_L_SFT, 1, 1),
1776 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1777 RT5665_M_BST2_OM_L_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1779 RT5665_M_BST3_OM_L_SFT, 1, 1),
1782 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1783 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1784 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1785 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1786 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1787 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1788 RT5665_M_BST2_OM_R_SFT, 1, 1),
1789 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1790 RT5665_M_BST3_OM_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1792 RT5665_M_BST4_OM_R_SFT, 1, 1),
1795 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1796 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1797 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1798 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1799 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1802 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1803 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1804 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1805 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1806 RT5665_M_OV_L_LM_SFT, 1, 1),
1809 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1810 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1811 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1812 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1813 RT5665_M_OV_R_LM_SFT, 1, 1),
1817 /*MX-17 [6:4], MX-17 [2:0]*/
1818 static const char * const rt5665_dac2_src[] = {
1819 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1822 static const SOC_ENUM_SINGLE_DECL(
1823 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1824 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1826 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1827 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1829 static const SOC_ENUM_SINGLE_DECL(
1830 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1831 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1833 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1834 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1837 /*MX-1B [6:4], MX-1B [2:0]*/
1838 static const char * const rt5665_dac3_src[] = {
1839 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1842 static const SOC_ENUM_SINGLE_DECL(
1843 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1844 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1846 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1847 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1849 static const SOC_ENUM_SINGLE_DECL(
1850 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1851 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1853 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1854 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1856 /* STO1 ADC1 Source */
1857 /* MX-26 [13] [5] */
1858 static const char * const rt5665_sto1_adc1_src[] = {
1862 static const SOC_ENUM_SINGLE_DECL(
1863 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1864 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1866 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1867 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1869 static const SOC_ENUM_SINGLE_DECL(
1870 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1871 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1873 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1874 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1876 /* STO1 ADC Source */
1877 /* MX-26 [11:10] [3:2] */
1878 static const char * const rt5665_sto1_adc_src[] = {
1879 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1882 static const SOC_ENUM_SINGLE_DECL(
1883 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1884 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1886 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1887 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1889 static const SOC_ENUM_SINGLE_DECL(
1890 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1891 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1893 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1894 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1896 /* STO1 ADC2 Source */
1897 /* MX-26 [12] [4] */
1898 static const char * const rt5665_sto1_adc2_src[] = {
1902 static const SOC_ENUM_SINGLE_DECL(
1903 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1904 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1906 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1907 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1909 static const SOC_ENUM_SINGLE_DECL(
1910 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1911 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1913 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1914 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1916 /* STO1 DMIC Source */
1918 static const char * const rt5665_sto1_dmic_src[] = {
1922 static const SOC_ENUM_SINGLE_DECL(
1923 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1924 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1926 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1927 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1930 static const char * const rt5665_sto1_dd_l_src[] = {
1931 "STO2 DAC", "MONO DAC"
1934 static const SOC_ENUM_SINGLE_DECL(
1935 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1936 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1938 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1939 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1942 static const char * const rt5665_sto1_dd_r_src[] = {
1943 "STO2 DAC", "MONO DAC", "AEC REF"
1946 static const SOC_ENUM_SINGLE_DECL(
1947 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1948 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1950 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1951 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1953 /* MONO ADC L2 Source */
1955 static const char * const rt5665_mono_adc_l2_src[] = {
1959 static const SOC_ENUM_SINGLE_DECL(
1960 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1961 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1963 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1964 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1967 /* MONO ADC L1 Source */
1969 static const char * const rt5665_mono_adc_l1_src[] = {
1973 static const SOC_ENUM_SINGLE_DECL(
1974 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1975 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1977 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1978 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1981 static const char * const rt5665_mono_dd_src[] = {
1982 "STO2 DAC", "MONO DAC"
1985 static const SOC_ENUM_SINGLE_DECL(
1986 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1987 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1989 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1990 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1992 static const SOC_ENUM_SINGLE_DECL(
1993 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1994 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1996 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1997 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1999 /* MONO ADC L Source, MONO ADC R Source*/
2000 /* MX-27 [11:10], MX-27 [3:2] */
2001 static const char * const rt5665_mono_adc_src[] = {
2002 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2005 static const SOC_ENUM_SINGLE_DECL(
2006 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2007 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2009 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2010 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2012 static const SOC_ENUM_SINGLE_DECL(
2013 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2014 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2016 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2017 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2019 /* MONO DMIC L Source */
2021 static const char * const rt5665_mono_dmic_l_src[] = {
2022 "DMIC1 L", "DMIC2 L"
2025 static const SOC_ENUM_SINGLE_DECL(
2026 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2027 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2029 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2030 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2032 /* MONO ADC R2 Source */
2034 static const char * const rt5665_mono_adc_r2_src[] = {
2038 static const SOC_ENUM_SINGLE_DECL(
2039 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2040 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2042 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2043 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2045 /* MONO ADC R1 Source */
2047 static const char * const rt5665_mono_adc_r1_src[] = {
2051 static const SOC_ENUM_SINGLE_DECL(
2052 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2053 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2055 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2056 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2058 /* MONO DMIC R Source */
2060 static const char * const rt5665_mono_dmic_r_src[] = {
2061 "DMIC1 R", "DMIC2 R"
2064 static const SOC_ENUM_SINGLE_DECL(
2065 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2066 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2068 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2069 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2072 /* STO2 ADC1 Source */
2073 /* MX-28 [13] [5] */
2074 static const char * const rt5665_sto2_adc1_src[] = {
2078 static const SOC_ENUM_SINGLE_DECL(
2079 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2080 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2082 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2083 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2085 static const SOC_ENUM_SINGLE_DECL(
2086 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2087 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2089 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2090 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2092 /* STO2 ADC Source */
2093 /* MX-28 [11:10] [3:2] */
2094 static const char * const rt5665_sto2_adc_src[] = {
2095 "ADC1 L", "ADC1 R", "ADC2 L"
2098 static const SOC_ENUM_SINGLE_DECL(
2099 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2100 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2102 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2103 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2105 static const SOC_ENUM_SINGLE_DECL(
2106 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2107 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2109 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2110 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2112 /* STO2 ADC2 Source */
2113 /* MX-28 [12] [4] */
2114 static const char * const rt5665_sto2_adc2_src[] = {
2118 static const SOC_ENUM_SINGLE_DECL(
2119 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2120 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2122 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2123 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2125 static const SOC_ENUM_SINGLE_DECL(
2126 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2127 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2129 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2130 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2132 /* STO2 DMIC Source */
2134 static const char * const rt5665_sto2_dmic_src[] = {
2138 static const SOC_ENUM_SINGLE_DECL(
2139 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2140 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2142 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2143 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2146 static const char * const rt5665_sto2_dd_l_src[] = {
2147 "STO2 DAC", "MONO DAC"
2150 static const SOC_ENUM_SINGLE_DECL(
2151 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2152 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2154 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2155 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2158 static const char * const rt5665_sto2_dd_r_src[] = {
2159 "STO2 DAC", "MONO DAC"
2162 static const SOC_ENUM_SINGLE_DECL(
2163 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2164 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2166 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2167 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2169 /* DAC R1 Source, DAC L1 Source*/
2170 /* MX-29 [11:10], MX-29 [9:8]*/
2171 static const char * const rt5665_dac1_src[] = {
2172 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2175 static const SOC_ENUM_SINGLE_DECL(
2176 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2177 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2179 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2180 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2182 static const SOC_ENUM_SINGLE_DECL(
2183 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2184 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2186 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2187 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2189 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2190 /* MX-2D [13:12], MX-2D [9:8]*/
2191 static const char * const rt5665_dig_dac_mix_src[] = {
2192 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2195 static const SOC_ENUM_SINGLE_DECL(
2196 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2197 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2199 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2200 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2202 static const SOC_ENUM_SINGLE_DECL(
2203 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2204 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2206 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2207 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2209 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2210 /* MX-2D [5:4], MX-2D [1:0]*/
2211 static const char * const rt5665_alg_dac1_src[] = {
2212 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2215 static const SOC_ENUM_SINGLE_DECL(
2216 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2217 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2219 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2220 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2222 static const SOC_ENUM_SINGLE_DECL(
2223 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2224 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2226 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2227 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2229 /* Analog DAC LR Source, Analog DAC R2 Source*/
2230 /* MX-2E [5:4], MX-2E [0]*/
2231 static const char * const rt5665_alg_dac2_src[] = {
2232 "Mono DAC Mixer", "DAC2"
2235 static const SOC_ENUM_SINGLE_DECL(
2236 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2237 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2239 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2240 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2242 static const SOC_ENUM_SINGLE_DECL(
2243 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2244 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2246 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2247 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2249 /* Interface2 ADC Data Input*/
2251 static const char * const rt5665_if2_1_adc_in_src[] = {
2252 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2253 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2256 static const SOC_ENUM_SINGLE_DECL(
2257 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2258 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2260 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2261 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2264 static const char * const rt5665_if2_2_adc_in_src[] = {
2265 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2266 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2269 static const SOC_ENUM_SINGLE_DECL(
2270 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2271 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2273 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2274 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2276 /* Interface3 ADC Data Input*/
2278 static const char * const rt5665_if3_adc_in_src[] = {
2279 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2280 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2283 static const SOC_ENUM_SINGLE_DECL(
2284 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2285 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2287 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2288 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2291 /* MX-31 [11:10] [9:8] */
2292 static const char * const rt5665_pdm_src[] = {
2293 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2296 static const SOC_ENUM_SINGLE_DECL(
2297 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2298 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2300 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2301 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2303 static const SOC_ENUM_SINGLE_DECL(
2304 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2305 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2307 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2308 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2311 /* I2S1 TDM ADCDAT Source */
2313 static const char * const rt5665_if1_1_adc1_data_src[] = {
2314 "STO1 ADC", "IF2_1 DAC",
2317 static const SOC_ENUM_SINGLE_DECL(
2318 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2319 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2321 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2322 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2325 static const char * const rt5665_if1_1_adc2_data_src[] = {
2326 "STO2 ADC", "IF2_2 DAC",
2329 static const SOC_ENUM_SINGLE_DECL(
2330 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2331 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2333 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2334 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2337 static const char * const rt5665_if1_1_adc3_data_src[] = {
2338 "MONO ADC", "IF3 DAC",
2341 static const SOC_ENUM_SINGLE_DECL(
2342 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2343 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2345 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2346 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2349 static const char * const rt5665_if1_2_adc1_data_src[] = {
2350 "STO1 ADC", "IF1 DAC",
2353 static const SOC_ENUM_SINGLE_DECL(
2354 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2355 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2357 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2358 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2361 static const char * const rt5665_if1_2_adc2_data_src[] = {
2362 "STO2 ADC", "IF2_1 DAC",
2365 static const SOC_ENUM_SINGLE_DECL(
2366 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2367 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2369 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2370 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2373 static const char * const rt5665_if1_2_adc3_data_src[] = {
2374 "MONO ADC", "IF2_2 DAC",
2377 static const SOC_ENUM_SINGLE_DECL(
2378 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2379 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2381 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2382 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2385 static const char * const rt5665_if1_2_adc4_data_src[] = {
2389 static const SOC_ENUM_SINGLE_DECL(
2390 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2391 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2393 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2394 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2396 /* MX-7a[4:0] MX-7b[4:0] */
2397 static const char * const rt5665_tdm_adc_data_src[] = {
2398 "1234", "1243", "1324", "1342", "1432", "1423",
2399 "2134", "2143", "2314", "2341", "2431", "2413",
2400 "3124", "3142", "3214", "3241", "3412", "3421",
2401 "4123", "4132", "4213", "4231", "4312", "4321"
2404 static const SOC_ENUM_SINGLE_DECL(
2405 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2406 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2408 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2409 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2411 static const SOC_ENUM_SINGLE_DECL(
2412 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2413 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2415 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2416 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2418 /* Out Volume Switch */
2419 static const struct snd_kcontrol_new monovol_switch =
2420 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2422 static const struct snd_kcontrol_new outvol_l_switch =
2423 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2425 static const struct snd_kcontrol_new outvol_r_switch =
2426 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2429 static const struct snd_kcontrol_new mono_switch =
2430 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2432 static const struct snd_kcontrol_new hpo_switch =
2433 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2434 RT5665_VOL_L_SFT, 1, 0);
2436 static const struct snd_kcontrol_new lout_l_switch =
2437 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2439 static const struct snd_kcontrol_new lout_r_switch =
2440 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2442 static const struct snd_kcontrol_new pdm_l_switch =
2443 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2444 RT5665_M_PDM1_L_SFT, 1, 1);
2446 static const struct snd_kcontrol_new pdm_r_switch =
2447 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2448 RT5665_M_PDM1_R_SFT, 1, 1);
2450 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2451 struct snd_kcontrol *kcontrol, int event)
2453 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2456 case SND_SOC_DAPM_PRE_PMU:
2457 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2458 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2459 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2461 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2462 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2465 case SND_SOC_DAPM_POST_PMD:
2466 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2468 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2470 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2471 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2482 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2483 struct snd_kcontrol *kcontrol, int event)
2485 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2488 case SND_SOC_DAPM_PRE_PMU:
2489 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2490 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2491 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2494 case SND_SOC_DAPM_POST_PMD:
2495 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2496 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2497 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2508 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2509 struct snd_kcontrol *kcontrol, int event)
2511 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2514 case SND_SOC_DAPM_POST_PMU:
2515 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2516 RT5665_PUMP_EN, RT5665_PUMP_EN);
2519 case SND_SOC_DAPM_PRE_PMD:
2520 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2532 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2533 struct snd_kcontrol *kcontrol, int event)
2536 case SND_SOC_DAPM_POST_PMU:
2537 /*Add delay to avoid pop noise*/
2548 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2549 struct snd_kcontrol *kcontrol, int event)
2551 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2554 case SND_SOC_DAPM_PRE_PMU:
2556 case RT5665_PWR_VREF1_BIT:
2557 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2561 case RT5665_PWR_VREF2_BIT:
2562 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2566 case RT5665_PWR_VREF3_BIT:
2567 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2576 case SND_SOC_DAPM_POST_PMU:
2577 usleep_range(15000, 20000);
2579 case RT5665_PWR_VREF1_BIT:
2580 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2581 RT5665_PWR_FV1, RT5665_PWR_FV1);
2584 case RT5665_PWR_VREF2_BIT:
2585 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2586 RT5665_PWR_FV2, RT5665_PWR_FV2);
2589 case RT5665_PWR_VREF3_BIT:
2590 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2591 RT5665_PWR_FV3, RT5665_PWR_FV3);
2606 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2607 struct snd_kcontrol *kcontrol, int event)
2609 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2610 unsigned int val1, val2, mask1, mask2 = 0;
2613 case RT5665_PWR_I2S2_1_BIT:
2614 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2615 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2616 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2617 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2619 case RT5665_PWR_I2S2_2_BIT:
2620 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2621 RT5665_GP8_PIN_MASK;
2622 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2623 RT5665_GP8_PIN_DACDAT2_2;
2624 mask2 = RT5665_GP9_PIN_MASK;
2625 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2627 case RT5665_PWR_I2S3_BIT:
2628 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2629 RT5665_GP8_PIN_MASK;
2630 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2631 RT5665_GP8_PIN_DACDAT3;
2632 mask2 = RT5665_GP9_PIN_MASK;
2633 val2 = RT5665_GP9_PIN_ADCDAT3;
2637 case SND_SOC_DAPM_PRE_PMU:
2638 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, val1);
2640 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2643 case SND_SOC_DAPM_POST_PMD:
2644 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, 0);
2646 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2656 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2657 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2659 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2661 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2662 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2663 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2664 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2665 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2666 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2667 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2668 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2671 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2672 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2674 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2676 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2678 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2680 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2681 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2682 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2684 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2685 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2686 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2687 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2688 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2689 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2690 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2692 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2694 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2696 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2698 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2701 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2703 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2705 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2709 SND_SOC_DAPM_INPUT("DMIC L1"),
2710 SND_SOC_DAPM_INPUT("DMIC R1"),
2711 SND_SOC_DAPM_INPUT("DMIC L2"),
2712 SND_SOC_DAPM_INPUT("DMIC R2"),
2714 SND_SOC_DAPM_INPUT("IN1P"),
2715 SND_SOC_DAPM_INPUT("IN1N"),
2716 SND_SOC_DAPM_INPUT("IN2P"),
2717 SND_SOC_DAPM_INPUT("IN2N"),
2718 SND_SOC_DAPM_INPUT("IN3P"),
2719 SND_SOC_DAPM_INPUT("IN3N"),
2720 SND_SOC_DAPM_INPUT("IN4P"),
2721 SND_SOC_DAPM_INPUT("IN4N"),
2723 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2724 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2726 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2727 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2728 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2729 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2730 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2731 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2734 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2736 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2738 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2740 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2742 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2744 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2745 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2746 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2747 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2749 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2751 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2753 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2755 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2757 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2759 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2761 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2765 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2767 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2771 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2772 ARRAY_SIZE(rt5665_rec1_l_mix)),
2773 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2774 ARRAY_SIZE(rt5665_rec1_r_mix)),
2775 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2776 ARRAY_SIZE(rt5665_rec2_l_mix)),
2777 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2778 ARRAY_SIZE(rt5665_rec2_r_mix)),
2779 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2780 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2781 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2782 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2784 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2786 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2789 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2790 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2791 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2792 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2794 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2795 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2796 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2797 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2798 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2799 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2800 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2801 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2802 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2803 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2804 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2805 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2808 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5665_sto1_dmic_mux),
2810 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5665_sto1_dmic_mux),
2812 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5665_sto1_adc1l_mux),
2814 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5665_sto1_adc1r_mux),
2816 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5665_sto1_adc2l_mux),
2818 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5665_sto1_adc2r_mux),
2820 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5665_sto1_adcl_mux),
2822 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5665_sto1_adcr_mux),
2824 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5665_sto1_dd_l_mux),
2826 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5665_sto1_dd_r_mux),
2828 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5665_mono_adc_l2_mux),
2830 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5665_mono_adc_r2_mux),
2832 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5665_mono_adc_l1_mux),
2834 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5665_mono_adc_r1_mux),
2836 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5665_mono_dmic_l_mux),
2838 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5665_mono_dmic_r_mux),
2840 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2841 &rt5665_mono_adc_l_mux),
2842 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2843 &rt5665_mono_adc_r_mux),
2844 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2845 &rt5665_mono_dd_l_mux),
2846 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2847 &rt5665_mono_dd_r_mux),
2848 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2849 &rt5665_sto2_dmic_mux),
2850 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5665_sto2_dmic_mux),
2852 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5665_sto2_adc1l_mux),
2854 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5665_sto2_adc1r_mux),
2856 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5665_sto2_adc2l_mux),
2858 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5665_sto2_adc2r_mux),
2860 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2861 &rt5665_sto2_adcl_mux),
2862 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2863 &rt5665_sto2_adcr_mux),
2864 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2865 &rt5665_sto2_dd_l_mux),
2866 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2867 &rt5665_sto2_dd_r_mux),
2869 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2870 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2871 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2872 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2873 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2874 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2875 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2876 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2877 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2878 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2879 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2880 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2881 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2882 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2883 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2884 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2885 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2886 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2887 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2888 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2889 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2890 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2891 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2892 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2893 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2894 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2897 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 /* Digital Interface */
2902 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2904 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2906 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2907 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2908 SND_SOC_DAPM_POST_PMD),
2909 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2910 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2911 SND_SOC_DAPM_POST_PMD),
2912 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2913 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2914 SND_SOC_DAPM_POST_PMD),
2915 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2916 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2917 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2923 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2925 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2926 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2927 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2928 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2929 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2930 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2931 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2932 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2934 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2935 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2936 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2937 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2939 /* Digital Interface Select */
2940 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5665_if1_1_adc1_mux),
2942 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if1_1_adc2_mux),
2944 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if1_1_adc3_mux),
2946 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2947 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5665_if1_2_adc1_mux),
2949 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5665_if1_2_adc2_mux),
2951 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5665_if1_2_adc3_mux),
2953 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5665_if1_2_adc4_mux),
2955 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5665_tdm1_adc_mux),
2957 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5665_tdm1_adc_mux),
2959 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5665_tdm1_adc_mux),
2961 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5665_tdm1_adc_mux),
2963 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_tdm2_adc_mux),
2965 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_tdm2_adc_mux),
2967 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_tdm2_adc_mux),
2969 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5665_tdm2_adc_mux),
2971 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5665_if2_1_adc_in_mux),
2973 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5665_if2_2_adc_in_mux),
2975 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5665_if3_adc_in_mux),
2977 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5665_if1_1_01_adc_swap_mux),
2979 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5665_if1_1_01_adc_swap_mux),
2981 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5665_if1_1_23_adc_swap_mux),
2983 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5665_if1_1_23_adc_swap_mux),
2985 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5665_if1_1_45_adc_swap_mux),
2987 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5665_if1_1_45_adc_swap_mux),
2989 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5665_if1_1_67_adc_swap_mux),
2991 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5665_if1_1_67_adc_swap_mux),
2993 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5665_if1_2_01_adc_swap_mux),
2995 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5665_if1_2_01_adc_swap_mux),
2997 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5665_if1_2_23_adc_swap_mux),
2999 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5665_if1_2_23_adc_swap_mux),
3001 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3002 &rt5665_if1_2_45_adc_swap_mux),
3003 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3004 &rt5665_if1_2_45_adc_swap_mux),
3005 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3006 &rt5665_if1_2_67_adc_swap_mux),
3007 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008 &rt5665_if1_2_67_adc_swap_mux),
3009 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3010 &rt5665_if2_1_dac_swap_mux),
3011 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3012 &rt5665_if2_1_adc_swap_mux),
3013 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3014 &rt5665_if2_2_dac_swap_mux),
3015 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3016 &rt5665_if2_2_adc_swap_mux),
3017 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3018 &rt5665_if3_dac_swap_mux),
3019 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3020 &rt5665_if3_adc_swap_mux),
3022 /* Audio Interface */
3023 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3024 0, SND_SOC_NOPM, 0, 0),
3025 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3026 1, SND_SOC_NOPM, 0, 0),
3027 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3028 2, SND_SOC_NOPM, 0, 0),
3029 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3030 3, SND_SOC_NOPM, 0, 0),
3031 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3032 4, SND_SOC_NOPM, 0, 0),
3033 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3034 5, SND_SOC_NOPM, 0, 0),
3035 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3036 6, SND_SOC_NOPM, 0, 0),
3037 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3038 7, SND_SOC_NOPM, 0, 0),
3039 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3040 0, SND_SOC_NOPM, 0, 0),
3041 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3042 1, SND_SOC_NOPM, 0, 0),
3043 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3044 2, SND_SOC_NOPM, 0, 0),
3045 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3046 3, SND_SOC_NOPM, 0, 0),
3047 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3048 4, SND_SOC_NOPM, 0, 0),
3049 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3050 5, SND_SOC_NOPM, 0, 0),
3051 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3052 6, SND_SOC_NOPM, 0, 0),
3053 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3054 7, SND_SOC_NOPM, 0, 0),
3055 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3056 0, SND_SOC_NOPM, 0, 0),
3057 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3058 0, SND_SOC_NOPM, 0, 0),
3059 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3060 0, SND_SOC_NOPM, 0, 0),
3061 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3062 0, SND_SOC_NOPM, 0, 0),
3063 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3064 0, SND_SOC_NOPM, 0, 0),
3065 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3066 0, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3068 0, SND_SOC_NOPM, 0, 0),
3071 /* DAC mixer before sound effect */
3072 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3073 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3074 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3075 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3077 /* DAC channel Mux */
3078 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3079 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3080 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3081 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3082 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3083 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3085 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3086 &rt5665_alg_dac_l1_mux),
3087 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3088 &rt5665_alg_dac_r1_mux),
3089 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3090 &rt5665_alg_dac_l2_mux),
3091 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3092 &rt5665_alg_dac_r2_mux),
3095 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3096 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3097 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3098 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3099 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3100 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3101 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3102 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3103 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3104 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3105 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3106 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3107 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3108 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3109 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3110 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3111 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3112 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3113 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3114 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3115 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3116 &rt5665_dig_dac_mixl_mux),
3117 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3118 &rt5665_dig_dac_mixr_mux),
3121 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3122 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3124 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3125 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3126 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3127 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3128 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3129 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3130 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3132 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3133 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3134 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3135 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3138 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3139 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3140 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3141 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3142 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3143 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3146 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3148 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3150 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3154 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3155 ARRAY_SIZE(rt5665_mono_mix)),
3156 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3157 ARRAY_SIZE(rt5665_lout_l_mix)),
3158 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3159 ARRAY_SIZE(rt5665_lout_r_mix)),
3160 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3161 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3162 SND_SOC_DAPM_PRE_PMU),
3163 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3164 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3165 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3166 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3167 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3168 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3170 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3171 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3172 SND_SOC_DAPM_POST_PMD),
3174 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3176 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3178 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3180 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3182 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3184 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3188 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3189 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3190 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3191 0, 1, &rt5665_pdm_l_mux),
3192 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3193 0, 1, &rt5665_pdm_r_mux),
3196 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3198 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3200 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3202 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3204 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3208 SND_SOC_DAPM_OUTPUT("HPOL"),
3209 SND_SOC_DAPM_OUTPUT("HPOR"),
3210 SND_SOC_DAPM_OUTPUT("LOUTL"),
3211 SND_SOC_DAPM_OUTPUT("LOUTR"),
3212 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3213 SND_SOC_DAPM_OUTPUT("PDML"),
3214 SND_SOC_DAPM_OUTPUT("PDMR"),
3217 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3219 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3220 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3221 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3222 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3223 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3224 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3225 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3226 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3229 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3230 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3231 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3232 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3233 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3234 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3235 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3236 {"I2S1 ASRC", NULL, "CLKDET"},
3237 {"I2S2 ASRC", NULL, "CLKDET"},
3238 {"I2S3 ASRC", NULL, "CLKDET"},
3241 {"Mic Det Power", NULL, "Vref2"},
3242 {"MICBIAS1", NULL, "Vref1"},
3243 {"MICBIAS1", NULL, "Vref2"},
3244 {"MICBIAS2", NULL, "Vref1"},
3245 {"MICBIAS2", NULL, "Vref2"},
3246 {"MICBIAS3", NULL, "Vref1"},
3247 {"MICBIAS3", NULL, "Vref2"},
3249 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3250 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3251 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3252 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3253 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3254 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3256 {"I2S1_1", NULL, "I2S1 ASRC"},
3257 {"I2S1_2", NULL, "I2S1 ASRC"},
3258 {"I2S2_1", NULL, "I2S2 ASRC"},
3259 {"I2S2_2", NULL, "I2S2 ASRC"},
3260 {"I2S3", NULL, "I2S3 ASRC"},
3262 {"CLKDET SYS", NULL, "CLKDET"},
3263 {"CLKDET HP", NULL, "CLKDET"},
3264 {"CLKDET MONO", NULL, "CLKDET"},
3265 {"CLKDET LOUT", NULL, "CLKDET"},
3267 {"IN1P", NULL, "LDO2"},
3268 {"IN2P", NULL, "LDO2"},
3269 {"IN3P", NULL, "LDO2"},
3270 {"IN4P", NULL, "LDO2"},
3272 {"DMIC1", NULL, "DMIC L1"},
3273 {"DMIC1", NULL, "DMIC R1"},
3274 {"DMIC2", NULL, "DMIC L2"},
3275 {"DMIC2", NULL, "DMIC R2"},
3277 {"BST1", NULL, "IN1P"},
3278 {"BST1", NULL, "IN1N"},
3279 {"BST1", NULL, "BST1 Power"},
3280 {"BST1", NULL, "BST1P Power"},
3281 {"BST2", NULL, "IN2P"},
3282 {"BST2", NULL, "IN2N"},
3283 {"BST2", NULL, "BST2 Power"},
3284 {"BST2", NULL, "BST2P Power"},
3285 {"BST3", NULL, "IN3P"},
3286 {"BST3", NULL, "IN3N"},
3287 {"BST3", NULL, "BST3 Power"},
3288 {"BST3", NULL, "BST3P Power"},
3289 {"BST4", NULL, "IN4P"},
3290 {"BST4", NULL, "IN4N"},
3291 {"BST4", NULL, "BST4 Power"},
3292 {"BST4", NULL, "BST4P Power"},
3293 {"BST1 CBJ", NULL, "IN1P"},
3294 {"BST1 CBJ", NULL, "IN1N"},
3295 {"BST1 CBJ", NULL, "CBJ Power"},
3296 {"CBJ Power", NULL, "Vref2"},
3298 {"INL VOL", NULL, "IN3P"},
3299 {"INR VOL", NULL, "IN3N"},
3301 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3302 {"RECMIX1L", "INL Switch", "INL VOL"},
3303 {"RECMIX1L", "INR Switch", "INR VOL"},
3304 {"RECMIX1L", "BST4 Switch", "BST4"},
3305 {"RECMIX1L", "BST3 Switch", "BST3"},
3306 {"RECMIX1L", "BST2 Switch", "BST2"},
3307 {"RECMIX1L", "BST1 Switch", "BST1"},
3308 {"RECMIX1L", NULL, "RECMIX1L Power"},
3310 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3311 {"RECMIX1R", "INR Switch", "INR VOL"},
3312 {"RECMIX1R", "BST4 Switch", "BST4"},
3313 {"RECMIX1R", "BST3 Switch", "BST3"},
3314 {"RECMIX1R", "BST2 Switch", "BST2"},
3315 {"RECMIX1R", "BST1 Switch", "BST1"},
3316 {"RECMIX1R", NULL, "RECMIX1R Power"},
3318 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3319 {"RECMIX2L", "INL Switch", "INL VOL"},
3320 {"RECMIX2L", "INR Switch", "INR VOL"},
3321 {"RECMIX2L", "BST4 Switch", "BST4"},
3322 {"RECMIX2L", "BST3 Switch", "BST3"},
3323 {"RECMIX2L", "BST2 Switch", "BST2"},
3324 {"RECMIX2L", "BST1 Switch", "BST1"},
3325 {"RECMIX2L", NULL, "RECMIX2L Power"},
3327 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3328 {"RECMIX2R", "INL Switch", "INL VOL"},
3329 {"RECMIX2R", "INR Switch", "INR VOL"},
3330 {"RECMIX2R", "BST4 Switch", "BST4"},
3331 {"RECMIX2R", "BST3 Switch", "BST3"},
3332 {"RECMIX2R", "BST2 Switch", "BST2"},
3333 {"RECMIX2R", "BST1 Switch", "BST1"},
3334 {"RECMIX2R", NULL, "RECMIX2R Power"},
3336 {"ADC1 L", NULL, "RECMIX1L"},
3337 {"ADC1 L", NULL, "ADC1 L Power"},
3338 {"ADC1 L", NULL, "ADC1 clock"},
3339 {"ADC1 R", NULL, "RECMIX1R"},
3340 {"ADC1 R", NULL, "ADC1 R Power"},
3341 {"ADC1 R", NULL, "ADC1 clock"},
3343 {"ADC2 L", NULL, "RECMIX2L"},
3344 {"ADC2 L", NULL, "ADC2 L Power"},
3345 {"ADC2 L", NULL, "ADC2 clock"},
3346 {"ADC2 R", NULL, "RECMIX2R"},
3347 {"ADC2 R", NULL, "ADC2 R Power"},
3348 {"ADC2 R", NULL, "ADC2 clock"},
3350 {"DMIC L1", NULL, "DMIC CLK"},
3351 {"DMIC L1", NULL, "DMIC1 Power"},
3352 {"DMIC R1", NULL, "DMIC CLK"},
3353 {"DMIC R1", NULL, "DMIC1 Power"},
3354 {"DMIC L2", NULL, "DMIC CLK"},
3355 {"DMIC L2", NULL, "DMIC2 Power"},
3356 {"DMIC R2", NULL, "DMIC CLK"},
3357 {"DMIC R2", NULL, "DMIC2 Power"},
3359 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3360 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3362 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3363 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3365 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3366 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3368 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3369 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3371 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3372 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3374 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3375 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3377 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3378 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3379 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3380 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3381 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3382 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3383 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3384 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3386 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3387 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3389 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3390 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3392 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3393 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3394 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3395 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3397 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3398 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3399 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3400 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3402 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3403 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3404 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3405 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3407 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3408 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3409 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3410 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3412 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3413 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3415 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3416 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3418 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3419 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3420 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3421 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3423 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3424 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3425 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3426 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3428 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3429 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3430 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3431 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3432 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3433 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3435 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3436 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3438 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3439 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3441 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3442 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3443 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3444 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3446 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3447 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3448 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3449 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3451 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3452 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3453 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3455 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3456 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3457 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3459 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3460 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3461 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3463 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3464 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3465 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3467 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3468 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3469 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3471 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3472 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3473 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3475 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3476 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3477 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3478 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3479 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3480 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3482 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3483 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3484 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3485 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3486 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3487 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3488 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3490 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3491 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3492 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3493 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3494 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3495 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3496 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3497 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3499 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3500 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3501 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3503 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3504 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3505 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3506 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3507 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3508 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3509 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3511 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3512 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3514 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3515 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3516 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3518 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3519 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3520 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3521 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3522 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3523 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3525 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3526 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3527 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3528 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3529 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3530 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3531 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3532 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3533 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3534 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3535 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3536 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3537 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3538 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3539 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3540 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3541 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3542 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3543 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3544 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3545 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3546 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3547 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3548 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3549 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3551 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3552 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3553 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3555 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3556 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3557 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3558 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3559 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3560 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3561 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3563 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3564 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3565 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3566 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3567 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3568 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3569 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3570 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3571 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3572 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3573 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3574 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3575 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3577 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3578 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3579 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3580 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3581 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3583 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3584 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3585 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3586 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3587 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3588 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3589 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3590 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3591 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3592 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3593 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3594 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3595 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3596 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3597 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3598 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3599 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3600 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3601 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3604 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3605 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3606 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3608 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3609 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3610 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3611 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3612 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3613 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3614 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3616 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3617 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3619 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3620 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3621 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3623 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3624 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3626 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3627 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3628 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3630 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3631 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3632 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3633 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3634 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3635 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3636 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3637 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3638 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3639 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3640 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3641 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3642 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3643 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3644 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3645 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3646 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3647 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3648 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3649 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3650 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3651 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3652 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3653 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3654 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3656 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3657 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3658 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3660 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3661 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3662 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3663 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3664 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3665 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3666 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3668 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3669 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3670 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3671 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3672 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3673 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3674 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3675 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3676 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3677 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3678 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3679 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3680 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3682 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3683 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3684 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3685 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3686 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3688 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3689 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3690 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3691 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3692 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3693 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3694 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3695 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3696 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3697 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3698 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3699 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3700 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3701 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3702 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3703 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3704 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3705 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3706 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3708 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3709 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3710 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3711 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3712 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3713 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3714 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3715 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3716 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3717 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3718 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3719 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3720 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3721 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3722 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3723 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3724 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3725 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3726 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3727 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3728 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3729 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3730 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3731 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3732 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3733 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3734 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3735 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3736 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3737 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3738 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3739 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3741 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3742 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3743 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3744 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3745 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3746 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3747 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3748 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3749 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3750 {"IF2_1 ADC", NULL, "I2S2_1"},
3752 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3753 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3754 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3755 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3756 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3757 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3758 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3759 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3760 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3761 {"IF2_2 ADC", NULL, "I2S2_2"},
3763 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3764 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3765 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3766 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3767 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3768 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3769 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3770 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3771 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3772 {"IF3 ADC", NULL, "I2S3"},
3774 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3775 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3776 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3777 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3778 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3779 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3780 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3781 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3782 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3783 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3784 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3785 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3786 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3787 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3788 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3789 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3790 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3791 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3792 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3793 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3794 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3795 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3796 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3797 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3798 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3799 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3800 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3801 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3802 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3803 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3804 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3806 {"IF1 DAC1", NULL, "AIF1RX"},
3807 {"IF1 DAC2", NULL, "AIF1RX"},
3808 {"IF1 DAC3", NULL, "AIF1RX"},
3809 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3810 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3811 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3812 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3813 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3814 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3815 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3816 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3817 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3818 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3819 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3820 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3821 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3822 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3823 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3825 {"IF1 DAC1", NULL, "I2S1_1"},
3826 {"IF1 DAC2", NULL, "I2S1_1"},
3827 {"IF1 DAC3", NULL, "I2S1_1"},
3828 {"IF2_1 DAC", NULL, "I2S2_1"},
3829 {"IF2_2 DAC", NULL, "I2S2_2"},
3830 {"IF3 DAC", NULL, "I2S3"},
3832 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3833 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3834 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3835 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3836 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3837 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3838 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3839 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3840 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3841 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3842 {"IF3 DAC L", NULL, "IF3 DAC"},
3843 {"IF3 DAC R", NULL, "IF3 DAC"},
3845 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3846 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3847 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3848 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3849 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3851 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3852 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3853 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3854 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3855 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3857 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3858 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3859 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3860 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3862 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3863 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3865 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3866 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3867 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3868 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3869 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3870 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3872 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3873 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3874 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3875 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3876 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3877 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3879 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3880 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3881 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3882 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3883 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3884 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3886 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3887 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3888 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3889 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3890 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3891 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3893 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3894 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3895 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3896 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3898 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3899 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3900 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3901 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3903 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3904 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3905 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3907 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3908 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3909 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3911 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3912 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3913 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3914 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3915 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3916 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3917 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3918 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3920 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3921 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3922 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3923 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3924 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3925 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3927 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3928 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3929 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3930 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3931 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3932 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3934 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3935 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3936 {"DAC L2 Source", NULL, "DAC L2 Power"},
3937 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3938 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3939 {"DAC R2 Source", NULL, "DAC R2 Power"},
3941 {"DAC L1", NULL, "DAC L1 Source"},
3942 {"DAC R1", NULL, "DAC R1 Source"},
3943 {"DAC L2", NULL, "DAC L2 Source"},
3944 {"DAC R2", NULL, "DAC R2 Source"},
3946 {"DAC L1", NULL, "DAC 1 Clock"},
3947 {"DAC R1", NULL, "DAC 1 Clock"},
3948 {"DAC L2", NULL, "DAC 2 Clock"},
3949 {"DAC R2", NULL, "DAC 2 Clock"},
3951 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3952 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3953 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3954 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3955 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3957 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3958 {"OUT MIXL", "INL Switch", "INL VOL"},
3959 {"OUT MIXL", "BST1 Switch", "BST1"},
3960 {"OUT MIXL", "BST2 Switch", "BST2"},
3961 {"OUT MIXL", "BST3 Switch", "BST3"},
3962 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3963 {"OUT MIXR", "INR Switch", "INR VOL"},
3964 {"OUT MIXR", "BST2 Switch", "BST2"},
3965 {"OUT MIXR", "BST3 Switch", "BST3"},
3966 {"OUT MIXR", "BST4 Switch", "BST4"},
3968 {"MONOVOL", "Switch", "MONOVOL MIX"},
3969 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3970 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3971 {"Mono Amp", NULL, "Mono MIX"},
3972 {"Mono Amp", NULL, "Vref2"},
3973 {"Mono Amp", NULL, "Vref3"},
3974 {"Mono Amp", NULL, "CLKDET SYS"},
3975 {"Mono Amp", NULL, "CLKDET MONO"},
3976 {"Mono Playback", "Switch", "Mono Amp"},
3977 {"MONOOUT", NULL, "Mono Playback"},
3979 {"HP Amp", NULL, "DAC L1"},
3980 {"HP Amp", NULL, "DAC R1"},
3981 {"HP Amp", NULL, "Charge Pump"},
3982 {"HP Amp", NULL, "CLKDET SYS"},
3983 {"HP Amp", NULL, "CLKDET HP"},
3984 {"HP Amp", NULL, "CBJ Power"},
3985 {"HP Amp", NULL, "Vref2"},
3986 {"HPO Playback", "Switch", "HP Amp"},
3987 {"HPOL", NULL, "HPO Playback"},
3988 {"HPOR", NULL, "HPO Playback"},
3990 {"OUTVOL L", "Switch", "OUT MIXL"},
3991 {"OUTVOL R", "Switch", "OUT MIXR"},
3992 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3993 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3994 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3995 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3996 {"LOUT Amp", NULL, "LOUT L MIX"},
3997 {"LOUT Amp", NULL, "LOUT R MIX"},
3998 {"LOUT Amp", NULL, "Vref1"},
3999 {"LOUT Amp", NULL, "Vref2"},
4000 {"LOUT Amp", NULL, "CLKDET SYS"},
4001 {"LOUT Amp", NULL, "CLKDET LOUT"},
4002 {"LOUT L Playback", "Switch", "LOUT Amp"},
4003 {"LOUT R Playback", "Switch", "LOUT Amp"},
4004 {"LOUTL", NULL, "LOUT L Playback"},
4005 {"LOUTR", NULL, "LOUT R Playback"},
4007 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4008 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4009 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4010 {"PDM L Mux", NULL, "PDM Power"},
4011 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4012 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4013 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4014 {"PDM R Mux", NULL, "PDM Power"},
4015 {"PDM L Playback", "Switch", "PDM L Mux"},
4016 {"PDM R Playback", "Switch", "PDM R Mux"},
4017 {"PDML", NULL, "PDM L Playback"},
4018 {"PDMR", NULL, "PDM R Playback"},
4021 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4022 unsigned int rx_mask, int slots, int slot_width)
4024 struct snd_soc_codec *codec = dai->codec;
4025 unsigned int val = 0;
4027 if (rx_mask || tx_mask)
4028 val |= RT5665_I2S1_MODE_TDM;
4032 val |= RT5665_TDM_IN_CH_4;
4033 val |= RT5665_TDM_OUT_CH_4;
4036 val |= RT5665_TDM_IN_CH_6;
4037 val |= RT5665_TDM_OUT_CH_6;
4040 val |= RT5665_TDM_IN_CH_8;
4041 val |= RT5665_TDM_OUT_CH_8;
4049 switch (slot_width) {
4051 val |= RT5665_TDM_IN_LEN_20;
4052 val |= RT5665_TDM_OUT_LEN_20;
4055 val |= RT5665_TDM_IN_LEN_24;
4056 val |= RT5665_TDM_OUT_LEN_24;
4059 val |= RT5665_TDM_IN_LEN_32;
4060 val |= RT5665_TDM_OUT_LEN_32;
4068 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4069 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4070 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4071 RT5665_TDM_OUT_LEN_MASK, val);
4077 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4078 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4080 struct snd_soc_codec *codec = dai->codec;
4081 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4082 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4083 int pre_div, frame_size;
4085 rt5665->lrck[dai->id] = params_rate(params);
4086 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4088 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4089 rt5665->lrck[dai->id], dai->id);
4092 frame_size = snd_soc_params_to_frame_size(params);
4093 if (frame_size < 0) {
4094 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4098 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4099 rt5665->lrck[dai->id], pre_div, dai->id);
4101 switch (params_width(params)) {
4106 val_len |= RT5665_I2S_DL_20;
4110 val_len |= RT5665_I2S_DL_24;
4114 val_len |= RT5665_I2S_DL_8;
4123 if (params_channels(params) > 2)
4124 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4125 params_channels(params), params_width(params));
4126 reg_clk = RT5665_ADDA_CLK_1;
4127 mask_clk = RT5665_I2S_PD1_MASK;
4128 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4129 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4130 RT5665_I2S_DL_MASK, val_len);
4134 reg_clk = RT5665_ADDA_CLK_2;
4135 mask_clk = RT5665_I2S_PD2_MASK;
4136 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4137 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4138 RT5665_I2S_DL_MASK, val_len);
4141 reg_clk = RT5665_ADDA_CLK_2;
4142 mask_clk = RT5665_I2S_PD3_MASK;
4143 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4144 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4145 RT5665_I2S_DL_MASK, val_len);
4148 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4152 snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
4153 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4155 switch (rt5665->lrck[dai->id]) {
4157 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4158 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4159 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4162 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4163 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4164 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4167 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4168 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4169 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4176 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4178 struct snd_soc_codec *codec = dai->codec;
4179 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4180 unsigned int reg_val = 0;
4182 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4183 case SND_SOC_DAIFMT_CBM_CFM:
4184 rt5665->master[dai->id] = 1;
4186 case SND_SOC_DAIFMT_CBS_CFS:
4187 reg_val |= RT5665_I2S_MS_S;
4188 rt5665->master[dai->id] = 0;
4194 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4195 case SND_SOC_DAIFMT_NB_NF:
4197 case SND_SOC_DAIFMT_IB_NF:
4198 reg_val |= RT5665_I2S_BP_INV;
4204 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4205 case SND_SOC_DAIFMT_I2S:
4207 case SND_SOC_DAIFMT_LEFT_J:
4208 reg_val |= RT5665_I2S_DF_LEFT;
4210 case SND_SOC_DAIFMT_DSP_A:
4211 reg_val |= RT5665_I2S_DF_PCM_A;
4213 case SND_SOC_DAIFMT_DSP_B:
4214 reg_val |= RT5665_I2S_DF_PCM_B;
4223 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4224 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4225 RT5665_I2S_DF_MASK, reg_val);
4229 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4230 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4231 RT5665_I2S_DF_MASK, reg_val);
4234 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4235 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4236 RT5665_I2S_DF_MASK, reg_val);
4239 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4245 static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4246 int source, unsigned int freq, int dir)
4248 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4249 unsigned int reg_val = 0;
4251 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4255 case RT5665_SCLK_S_MCLK:
4256 reg_val |= RT5665_SCLK_SRC_MCLK;
4258 case RT5665_SCLK_S_PLL1:
4259 reg_val |= RT5665_SCLK_SRC_PLL1;
4261 case RT5665_SCLK_S_RCCLK:
4262 reg_val |= RT5665_SCLK_SRC_RCCLK;
4265 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4268 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4269 RT5665_SCLK_SRC_MASK, reg_val);
4270 rt5665->sysclk = freq;
4271 rt5665->sysclk_src = clk_id;
4273 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4278 static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4279 int source, unsigned int freq_in,
4280 unsigned int freq_out)
4282 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4283 struct rl6231_pll_code pll_code;
4286 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4287 freq_out == rt5665->pll_out)
4290 if (!freq_in || !freq_out) {
4291 dev_dbg(codec->dev, "PLL disabled\n");
4294 rt5665->pll_out = 0;
4295 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4296 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4301 case RT5665_PLL1_S_MCLK:
4302 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4303 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4305 case RT5665_PLL1_S_BCLK1:
4306 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4307 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4309 case RT5665_PLL1_S_BCLK2:
4310 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4311 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4313 case RT5665_PLL1_S_BCLK3:
4314 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4315 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4318 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
4322 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4324 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4328 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4329 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4330 pll_code.n_code, pll_code.k_code);
4332 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4333 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4334 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4335 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4336 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4338 rt5665->pll_in = freq_in;
4339 rt5665->pll_out = freq_out;
4340 rt5665->pll_src = source;
4345 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4347 struct snd_soc_codec *codec = dai->codec;
4348 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4350 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4352 rt5665->bclk[dai->id] = ratio;
4358 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4359 RT5665_I2S_BCLK_MS2_MASK,
4360 RT5665_I2S_BCLK_MS2_64);
4363 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4364 RT5665_I2S_BCLK_MS3_MASK,
4365 RT5665_I2S_BCLK_MS3_64);
4373 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4374 enum snd_soc_bias_level level)
4376 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4379 case SND_SOC_BIAS_PREPARE:
4380 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4381 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4384 case SND_SOC_BIAS_STANDBY:
4385 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4386 RT5665_PWR_LDO, RT5665_PWR_LDO);
4387 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4388 RT5665_PWR_MB, RT5665_PWR_MB);
4389 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4390 RT5665_DIG_GATE_CTRL, 0);
4392 case SND_SOC_BIAS_OFF:
4393 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4395 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4406 static int rt5665_probe(struct snd_soc_codec *codec)
4408 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4410 rt5665->codec = codec;
4412 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4417 static int rt5665_remove(struct snd_soc_codec *codec)
4419 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4421 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4427 static int rt5665_suspend(struct snd_soc_codec *codec)
4429 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4431 regcache_cache_only(rt5665->regmap, true);
4432 regcache_mark_dirty(rt5665->regmap);
4436 static int rt5665_resume(struct snd_soc_codec *codec)
4438 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4440 regcache_cache_only(rt5665->regmap, false);
4441 regcache_sync(rt5665->regmap);
4446 #define rt5665_suspend NULL
4447 #define rt5665_resume NULL
4450 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4451 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4452 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4454 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4455 .hw_params = rt5665_hw_params,
4456 .set_fmt = rt5665_set_dai_fmt,
4457 .set_tdm_slot = rt5665_set_tdm_slot,
4458 .set_bclk_ratio = rt5665_set_bclk_ratio,
4461 static struct snd_soc_dai_driver rt5665_dai[] = {
4463 .name = "rt5665-aif1_1",
4464 .id = RT5665_AIF1_1,
4466 .stream_name = "AIF1 Playback",
4469 .rates = RT5665_STEREO_RATES,
4470 .formats = RT5665_FORMATS,
4473 .stream_name = "AIF1_1 Capture",
4476 .rates = RT5665_STEREO_RATES,
4477 .formats = RT5665_FORMATS,
4479 .ops = &rt5665_aif_dai_ops,
4482 .name = "rt5665-aif1_2",
4483 .id = RT5665_AIF1_2,
4485 .stream_name = "AIF1_2 Capture",
4488 .rates = RT5665_STEREO_RATES,
4489 .formats = RT5665_FORMATS,
4491 .ops = &rt5665_aif_dai_ops,
4494 .name = "rt5665-aif2_1",
4495 .id = RT5665_AIF2_1,
4497 .stream_name = "AIF2_1 Playback",
4500 .rates = RT5665_STEREO_RATES,
4501 .formats = RT5665_FORMATS,
4504 .stream_name = "AIF2_1 Capture",
4507 .rates = RT5665_STEREO_RATES,
4508 .formats = RT5665_FORMATS,
4510 .ops = &rt5665_aif_dai_ops,
4513 .name = "rt5665-aif2_2",
4514 .id = RT5665_AIF2_2,
4516 .stream_name = "AIF2_2 Playback",
4519 .rates = RT5665_STEREO_RATES,
4520 .formats = RT5665_FORMATS,
4523 .stream_name = "AIF2_2 Capture",
4526 .rates = RT5665_STEREO_RATES,
4527 .formats = RT5665_FORMATS,
4529 .ops = &rt5665_aif_dai_ops,
4532 .name = "rt5665-aif3",
4535 .stream_name = "AIF3 Playback",
4538 .rates = RT5665_STEREO_RATES,
4539 .formats = RT5665_FORMATS,
4542 .stream_name = "AIF3 Capture",
4545 .rates = RT5665_STEREO_RATES,
4546 .formats = RT5665_FORMATS,
4548 .ops = &rt5665_aif_dai_ops,
4552 static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4553 .probe = rt5665_probe,
4554 .remove = rt5665_remove,
4555 .suspend = rt5665_suspend,
4556 .resume = rt5665_resume,
4557 .set_bias_level = rt5665_set_bias_level,
4558 .idle_bias_off = true,
4559 .component_driver = {
4560 .controls = rt5665_snd_controls,
4561 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4562 .dapm_widgets = rt5665_dapm_widgets,
4563 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4564 .dapm_routes = rt5665_dapm_routes,
4565 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4567 .set_sysclk = rt5665_set_codec_sysclk,
4568 .set_pll = rt5665_set_codec_pll,
4569 .set_jack = rt5665_set_jack_detect,
4573 static const struct regmap_config rt5665_regmap = {
4576 .max_register = 0x0400,
4577 .volatile_reg = rt5665_volatile_register,
4578 .readable_reg = rt5665_readable_register,
4579 .cache_type = REGCACHE_RBTREE,
4580 .reg_defaults = rt5665_reg,
4581 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4582 .use_single_rw = true,
4585 static const struct i2c_device_id rt5665_i2c_id[] = {
4589 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4591 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4593 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4594 "realtek,in1-differential");
4595 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4596 "realtek,in2-differential");
4597 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4598 "realtek,in3-differential");
4599 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4600 "realtek,in4-differential");
4602 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4603 &rt5665->pdata.dmic1_data_pin);
4604 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4605 &rt5665->pdata.dmic2_data_pin);
4606 of_property_read_u32(dev->of_node, "realtek,jd-src",
4607 &rt5665->pdata.jd_src);
4609 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4610 "realtek,ldo1-en-gpios", 0);
4615 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4619 mutex_lock(&rt5665->calibrate_mutex);
4621 regcache_cache_bypass(rt5665->regmap, true);
4623 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4624 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4625 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4626 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4627 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4628 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4629 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4630 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4631 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4632 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4633 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4634 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4635 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4636 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4637 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4638 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4639 usleep_range(15000, 20000);
4640 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4641 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4643 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4646 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4648 usleep_range(10000, 10005);
4653 pr_err("HP Calibration Failure\n");
4654 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4655 regcache_cache_bypass(rt5665->regmap, false);
4662 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4665 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4667 usleep_range(10000, 10005);
4672 pr_err("MONO Calibration Failure\n");
4673 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4674 regcache_cache_bypass(rt5665->regmap, false);
4681 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4682 regcache_cache_bypass(rt5665->regmap, false);
4684 regcache_mark_dirty(rt5665->regmap);
4685 regcache_sync(rt5665->regmap);
4687 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4688 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4691 mutex_unlock(&rt5665->calibrate_mutex);
4694 static void rt5665_calibrate_handler(struct work_struct *work)
4696 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4697 calibrate_work.work);
4699 while (!rt5665->codec->component.card->instantiated) {
4700 pr_debug("%s\n", __func__);
4701 usleep_range(10000, 15000);
4704 rt5665_calibrate(rt5665);
4707 static int rt5665_i2c_probe(struct i2c_client *i2c,
4708 const struct i2c_device_id *id)
4710 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4711 struct rt5665_priv *rt5665;
4715 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4721 i2c_set_clientdata(i2c, rt5665);
4724 rt5665->pdata = *pdata;
4726 rt5665_parse_dt(rt5665, &i2c->dev);
4728 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4729 rt5665->supplies[i].supply = rt5665_supply_names[i];
4731 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4734 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4738 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4741 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4745 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4746 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4747 GPIOF_OUT_INIT_HIGH, "rt5665"))
4748 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4751 /* Sleep for 300 ms miniumum */
4752 usleep_range(300000, 350000);
4754 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4755 if (IS_ERR(rt5665->regmap)) {
4756 ret = PTR_ERR(rt5665->regmap);
4757 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4762 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4763 if (val != DEVICE_ID) {
4765 "Device with ID register %x is not rt5665\n", val);
4769 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4772 rt5665->id = CODEC_5666;
4775 rt5665->id = CODEC_5668;
4779 rt5665->id = CODEC_5665;
4783 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4785 /* line in diff mode*/
4786 if (rt5665->pdata.in1_diff)
4787 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4788 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4789 if (rt5665->pdata.in2_diff)
4790 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4791 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4792 if (rt5665->pdata.in3_diff)
4793 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4794 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4795 if (rt5665->pdata.in4_diff)
4796 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4797 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4800 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4801 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4802 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4803 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4804 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4805 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4806 switch (rt5665->pdata.dmic1_data_pin) {
4807 case RT5665_DMIC1_DATA_IN2N:
4808 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4809 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4812 case RT5665_DMIC1_DATA_GPIO4:
4813 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4814 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4815 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4816 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4820 dev_dbg(&i2c->dev, "no DMIC1\n");
4824 switch (rt5665->pdata.dmic2_data_pin) {
4825 case RT5665_DMIC2_DATA_IN2P:
4826 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4827 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4830 case RT5665_DMIC2_DATA_GPIO5:
4831 regmap_update_bits(rt5665->regmap,
4833 RT5665_DMIC_2_DP_MASK,
4834 RT5665_DMIC_2_DP_GPIO5);
4835 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4836 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4840 dev_dbg(&i2c->dev, "no DMIC2\n");
4846 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4847 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4848 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4849 /* Work around for pow_pump */
4850 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4851 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4853 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4854 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4856 /* Set GPIO4,8 as input for combo jack */
4857 if (rt5665->id == CODEC_5666) {
4858 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4859 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4860 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4861 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4864 /* Enhance performance*/
4865 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4866 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4867 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4869 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4870 rt5665_jack_detect_handler);
4871 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4872 rt5665_calibrate_handler);
4873 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4874 rt5665_jd_check_handler);
4876 mutex_init(&rt5665->calibrate_mutex);
4879 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4880 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4881 | IRQF_ONESHOT, "rt5665", rt5665);
4883 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4887 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4888 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4891 static int rt5665_i2c_remove(struct i2c_client *i2c)
4893 snd_soc_unregister_codec(&i2c->dev);
4898 static void rt5665_i2c_shutdown(struct i2c_client *client)
4900 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4902 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4906 static const struct of_device_id rt5665_of_match[] = {
4907 {.compatible = "realtek,rt5665"},
4908 {.compatible = "realtek,rt5666"},
4909 {.compatible = "realtek,rt5668"},
4912 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4916 static struct acpi_device_id rt5665_acpi_match[] = {
4922 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4925 struct i2c_driver rt5665_i2c_driver = {
4928 .of_match_table = of_match_ptr(rt5665_of_match),
4929 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4931 .probe = rt5665_i2c_probe,
4932 .remove = rt5665_i2c_remove,
4933 .shutdown = rt5665_i2c_shutdown,
4934 .id_table = rt5665_i2c_id,
4936 module_i2c_driver(rt5665_i2c_driver);
4938 MODULE_DESCRIPTION("ASoC RT5665 driver");
4939 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4940 MODULE_LICENSE("GPL v2");
git.samba.org / sfrench / cifs-2.6.git / blob