2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5665.h>
38 #define RT5665_NUM_SUPPLIES 3
40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
73 bool calibration_done;
76 static const struct reg_default rt5665_reg[] = {
467 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
471 case RT5665_EJD_CTRL_2:
472 case RT5665_GPIO_STA:
473 case RT5665_INT_ST_1:
474 case RT5665_IL_CMD_1:
475 case RT5665_4BTN_IL_CMD_1:
476 case RT5665_PSV_IL_CMD_1:
477 case RT5665_AJD1_CTRL:
478 case RT5665_JD_CTRL_3:
479 case RT5665_STO_NG2_CTRL_1:
480 case RT5665_SAR_IL_CMD_4:
481 case RT5665_DEVICE_ID:
482 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
483 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
484 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
485 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
492 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
496 case RT5665_VENDOR_ID:
497 case RT5665_VENDOR_ID_1:
498 case RT5665_DEVICE_ID:
500 case RT5665_HP_CTRL_1:
501 case RT5665_HP_CTRL_2:
502 case RT5665_MONO_OUT:
503 case RT5665_HPL_GAIN:
504 case RT5665_HPR_GAIN:
505 case RT5665_MONO_GAIN:
506 case RT5665_CAL_BST_CTRL:
507 case RT5665_CBJ_BST_CTRL:
510 case RT5665_INL1_INR1_VOL:
511 case RT5665_EJD_CTRL_1:
512 case RT5665_EJD_CTRL_2:
513 case RT5665_EJD_CTRL_3:
514 case RT5665_EJD_CTRL_4:
515 case RT5665_EJD_CTRL_5:
516 case RT5665_EJD_CTRL_6:
517 case RT5665_EJD_CTRL_7:
518 case RT5665_DAC2_CTRL:
519 case RT5665_DAC2_DIG_VOL:
520 case RT5665_DAC1_DIG_VOL:
521 case RT5665_DAC3_DIG_VOL:
522 case RT5665_DAC3_CTRL:
523 case RT5665_STO1_ADC_DIG_VOL:
524 case RT5665_MONO_ADC_DIG_VOL:
525 case RT5665_STO2_ADC_DIG_VOL:
526 case RT5665_STO1_ADC_BOOST:
527 case RT5665_MONO_ADC_BOOST:
528 case RT5665_STO2_ADC_BOOST:
529 case RT5665_HP_IMP_GAIN_1:
530 case RT5665_HP_IMP_GAIN_2:
531 case RT5665_STO1_ADC_MIXER:
532 case RT5665_MONO_ADC_MIXER:
533 case RT5665_STO2_ADC_MIXER:
534 case RT5665_AD_DA_MIXER:
535 case RT5665_STO1_DAC_MIXER:
536 case RT5665_MONO_DAC_MIXER:
537 case RT5665_STO2_DAC_MIXER:
538 case RT5665_A_DAC1_MUX:
539 case RT5665_A_DAC2_MUX:
540 case RT5665_DIG_INF2_DATA:
541 case RT5665_DIG_INF3_DATA:
542 case RT5665_PDM_OUT_CTRL:
543 case RT5665_PDM_DATA_CTRL_1:
544 case RT5665_PDM_DATA_CTRL_2:
545 case RT5665_PDM_DATA_CTRL_3:
546 case RT5665_PDM_DATA_CTRL_4:
547 case RT5665_REC1_GAIN:
548 case RT5665_REC1_L1_MIXER:
549 case RT5665_REC1_L2_MIXER:
550 case RT5665_REC1_R1_MIXER:
551 case RT5665_REC1_R2_MIXER:
552 case RT5665_REC2_GAIN:
553 case RT5665_REC2_L1_MIXER:
554 case RT5665_REC2_L2_MIXER:
555 case RT5665_REC2_R1_MIXER:
556 case RT5665_REC2_R2_MIXER:
558 case RT5665_ALC_BACK_GAIN:
559 case RT5665_MONOMIX_GAIN:
560 case RT5665_MONOMIX_IN_GAIN:
561 case RT5665_OUT_L_GAIN:
562 case RT5665_OUT_L_MIXER:
563 case RT5665_OUT_R_GAIN:
564 case RT5665_OUT_R_MIXER:
565 case RT5665_LOUT_MIXER:
566 case RT5665_PWR_DIG_1:
567 case RT5665_PWR_DIG_2:
568 case RT5665_PWR_ANLG_1:
569 case RT5665_PWR_ANLG_2:
570 case RT5665_PWR_ANLG_3:
571 case RT5665_PWR_MIXER:
574 case RT5665_HPF_CTRL1:
575 case RT5665_DMIC_CTRL_1:
576 case RT5665_DMIC_CTRL_2:
577 case RT5665_I2S1_SDP:
578 case RT5665_I2S2_SDP:
579 case RT5665_I2S3_SDP:
580 case RT5665_ADDA_CLK_1:
581 case RT5665_ADDA_CLK_2:
582 case RT5665_I2S1_F_DIV_CTRL_1:
583 case RT5665_I2S1_F_DIV_CTRL_2:
584 case RT5665_TDM_CTRL_1:
585 case RT5665_TDM_CTRL_2:
586 case RT5665_TDM_CTRL_3:
587 case RT5665_TDM_CTRL_4:
588 case RT5665_TDM_CTRL_5:
589 case RT5665_TDM_CTRL_6:
590 case RT5665_TDM_CTRL_7:
591 case RT5665_TDM_CTRL_8:
593 case RT5665_PLL_CTRL_1:
594 case RT5665_PLL_CTRL_2:
607 case RT5665_HP_CHARGE_PUMP_1:
608 case RT5665_HP_CHARGE_PUMP_2:
609 case RT5665_MICBIAS_1:
610 case RT5665_MICBIAS_2:
614 case RT5665_RC_CLK_CTRL:
615 case RT5665_I2S_M_CLK_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_1:
617 case RT5665_I2S2_F_DIV_CTRL_2:
618 case RT5665_I2S3_F_DIV_CTRL_1:
619 case RT5665_I2S3_F_DIV_CTRL_2:
620 case RT5665_EQ_CTRL_1:
621 case RT5665_EQ_CTRL_2:
622 case RT5665_IRQ_CTRL_1:
623 case RT5665_IRQ_CTRL_2:
624 case RT5665_IRQ_CTRL_3:
625 case RT5665_IRQ_CTRL_4:
626 case RT5665_IRQ_CTRL_5:
627 case RT5665_IRQ_CTRL_6:
628 case RT5665_INT_ST_1:
629 case RT5665_GPIO_CTRL_1:
630 case RT5665_GPIO_CTRL_2:
631 case RT5665_GPIO_CTRL_3:
632 case RT5665_GPIO_CTRL_4:
633 case RT5665_GPIO_STA:
634 case RT5665_HP_AMP_DET_CTRL_1:
635 case RT5665_HP_AMP_DET_CTRL_2:
636 case RT5665_MID_HP_AMP_DET:
637 case RT5665_LOW_HP_AMP_DET:
638 case RT5665_SV_ZCD_1:
639 case RT5665_SV_ZCD_2:
640 case RT5665_IL_CMD_1:
641 case RT5665_IL_CMD_2:
642 case RT5665_IL_CMD_3:
643 case RT5665_IL_CMD_4:
644 case RT5665_4BTN_IL_CMD_1:
645 case RT5665_4BTN_IL_CMD_2:
646 case RT5665_4BTN_IL_CMD_3:
647 case RT5665_PSV_IL_CMD_1:
648 case RT5665_ADC_STO1_HP_CTRL_1:
649 case RT5665_ADC_STO1_HP_CTRL_2:
650 case RT5665_ADC_MONO_HP_CTRL_1:
651 case RT5665_ADC_MONO_HP_CTRL_2:
652 case RT5665_ADC_STO2_HP_CTRL_1:
653 case RT5665_ADC_STO2_HP_CTRL_2:
654 case RT5665_AJD1_CTRL:
657 case RT5665_JD_CTRL_1:
658 case RT5665_JD_CTRL_2:
659 case RT5665_JD_CTRL_3:
660 case RT5665_DIG_MISC:
663 case RT5665_DAC_ADC_DIG_VOL1:
664 case RT5665_DAC_ADC_DIG_VOL2:
665 case RT5665_BIAS_CUR_CTRL_1:
666 case RT5665_BIAS_CUR_CTRL_2:
667 case RT5665_BIAS_CUR_CTRL_3:
668 case RT5665_BIAS_CUR_CTRL_4:
669 case RT5665_BIAS_CUR_CTRL_5:
670 case RT5665_BIAS_CUR_CTRL_6:
671 case RT5665_BIAS_CUR_CTRL_7:
672 case RT5665_BIAS_CUR_CTRL_8:
673 case RT5665_BIAS_CUR_CTRL_9:
674 case RT5665_BIAS_CUR_CTRL_10:
675 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
676 case RT5665_CHARGE_PUMP_1:
677 case RT5665_DIG_IN_CTRL_1:
678 case RT5665_DIG_IN_CTRL_2:
679 case RT5665_PAD_DRIVING_CTRL:
680 case RT5665_SOFT_RAMP_DEPOP:
682 case RT5665_CHOP_DAC:
683 case RT5665_CHOP_ADC:
684 case RT5665_CALIB_ADC_CTRL:
685 case RT5665_VOL_TEST:
686 case RT5665_TEST_MODE_CTRL_1:
687 case RT5665_TEST_MODE_CTRL_2:
688 case RT5665_TEST_MODE_CTRL_3:
689 case RT5665_TEST_MODE_CTRL_4:
690 case RT5665_BASSBACK_CTRL:
691 case RT5665_STO_NG2_CTRL_1:
692 case RT5665_STO_NG2_CTRL_2:
693 case RT5665_STO_NG2_CTRL_3:
694 case RT5665_STO_NG2_CTRL_4:
695 case RT5665_STO_NG2_CTRL_5:
696 case RT5665_STO_NG2_CTRL_6:
697 case RT5665_STO_NG2_CTRL_7:
698 case RT5665_STO_NG2_CTRL_8:
699 case RT5665_MONO_NG2_CTRL_1:
700 case RT5665_MONO_NG2_CTRL_2:
701 case RT5665_MONO_NG2_CTRL_3:
702 case RT5665_MONO_NG2_CTRL_4:
703 case RT5665_MONO_NG2_CTRL_5:
704 case RT5665_MONO_NG2_CTRL_6:
705 case RT5665_STO1_DAC_SIL_DET:
706 case RT5665_MONOL_DAC_SIL_DET:
707 case RT5665_MONOR_DAC_SIL_DET:
708 case RT5665_STO2_DAC_SIL_DET:
709 case RT5665_SIL_PSV_CTRL1:
710 case RT5665_SIL_PSV_CTRL2:
711 case RT5665_SIL_PSV_CTRL3:
712 case RT5665_SIL_PSV_CTRL4:
713 case RT5665_SIL_PSV_CTRL5:
714 case RT5665_SIL_PSV_CTRL6:
715 case RT5665_MONO_AMP_CALIB_CTRL_1:
716 case RT5665_MONO_AMP_CALIB_CTRL_2:
717 case RT5665_MONO_AMP_CALIB_CTRL_3:
718 case RT5665_MONO_AMP_CALIB_CTRL_4:
719 case RT5665_MONO_AMP_CALIB_CTRL_5:
720 case RT5665_MONO_AMP_CALIB_CTRL_6:
721 case RT5665_MONO_AMP_CALIB_CTRL_7:
722 case RT5665_MONO_AMP_CALIB_STA1:
723 case RT5665_MONO_AMP_CALIB_STA2:
724 case RT5665_MONO_AMP_CALIB_STA3:
725 case RT5665_MONO_AMP_CALIB_STA4:
726 case RT5665_MONO_AMP_CALIB_STA6:
727 case RT5665_HP_IMP_SENS_CTRL_01:
728 case RT5665_HP_IMP_SENS_CTRL_02:
729 case RT5665_HP_IMP_SENS_CTRL_03:
730 case RT5665_HP_IMP_SENS_CTRL_04:
731 case RT5665_HP_IMP_SENS_CTRL_05:
732 case RT5665_HP_IMP_SENS_CTRL_06:
733 case RT5665_HP_IMP_SENS_CTRL_07:
734 case RT5665_HP_IMP_SENS_CTRL_08:
735 case RT5665_HP_IMP_SENS_CTRL_09:
736 case RT5665_HP_IMP_SENS_CTRL_10:
737 case RT5665_HP_IMP_SENS_CTRL_11:
738 case RT5665_HP_IMP_SENS_CTRL_12:
739 case RT5665_HP_IMP_SENS_CTRL_13:
740 case RT5665_HP_IMP_SENS_CTRL_14:
741 case RT5665_HP_IMP_SENS_CTRL_15:
742 case RT5665_HP_IMP_SENS_CTRL_16:
743 case RT5665_HP_IMP_SENS_CTRL_17:
744 case RT5665_HP_IMP_SENS_CTRL_18:
745 case RT5665_HP_IMP_SENS_CTRL_19:
746 case RT5665_HP_IMP_SENS_CTRL_20:
747 case RT5665_HP_IMP_SENS_CTRL_21:
748 case RT5665_HP_IMP_SENS_CTRL_22:
749 case RT5665_HP_IMP_SENS_CTRL_23:
750 case RT5665_HP_IMP_SENS_CTRL_24:
751 case RT5665_HP_IMP_SENS_CTRL_25:
752 case RT5665_HP_IMP_SENS_CTRL_26:
753 case RT5665_HP_IMP_SENS_CTRL_27:
754 case RT5665_HP_IMP_SENS_CTRL_28:
755 case RT5665_HP_IMP_SENS_CTRL_29:
756 case RT5665_HP_IMP_SENS_CTRL_30:
757 case RT5665_HP_IMP_SENS_CTRL_31:
758 case RT5665_HP_IMP_SENS_CTRL_32:
759 case RT5665_HP_IMP_SENS_CTRL_33:
760 case RT5665_HP_IMP_SENS_CTRL_34:
761 case RT5665_HP_LOGIC_CTRL_1:
762 case RT5665_HP_LOGIC_CTRL_2:
763 case RT5665_HP_LOGIC_CTRL_3:
764 case RT5665_HP_CALIB_CTRL_1:
765 case RT5665_HP_CALIB_CTRL_2:
766 case RT5665_HP_CALIB_CTRL_3:
767 case RT5665_HP_CALIB_CTRL_4:
768 case RT5665_HP_CALIB_CTRL_5:
769 case RT5665_HP_CALIB_CTRL_6:
770 case RT5665_HP_CALIB_CTRL_7:
771 case RT5665_HP_CALIB_CTRL_9:
772 case RT5665_HP_CALIB_CTRL_10:
773 case RT5665_HP_CALIB_CTRL_11:
774 case RT5665_HP_CALIB_STA_1:
775 case RT5665_HP_CALIB_STA_2:
776 case RT5665_HP_CALIB_STA_3:
777 case RT5665_HP_CALIB_STA_4:
778 case RT5665_HP_CALIB_STA_5:
779 case RT5665_HP_CALIB_STA_6:
780 case RT5665_HP_CALIB_STA_7:
781 case RT5665_HP_CALIB_STA_8:
782 case RT5665_HP_CALIB_STA_9:
783 case RT5665_HP_CALIB_STA_10:
784 case RT5665_HP_CALIB_STA_11:
785 case RT5665_PGM_TAB_CTRL1:
786 case RT5665_PGM_TAB_CTRL2:
787 case RT5665_PGM_TAB_CTRL3:
788 case RT5665_PGM_TAB_CTRL4:
789 case RT5665_PGM_TAB_CTRL5:
790 case RT5665_PGM_TAB_CTRL6:
791 case RT5665_PGM_TAB_CTRL7:
792 case RT5665_PGM_TAB_CTRL8:
793 case RT5665_PGM_TAB_CTRL9:
794 case RT5665_SAR_IL_CMD_1:
795 case RT5665_SAR_IL_CMD_2:
796 case RT5665_SAR_IL_CMD_3:
797 case RT5665_SAR_IL_CMD_4:
798 case RT5665_SAR_IL_CMD_5:
799 case RT5665_SAR_IL_CMD_6:
800 case RT5665_SAR_IL_CMD_7:
801 case RT5665_SAR_IL_CMD_8:
802 case RT5665_SAR_IL_CMD_9:
803 case RT5665_SAR_IL_CMD_10:
804 case RT5665_SAR_IL_CMD_11:
805 case RT5665_SAR_IL_CMD_12:
806 case RT5665_DRC1_CTRL_0:
807 case RT5665_DRC1_CTRL_1:
808 case RT5665_DRC1_CTRL_2:
809 case RT5665_DRC1_CTRL_3:
810 case RT5665_DRC1_CTRL_4:
811 case RT5665_DRC1_CTRL_5:
812 case RT5665_DRC1_CTRL_6:
813 case RT5665_DRC1_HARD_LMT_CTRL_1:
814 case RT5665_DRC1_HARD_LMT_CTRL_2:
815 case RT5665_DRC1_PRIV_1:
816 case RT5665_DRC1_PRIV_2:
817 case RT5665_DRC1_PRIV_3:
818 case RT5665_DRC1_PRIV_4:
819 case RT5665_DRC1_PRIV_5:
820 case RT5665_DRC1_PRIV_6:
821 case RT5665_DRC1_PRIV_7:
822 case RT5665_DRC1_PRIV_8:
823 case RT5665_ALC_PGA_CTRL_1:
824 case RT5665_ALC_PGA_CTRL_2:
825 case RT5665_ALC_PGA_CTRL_3:
826 case RT5665_ALC_PGA_CTRL_4:
827 case RT5665_ALC_PGA_CTRL_5:
828 case RT5665_ALC_PGA_CTRL_6:
829 case RT5665_ALC_PGA_CTRL_7:
830 case RT5665_ALC_PGA_CTRL_8:
831 case RT5665_ALC_PGA_STA_1:
832 case RT5665_ALC_PGA_STA_2:
833 case RT5665_ALC_PGA_STA_3:
834 case RT5665_EQ_AUTO_RCV_CTRL1:
835 case RT5665_EQ_AUTO_RCV_CTRL2:
836 case RT5665_EQ_AUTO_RCV_CTRL3:
837 case RT5665_EQ_AUTO_RCV_CTRL4:
838 case RT5665_EQ_AUTO_RCV_CTRL5:
839 case RT5665_EQ_AUTO_RCV_CTRL6:
840 case RT5665_EQ_AUTO_RCV_CTRL7:
841 case RT5665_EQ_AUTO_RCV_CTRL8:
842 case RT5665_EQ_AUTO_RCV_CTRL9:
843 case RT5665_EQ_AUTO_RCV_CTRL10:
844 case RT5665_EQ_AUTO_RCV_CTRL11:
845 case RT5665_EQ_AUTO_RCV_CTRL12:
846 case RT5665_EQ_AUTO_RCV_CTRL13:
847 case RT5665_ADC_L_EQ_LPF1_A1:
848 case RT5665_R_EQ_LPF1_A1:
849 case RT5665_L_EQ_LPF1_H0:
850 case RT5665_R_EQ_LPF1_H0:
851 case RT5665_L_EQ_BPF1_A1:
852 case RT5665_R_EQ_BPF1_A1:
853 case RT5665_L_EQ_BPF1_A2:
854 case RT5665_R_EQ_BPF1_A2:
855 case RT5665_L_EQ_BPF1_H0:
856 case RT5665_R_EQ_BPF1_H0:
857 case RT5665_L_EQ_BPF2_A1:
858 case RT5665_R_EQ_BPF2_A1:
859 case RT5665_L_EQ_BPF2_A2:
860 case RT5665_R_EQ_BPF2_A2:
861 case RT5665_L_EQ_BPF2_H0:
862 case RT5665_R_EQ_BPF2_H0:
863 case RT5665_L_EQ_BPF3_A1:
864 case RT5665_R_EQ_BPF3_A1:
865 case RT5665_L_EQ_BPF3_A2:
866 case RT5665_R_EQ_BPF3_A2:
867 case RT5665_L_EQ_BPF3_H0:
868 case RT5665_R_EQ_BPF3_H0:
869 case RT5665_L_EQ_BPF4_A1:
870 case RT5665_R_EQ_BPF4_A1:
871 case RT5665_L_EQ_BPF4_A2:
872 case RT5665_R_EQ_BPF4_A2:
873 case RT5665_L_EQ_BPF4_H0:
874 case RT5665_R_EQ_BPF4_H0:
875 case RT5665_L_EQ_HPF1_A1:
876 case RT5665_R_EQ_HPF1_A1:
877 case RT5665_L_EQ_HPF1_H0:
878 case RT5665_R_EQ_HPF1_H0:
879 case RT5665_L_EQ_PRE_VOL:
880 case RT5665_R_EQ_PRE_VOL:
881 case RT5665_L_EQ_POST_VOL:
882 case RT5665_R_EQ_POST_VOL:
883 case RT5665_SCAN_MODE_CTRL:
884 case RT5665_I2C_MODE:
891 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
894 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
895 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
896 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
897 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
898 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
900 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
901 static const DECLARE_TLV_DB_RANGE(bst_tlv,
902 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
903 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
904 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
905 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
906 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
907 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
908 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
911 /* Interface data select */
912 static const char * const rt5665_data_select[] = {
913 "L/R", "R/L", "L/L", "R/R"
916 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
917 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
919 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
920 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
922 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
923 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
925 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
926 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
928 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
929 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
931 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
932 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
934 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
935 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
937 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
938 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
940 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
941 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
943 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
944 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
946 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
947 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
949 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
950 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
952 static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
953 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
955 static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
956 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
958 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
959 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
961 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
962 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
964 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
965 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
967 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
968 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
970 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
971 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
973 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
974 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
976 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
977 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
979 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
980 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
982 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
983 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
985 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
986 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
988 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
989 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
991 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
992 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
994 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
995 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
997 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
998 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
1000 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1003 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1004 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1006 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1007 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1008 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1009 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1010 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1016 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_value *ucontrol)
1019 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1020 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1022 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1023 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1024 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1025 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1026 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1033 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1034 * @codec: SoC audio codec device.
1035 * @filter_mask: mask of filters.
1036 * @clk_src: clock source
1038 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1039 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1040 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1041 * ASRC function will track i2s clock and generate a corresponding system clock
1042 * for codec. This function provides an API to select the clock source for a
1043 * set of filters specified by the mask. And the codec driver will turn on ASRC
1044 * for these filters if ASRC is selected as their clock source.
1046 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1047 unsigned int filter_mask, unsigned int clk_src)
1049 unsigned int asrc2_mask = 0;
1050 unsigned int asrc2_value = 0;
1051 unsigned int asrc3_mask = 0;
1052 unsigned int asrc3_value = 0;
1055 case RT5665_CLK_SEL_SYS:
1056 case RT5665_CLK_SEL_I2S1_ASRC:
1057 case RT5665_CLK_SEL_I2S2_ASRC:
1058 case RT5665_CLK_SEL_I2S3_ASRC:
1059 case RT5665_CLK_SEL_SYS2:
1060 case RT5665_CLK_SEL_SYS3:
1061 case RT5665_CLK_SEL_SYS4:
1068 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1069 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1070 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1071 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1074 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1075 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1076 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1077 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1080 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1081 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1082 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1083 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1086 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1087 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1088 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1089 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1092 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1093 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1094 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1095 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1098 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1099 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1100 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1101 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1104 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1105 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1106 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1107 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1110 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1111 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1112 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1113 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1117 snd_soc_update_bits(codec, RT5665_ASRC_2,
1118 asrc2_mask, asrc2_value);
1121 snd_soc_update_bits(codec, RT5665_ASRC_3,
1122 asrc3_mask, asrc3_value);
1126 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1128 static int rt5665_button_detect(struct snd_soc_codec *codec)
1132 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1133 btn_type = val & 0xfff0;
1134 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1139 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1143 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1144 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1145 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1146 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1147 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1148 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1149 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1150 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1152 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1153 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1154 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1155 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1156 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1157 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1162 * rt5665_headset_detect - Detect headset.
1163 * @codec: SoC audio codec device.
1164 * @jack_insert: Jack insert or not.
1166 * Detect whether is headset or not when jack inserted.
1168 * Returns detect status.
1170 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1172 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1173 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1174 unsigned int sar_hs_type, val;
1177 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1178 snd_soc_dapm_sync(dapm);
1180 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1183 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1185 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1188 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1190 usleep_range(10000, 15000);
1191 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1196 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1198 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1199 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1200 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1202 usleep_range(10000, 15000);
1204 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1205 RT5665_SAR_IL_CMD_4) & 0x7ff;
1207 sar_hs_type = rt5665->pdata.sar_hs_type ?
1208 rt5665->pdata.sar_hs_type : 729;
1210 if (rt5665->sar_adc_value > sar_hs_type) {
1211 rt5665->jack_type = SND_JACK_HEADSET;
1212 rt5665_enable_push_button_irq(codec, true);
1214 rt5665->jack_type = SND_JACK_HEADPHONE;
1215 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1217 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1219 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1220 snd_soc_dapm_sync(dapm);
1223 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1224 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1225 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1226 snd_soc_dapm_sync(dapm);
1227 if (rt5665->jack_type == SND_JACK_HEADSET)
1228 rt5665_enable_push_button_irq(codec, false);
1229 rt5665->jack_type = 0;
1232 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1233 return rt5665->jack_type;
1236 static irqreturn_t rt5665_irq(int irq, void *data)
1238 struct rt5665_priv *rt5665 = data;
1240 mod_delayed_work(system_power_efficient_wq,
1241 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1246 static void rt5665_jd_check_handler(struct work_struct *work)
1248 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1249 jd_check_work.work);
1251 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1253 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1255 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1257 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1258 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1260 schedule_delayed_work(&rt5665->jd_check_work, 500);
1264 static int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1265 struct snd_soc_jack *hs_jack, void *data)
1267 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1269 switch (rt5665->pdata.jd_src) {
1271 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1272 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1273 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1275 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1276 RT5665_PWR_JD1, RT5665_PWR_JD1);
1277 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1280 case RT5665_JD_NULL:
1284 dev_warn(codec->dev, "Wrong JD source\n");
1288 rt5665->hs_jack = hs_jack;
1293 static void rt5665_jack_detect_handler(struct work_struct *work)
1295 struct rt5665_priv *rt5665 =
1296 container_of(work, struct rt5665_priv, jack_detect_work.work);
1299 while (!rt5665->codec) {
1300 pr_debug("%s codec = null\n", __func__);
1301 usleep_range(10000, 15000);
1304 while (!rt5665->codec->component.card->instantiated) {
1305 pr_debug("%s\n", __func__);
1306 usleep_range(10000, 15000);
1309 while (!rt5665->calibration_done) {
1310 pr_debug("%s calibration not ready\n", __func__);
1311 usleep_range(10000, 15000);
1314 mutex_lock(&rt5665->calibrate_mutex);
1316 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1319 if (rt5665->jack_type == 0) {
1320 /* jack was out, report jack type */
1322 rt5665_headset_detect(rt5665->codec, 1);
1324 /* jack is already in, report button event */
1325 rt5665->jack_type = SND_JACK_HEADSET;
1326 btn_type = rt5665_button_detect(rt5665->codec);
1328 * rt5665 can report three kinds of button behavior,
1329 * one click, double click and hold. However,
1330 * currently we will report button pressed/released
1331 * event. So all the three button behaviors are
1332 * treated as button pressed.
1338 rt5665->jack_type |= SND_JACK_BTN_0;
1343 rt5665->jack_type |= SND_JACK_BTN_1;
1348 rt5665->jack_type |= SND_JACK_BTN_2;
1353 rt5665->jack_type |= SND_JACK_BTN_3;
1355 case 0x0000: /* unpressed */
1359 dev_err(rt5665->codec->dev,
1360 "Unexpected button code 0x%04x\n",
1367 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1370 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1372 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1373 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1375 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1376 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1377 schedule_delayed_work(&rt5665->jd_check_work, 0);
1379 cancel_delayed_work_sync(&rt5665->jd_check_work);
1381 mutex_unlock(&rt5665->calibrate_mutex);
1384 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1385 /* Headphone Output Volume */
1386 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1387 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1388 rt5665_hp_vol_put, hp_vol_tlv),
1390 /* Mono Output Volume */
1391 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1392 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1393 rt5665_mono_vol_put, mono_vol_tlv),
1396 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1397 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1399 /* DAC Digital Volume */
1400 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1401 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1402 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1403 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1404 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1405 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1407 /* IN1/IN2/IN3/IN4 Volume */
1408 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1409 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1410 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1411 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1412 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1413 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1414 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1415 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1416 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1417 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1419 /* INL/INR Volume Control */
1420 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1421 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1423 /* ADC Digital Volume Control */
1424 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1425 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1426 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1427 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1428 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1429 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1430 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1431 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1432 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1433 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1434 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1435 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1437 /* ADC Boost Volume Control */
1438 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1439 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1442 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1443 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1446 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1447 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1452 * set_dmic_clk - Set parameter of dmic.
1455 * @kcontrol: The kcontrol of this widget.
1458 * Choose dmic clock between 1MHz and 3MHz.
1459 * It is better for clock to approximate 3MHz.
1461 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1462 struct snd_kcontrol *kcontrol, int event)
1464 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1465 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1466 int pd, idx = -EINVAL;
1468 pd = rl6231_get_pre_div(rt5665->regmap,
1469 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1470 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1473 dev_err(codec->dev, "Failed to set DMIC clock\n");
1475 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1476 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1481 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1482 struct snd_kcontrol *kcontrol, int event)
1484 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1487 case SND_SOC_DAPM_PRE_PMU:
1488 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1489 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1490 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1492 case SND_SOC_DAPM_POST_PMD:
1493 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1494 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1495 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1504 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1505 struct snd_soc_dapm_widget *sink)
1508 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1510 val = snd_soc_read(codec, RT5665_GLB_CLK);
1511 val &= RT5665_SCLK_SRC_MASK;
1512 if (val == RT5665_SCLK_SRC_PLL1)
1518 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1519 struct snd_soc_dapm_widget *sink)
1521 unsigned int reg, shift, val;
1522 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1525 case RT5665_ADC_MONO_R_ASRC_SFT:
1526 reg = RT5665_ASRC_3;
1527 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1529 case RT5665_ADC_MONO_L_ASRC_SFT:
1530 reg = RT5665_ASRC_3;
1531 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1533 case RT5665_ADC_STO1_ASRC_SFT:
1534 reg = RT5665_ASRC_3;
1535 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1537 case RT5665_ADC_STO2_ASRC_SFT:
1538 reg = RT5665_ASRC_3;
1539 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1541 case RT5665_DAC_MONO_R_ASRC_SFT:
1542 reg = RT5665_ASRC_2;
1543 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1545 case RT5665_DAC_MONO_L_ASRC_SFT:
1546 reg = RT5665_ASRC_2;
1547 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1549 case RT5665_DAC_STO1_ASRC_SFT:
1550 reg = RT5665_ASRC_2;
1551 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1553 case RT5665_DAC_STO2_ASRC_SFT:
1554 reg = RT5665_ASRC_2;
1555 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1561 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1563 case RT5665_CLK_SEL_I2S1_ASRC:
1564 case RT5665_CLK_SEL_I2S2_ASRC:
1565 case RT5665_CLK_SEL_I2S3_ASRC:
1566 /* I2S_Pre_Div1 should be 1 in asrc mode */
1567 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1568 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1577 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1578 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1579 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1580 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1581 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1584 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1585 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1586 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1587 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1588 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1591 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1592 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1593 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1594 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1595 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1598 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1599 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1600 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1601 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1602 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1605 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1606 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1607 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1608 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1609 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1612 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1613 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1614 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1615 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1616 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1619 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1620 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1621 RT5665_M_ADCMIX_L_SFT, 1, 1),
1622 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1623 RT5665_M_DAC1_L_SFT, 1, 1),
1626 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1627 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1628 RT5665_M_ADCMIX_R_SFT, 1, 1),
1629 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1630 RT5665_M_DAC1_R_SFT, 1, 1),
1633 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1634 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1635 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1636 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1637 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1639 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1644 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1645 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1646 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1647 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1648 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1650 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1652 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1655 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1656 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1657 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1658 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1659 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1664 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1665 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1666 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1667 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1668 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1670 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1673 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1674 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1675 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1676 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1677 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1679 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1684 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1685 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1686 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1687 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1688 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1689 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1690 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1692 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1695 /* Analog Input Mixer */
1696 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1697 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1698 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1700 RT5665_M_INL_RM1_L_SFT, 1, 1),
1701 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1702 RT5665_M_INR_RM1_L_SFT, 1, 1),
1703 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1704 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1705 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1706 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1707 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1708 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1709 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1710 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1713 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1714 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1715 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1717 RT5665_M_INR_RM1_R_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1719 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1720 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1721 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1722 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1723 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1725 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1728 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1729 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1730 RT5665_M_INL_RM2_L_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1732 RT5665_M_INR_RM2_L_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1734 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1736 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1737 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1738 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1740 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1741 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1742 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1745 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1746 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1747 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1749 RT5665_M_INL_RM2_R_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1751 RT5665_M_INR_RM2_R_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1753 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1754 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1755 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1756 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1757 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1758 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1759 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1762 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1763 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1764 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1766 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1767 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1768 RT5665_M_BST1_MM_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1770 RT5665_M_BST2_MM_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1772 RT5665_M_BST3_MM_SFT, 1, 1),
1775 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1776 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1777 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1779 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1780 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1781 RT5665_M_BST1_OM_L_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1783 RT5665_M_BST2_OM_L_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1785 RT5665_M_BST3_OM_L_SFT, 1, 1),
1788 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1789 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1790 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1792 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1794 RT5665_M_BST2_OM_R_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1796 RT5665_M_BST3_OM_R_SFT, 1, 1),
1797 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1798 RT5665_M_BST4_OM_R_SFT, 1, 1),
1801 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1802 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1803 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1804 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1805 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1808 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1809 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1810 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1811 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1812 RT5665_M_OV_L_LM_SFT, 1, 1),
1815 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1816 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1817 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1818 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1819 RT5665_M_OV_R_LM_SFT, 1, 1),
1823 /*MX-17 [6:4], MX-17 [2:0]*/
1824 static const char * const rt5665_dac2_src[] = {
1825 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1828 static SOC_ENUM_SINGLE_DECL(
1829 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1830 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1832 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1833 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1835 static SOC_ENUM_SINGLE_DECL(
1836 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1837 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1839 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1840 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1843 /*MX-1B [6:4], MX-1B [2:0]*/
1844 static const char * const rt5665_dac3_src[] = {
1845 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1848 static SOC_ENUM_SINGLE_DECL(
1849 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1850 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1852 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1853 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1855 static SOC_ENUM_SINGLE_DECL(
1856 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1857 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1859 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1860 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1862 /* STO1 ADC1 Source */
1863 /* MX-26 [13] [5] */
1864 static const char * const rt5665_sto1_adc1_src[] = {
1868 static SOC_ENUM_SINGLE_DECL(
1869 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1870 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1872 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1873 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1875 static SOC_ENUM_SINGLE_DECL(
1876 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1877 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1879 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1880 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1882 /* STO1 ADC Source */
1883 /* MX-26 [11:10] [3:2] */
1884 static const char * const rt5665_sto1_adc_src[] = {
1885 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1888 static SOC_ENUM_SINGLE_DECL(
1889 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1890 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1892 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1893 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1895 static SOC_ENUM_SINGLE_DECL(
1896 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1897 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1899 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1900 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1902 /* STO1 ADC2 Source */
1903 /* MX-26 [12] [4] */
1904 static const char * const rt5665_sto1_adc2_src[] = {
1908 static SOC_ENUM_SINGLE_DECL(
1909 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1910 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1912 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1913 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1915 static SOC_ENUM_SINGLE_DECL(
1916 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1917 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1919 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1920 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1922 /* STO1 DMIC Source */
1924 static const char * const rt5665_sto1_dmic_src[] = {
1928 static SOC_ENUM_SINGLE_DECL(
1929 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1930 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1932 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1933 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1936 static const char * const rt5665_sto1_dd_l_src[] = {
1937 "STO2 DAC", "MONO DAC"
1940 static SOC_ENUM_SINGLE_DECL(
1941 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1942 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1944 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1945 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1948 static const char * const rt5665_sto1_dd_r_src[] = {
1949 "STO2 DAC", "MONO DAC", "AEC REF"
1952 static SOC_ENUM_SINGLE_DECL(
1953 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1954 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1956 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1957 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1959 /* MONO ADC L2 Source */
1961 static const char * const rt5665_mono_adc_l2_src[] = {
1965 static SOC_ENUM_SINGLE_DECL(
1966 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1967 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1969 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1970 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1973 /* MONO ADC L1 Source */
1975 static const char * const rt5665_mono_adc_l1_src[] = {
1979 static SOC_ENUM_SINGLE_DECL(
1980 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1981 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1983 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1984 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1987 static const char * const rt5665_mono_dd_src[] = {
1988 "STO2 DAC", "MONO DAC"
1991 static SOC_ENUM_SINGLE_DECL(
1992 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1993 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1995 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1996 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1998 static SOC_ENUM_SINGLE_DECL(
1999 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
2000 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
2002 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
2003 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2005 /* MONO ADC L Source, MONO ADC R Source*/
2006 /* MX-27 [11:10], MX-27 [3:2] */
2007 static const char * const rt5665_mono_adc_src[] = {
2008 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2011 static SOC_ENUM_SINGLE_DECL(
2012 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2013 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2015 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2016 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2018 static SOC_ENUM_SINGLE_DECL(
2019 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2020 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2022 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2023 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2025 /* MONO DMIC L Source */
2027 static const char * const rt5665_mono_dmic_l_src[] = {
2028 "DMIC1 L", "DMIC2 L"
2031 static SOC_ENUM_SINGLE_DECL(
2032 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2033 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2035 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2036 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2038 /* MONO ADC R2 Source */
2040 static const char * const rt5665_mono_adc_r2_src[] = {
2044 static SOC_ENUM_SINGLE_DECL(
2045 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2046 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2048 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2049 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2051 /* MONO ADC R1 Source */
2053 static const char * const rt5665_mono_adc_r1_src[] = {
2057 static SOC_ENUM_SINGLE_DECL(
2058 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2059 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2061 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2062 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2064 /* MONO DMIC R Source */
2066 static const char * const rt5665_mono_dmic_r_src[] = {
2067 "DMIC1 R", "DMIC2 R"
2070 static SOC_ENUM_SINGLE_DECL(
2071 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2072 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2074 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2075 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2078 /* STO2 ADC1 Source */
2079 /* MX-28 [13] [5] */
2080 static const char * const rt5665_sto2_adc1_src[] = {
2084 static SOC_ENUM_SINGLE_DECL(
2085 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2086 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2088 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2089 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2091 static SOC_ENUM_SINGLE_DECL(
2092 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2093 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2095 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2096 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2098 /* STO2 ADC Source */
2099 /* MX-28 [11:10] [3:2] */
2100 static const char * const rt5665_sto2_adc_src[] = {
2101 "ADC1 L", "ADC1 R", "ADC2 L"
2104 static SOC_ENUM_SINGLE_DECL(
2105 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2106 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2108 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2109 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2111 static SOC_ENUM_SINGLE_DECL(
2112 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2113 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2115 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2116 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2118 /* STO2 ADC2 Source */
2119 /* MX-28 [12] [4] */
2120 static const char * const rt5665_sto2_adc2_src[] = {
2124 static SOC_ENUM_SINGLE_DECL(
2125 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2126 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2128 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2129 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2131 static SOC_ENUM_SINGLE_DECL(
2132 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2133 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2135 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2136 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2138 /* STO2 DMIC Source */
2140 static const char * const rt5665_sto2_dmic_src[] = {
2144 static SOC_ENUM_SINGLE_DECL(
2145 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2146 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2148 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2149 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2152 static const char * const rt5665_sto2_dd_l_src[] = {
2153 "STO2 DAC", "MONO DAC"
2156 static SOC_ENUM_SINGLE_DECL(
2157 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2158 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2160 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2161 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2164 static const char * const rt5665_sto2_dd_r_src[] = {
2165 "STO2 DAC", "MONO DAC"
2168 static SOC_ENUM_SINGLE_DECL(
2169 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2170 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2172 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2173 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2175 /* DAC R1 Source, DAC L1 Source*/
2176 /* MX-29 [11:10], MX-29 [9:8]*/
2177 static const char * const rt5665_dac1_src[] = {
2178 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2181 static SOC_ENUM_SINGLE_DECL(
2182 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2183 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2185 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2186 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2188 static SOC_ENUM_SINGLE_DECL(
2189 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2190 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2192 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2193 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2195 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2196 /* MX-2D [13:12], MX-2D [9:8]*/
2197 static const char * const rt5665_dig_dac_mix_src[] = {
2198 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2201 static SOC_ENUM_SINGLE_DECL(
2202 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2203 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2205 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2206 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2208 static SOC_ENUM_SINGLE_DECL(
2209 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2210 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2212 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2213 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2215 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2216 /* MX-2D [5:4], MX-2D [1:0]*/
2217 static const char * const rt5665_alg_dac1_src[] = {
2218 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2221 static SOC_ENUM_SINGLE_DECL(
2222 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2223 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2225 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2226 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2228 static SOC_ENUM_SINGLE_DECL(
2229 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2230 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2232 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2233 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2235 /* Analog DAC LR Source, Analog DAC R2 Source*/
2236 /* MX-2E [5:4], MX-2E [0]*/
2237 static const char * const rt5665_alg_dac2_src[] = {
2238 "Mono DAC Mixer", "DAC2"
2241 static SOC_ENUM_SINGLE_DECL(
2242 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2243 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2245 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2246 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2248 static SOC_ENUM_SINGLE_DECL(
2249 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2250 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2252 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2253 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2255 /* Interface2 ADC Data Input*/
2257 static const char * const rt5665_if2_1_adc_in_src[] = {
2258 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2259 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2262 static SOC_ENUM_SINGLE_DECL(
2263 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2264 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2266 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2267 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2270 static const char * const rt5665_if2_2_adc_in_src[] = {
2271 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2272 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2275 static SOC_ENUM_SINGLE_DECL(
2276 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2277 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2279 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2280 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2282 /* Interface3 ADC Data Input*/
2284 static const char * const rt5665_if3_adc_in_src[] = {
2285 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2286 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2289 static SOC_ENUM_SINGLE_DECL(
2290 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2291 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2293 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2294 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2297 /* MX-31 [11:10] [9:8] */
2298 static const char * const rt5665_pdm_src[] = {
2299 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2302 static SOC_ENUM_SINGLE_DECL(
2303 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2304 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2306 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2307 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2309 static SOC_ENUM_SINGLE_DECL(
2310 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2311 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2313 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2314 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2317 /* I2S1 TDM ADCDAT Source */
2319 static const char * const rt5665_if1_1_adc1_data_src[] = {
2320 "STO1 ADC", "IF2_1 DAC",
2323 static SOC_ENUM_SINGLE_DECL(
2324 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2325 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2327 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2328 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2331 static const char * const rt5665_if1_1_adc2_data_src[] = {
2332 "STO2 ADC", "IF2_2 DAC",
2335 static SOC_ENUM_SINGLE_DECL(
2336 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2337 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2339 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2340 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2343 static const char * const rt5665_if1_1_adc3_data_src[] = {
2344 "MONO ADC", "IF3 DAC",
2347 static SOC_ENUM_SINGLE_DECL(
2348 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2349 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2351 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2352 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2355 static const char * const rt5665_if1_2_adc1_data_src[] = {
2356 "STO1 ADC", "IF1 DAC",
2359 static SOC_ENUM_SINGLE_DECL(
2360 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2361 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2363 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2364 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2367 static const char * const rt5665_if1_2_adc2_data_src[] = {
2368 "STO2 ADC", "IF2_1 DAC",
2371 static SOC_ENUM_SINGLE_DECL(
2372 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2373 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2375 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2376 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2379 static const char * const rt5665_if1_2_adc3_data_src[] = {
2380 "MONO ADC", "IF2_2 DAC",
2383 static SOC_ENUM_SINGLE_DECL(
2384 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2385 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2387 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2388 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2391 static const char * const rt5665_if1_2_adc4_data_src[] = {
2395 static SOC_ENUM_SINGLE_DECL(
2396 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2397 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2399 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2400 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2402 /* MX-7a[4:0] MX-7b[4:0] */
2403 static const char * const rt5665_tdm_adc_data_src[] = {
2404 "1234", "1243", "1324", "1342", "1432", "1423",
2405 "2134", "2143", "2314", "2341", "2431", "2413",
2406 "3124", "3142", "3214", "3241", "3412", "3421",
2407 "4123", "4132", "4213", "4231", "4312", "4321"
2410 static SOC_ENUM_SINGLE_DECL(
2411 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2412 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2414 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2415 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2417 static SOC_ENUM_SINGLE_DECL(
2418 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2419 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2421 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2422 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2424 /* Out Volume Switch */
2425 static const struct snd_kcontrol_new monovol_switch =
2426 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2428 static const struct snd_kcontrol_new outvol_l_switch =
2429 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2431 static const struct snd_kcontrol_new outvol_r_switch =
2432 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2435 static const struct snd_kcontrol_new mono_switch =
2436 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2438 static const struct snd_kcontrol_new hpo_switch =
2439 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2440 RT5665_VOL_L_SFT, 1, 0);
2442 static const struct snd_kcontrol_new lout_l_switch =
2443 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2445 static const struct snd_kcontrol_new lout_r_switch =
2446 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2448 static const struct snd_kcontrol_new pdm_l_switch =
2449 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2450 RT5665_M_PDM1_L_SFT, 1, 1);
2452 static const struct snd_kcontrol_new pdm_r_switch =
2453 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2454 RT5665_M_PDM1_R_SFT, 1, 1);
2456 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2457 struct snd_kcontrol *kcontrol, int event)
2459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2462 case SND_SOC_DAPM_PRE_PMU:
2463 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2464 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2465 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2468 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2471 case SND_SOC_DAPM_POST_PMD:
2472 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2473 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2474 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2476 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2477 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2488 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2489 struct snd_kcontrol *kcontrol, int event)
2491 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2494 case SND_SOC_DAPM_PRE_PMU:
2495 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2496 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2497 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2500 case SND_SOC_DAPM_POST_PMD:
2501 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2502 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2503 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2514 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2515 struct snd_kcontrol *kcontrol, int event)
2517 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2520 case SND_SOC_DAPM_POST_PMU:
2521 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2522 RT5665_PUMP_EN, RT5665_PUMP_EN);
2525 case SND_SOC_DAPM_PRE_PMD:
2526 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2538 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2539 struct snd_kcontrol *kcontrol, int event)
2542 case SND_SOC_DAPM_POST_PMU:
2543 /*Add delay to avoid pop noise*/
2554 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2555 struct snd_kcontrol *kcontrol, int event)
2557 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2560 case SND_SOC_DAPM_PRE_PMU:
2562 case RT5665_PWR_VREF1_BIT:
2563 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2567 case RT5665_PWR_VREF2_BIT:
2568 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2572 case RT5665_PWR_VREF3_BIT:
2573 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2582 case SND_SOC_DAPM_POST_PMU:
2583 usleep_range(15000, 20000);
2585 case RT5665_PWR_VREF1_BIT:
2586 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2587 RT5665_PWR_FV1, RT5665_PWR_FV1);
2590 case RT5665_PWR_VREF2_BIT:
2591 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2592 RT5665_PWR_FV2, RT5665_PWR_FV2);
2595 case RT5665_PWR_VREF3_BIT:
2596 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2597 RT5665_PWR_FV3, RT5665_PWR_FV3);
2612 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2613 struct snd_kcontrol *kcontrol, int event)
2615 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2616 unsigned int val1, val2, mask1 = 0, mask2 = 0;
2619 case RT5665_PWR_I2S2_1_BIT:
2620 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2621 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2622 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2623 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2625 case RT5665_PWR_I2S2_2_BIT:
2626 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2627 RT5665_GP8_PIN_MASK;
2628 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2629 RT5665_GP8_PIN_DACDAT2_2;
2630 mask2 = RT5665_GP9_PIN_MASK;
2631 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2633 case RT5665_PWR_I2S3_BIT:
2634 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2635 RT5665_GP8_PIN_MASK;
2636 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2637 RT5665_GP8_PIN_DACDAT3;
2638 mask2 = RT5665_GP9_PIN_MASK;
2639 val2 = RT5665_GP9_PIN_ADCDAT3;
2643 case SND_SOC_DAPM_PRE_PMU:
2645 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2648 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2651 case SND_SOC_DAPM_POST_PMD:
2653 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2656 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2666 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2667 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2669 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2671 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2672 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2674 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2675 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2676 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2677 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2678 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2681 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2682 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2684 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2685 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2686 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2687 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2688 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2689 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2690 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2692 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2694 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2696 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2698 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
2699 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2700 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2701 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2702 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2703 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2704 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2706 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2708 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2709 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2710 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2713 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2715 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2717 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2721 SND_SOC_DAPM_INPUT("DMIC L1"),
2722 SND_SOC_DAPM_INPUT("DMIC R1"),
2723 SND_SOC_DAPM_INPUT("DMIC L2"),
2724 SND_SOC_DAPM_INPUT("DMIC R2"),
2726 SND_SOC_DAPM_INPUT("IN1P"),
2727 SND_SOC_DAPM_INPUT("IN1N"),
2728 SND_SOC_DAPM_INPUT("IN2P"),
2729 SND_SOC_DAPM_INPUT("IN2N"),
2730 SND_SOC_DAPM_INPUT("IN3P"),
2731 SND_SOC_DAPM_INPUT("IN3N"),
2732 SND_SOC_DAPM_INPUT("IN4P"),
2733 SND_SOC_DAPM_INPUT("IN4N"),
2735 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2736 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2738 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2739 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2740 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2741 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2742 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2743 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2746 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2748 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2750 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2752 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2754 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2756 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2757 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2759 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2761 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2762 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2763 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2764 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2765 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2766 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2767 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2768 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2769 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2770 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2771 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2772 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2773 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2777 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2779 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2783 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2784 ARRAY_SIZE(rt5665_rec1_l_mix)),
2785 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2786 ARRAY_SIZE(rt5665_rec1_r_mix)),
2787 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2788 ARRAY_SIZE(rt5665_rec2_l_mix)),
2789 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2790 ARRAY_SIZE(rt5665_rec2_r_mix)),
2791 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2792 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2793 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2794 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2795 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2796 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2797 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2798 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2801 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2802 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2803 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2804 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2806 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2807 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2808 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2809 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2810 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2811 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2812 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2813 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2814 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2815 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2816 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2817 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2820 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5665_sto1_dmic_mux),
2822 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5665_sto1_dmic_mux),
2824 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5665_sto1_adc1l_mux),
2826 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5665_sto1_adc1r_mux),
2828 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5665_sto1_adc2l_mux),
2830 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5665_sto1_adc2r_mux),
2832 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5665_sto1_adcl_mux),
2834 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5665_sto1_adcr_mux),
2836 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5665_sto1_dd_l_mux),
2838 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5665_sto1_dd_r_mux),
2840 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2841 &rt5665_mono_adc_l2_mux),
2842 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2843 &rt5665_mono_adc_r2_mux),
2844 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2845 &rt5665_mono_adc_l1_mux),
2846 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2847 &rt5665_mono_adc_r1_mux),
2848 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2849 &rt5665_mono_dmic_l_mux),
2850 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5665_mono_dmic_r_mux),
2852 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5665_mono_adc_l_mux),
2854 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5665_mono_adc_r_mux),
2856 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5665_mono_dd_l_mux),
2858 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5665_mono_dd_r_mux),
2860 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2861 &rt5665_sto2_dmic_mux),
2862 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2863 &rt5665_sto2_dmic_mux),
2864 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2865 &rt5665_sto2_adc1l_mux),
2866 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2867 &rt5665_sto2_adc1r_mux),
2868 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2869 &rt5665_sto2_adc2l_mux),
2870 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2871 &rt5665_sto2_adc2r_mux),
2872 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2873 &rt5665_sto2_adcl_mux),
2874 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2875 &rt5665_sto2_adcr_mux),
2876 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2877 &rt5665_sto2_dd_l_mux),
2878 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2879 &rt5665_sto2_dd_r_mux),
2881 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2882 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2883 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2884 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2885 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2886 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2887 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2888 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2889 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2890 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2891 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2892 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2893 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2894 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2895 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2896 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2897 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2898 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2899 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2900 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2901 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2902 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2903 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2904 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2905 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2906 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2909 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 /* Digital Interface */
2914 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2916 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2918 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2919 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2920 SND_SOC_DAPM_POST_PMD),
2921 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2922 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2923 SND_SOC_DAPM_POST_PMD),
2924 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2925 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2926 SND_SOC_DAPM_POST_PMD),
2927 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2928 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2929 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2930 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2931 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2932 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2933 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2934 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2935 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2937 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2938 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2939 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2940 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2941 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2942 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2943 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2944 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2946 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2947 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2948 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2949 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2951 /* Digital Interface Select */
2952 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_1_adc1_mux),
2954 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if1_1_adc2_mux),
2956 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_if1_1_adc3_mux),
2958 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2959 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5665_if1_2_adc1_mux),
2961 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5665_if1_2_adc2_mux),
2963 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_if1_2_adc3_mux),
2965 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_if1_2_adc4_mux),
2967 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_tdm1_adc_mux),
2969 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5665_tdm1_adc_mux),
2971 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5665_tdm1_adc_mux),
2973 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5665_tdm1_adc_mux),
2975 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5665_tdm2_adc_mux),
2977 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5665_tdm2_adc_mux),
2979 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5665_tdm2_adc_mux),
2981 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5665_tdm2_adc_mux),
2983 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5665_if2_1_adc_in_mux),
2985 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5665_if2_2_adc_in_mux),
2987 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5665_if3_adc_in_mux),
2989 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5665_if1_1_01_adc_swap_mux),
2991 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5665_if1_1_01_adc_swap_mux),
2993 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5665_if1_1_23_adc_swap_mux),
2995 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5665_if1_1_23_adc_swap_mux),
2997 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5665_if1_1_45_adc_swap_mux),
2999 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5665_if1_1_45_adc_swap_mux),
3001 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3002 &rt5665_if1_1_67_adc_swap_mux),
3003 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3004 &rt5665_if1_1_67_adc_swap_mux),
3005 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3006 &rt5665_if1_2_01_adc_swap_mux),
3007 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008 &rt5665_if1_2_01_adc_swap_mux),
3009 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3010 &rt5665_if1_2_23_adc_swap_mux),
3011 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3012 &rt5665_if1_2_23_adc_swap_mux),
3013 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3014 &rt5665_if1_2_45_adc_swap_mux),
3015 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3016 &rt5665_if1_2_45_adc_swap_mux),
3017 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3018 &rt5665_if1_2_67_adc_swap_mux),
3019 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3020 &rt5665_if1_2_67_adc_swap_mux),
3021 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3022 &rt5665_if2_1_dac_swap_mux),
3023 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3024 &rt5665_if2_1_adc_swap_mux),
3025 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3026 &rt5665_if2_2_dac_swap_mux),
3027 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3028 &rt5665_if2_2_adc_swap_mux),
3029 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3030 &rt5665_if3_dac_swap_mux),
3031 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3032 &rt5665_if3_adc_swap_mux),
3034 /* Audio Interface */
3035 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3036 0, SND_SOC_NOPM, 0, 0),
3037 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3038 1, SND_SOC_NOPM, 0, 0),
3039 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3040 2, SND_SOC_NOPM, 0, 0),
3041 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3042 3, SND_SOC_NOPM, 0, 0),
3043 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3044 4, SND_SOC_NOPM, 0, 0),
3045 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3046 5, SND_SOC_NOPM, 0, 0),
3047 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3048 6, SND_SOC_NOPM, 0, 0),
3049 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3050 7, SND_SOC_NOPM, 0, 0),
3051 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3052 0, SND_SOC_NOPM, 0, 0),
3053 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3054 1, SND_SOC_NOPM, 0, 0),
3055 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3056 2, SND_SOC_NOPM, 0, 0),
3057 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3058 3, SND_SOC_NOPM, 0, 0),
3059 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3060 4, SND_SOC_NOPM, 0, 0),
3061 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3062 5, SND_SOC_NOPM, 0, 0),
3063 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3064 6, SND_SOC_NOPM, 0, 0),
3065 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3066 7, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3068 0, SND_SOC_NOPM, 0, 0),
3069 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3070 0, SND_SOC_NOPM, 0, 0),
3071 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3072 0, SND_SOC_NOPM, 0, 0),
3073 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3074 0, SND_SOC_NOPM, 0, 0),
3075 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3076 0, SND_SOC_NOPM, 0, 0),
3077 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3078 0, SND_SOC_NOPM, 0, 0),
3079 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3080 0, SND_SOC_NOPM, 0, 0),
3083 /* DAC mixer before sound effect */
3084 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3085 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3086 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3087 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3089 /* DAC channel Mux */
3090 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3091 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3092 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3093 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3094 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3095 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3097 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3098 &rt5665_alg_dac_l1_mux),
3099 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3100 &rt5665_alg_dac_r1_mux),
3101 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3102 &rt5665_alg_dac_l2_mux),
3103 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3104 &rt5665_alg_dac_r2_mux),
3107 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3108 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3109 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3110 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3111 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3112 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3113 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3114 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3115 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3116 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3117 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3118 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3119 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3120 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3121 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3122 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3123 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3124 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3125 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3126 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3127 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3128 &rt5665_dig_dac_mixl_mux),
3129 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3130 &rt5665_dig_dac_mixr_mux),
3133 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3134 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3136 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3137 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3138 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3139 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3140 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3141 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3142 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3144 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3145 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3146 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3147 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3150 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3151 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3152 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3153 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3154 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3155 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3158 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3160 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3162 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3166 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3167 ARRAY_SIZE(rt5665_mono_mix)),
3168 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3169 ARRAY_SIZE(rt5665_lout_l_mix)),
3170 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3171 ARRAY_SIZE(rt5665_lout_r_mix)),
3172 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3173 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3174 SND_SOC_DAPM_PRE_PMU),
3175 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3176 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3177 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3178 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3179 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3180 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3182 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3183 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3184 SND_SOC_DAPM_POST_PMD),
3186 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3188 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3190 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3192 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3194 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3196 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3200 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3201 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3202 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3203 0, 1, &rt5665_pdm_l_mux),
3204 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3205 0, 1, &rt5665_pdm_r_mux),
3208 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3210 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3212 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3214 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3216 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3220 SND_SOC_DAPM_OUTPUT("HPOL"),
3221 SND_SOC_DAPM_OUTPUT("HPOR"),
3222 SND_SOC_DAPM_OUTPUT("LOUTL"),
3223 SND_SOC_DAPM_OUTPUT("LOUTR"),
3224 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3225 SND_SOC_DAPM_OUTPUT("PDML"),
3226 SND_SOC_DAPM_OUTPUT("PDMR"),
3229 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3231 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3232 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3233 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3234 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3235 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3236 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3237 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3238 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3241 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3242 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3243 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3244 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3245 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3246 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3247 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3248 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3249 {"I2S1 ASRC", NULL, "CLKDET"},
3250 {"I2S2 ASRC", NULL, "CLKDET"},
3251 {"I2S3 ASRC", NULL, "CLKDET"},
3254 {"Mic Det Power", NULL, "Vref2"},
3255 {"MICBIAS1", NULL, "Vref1"},
3256 {"MICBIAS1", NULL, "Vref2"},
3257 {"MICBIAS2", NULL, "Vref1"},
3258 {"MICBIAS2", NULL, "Vref2"},
3259 {"MICBIAS3", NULL, "Vref1"},
3260 {"MICBIAS3", NULL, "Vref2"},
3262 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3263 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3264 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3265 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3266 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3267 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3269 {"I2S1_1", NULL, "I2S1 ASRC"},
3270 {"I2S1_2", NULL, "I2S1 ASRC"},
3271 {"I2S2_1", NULL, "I2S2 ASRC"},
3272 {"I2S2_2", NULL, "I2S2 ASRC"},
3273 {"I2S3", NULL, "I2S3 ASRC"},
3275 {"CLKDET SYS", NULL, "CLKDET"},
3276 {"CLKDET HP", NULL, "CLKDET"},
3277 {"CLKDET MONO", NULL, "CLKDET"},
3278 {"CLKDET LOUT", NULL, "CLKDET"},
3280 {"IN1P", NULL, "LDO2"},
3281 {"IN2P", NULL, "LDO2"},
3282 {"IN3P", NULL, "LDO2"},
3283 {"IN4P", NULL, "LDO2"},
3285 {"DMIC1", NULL, "DMIC L1"},
3286 {"DMIC1", NULL, "DMIC R1"},
3287 {"DMIC2", NULL, "DMIC L2"},
3288 {"DMIC2", NULL, "DMIC R2"},
3290 {"BST1", NULL, "IN1P"},
3291 {"BST1", NULL, "IN1N"},
3292 {"BST1", NULL, "BST1 Power"},
3293 {"BST1", NULL, "BST1P Power"},
3294 {"BST2", NULL, "IN2P"},
3295 {"BST2", NULL, "IN2N"},
3296 {"BST2", NULL, "BST2 Power"},
3297 {"BST2", NULL, "BST2P Power"},
3298 {"BST3", NULL, "IN3P"},
3299 {"BST3", NULL, "IN3N"},
3300 {"BST3", NULL, "BST3 Power"},
3301 {"BST3", NULL, "BST3P Power"},
3302 {"BST4", NULL, "IN4P"},
3303 {"BST4", NULL, "IN4N"},
3304 {"BST4", NULL, "BST4 Power"},
3305 {"BST4", NULL, "BST4P Power"},
3306 {"BST1 CBJ", NULL, "IN1P"},
3307 {"BST1 CBJ", NULL, "IN1N"},
3308 {"BST1 CBJ", NULL, "CBJ Power"},
3309 {"CBJ Power", NULL, "Vref2"},
3311 {"INL VOL", NULL, "IN3P"},
3312 {"INR VOL", NULL, "IN3N"},
3314 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3315 {"RECMIX1L", "INL Switch", "INL VOL"},
3316 {"RECMIX1L", "INR Switch", "INR VOL"},
3317 {"RECMIX1L", "BST4 Switch", "BST4"},
3318 {"RECMIX1L", "BST3 Switch", "BST3"},
3319 {"RECMIX1L", "BST2 Switch", "BST2"},
3320 {"RECMIX1L", "BST1 Switch", "BST1"},
3321 {"RECMIX1L", NULL, "RECMIX1L Power"},
3323 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3324 {"RECMIX1R", "INR Switch", "INR VOL"},
3325 {"RECMIX1R", "BST4 Switch", "BST4"},
3326 {"RECMIX1R", "BST3 Switch", "BST3"},
3327 {"RECMIX1R", "BST2 Switch", "BST2"},
3328 {"RECMIX1R", "BST1 Switch", "BST1"},
3329 {"RECMIX1R", NULL, "RECMIX1R Power"},
3331 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3332 {"RECMIX2L", "INL Switch", "INL VOL"},
3333 {"RECMIX2L", "INR Switch", "INR VOL"},
3334 {"RECMIX2L", "BST4 Switch", "BST4"},
3335 {"RECMIX2L", "BST3 Switch", "BST3"},
3336 {"RECMIX2L", "BST2 Switch", "BST2"},
3337 {"RECMIX2L", "BST1 Switch", "BST1"},
3338 {"RECMIX2L", NULL, "RECMIX2L Power"},
3340 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3341 {"RECMIX2R", "INL Switch", "INL VOL"},
3342 {"RECMIX2R", "INR Switch", "INR VOL"},
3343 {"RECMIX2R", "BST4 Switch", "BST4"},
3344 {"RECMIX2R", "BST3 Switch", "BST3"},
3345 {"RECMIX2R", "BST2 Switch", "BST2"},
3346 {"RECMIX2R", "BST1 Switch", "BST1"},
3347 {"RECMIX2R", NULL, "RECMIX2R Power"},
3349 {"ADC1 L", NULL, "RECMIX1L"},
3350 {"ADC1 L", NULL, "ADC1 L Power"},
3351 {"ADC1 L", NULL, "ADC1 clock"},
3352 {"ADC1 R", NULL, "RECMIX1R"},
3353 {"ADC1 R", NULL, "ADC1 R Power"},
3354 {"ADC1 R", NULL, "ADC1 clock"},
3356 {"ADC2 L", NULL, "RECMIX2L"},
3357 {"ADC2 L", NULL, "ADC2 L Power"},
3358 {"ADC2 L", NULL, "ADC2 clock"},
3359 {"ADC2 R", NULL, "RECMIX2R"},
3360 {"ADC2 R", NULL, "ADC2 R Power"},
3361 {"ADC2 R", NULL, "ADC2 clock"},
3363 {"DMIC L1", NULL, "DMIC CLK"},
3364 {"DMIC L1", NULL, "DMIC1 Power"},
3365 {"DMIC R1", NULL, "DMIC CLK"},
3366 {"DMIC R1", NULL, "DMIC1 Power"},
3367 {"DMIC L2", NULL, "DMIC CLK"},
3368 {"DMIC L2", NULL, "DMIC2 Power"},
3369 {"DMIC R2", NULL, "DMIC CLK"},
3370 {"DMIC R2", NULL, "DMIC2 Power"},
3372 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3373 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3375 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3376 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3378 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3379 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3381 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3382 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3384 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3385 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3387 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3388 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3390 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3391 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3392 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3393 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3394 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3395 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3396 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3397 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3399 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3400 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3402 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3403 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3405 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3406 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3407 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3408 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3410 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3411 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3412 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3413 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3415 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3416 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3417 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3418 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3420 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3421 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3422 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3423 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3425 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3426 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3428 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3429 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3431 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3432 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3433 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3434 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3436 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3437 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3438 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3439 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3441 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3442 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3443 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3444 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3445 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3446 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3448 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3449 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3451 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3452 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3454 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3455 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3456 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3457 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3459 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3460 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3461 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3462 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3464 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3465 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3466 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3468 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3469 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3470 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3472 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3473 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3474 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3476 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3477 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3478 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3480 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3481 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3482 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3484 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3485 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3486 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3488 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3489 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3490 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3491 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3492 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3493 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3495 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3496 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3497 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3498 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3499 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3500 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3501 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3503 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3504 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3505 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3506 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3507 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3508 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3509 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3510 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3512 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3513 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3514 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3515 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3517 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3518 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3519 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3520 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3521 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3522 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3523 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3524 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3525 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3526 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3527 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3528 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3529 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3530 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3531 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3532 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3533 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3534 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3535 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3536 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3538 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3540 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3543 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3544 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3545 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3546 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3547 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3548 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3549 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3550 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3551 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3552 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3553 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3555 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3556 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3557 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3558 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3559 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3560 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3561 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3564 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3565 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3566 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3567 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3568 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3569 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3570 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3571 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3572 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3573 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3574 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3575 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3576 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3577 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3578 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3579 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3580 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3581 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3583 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3584 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3585 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3587 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3588 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3590 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3591 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3592 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3593 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3594 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3595 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3596 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3597 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3598 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3599 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3600 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3601 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3602 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3603 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3604 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3605 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3606 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3607 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3608 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3609 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3610 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3611 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3612 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3613 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3614 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3617 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3618 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3619 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3620 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3622 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3623 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3624 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3625 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3626 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3627 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3628 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3629 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3630 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3631 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3632 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3633 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3634 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3635 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3636 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3638 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3639 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3640 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3641 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3643 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3645 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3648 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3649 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3650 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3651 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3652 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3653 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3654 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3655 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3656 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3657 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3658 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3660 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3661 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3662 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3663 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3664 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3665 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3666 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3669 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3670 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3671 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3672 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3673 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3674 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3675 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3676 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3677 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3678 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3679 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3680 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3681 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3682 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3683 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3684 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3685 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3686 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3688 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3689 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3690 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3692 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3693 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3695 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3696 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3697 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3699 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3700 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3701 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3702 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3703 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3704 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3705 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3706 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3707 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3708 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3709 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3710 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3711 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3712 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3713 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3714 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3715 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3716 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3717 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3718 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3719 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3721 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3722 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3723 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3724 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3725 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3726 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3727 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3728 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3729 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3730 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3731 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3732 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3733 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3734 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3735 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3736 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3737 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3738 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3739 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3740 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3741 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3742 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3743 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3744 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3745 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3746 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3747 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3748 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3749 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3750 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3751 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3752 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3754 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3755 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3756 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3757 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3758 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3759 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3760 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3761 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3762 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3763 {"IF2_1 ADC", NULL, "I2S2_1"},
3765 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3766 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3767 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3768 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3769 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3770 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3771 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3772 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3773 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3774 {"IF2_2 ADC", NULL, "I2S2_2"},
3776 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3777 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3778 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3779 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3780 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3781 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3782 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3783 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3784 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3785 {"IF3 ADC", NULL, "I2S3"},
3787 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3788 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3789 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3790 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3791 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3792 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3793 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3794 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3795 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3796 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3797 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3798 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3799 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3800 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3801 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3802 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3803 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3804 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3805 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3806 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3807 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3808 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3809 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3810 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3811 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3812 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3813 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3814 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3815 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3816 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3817 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3819 {"IF1 DAC1", NULL, "AIF1RX"},
3820 {"IF1 DAC2", NULL, "AIF1RX"},
3821 {"IF1 DAC3", NULL, "AIF1RX"},
3822 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3823 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3824 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3825 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3826 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3827 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3828 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3829 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3830 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3831 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3832 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3833 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3834 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3835 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3836 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3838 {"IF1 DAC1", NULL, "I2S1_1"},
3839 {"IF1 DAC2", NULL, "I2S1_1"},
3840 {"IF1 DAC3", NULL, "I2S1_1"},
3841 {"IF2_1 DAC", NULL, "I2S2_1"},
3842 {"IF2_2 DAC", NULL, "I2S2_2"},
3843 {"IF3 DAC", NULL, "I2S3"},
3845 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3846 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3847 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3848 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3849 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3850 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3851 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3852 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3853 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3854 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3855 {"IF3 DAC L", NULL, "IF3 DAC"},
3856 {"IF3 DAC R", NULL, "IF3 DAC"},
3858 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3859 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3860 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3861 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3862 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3864 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3865 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3866 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3867 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3868 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3870 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3871 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3872 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3873 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3875 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3876 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3878 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3879 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3880 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3881 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3882 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3883 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3885 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3886 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3887 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3888 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3889 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3890 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3892 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3893 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3894 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3895 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3896 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3897 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3899 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3900 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3901 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3902 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3903 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3904 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3906 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3907 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3908 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3909 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3911 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3912 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3913 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3914 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3916 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3917 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3918 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3920 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3921 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3922 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3924 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3925 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3926 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3927 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3928 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3929 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3930 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3931 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3933 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3934 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3935 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3936 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3937 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3938 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3940 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3941 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3942 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3943 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3944 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3945 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3947 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3948 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3949 {"DAC L2 Source", NULL, "DAC L2 Power"},
3950 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3951 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3952 {"DAC R2 Source", NULL, "DAC R2 Power"},
3954 {"DAC L1", NULL, "DAC L1 Source"},
3955 {"DAC R1", NULL, "DAC R1 Source"},
3956 {"DAC L2", NULL, "DAC L2 Source"},
3957 {"DAC R2", NULL, "DAC R2 Source"},
3959 {"DAC L1", NULL, "DAC 1 Clock"},
3960 {"DAC R1", NULL, "DAC 1 Clock"},
3961 {"DAC L2", NULL, "DAC 2 Clock"},
3962 {"DAC R2", NULL, "DAC 2 Clock"},
3964 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3965 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3966 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3967 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3968 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3970 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3971 {"OUT MIXL", "INL Switch", "INL VOL"},
3972 {"OUT MIXL", "BST1 Switch", "BST1"},
3973 {"OUT MIXL", "BST2 Switch", "BST2"},
3974 {"OUT MIXL", "BST3 Switch", "BST3"},
3975 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3976 {"OUT MIXR", "INR Switch", "INR VOL"},
3977 {"OUT MIXR", "BST2 Switch", "BST2"},
3978 {"OUT MIXR", "BST3 Switch", "BST3"},
3979 {"OUT MIXR", "BST4 Switch", "BST4"},
3981 {"MONOVOL", "Switch", "MONOVOL MIX"},
3982 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3983 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3984 {"Mono Amp", NULL, "Mono MIX"},
3985 {"Mono Amp", NULL, "Vref2"},
3986 {"Mono Amp", NULL, "Vref3"},
3987 {"Mono Amp", NULL, "CLKDET SYS"},
3988 {"Mono Amp", NULL, "CLKDET MONO"},
3989 {"Mono Playback", "Switch", "Mono Amp"},
3990 {"MONOOUT", NULL, "Mono Playback"},
3992 {"HP Amp", NULL, "DAC L1"},
3993 {"HP Amp", NULL, "DAC R1"},
3994 {"HP Amp", NULL, "Charge Pump"},
3995 {"HP Amp", NULL, "CLKDET SYS"},
3996 {"HP Amp", NULL, "CLKDET HP"},
3997 {"HP Amp", NULL, "CBJ Power"},
3998 {"HP Amp", NULL, "Vref2"},
3999 {"HPO Playback", "Switch", "HP Amp"},
4000 {"HPOL", NULL, "HPO Playback"},
4001 {"HPOR", NULL, "HPO Playback"},
4003 {"OUTVOL L", "Switch", "OUT MIXL"},
4004 {"OUTVOL R", "Switch", "OUT MIXR"},
4005 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
4006 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
4007 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
4008 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
4009 {"LOUT Amp", NULL, "LOUT L MIX"},
4010 {"LOUT Amp", NULL, "LOUT R MIX"},
4011 {"LOUT Amp", NULL, "Vref1"},
4012 {"LOUT Amp", NULL, "Vref2"},
4013 {"LOUT Amp", NULL, "CLKDET SYS"},
4014 {"LOUT Amp", NULL, "CLKDET LOUT"},
4015 {"LOUT L Playback", "Switch", "LOUT Amp"},
4016 {"LOUT R Playback", "Switch", "LOUT Amp"},
4017 {"LOUTL", NULL, "LOUT L Playback"},
4018 {"LOUTR", NULL, "LOUT R Playback"},
4020 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4021 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4022 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4023 {"PDM L Mux", NULL, "PDM Power"},
4024 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4025 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4026 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4027 {"PDM R Mux", NULL, "PDM Power"},
4028 {"PDM L Playback", "Switch", "PDM L Mux"},
4029 {"PDM R Playback", "Switch", "PDM R Mux"},
4030 {"PDML", NULL, "PDM L Playback"},
4031 {"PDMR", NULL, "PDM R Playback"},
4034 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4035 unsigned int rx_mask, int slots, int slot_width)
4037 struct snd_soc_codec *codec = dai->codec;
4038 unsigned int val = 0;
4040 if (rx_mask || tx_mask)
4041 val |= RT5665_I2S1_MODE_TDM;
4045 val |= RT5665_TDM_IN_CH_4;
4046 val |= RT5665_TDM_OUT_CH_4;
4049 val |= RT5665_TDM_IN_CH_6;
4050 val |= RT5665_TDM_OUT_CH_6;
4053 val |= RT5665_TDM_IN_CH_8;
4054 val |= RT5665_TDM_OUT_CH_8;
4062 switch (slot_width) {
4064 val |= RT5665_TDM_IN_LEN_20;
4065 val |= RT5665_TDM_OUT_LEN_20;
4068 val |= RT5665_TDM_IN_LEN_24;
4069 val |= RT5665_TDM_OUT_LEN_24;
4072 val |= RT5665_TDM_IN_LEN_32;
4073 val |= RT5665_TDM_OUT_LEN_32;
4081 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4082 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4083 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4084 RT5665_TDM_OUT_LEN_MASK, val);
4090 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4091 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4093 struct snd_soc_codec *codec = dai->codec;
4094 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4095 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4096 int pre_div, frame_size;
4098 rt5665->lrck[dai->id] = params_rate(params);
4099 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4101 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4102 rt5665->lrck[dai->id], dai->id);
4105 frame_size = snd_soc_params_to_frame_size(params);
4106 if (frame_size < 0) {
4107 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4111 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4112 rt5665->lrck[dai->id], pre_div, dai->id);
4114 switch (params_width(params)) {
4119 val_len |= RT5665_I2S_DL_20;
4123 val_len |= RT5665_I2S_DL_24;
4127 val_len |= RT5665_I2S_DL_8;
4136 if (params_channels(params) > 2)
4137 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4138 params_channels(params), params_width(params));
4139 reg_clk = RT5665_ADDA_CLK_1;
4140 mask_clk = RT5665_I2S_PD1_MASK;
4141 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4142 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4143 RT5665_I2S_DL_MASK, val_len);
4147 reg_clk = RT5665_ADDA_CLK_2;
4148 mask_clk = RT5665_I2S_PD2_MASK;
4149 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4150 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4151 RT5665_I2S_DL_MASK, val_len);
4154 reg_clk = RT5665_ADDA_CLK_2;
4155 mask_clk = RT5665_I2S_PD3_MASK;
4156 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4157 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4158 RT5665_I2S_DL_MASK, val_len);
4161 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4165 snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
4166 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4168 switch (rt5665->lrck[dai->id]) {
4170 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4171 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4172 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4175 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4176 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4177 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4180 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4181 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4182 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4189 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4191 struct snd_soc_codec *codec = dai->codec;
4192 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4193 unsigned int reg_val = 0;
4195 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4196 case SND_SOC_DAIFMT_CBM_CFM:
4197 rt5665->master[dai->id] = 1;
4199 case SND_SOC_DAIFMT_CBS_CFS:
4200 reg_val |= RT5665_I2S_MS_S;
4201 rt5665->master[dai->id] = 0;
4207 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4208 case SND_SOC_DAIFMT_NB_NF:
4210 case SND_SOC_DAIFMT_IB_NF:
4211 reg_val |= RT5665_I2S_BP_INV;
4217 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4218 case SND_SOC_DAIFMT_I2S:
4220 case SND_SOC_DAIFMT_LEFT_J:
4221 reg_val |= RT5665_I2S_DF_LEFT;
4223 case SND_SOC_DAIFMT_DSP_A:
4224 reg_val |= RT5665_I2S_DF_PCM_A;
4226 case SND_SOC_DAIFMT_DSP_B:
4227 reg_val |= RT5665_I2S_DF_PCM_B;
4236 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4237 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4238 RT5665_I2S_DF_MASK, reg_val);
4242 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4243 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4244 RT5665_I2S_DF_MASK, reg_val);
4247 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4248 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4249 RT5665_I2S_DF_MASK, reg_val);
4252 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4258 static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4259 int source, unsigned int freq, int dir)
4261 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4262 unsigned int reg_val = 0;
4264 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4268 case RT5665_SCLK_S_MCLK:
4269 reg_val |= RT5665_SCLK_SRC_MCLK;
4271 case RT5665_SCLK_S_PLL1:
4272 reg_val |= RT5665_SCLK_SRC_PLL1;
4274 case RT5665_SCLK_S_RCCLK:
4275 reg_val |= RT5665_SCLK_SRC_RCCLK;
4278 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4281 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4282 RT5665_SCLK_SRC_MASK, reg_val);
4283 rt5665->sysclk = freq;
4284 rt5665->sysclk_src = clk_id;
4286 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4291 static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4292 int source, unsigned int freq_in,
4293 unsigned int freq_out)
4295 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4296 struct rl6231_pll_code pll_code;
4299 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4300 freq_out == rt5665->pll_out)
4303 if (!freq_in || !freq_out) {
4304 dev_dbg(codec->dev, "PLL disabled\n");
4307 rt5665->pll_out = 0;
4308 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4309 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4314 case RT5665_PLL1_S_MCLK:
4315 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4316 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4318 case RT5665_PLL1_S_BCLK1:
4319 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4320 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4322 case RT5665_PLL1_S_BCLK2:
4323 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4324 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4326 case RT5665_PLL1_S_BCLK3:
4327 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4328 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4331 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
4335 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4337 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4341 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4342 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4343 pll_code.n_code, pll_code.k_code);
4345 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4346 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4347 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4348 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4349 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4351 rt5665->pll_in = freq_in;
4352 rt5665->pll_out = freq_out;
4353 rt5665->pll_src = source;
4358 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4360 struct snd_soc_codec *codec = dai->codec;
4361 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4363 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4365 rt5665->bclk[dai->id] = ratio;
4371 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4372 RT5665_I2S_BCLK_MS2_MASK,
4373 RT5665_I2S_BCLK_MS2_64);
4376 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4377 RT5665_I2S_BCLK_MS3_MASK,
4378 RT5665_I2S_BCLK_MS3_64);
4386 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4387 enum snd_soc_bias_level level)
4389 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4392 case SND_SOC_BIAS_PREPARE:
4393 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4394 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4397 case SND_SOC_BIAS_STANDBY:
4398 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4399 RT5665_PWR_LDO, RT5665_PWR_LDO);
4400 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4401 RT5665_PWR_MB, RT5665_PWR_MB);
4402 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4403 RT5665_DIG_GATE_CTRL, 0);
4405 case SND_SOC_BIAS_OFF:
4406 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4408 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4419 static int rt5665_probe(struct snd_soc_codec *codec)
4421 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4423 rt5665->codec = codec;
4425 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4430 static int rt5665_remove(struct snd_soc_codec *codec)
4432 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4434 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4440 static int rt5665_suspend(struct snd_soc_codec *codec)
4442 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4444 regcache_cache_only(rt5665->regmap, true);
4445 regcache_mark_dirty(rt5665->regmap);
4449 static int rt5665_resume(struct snd_soc_codec *codec)
4451 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4453 regcache_cache_only(rt5665->regmap, false);
4454 regcache_sync(rt5665->regmap);
4459 #define rt5665_suspend NULL
4460 #define rt5665_resume NULL
4463 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4464 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4465 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4467 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4468 .hw_params = rt5665_hw_params,
4469 .set_fmt = rt5665_set_dai_fmt,
4470 .set_tdm_slot = rt5665_set_tdm_slot,
4471 .set_bclk_ratio = rt5665_set_bclk_ratio,
4474 static struct snd_soc_dai_driver rt5665_dai[] = {
4476 .name = "rt5665-aif1_1",
4477 .id = RT5665_AIF1_1,
4479 .stream_name = "AIF1 Playback",
4482 .rates = RT5665_STEREO_RATES,
4483 .formats = RT5665_FORMATS,
4486 .stream_name = "AIF1_1 Capture",
4489 .rates = RT5665_STEREO_RATES,
4490 .formats = RT5665_FORMATS,
4492 .ops = &rt5665_aif_dai_ops,
4495 .name = "rt5665-aif1_2",
4496 .id = RT5665_AIF1_2,
4498 .stream_name = "AIF1_2 Capture",
4501 .rates = RT5665_STEREO_RATES,
4502 .formats = RT5665_FORMATS,
4504 .ops = &rt5665_aif_dai_ops,
4507 .name = "rt5665-aif2_1",
4508 .id = RT5665_AIF2_1,
4510 .stream_name = "AIF2_1 Playback",
4513 .rates = RT5665_STEREO_RATES,
4514 .formats = RT5665_FORMATS,
4517 .stream_name = "AIF2_1 Capture",
4520 .rates = RT5665_STEREO_RATES,
4521 .formats = RT5665_FORMATS,
4523 .ops = &rt5665_aif_dai_ops,
4526 .name = "rt5665-aif2_2",
4527 .id = RT5665_AIF2_2,
4529 .stream_name = "AIF2_2 Playback",
4532 .rates = RT5665_STEREO_RATES,
4533 .formats = RT5665_FORMATS,
4536 .stream_name = "AIF2_2 Capture",
4539 .rates = RT5665_STEREO_RATES,
4540 .formats = RT5665_FORMATS,
4542 .ops = &rt5665_aif_dai_ops,
4545 .name = "rt5665-aif3",
4548 .stream_name = "AIF3 Playback",
4551 .rates = RT5665_STEREO_RATES,
4552 .formats = RT5665_FORMATS,
4555 .stream_name = "AIF3 Capture",
4558 .rates = RT5665_STEREO_RATES,
4559 .formats = RT5665_FORMATS,
4561 .ops = &rt5665_aif_dai_ops,
4565 static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4566 .probe = rt5665_probe,
4567 .remove = rt5665_remove,
4568 .suspend = rt5665_suspend,
4569 .resume = rt5665_resume,
4570 .set_bias_level = rt5665_set_bias_level,
4571 .idle_bias_off = true,
4572 .component_driver = {
4573 .controls = rt5665_snd_controls,
4574 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4575 .dapm_widgets = rt5665_dapm_widgets,
4576 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4577 .dapm_routes = rt5665_dapm_routes,
4578 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4580 .set_sysclk = rt5665_set_codec_sysclk,
4581 .set_pll = rt5665_set_codec_pll,
4582 .set_jack = rt5665_set_jack_detect,
4586 static const struct regmap_config rt5665_regmap = {
4589 .max_register = 0x0400,
4590 .volatile_reg = rt5665_volatile_register,
4591 .readable_reg = rt5665_readable_register,
4592 .cache_type = REGCACHE_RBTREE,
4593 .reg_defaults = rt5665_reg,
4594 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4595 .use_single_rw = true,
4598 static const struct i2c_device_id rt5665_i2c_id[] = {
4602 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4604 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4606 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4607 "realtek,in1-differential");
4608 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4609 "realtek,in2-differential");
4610 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4611 "realtek,in3-differential");
4612 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4613 "realtek,in4-differential");
4615 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4616 &rt5665->pdata.dmic1_data_pin);
4617 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4618 &rt5665->pdata.dmic2_data_pin);
4619 of_property_read_u32(dev->of_node, "realtek,jd-src",
4620 &rt5665->pdata.jd_src);
4622 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4623 "realtek,ldo1-en-gpios", 0);
4628 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4632 mutex_lock(&rt5665->calibrate_mutex);
4634 regcache_cache_bypass(rt5665->regmap, true);
4636 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4637 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4638 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4639 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4640 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4641 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4642 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4643 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4644 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4645 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4646 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4647 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4648 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4649 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4650 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4651 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4652 usleep_range(15000, 20000);
4653 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4654 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4656 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4659 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4661 usleep_range(10000, 10005);
4666 pr_err("HP Calibration Failure\n");
4667 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4668 regcache_cache_bypass(rt5665->regmap, false);
4675 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4678 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4680 usleep_range(10000, 10005);
4685 pr_err("MONO Calibration Failure\n");
4686 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4687 regcache_cache_bypass(rt5665->regmap, false);
4694 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4695 regcache_cache_bypass(rt5665->regmap, false);
4697 regcache_mark_dirty(rt5665->regmap);
4698 regcache_sync(rt5665->regmap);
4700 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4701 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4704 rt5665->calibration_done = true;
4705 mutex_unlock(&rt5665->calibrate_mutex);
4708 static void rt5665_calibrate_handler(struct work_struct *work)
4710 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4711 calibrate_work.work);
4713 while (!rt5665->codec->component.card->instantiated) {
4714 pr_debug("%s\n", __func__);
4715 usleep_range(10000, 15000);
4718 rt5665_calibrate(rt5665);
4721 static int rt5665_i2c_probe(struct i2c_client *i2c,
4722 const struct i2c_device_id *id)
4724 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4725 struct rt5665_priv *rt5665;
4729 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4735 i2c_set_clientdata(i2c, rt5665);
4738 rt5665->pdata = *pdata;
4740 rt5665_parse_dt(rt5665, &i2c->dev);
4742 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4743 rt5665->supplies[i].supply = rt5665_supply_names[i];
4745 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4748 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4752 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4755 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4759 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4760 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4761 GPIOF_OUT_INIT_HIGH, "rt5665"))
4762 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4765 /* Sleep for 300 ms miniumum */
4766 usleep_range(300000, 350000);
4768 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4769 if (IS_ERR(rt5665->regmap)) {
4770 ret = PTR_ERR(rt5665->regmap);
4771 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4776 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4777 if (val != DEVICE_ID) {
4779 "Device with ID register %x is not rt5665\n", val);
4783 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4786 rt5665->id = CODEC_5666;
4789 rt5665->id = CODEC_5668;
4793 rt5665->id = CODEC_5665;
4797 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4799 /* line in diff mode*/
4800 if (rt5665->pdata.in1_diff)
4801 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4802 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4803 if (rt5665->pdata.in2_diff)
4804 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4805 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4806 if (rt5665->pdata.in3_diff)
4807 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4808 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4809 if (rt5665->pdata.in4_diff)
4810 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4811 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4814 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4815 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4816 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4817 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4818 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4819 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4820 switch (rt5665->pdata.dmic1_data_pin) {
4821 case RT5665_DMIC1_DATA_IN2N:
4822 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4823 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4826 case RT5665_DMIC1_DATA_GPIO4:
4827 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4828 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4829 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4830 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4834 dev_dbg(&i2c->dev, "no DMIC1\n");
4838 switch (rt5665->pdata.dmic2_data_pin) {
4839 case RT5665_DMIC2_DATA_IN2P:
4840 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4841 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4844 case RT5665_DMIC2_DATA_GPIO5:
4845 regmap_update_bits(rt5665->regmap,
4847 RT5665_DMIC_2_DP_MASK,
4848 RT5665_DMIC_2_DP_GPIO5);
4849 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4850 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4854 dev_dbg(&i2c->dev, "no DMIC2\n");
4860 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4861 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4862 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4863 /* Work around for pow_pump */
4864 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4865 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4867 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4868 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4870 /* Set GPIO4,8 as input for combo jack */
4871 if (rt5665->id == CODEC_5666) {
4872 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4873 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4874 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4875 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4878 /* Enhance performance*/
4879 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4880 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4881 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4883 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4884 rt5665_jack_detect_handler);
4885 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4886 rt5665_calibrate_handler);
4887 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4888 rt5665_jd_check_handler);
4890 mutex_init(&rt5665->calibrate_mutex);
4893 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4894 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4895 | IRQF_ONESHOT, "rt5665", rt5665);
4897 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4901 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4902 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4905 static int rt5665_i2c_remove(struct i2c_client *i2c)
4907 snd_soc_unregister_codec(&i2c->dev);
4912 static void rt5665_i2c_shutdown(struct i2c_client *client)
4914 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4916 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4920 static const struct of_device_id rt5665_of_match[] = {
4921 {.compatible = "realtek,rt5665"},
4922 {.compatible = "realtek,rt5666"},
4923 {.compatible = "realtek,rt5668"},
4926 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4930 static struct acpi_device_id rt5665_acpi_match[] = {
4936 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4939 static struct i2c_driver rt5665_i2c_driver = {
4942 .of_match_table = of_match_ptr(rt5665_of_match),
4943 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4945 .probe = rt5665_i2c_probe,
4946 .remove = rt5665_i2c_remove,
4947 .shutdown = rt5665_i2c_shutdown,
4948 .id_table = rt5665_i2c_id,
4950 module_i2c_driver(rt5665_i2c_driver);
4952 MODULE_DESCRIPTION("ASoC RT5665 driver");
4953 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4954 MODULE_LICENSE("GPL v2");
git.samba.org / sfrench / cifs-2.6.git / blob