sound/soc/codecs/rt5514.c

   1 /*
   2  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2015 Realtek Semiconductor Corp.
   5  * Author: Oder Chiou <oder_chiou@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/fs.h>
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/regmap.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/firmware.h>
  22 #include <linux/gpio.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5514.h"
  33 #if defined(CONFIG_SND_SOC_RT5514_SPI)
  34 #include "rt5514-spi.h"
  35 #endif
  36
  37 static const struct reg_sequence rt5514_i2c_patch[] = {
  38         {0x1800101c, 0x00000000},
  39         {0x18001100, 0x0000031f},
  40         {0x18001104, 0x00000007},
  41         {0x18001108, 0x00000000},
  42         {0x1800110c, 0x00000000},
  43         {0x18001110, 0x00000000},
  44         {0x18001114, 0x00000001},
  45         {0x18001118, 0x00000000},
  46         {0x18002f08, 0x00000006},
  47         {0x18002f00, 0x00055149},
  48         {0x18002f00, 0x0005514b},
  49         {0x18002f00, 0x00055149},
  50         {0xfafafafa, 0x00000001},
  51         {0x18002f10, 0x00000001},
  52         {0x18002f10, 0x00000000},
  53         {0x18002f10, 0x00000001},
  54         {0xfafafafa, 0x00000001},
  55         {0x18002000, 0x000010ec},
  56         {0xfafafafa, 0x00000000},
  57 };
  58
  59 static const struct reg_sequence rt5514_patch[] = {
  60         {RT5514_DIG_IO_CTRL,            0x00000040},
  61         {RT5514_CLK_CTRL1,              0x38020041},
  62         {RT5514_SRC_CTRL,               0x44000eee},
  63         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  64         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
  65 };
  66
  67 static const struct reg_default rt5514_reg[] = {
  68         {RT5514_RESET,                  0x00000000},
  69         {RT5514_PWR_ANA1,               0x00808880},
  70         {RT5514_PWR_ANA2,               0x00220000},
  71         {RT5514_I2S_CTRL1,              0x00000330},
  72         {RT5514_I2S_CTRL2,              0x20000000},
  73         {RT5514_VAD_CTRL6,              0xc00007d2},
  74         {RT5514_EXT_VAD_CTRL,           0x80000080},
  75         {RT5514_DIG_IO_CTRL,            0x00000040},
  76         {RT5514_PAD_CTRL1,              0x00804000},
  77         {RT5514_DMIC_DATA_CTRL,         0x00000005},
  78         {RT5514_DIG_SOURCE_CTRL,        0x00000002},
  79         {RT5514_SRC_CTRL,               0x44000eee},
  80         {RT5514_DOWNFILTER2_CTRL1,      0x0000882f},
  81         {RT5514_PLL_SOURCE_CTRL,        0x00000004},
  82         {RT5514_CLK_CTRL1,              0x38020041},
  83         {RT5514_CLK_CTRL2,              0x00000000},
  84         {RT5514_PLL3_CALIB_CTRL1,       0x00400200},
  85         {RT5514_PLL3_CALIB_CTRL5,       0x40220012},
  86         {RT5514_DELAY_BUF_CTRL1,        0x7fff006a},
  87         {RT5514_DELAY_BUF_CTRL3,        0x00000000},
  88         {RT5514_DOWNFILTER0_CTRL1,      0x00020c2f},
  89         {RT5514_DOWNFILTER0_CTRL2,      0x00020c2f},
  90         {RT5514_DOWNFILTER0_CTRL3,      0x00000362},
  91         {RT5514_DOWNFILTER1_CTRL1,      0x00020c2f},
  92         {RT5514_DOWNFILTER1_CTRL2,      0x00020c2f},
  93         {RT5514_DOWNFILTER1_CTRL3,      0x00000362},
  94         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  95         {RT5514_ANA_CTRL_LDO18_16,      0x02000345},
  96         {RT5514_ANA_CTRL_ADC12,         0x0000a2a8},
  97         {RT5514_ANA_CTRL_ADC21,         0x00001180},
  98         {RT5514_ANA_CTRL_ADC22,         0x0000aaa8},
  99         {RT5514_ANA_CTRL_ADC23,         0x00151427},
 100         {RT5514_ANA_CTRL_MICBST,        0x00002000},
 101         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
 102         {RT5514_ANA_CTRL_INBUF,         0x00000143},
 103         {RT5514_ANA_CTRL_VREF,          0x00008d50},
 104         {RT5514_ANA_CTRL_PLL3,          0x0000000e},
 105         {RT5514_ANA_CTRL_PLL1_1,        0x00000000},
 106         {RT5514_ANA_CTRL_PLL1_2,        0x00030220},
 107         {RT5514_DMIC_LP_CTRL,           0x00000000},
 108         {RT5514_MISC_CTRL_DSP,          0x00000000},
 109         {RT5514_DSP_CTRL1,              0x00055149},
 110         {RT5514_DSP_CTRL3,              0x00000006},
 111         {RT5514_DSP_CTRL4,              0x00000001},
 112         {RT5514_VENDOR_ID1,             0x00000001},
 113         {RT5514_VENDOR_ID2,             0x10ec5514},
 114 };
 115
 116 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
 117 {
 118         /* Reset */
 119         regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
 120         /* LDO_I_limit */
 121         regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
 122         /* I2C bypass enable */
 123         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
 124         /* mini-core reset */
 125         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
 126         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
 127         /* I2C bypass disable */
 128         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
 129         /* PIN config */
 130         regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
 131         /* PLL3(QN)=RCOSC*(10+2) */
 132         regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
 133         /* PLL3 source=RCOSC, fsi=rt_clk */
 134         regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
 135         /* Power on RCOSC, pll3 */
 136         regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
 137         /* DSP clk source = pll3, ENABLE DSP clk */
 138         regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
 139         /* Enable DSP clk auto switch */
 140         regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
 141         /* Reduce DSP power */
 142         regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
 143 }
 144
 145 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
 146 {
 147         switch (reg) {
 148         case RT5514_VENDOR_ID1:
 149         case RT5514_VENDOR_ID2:
 150                 return true;
 151
 152         default:
 153                 return false;
 154         }
 155 }
 156
 157 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
 158 {
 159         switch (reg) {
 160         case RT5514_RESET:
 161         case RT5514_PWR_ANA1:
 162         case RT5514_PWR_ANA2:
 163         case RT5514_I2S_CTRL1:
 164         case RT5514_I2S_CTRL2:
 165         case RT5514_VAD_CTRL6:
 166         case RT5514_EXT_VAD_CTRL:
 167         case RT5514_DIG_IO_CTRL:
 168         case RT5514_PAD_CTRL1:
 169         case RT5514_DMIC_DATA_CTRL:
 170         case RT5514_DIG_SOURCE_CTRL:
 171         case RT5514_SRC_CTRL:
 172         case RT5514_DOWNFILTER2_CTRL1:
 173         case RT5514_PLL_SOURCE_CTRL:
 174         case RT5514_CLK_CTRL1:
 175         case RT5514_CLK_CTRL2:
 176         case RT5514_PLL3_CALIB_CTRL1:
 177         case RT5514_PLL3_CALIB_CTRL5:
 178         case RT5514_DELAY_BUF_CTRL1:
 179         case RT5514_DELAY_BUF_CTRL3:
 180         case RT5514_DOWNFILTER0_CTRL1:
 181         case RT5514_DOWNFILTER0_CTRL2:
 182         case RT5514_DOWNFILTER0_CTRL3:
 183         case RT5514_DOWNFILTER1_CTRL1:
 184         case RT5514_DOWNFILTER1_CTRL2:
 185         case RT5514_DOWNFILTER1_CTRL3:
 186         case RT5514_ANA_CTRL_LDO10:
 187         case RT5514_ANA_CTRL_LDO18_16:
 188         case RT5514_ANA_CTRL_ADC12:
 189         case RT5514_ANA_CTRL_ADC21:
 190         case RT5514_ANA_CTRL_ADC22:
 191         case RT5514_ANA_CTRL_ADC23:
 192         case RT5514_ANA_CTRL_MICBST:
 193         case RT5514_ANA_CTRL_ADCFED:
 194         case RT5514_ANA_CTRL_INBUF:
 195         case RT5514_ANA_CTRL_VREF:
 196         case RT5514_ANA_CTRL_PLL3:
 197         case RT5514_ANA_CTRL_PLL1_1:
 198         case RT5514_ANA_CTRL_PLL1_2:
 199         case RT5514_DMIC_LP_CTRL:
 200         case RT5514_MISC_CTRL_DSP:
 201         case RT5514_DSP_CTRL1:
 202         case RT5514_DSP_CTRL3:
 203         case RT5514_DSP_CTRL4:
 204         case RT5514_VENDOR_ID1:
 205         case RT5514_VENDOR_ID2:
 206                 return true;
 207
 208         default:
 209                 return false;
 210         }
 211 }
 212
 213 static bool rt5514_i2c_readable_register(struct device *dev,
 214         unsigned int reg)
 215 {
 216         switch (reg) {
 217         case RT5514_DSP_MAPPING | RT5514_RESET:
 218         case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
 219         case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
 220         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
 221         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
 222         case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
 223         case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
 224         case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
 225         case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
 226         case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
 227         case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
 228         case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
 229         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
 230         case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
 231         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
 232         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
 233         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
 234         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
 235         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
 236         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
 237         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
 238         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
 239         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
 240         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
 241         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
 242         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
 243         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
 244         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
 245         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
 246         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
 247         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
 248         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
 249         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
 250         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
 251         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
 252         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
 253         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
 254         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
 255         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
 256         case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
 257         case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
 258         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
 259         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
 260         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
 261         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
 262         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
 263                 return true;
 264
 265         default:
 266                 return false;
 267         }
 268 }
 269
 270 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
 271 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 272         0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
 273         3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
 274         4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
 275         5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
 276         6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
 277         7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
 278         8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
 279 );
 280
 281 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 282
 283 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
 284                 struct snd_ctl_elem_value *ucontrol)
 285 {
 286         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 287         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 288
 289         ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
 290
 291         return 0;
 292 }
 293
 294 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
 295                 struct snd_ctl_elem_value *ucontrol)
 296 {
 297         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 298         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 299         struct snd_soc_codec *codec = rt5514->codec;
 300         const struct firmware *fw = NULL;
 301
 302         if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
 303                 return 0;
 304
 305         if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 306                 rt5514->dsp_enabled = ucontrol->value.integer.value[0];
 307
 308                 if (rt5514->dsp_enabled) {
 309                         rt5514_enable_dsp_prepare(rt5514);
 310
 311                         request_firmware(&fw, RT5514_FIRMWARE1, codec->dev);
 312                         if (fw) {
 313 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 314                                 rt5514_spi_burst_write(0x4ff60000, fw->data,
 315                                         ((fw->size/8)+1)*8);
 316 #else
 317                                 dev_err(codec->dev, "There is no SPI driver for"
 318                                         " loading the firmware\n");
 319 #endif
 320                                 release_firmware(fw);
 321                                 fw = NULL;
 322                         }
 323
 324                         request_firmware(&fw, RT5514_FIRMWARE2, codec->dev);
 325                         if (fw) {
 326 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 327                                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
 328                                         ((fw->size/8)+1)*8);
 329 #else
 330                                 dev_err(codec->dev, "There is no SPI driver for"
 331                                         " loading the firmware\n");
 332 #endif
 333                                 release_firmware(fw);
 334                                 fw = NULL;
 335                         }
 336
 337                         /* DSP run */
 338                         regmap_write(rt5514->i2c_regmap, 0x18002f00,
 339                                 0x00055148);
 340                 } else {
 341                         regmap_multi_reg_write(rt5514->i2c_regmap,
 342                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 343                         regcache_mark_dirty(rt5514->regmap);
 344                         regcache_sync(rt5514->regmap);
 345                 }
 346         }
 347
 348         return 0;
 349 }
 350
 351 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
 352         SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
 353                 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
 354         SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
 355                 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 356                 adc_vol_tlv),
 357         SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
 358                 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 359                 adc_vol_tlv),
 360         SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
 361                 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
 362 };
 363
 364 /* ADC Mixer*/
 365 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
 366         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
 367                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 368         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
 369                 RT5514_AD_AD_MIX_BIT, 1, 1),
 370 };
 371
 372 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
 373         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
 374                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 375         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
 376                 RT5514_AD_AD_MIX_BIT, 1, 1),
 377 };
 378
 379 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
 380         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
 381                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 382         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
 383                 RT5514_AD_AD_MIX_BIT, 1, 1),
 384 };
 385
 386 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
 387         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
 388                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 389         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
 390                 RT5514_AD_AD_MIX_BIT, 1, 1),
 391 };
 392
 393 /* DMIC Source */
 394 static const char * const rt5514_dmic_src[] = {
 395         "DMIC1", "DMIC2"
 396 };
 397
 398 static const SOC_ENUM_SINGLE_DECL(
 399         rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 400         RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 401
 402 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
 403         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
 404
 405 static const SOC_ENUM_SINGLE_DECL(
 406         rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 407         RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 408
 409 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
 410         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
 411
 412 /**
 413  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
 414  *
 415  * @rate: base clock rate.
 416  *
 417  * Choose divider parameter that gives the highest possible DMIC frequency in
 418  * 1MHz - 3MHz range.
 419  */
 420 static int rt5514_calc_dmic_clk(struct snd_soc_codec *codec, int rate)
 421 {
 422         int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
 423         int i;
 424
 425         if (rate < 1000000 * div[0]) {
 426                 pr_warn("Base clock rate %d is too low\n", rate);
 427                 return -EINVAL;
 428         }
 429
 430         for (i = 0; i < ARRAY_SIZE(div); i++) {
 431                 /* find divider that gives DMIC frequency below 3.072MHz */
 432                 if (3072000 * div[i] >= rate)
 433                         return i;
 434         }
 435
 436         dev_warn(codec->dev, "Base clock rate %d is too high\n", rate);
 437         return -EINVAL;
 438 }
 439
 440 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
 441         struct snd_kcontrol *kcontrol, int event)
 442 {
 443         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 444         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 445         int idx;
 446
 447         idx = rt5514_calc_dmic_clk(codec, rt5514->sysclk);
 448         if (idx < 0)
 449                 dev_err(codec->dev, "Failed to set DMIC clock\n");
 450         else
 451                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 452                         RT5514_CLK_DMIC_OUT_SEL_MASK,
 453                         idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
 454
 455         return idx;
 456 }
 457
 458 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 459                          struct snd_soc_dapm_widget *sink)
 460 {
 461         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 462         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 463
 464         if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
 465                 return 1;
 466         else
 467                 return 0;
 468 }
 469
 470 static int rt5514_pre_event(struct snd_soc_dapm_widget *w,
 471         struct snd_kcontrol *kcontrol, int event)
 472 {
 473         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 474         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 475
 476         switch (event) {
 477         case SND_SOC_DAPM_PRE_PMU:
 478                 /**
 479                  * If the DSP is enabled in start of recording, the DSP
 480                  * should be disabled, and sync back to normal recording
 481                  * settings to make sure recording properly.
 482                 */
 483                 if (rt5514->dsp_enabled) {
 484                         rt5514->dsp_enabled = 0;
 485                         regmap_multi_reg_write(rt5514->i2c_regmap,
 486                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 487                         regcache_mark_dirty(rt5514->regmap);
 488                         regcache_sync(rt5514->regmap);
 489                 }
 490                 break;
 491
 492         default:
 493                 return 0;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
 500         /* Input Lines */
 501         SND_SOC_DAPM_INPUT("DMIC1L"),
 502         SND_SOC_DAPM_INPUT("DMIC1R"),
 503         SND_SOC_DAPM_INPUT("DMIC2L"),
 504         SND_SOC_DAPM_INPUT("DMIC2R"),
 505
 506         SND_SOC_DAPM_INPUT("AMICL"),
 507         SND_SOC_DAPM_INPUT("AMICR"),
 508
 509         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 510         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 511
 512         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
 513                 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 514
 515         SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
 516                 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
 517
 518         SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
 519                 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
 520         SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
 521                 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
 522         SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
 523                 NULL, 0),
 524         SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
 525                 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
 526         SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
 527                 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
 528         SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
 529                 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
 530         SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
 531                 NULL, 0),
 532         SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
 533                 NULL, 0),
 534         SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
 535                 NULL, 0),
 536         SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 537
 538
 539         SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
 540                 NULL, 0),
 541         SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
 542                 NULL, 0),
 543         SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
 544                 NULL, 0),
 545         SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
 546                 NULL, 0),
 547         SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
 548                 0, NULL, 0),
 549         SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 550
 551         SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
 552                 NULL, 0),
 553         SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
 554                 NULL, 0),
 555         SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
 556                 NULL, 0),
 557         SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
 558                 NULL, 0),
 559         SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
 560                 0, NULL, 0),
 561         SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 562
 563         SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
 564                 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
 565         SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
 566                 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
 567         SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
 568                 NULL, 0),
 569
 570         /* ADC Mux */
 571         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 572                                 &rt5514_sto1_dmic_mux),
 573         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 574                                 &rt5514_sto2_dmic_mux),
 575
 576         /* ADC Mixer */
 577         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
 578                 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
 579         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
 580                 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
 581
 582         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 583                 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
 584         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 585                 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
 586         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 587                 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
 588         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 589                 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
 590
 591         SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
 592                 RT5514_AD_AD_MUTE_BIT, 1),
 593         SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
 594                 RT5514_AD_AD_MUTE_BIT, 1),
 595         SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
 596                 RT5514_AD_AD_MUTE_BIT, 1),
 597         SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
 598                 RT5514_AD_AD_MUTE_BIT, 1),
 599
 600         /* ADC PGA */
 601         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 602         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 603
 604         /* Audio Interface */
 605         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 606
 607         SND_SOC_DAPM_PRE("DAPM Pre", rt5514_pre_event),
 608 };
 609
 610 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
 611         { "DMIC1", NULL, "DMIC1L" },
 612         { "DMIC1", NULL, "DMIC1R" },
 613         { "DMIC2", NULL, "DMIC2L" },
 614         { "DMIC2", NULL, "DMIC2R" },
 615
 616         { "DMIC1L", NULL, "DMIC CLK" },
 617         { "DMIC1R", NULL, "DMIC CLK" },
 618         { "DMIC2L", NULL, "DMIC CLK" },
 619         { "DMIC2R", NULL, "DMIC CLK" },
 620
 621         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 622         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 623
 624         { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
 625         { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
 626         { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
 627         { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
 628
 629         { "ADC Power", NULL, "LDO18 IN" },
 630         { "ADC Power", NULL, "LDO18 ADC" },
 631         { "ADC Power", NULL, "LDO21" },
 632         { "ADC Power", NULL, "BG LDO18 IN" },
 633         { "ADC Power", NULL, "BG LDO21" },
 634         { "ADC Power", NULL, "BG MBIAS" },
 635         { "ADC Power", NULL, "MBIAS" },
 636         { "ADC Power", NULL, "VREF2" },
 637         { "ADC Power", NULL, "VREF1" },
 638
 639         { "ADCL Power", NULL, "LDO16L" },
 640         { "ADCL Power", NULL, "ADC1L" },
 641         { "ADCL Power", NULL, "BSTL2" },
 642         { "ADCL Power", NULL, "BSTL" },
 643         { "ADCL Power", NULL, "ADCFEDL" },
 644
 645         { "ADCR Power", NULL, "LDO16R" },
 646         { "ADCR Power", NULL, "ADC1R" },
 647         { "ADCR Power", NULL, "BSTR2" },
 648         { "ADCR Power", NULL, "BSTR" },
 649         { "ADCR Power", NULL, "ADCFEDR" },
 650
 651         { "AMICL", NULL, "ADC CLK" },
 652         { "AMICL", NULL, "ADC Power" },
 653         { "AMICL", NULL, "ADCL Power" },
 654         { "AMICR", NULL, "ADC CLK" },
 655         { "AMICR", NULL, "ADC Power" },
 656         { "AMICR", NULL, "ADCR Power" },
 657
 658         { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
 659         { "PLL1", NULL, "PLL1 LDO" },
 660
 661         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 662         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 663
 664         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 665         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 666         { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
 667         { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 668
 669         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 670         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 671
 672         { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
 673         { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
 674         { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
 675         { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
 676
 677         { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
 678         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 679
 680         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 681         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 682         { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
 683         { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 684
 685         { "AIF1TX", NULL, "Stereo1 ADC MIX"},
 686         { "AIF1TX", NULL, "Stereo2 ADC MIX"},
 687 };
 688
 689 static int rt5514_hw_params(struct snd_pcm_substream *substream,
 690         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 691 {
 692         struct snd_soc_codec *codec = dai->codec;
 693         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 694         int pre_div, bclk_ms, frame_size;
 695         unsigned int val_len = 0;
 696
 697         rt5514->lrck = params_rate(params);
 698         pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
 699         if (pre_div < 0) {
 700                 dev_err(codec->dev, "Unsupported clock setting\n");
 701                 return -EINVAL;
 702         }
 703
 704         frame_size = snd_soc_params_to_frame_size(params);
 705         if (frame_size < 0) {
 706                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
 707                 return -EINVAL;
 708         }
 709
 710         bclk_ms = frame_size > 32;
 711         rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
 712
 713         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 714                 rt5514->bclk, rt5514->lrck);
 715         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 716                                 bclk_ms, pre_div, dai->id);
 717
 718         switch (params_format(params)) {
 719         case SNDRV_PCM_FORMAT_S16_LE:
 720                 break;
 721         case SNDRV_PCM_FORMAT_S20_3LE:
 722                 val_len = RT5514_I2S_DL_20;
 723                 break;
 724         case SNDRV_PCM_FORMAT_S24_LE:
 725                 val_len = RT5514_I2S_DL_24;
 726                 break;
 727         case SNDRV_PCM_FORMAT_S8:
 728                 val_len = RT5514_I2S_DL_8;
 729                 break;
 730         default:
 731                 return -EINVAL;
 732         }
 733
 734         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
 735                 val_len);
 736         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 737                 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
 738                 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
 739                 pre_div << RT5514_SEL_ADC_OSR_SFT);
 740
 741         return 0;
 742 }
 743
 744 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 745 {
 746         struct snd_soc_codec *codec = dai->codec;
 747         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 748         unsigned int reg_val = 0;
 749
 750         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 751         case SND_SOC_DAIFMT_NB_NF:
 752                 break;
 753
 754         case SND_SOC_DAIFMT_NB_IF:
 755                 reg_val |= RT5514_I2S_LR_INV;
 756                 break;
 757
 758         case SND_SOC_DAIFMT_IB_NF:
 759                 reg_val |= RT5514_I2S_BP_INV;
 760                 break;
 761
 762         case SND_SOC_DAIFMT_IB_IF:
 763                 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
 764                 break;
 765
 766         default:
 767                 return -EINVAL;
 768         }
 769
 770         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 771         case SND_SOC_DAIFMT_I2S:
 772                 break;
 773
 774         case SND_SOC_DAIFMT_LEFT_J:
 775                 reg_val |= RT5514_I2S_DF_LEFT;
 776                 break;
 777
 778         case SND_SOC_DAIFMT_DSP_A:
 779                 reg_val |= RT5514_I2S_DF_PCM_A;
 780                 break;
 781
 782         case SND_SOC_DAIFMT_DSP_B:
 783                 reg_val |= RT5514_I2S_DF_PCM_B;
 784                 break;
 785
 786         default:
 787                 return -EINVAL;
 788         }
 789
 790         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
 791                 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
 792                 reg_val);
 793
 794         return 0;
 795 }
 796
 797 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
 798                 int clk_id, unsigned int freq, int dir)
 799 {
 800         struct snd_soc_codec *codec = dai->codec;
 801         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 802         unsigned int reg_val = 0;
 803
 804         if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
 805                 return 0;
 806
 807         switch (clk_id) {
 808         case RT5514_SCLK_S_MCLK:
 809                 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
 810                 break;
 811
 812         case RT5514_SCLK_S_PLL1:
 813                 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
 814                 break;
 815
 816         default:
 817                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 818                 return -EINVAL;
 819         }
 820
 821         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 822                 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
 823
 824         rt5514->sysclk = freq;
 825         rt5514->sysclk_src = clk_id;
 826
 827         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 828
 829         return 0;
 830 }
 831
 832 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 833                         unsigned int freq_in, unsigned int freq_out)
 834 {
 835         struct snd_soc_codec *codec = dai->codec;
 836         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 837         struct rl6231_pll_code pll_code;
 838         int ret;
 839
 840         if (!freq_in || !freq_out) {
 841                 dev_dbg(codec->dev, "PLL disabled\n");
 842
 843                 rt5514->pll_in = 0;
 844                 rt5514->pll_out = 0;
 845                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 846                         RT5514_CLK_SYS_PRE_SEL_MASK,
 847                         RT5514_CLK_SYS_PRE_SEL_MCLK);
 848
 849                 return 0;
 850         }
 851
 852         if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
 853             freq_out == rt5514->pll_out)
 854                 return 0;
 855
 856         switch (source) {
 857         case RT5514_PLL1_S_MCLK:
 858                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 859                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
 860                 break;
 861
 862         case RT5514_PLL1_S_BCLK:
 863                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 864                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
 865                 break;
 866
 867         default:
 868                 dev_err(codec->dev, "Unknown PLL source %d\n", source);
 869                 return -EINVAL;
 870         }
 871
 872         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 873         if (ret < 0) {
 874                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
 875                 return ret;
 876         }
 877
 878         dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
 879                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 880                 pll_code.n_code, pll_code.k_code);
 881
 882         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
 883                 pll_code.k_code << RT5514_PLL_K_SFT |
 884                 pll_code.n_code << RT5514_PLL_N_SFT |
 885                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
 886         regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
 887                 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
 888
 889         rt5514->pll_in = freq_in;
 890         rt5514->pll_out = freq_out;
 891         rt5514->pll_src = source;
 892
 893         return 0;
 894 }
 895
 896 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 897                         unsigned int rx_mask, int slots, int slot_width)
 898 {
 899         struct snd_soc_codec *codec = dai->codec;
 900         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 901         unsigned int val = 0;
 902
 903         if (rx_mask || tx_mask)
 904                 val |= RT5514_TDM_MODE;
 905
 906         if (slots == 4)
 907                 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
 908
 909
 910         switch (slot_width) {
 911         case 20:
 912                 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
 913                 break;
 914
 915         case 24:
 916                 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
 917                 break;
 918
 919         case 32:
 920                 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
 921                 break;
 922
 923         case 16:
 924         default:
 925                 break;
 926         }
 927
 928         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
 929                 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
 930                 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK, val);
 931
 932         return 0;
 933 }
 934
 935 static int rt5514_set_bias_level(struct snd_soc_codec *codec,
 936                         enum snd_soc_bias_level level)
 937 {
 938         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 939         int ret;
 940
 941         switch (level) {
 942         case SND_SOC_BIAS_PREPARE:
 943                 if (IS_ERR(rt5514->mclk))
 944                         break;
 945
 946                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
 947                         clk_disable_unprepare(rt5514->mclk);
 948                 } else {
 949                         ret = clk_prepare_enable(rt5514->mclk);
 950                         if (ret)
 951                                 return ret;
 952                 }
 953                 break;
 954
 955         default:
 956                 break;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int rt5514_probe(struct snd_soc_codec *codec)
 963 {
 964         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 965
 966         rt5514->mclk = devm_clk_get(codec->dev, "mclk");
 967         if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
 968                 return -EPROBE_DEFER;
 969
 970         rt5514->codec = codec;
 971
 972         return 0;
 973 }
 974
 975 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
 976 {
 977         struct i2c_client *client = context;
 978         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
 979
 980         regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
 981
 982         return 0;
 983 }
 984
 985 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
 986 {
 987         struct i2c_client *client = context;
 988         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
 989
 990         regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
 991
 992         return 0;
 993 }
 994
 995 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
 996 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 997                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
 998
 999 struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1000         .hw_params = rt5514_hw_params,
1001         .set_fmt = rt5514_set_dai_fmt,
1002         .set_sysclk = rt5514_set_dai_sysclk,
1003         .set_pll = rt5514_set_dai_pll,
1004         .set_tdm_slot = rt5514_set_tdm_slot,
1005 };
1006
1007 struct snd_soc_dai_driver rt5514_dai[] = {
1008         {
1009                 .name = "rt5514-aif1",
1010                 .id = 0,
1011                 .capture = {
1012                         .stream_name = "AIF1 Capture",
1013                         .channels_min = 1,
1014                         .channels_max = 4,
1015                         .rates = RT5514_STEREO_RATES,
1016                         .formats = RT5514_FORMATS,
1017                 },
1018                 .ops = &rt5514_aif_dai_ops,
1019         }
1020 };
1021
1022 static struct snd_soc_codec_driver soc_codec_dev_rt5514 = {
1023         .probe = rt5514_probe,
1024         .idle_bias_off = true,
1025         .set_bias_level = rt5514_set_bias_level,
1026         .component_driver = {
1027                 .controls               = rt5514_snd_controls,
1028                 .num_controls           = ARRAY_SIZE(rt5514_snd_controls),
1029                 .dapm_widgets           = rt5514_dapm_widgets,
1030                 .num_dapm_widgets       = ARRAY_SIZE(rt5514_dapm_widgets),
1031                 .dapm_routes            = rt5514_dapm_routes,
1032                 .num_dapm_routes        = ARRAY_SIZE(rt5514_dapm_routes),
1033         },
1034 };
1035
1036 static const struct regmap_config rt5514_i2c_regmap = {
1037         .name = "i2c",
1038         .reg_bits = 32,
1039         .val_bits = 32,
1040
1041         .readable_reg = rt5514_i2c_readable_register,
1042
1043         .cache_type = REGCACHE_NONE,
1044 };
1045
1046 static const struct regmap_config rt5514_regmap = {
1047         .reg_bits = 16,
1048         .val_bits = 32,
1049
1050         .max_register = RT5514_VENDOR_ID2,
1051         .volatile_reg = rt5514_volatile_register,
1052         .readable_reg = rt5514_readable_register,
1053         .reg_read = rt5514_i2c_read,
1054         .reg_write = rt5514_i2c_write,
1055
1056         .cache_type = REGCACHE_RBTREE,
1057         .reg_defaults = rt5514_reg,
1058         .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1059         .use_single_rw = true,
1060 };
1061
1062 static const struct i2c_device_id rt5514_i2c_id[] = {
1063         { "rt5514", 0 },
1064         { }
1065 };
1066 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1067
1068 #if defined(CONFIG_OF)
1069 static const struct of_device_id rt5514_of_match[] = {
1070         { .compatible = "realtek,rt5514", },
1071         {},
1072 };
1073 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1074 #endif
1075
1076 static int rt5514_i2c_probe(struct i2c_client *i2c,
1077                     const struct i2c_device_id *id)
1078 {
1079         struct rt5514_priv *rt5514;
1080         int ret;
1081         unsigned int val;
1082
1083         rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1084                                 GFP_KERNEL);
1085         if (rt5514 == NULL)
1086                 return -ENOMEM;
1087
1088         i2c_set_clientdata(i2c, rt5514);
1089
1090         rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1091         if (IS_ERR(rt5514->i2c_regmap)) {
1092                 ret = PTR_ERR(rt5514->i2c_regmap);
1093                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1094                         ret);
1095                 return ret;
1096         }
1097
1098         rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1099         if (IS_ERR(rt5514->regmap)) {
1100                 ret = PTR_ERR(rt5514->regmap);
1101                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1102                         ret);
1103                 return ret;
1104         }
1105
1106         regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1107         if (val != RT5514_DEVICE_ID) {
1108                 dev_err(&i2c->dev,
1109                         "Device with ID register %x is not rt5514\n", val);
1110                 return -ENODEV;
1111         }
1112
1113         ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1114                                     ARRAY_SIZE(rt5514_i2c_patch));
1115         if (ret != 0)
1116                 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1117                         ret);
1118
1119         ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1120                                     ARRAY_SIZE(rt5514_patch));
1121         if (ret != 0)
1122                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1123
1124         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5514,
1125                         rt5514_dai, ARRAY_SIZE(rt5514_dai));
1126 }
1127
1128 static int rt5514_i2c_remove(struct i2c_client *i2c)
1129 {
1130         snd_soc_unregister_codec(&i2c->dev);
1131
1132         return 0;
1133 }
1134
1135 struct i2c_driver rt5514_i2c_driver = {
1136         .driver = {
1137                 .name = "rt5514",
1138                 .of_match_table = of_match_ptr(rt5514_of_match),
1139         },
1140         .probe = rt5514_i2c_probe,
1141         .remove   = rt5514_i2c_remove,
1142         .id_table = rt5514_i2c_id,
1143 };
1144 module_i2c_driver(rt5514_i2c_driver);
1145
1146 MODULE_DESCRIPTION("ASoC RT5514 driver");
1147 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1148 MODULE_LICENSE("GPL v2");