treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[sfrench/cifs-2.6.git] / sound / soc / codecs / cs42l51.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * cs42l51.h
4  *
5  * ASoC Driver for Cirrus Logic CS42L51 codecs
6  *
7  * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
8  */
9 #ifndef _CS42L51_H
10 #define _CS42L51_H
11
12 struct device;
13
14 extern const struct regmap_config cs42l51_regmap;
15 int cs42l51_probe(struct device *dev, struct regmap *regmap);
16 int cs42l51_remove(struct device *dev);
17 int __maybe_unused cs42l51_suspend(struct device *dev);
18 int __maybe_unused cs42l51_resume(struct device *dev);
19 extern const struct of_device_id cs42l51_of_match[];
20
21 #define CS42L51_CHIP_ID                 0x1B
22 #define CS42L51_CHIP_REV_A              0x00
23 #define CS42L51_CHIP_REV_B              0x01
24 #define CS42L51_CHIP_REV_MASK           0x07
25
26 #define CS42L51_CHIP_REV_ID             0x01
27 #define CS42L51_MK_CHIP_REV(a, b)       ((a)<<3|(b))
28
29 #define CS42L51_POWER_CTL1              0x02
30 #define CS42L51_POWER_CTL1_PDN_DACB     (1<<6)
31 #define CS42L51_POWER_CTL1_PDN_DACA     (1<<5)
32 #define CS42L51_POWER_CTL1_PDN_PGAB     (1<<4)
33 #define CS42L51_POWER_CTL1_PDN_PGAA     (1<<3)
34 #define CS42L51_POWER_CTL1_PDN_ADCB     (1<<2)
35 #define CS42L51_POWER_CTL1_PDN_ADCA     (1<<1)
36 #define CS42L51_POWER_CTL1_PDN          (1<<0)
37
38 #define CS42L51_MIC_POWER_CTL           0x03
39 #define CS42L51_MIC_POWER_CTL_AUTO      (1<<7)
40 #define CS42L51_MIC_POWER_CTL_SPEED(x)  (((x)&3)<<5)
41 #define CS42L51_QSM_MODE                3
42 #define CS42L51_HSM_MODE                2
43 #define CS42L51_SSM_MODE                1
44 #define CS42L51_DSM_MODE                0
45 #define CS42L51_MIC_POWER_CTL_3ST_SP    (1<<4)
46 #define CS42L51_MIC_POWER_CTL_PDN_MICB  (1<<3)
47 #define CS42L51_MIC_POWER_CTL_PDN_MICA  (1<<2)
48 #define CS42L51_MIC_POWER_CTL_PDN_BIAS  (1<<1)
49 #define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0)
50
51 #define CS42L51_INTF_CTL                0x04
52 #define CS42L51_INTF_CTL_LOOPBACK       (1<<7)
53 #define CS42L51_INTF_CTL_MASTER         (1<<6)
54 #define CS42L51_INTF_CTL_DAC_FORMAT(x)  (((x)&7)<<3)
55 #define CS42L51_DAC_DIF_LJ24            0x00
56 #define CS42L51_DAC_DIF_I2S             0x01
57 #define CS42L51_DAC_DIF_RJ24            0x02
58 #define CS42L51_DAC_DIF_RJ20            0x03
59 #define CS42L51_DAC_DIF_RJ18            0x04
60 #define CS42L51_DAC_DIF_RJ16            0x05
61 #define CS42L51_INTF_CTL_ADC_I2S        (1<<2)
62 #define CS42L51_INTF_CTL_DIGMIX         (1<<1)
63 #define CS42L51_INTF_CTL_MICMIX         (1<<0)
64
65 #define CS42L51_MIC_CTL                 0x05
66 #define CS42L51_MIC_CTL_ADC_SNGVOL      (1<<7)
67 #define CS42L51_MIC_CTL_ADCD_DBOOST     (1<<6)
68 #define CS42L51_MIC_CTL_ADCA_DBOOST     (1<<5)
69 #define CS42L51_MIC_CTL_MICBIAS_SEL     (1<<4)
70 #define CS42L51_MIC_CTL_MICBIAS_LVL(x)  (((x)&3)<<2)
71 #define CS42L51_MIC_CTL_MICB_BOOST      (1<<1)
72 #define CS42L51_MIC_CTL_MICA_BOOST      (1<<0)
73
74 #define CS42L51_ADC_CTL                 0x06
75 #define CS42L51_ADC_CTL_ADCB_HPFEN      (1<<7)
76 #define CS42L51_ADC_CTL_ADCB_HPFRZ      (1<<6)
77 #define CS42L51_ADC_CTL_ADCA_HPFEN      (1<<5)
78 #define CS42L51_ADC_CTL_ADCA_HPFRZ      (1<<4)
79 #define CS42L51_ADC_CTL_SOFTB           (1<<3)
80 #define CS42L51_ADC_CTL_ZCROSSB         (1<<2)
81 #define CS42L51_ADC_CTL_SOFTA           (1<<1)
82 #define CS42L51_ADC_CTL_ZCROSSA         (1<<0)
83
84 #define CS42L51_ADC_INPUT               0x07
85 #define CS42L51_ADC_INPUT_AINB_MUX(x)   (((x)&3)<<6)
86 #define CS42L51_ADC_INPUT_AINA_MUX(x)   (((x)&3)<<4)
87 #define CS42L51_ADC_INPUT_INV_ADCB      (1<<3)
88 #define CS42L51_ADC_INPUT_INV_ADCA      (1<<2)
89 #define CS42L51_ADC_INPUT_ADCB_MUTE     (1<<1)
90 #define CS42L51_ADC_INPUT_ADCA_MUTE     (1<<0)
91
92 #define CS42L51_DAC_OUT_CTL             0x08
93 #define CS42L51_DAC_OUT_CTL_HP_GAIN(x)  (((x)&7)<<5)
94 #define CS42L51_DAC_OUT_CTL_DAC_SNGVOL  (1<<4)
95 #define CS42L51_DAC_OUT_CTL_INV_PCMB    (1<<3)
96 #define CS42L51_DAC_OUT_CTL_INV_PCMA    (1<<2)
97 #define CS42L51_DAC_OUT_CTL_DACB_MUTE   (1<<1)
98 #define CS42L51_DAC_OUT_CTL_DACA_MUTE   (1<<0)
99
100 #define CS42L51_DAC_CTL                 0x09
101 #define CS42L51_DAC_CTL_DATA_SEL(x)     (((x)&3)<<6)
102 #define CS42L51_DAC_CTL_FREEZE          (1<<5)
103 #define CS42L51_DAC_CTL_DEEMPH          (1<<3)
104 #define CS42L51_DAC_CTL_AMUTE           (1<<2)
105 #define CS42L51_DAC_CTL_DACSZ(x)        (((x)&3)<<0)
106
107 #define CS42L51_ALC_PGA_CTL             0x0A
108 #define CS42L51_ALC_PGB_CTL             0x0B
109 #define CS42L51_ALC_PGX_ALCX_SRDIS      (1<<7)
110 #define CS42L51_ALC_PGX_ALCX_ZCDIS      (1<<6)
111 #define CS42L51_ALC_PGX_PGX_VOL(x)      (((x)&0x1f)<<0)
112
113 #define CS42L51_ADCA_ATT                0x0C
114 #define CS42L51_ADCB_ATT                0x0D
115
116 #define CS42L51_ADCA_VOL                0x0E
117 #define CS42L51_ADCB_VOL                0x0F
118 #define CS42L51_PCMA_VOL                0x10
119 #define CS42L51_PCMB_VOL                0x11
120 #define CS42L51_MIX_MUTE_ADCMIX         (1<<7)
121 #define CS42L51_MIX_VOLUME(x)           (((x)&0x7f)<<0)
122
123 #define CS42L51_BEEP_FREQ               0x12
124 #define CS42L51_BEEP_VOL                0x13
125 #define CS42L51_BEEP_CONF               0x14
126
127 #define CS42L51_TONE_CTL                0x15
128 #define CS42L51_TONE_CTL_TREB(x)        (((x)&0xf)<<4)
129 #define CS42L51_TONE_CTL_BASS(x)        (((x)&0xf)<<0)
130
131 #define CS42L51_AOUTA_VOL               0x16
132 #define CS42L51_AOUTB_VOL               0x17
133 #define CS42L51_PCM_MIXER               0x18
134 #define CS42L51_LIMIT_THRES_DIS         0x19
135 #define CS42L51_LIMIT_REL               0x1A
136 #define CS42L51_LIMIT_ATT               0x1B
137 #define CS42L51_ALC_EN                  0x1C
138 #define CS42L51_ALC_REL                 0x1D
139 #define CS42L51_ALC_THRES               0x1E
140 #define CS42L51_NOISE_CONF              0x1F
141
142 #define CS42L51_STATUS                  0x20
143 #define CS42L51_STATUS_SP_CLKERR        (1<<6)
144 #define CS42L51_STATUS_SPEA_OVFL        (1<<5)
145 #define CS42L51_STATUS_SPEB_OVFL        (1<<4)
146 #define CS42L51_STATUS_PCMA_OVFL        (1<<3)
147 #define CS42L51_STATUS_PCMB_OVFL        (1<<2)
148 #define CS42L51_STATUS_ADCA_OVFL        (1<<1)
149 #define CS42L51_STATUS_ADCB_OVFL        (1<<0)
150
151 #define CS42L51_CHARGE_FREQ             0x21
152
153 #define CS42L51_FIRSTREG        0x01
154 /*
155  * Hack: with register 0x21, it makes 33 registers. Looks like someone in the
156  * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
157  * 32 regs
158  */
159 #define CS42L51_LASTREG         0x20
160 #define CS42L51_NUMREGS         (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
161
162 #endif