sound/soc/codecs/cs42l42.c

   1 /*
   2  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   3  *
   4  * Copyright 2016 Cirrus Logic, Inc.
   5  *
   6  * Author: James Schulman <james.schulman@cirrus.com>
   7  * Author: Brian Austin <brian.austin@cirrus.com>
   8  * Author: Michael White <michael.white@cirrus.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/version.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/i2c.h>
  23 #include <linux/gpio.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/of.h>
  30 #include <linux/of_gpio.h>
  31 #include <linux/of_device.h>
  32 #include <sound/core.h>
  33 #include <sound/pcm.h>
  34 #include <sound/pcm_params.h>
  35 #include <sound/soc.h>
  36 #include <sound/soc-dapm.h>
  37 #include <sound/initval.h>
  38 #include <sound/tlv.h>
  39 #include <dt-bindings/sound/cs42l42.h>
  40
  41 #include "cs42l42.h"
  42
  43 static const struct reg_default cs42l42_reg_defaults[] = {
  44         { CS42L42_FRZ_CTL,                      0x00 },
  45         { CS42L42_SRC_CTL,                      0x10 },
  46         { CS42L42_MCLK_STATUS,                  0x02 },
  47         { CS42L42_MCLK_CTL,                     0x02 },
  48         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  49         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  50         { CS42L42_I2C_STRETCH,                  0x03 },
  51         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  52         { CS42L42_PWR_CTL1,                     0xFF },
  53         { CS42L42_PWR_CTL2,                     0x84 },
  54         { CS42L42_PWR_CTL3,                     0x20 },
  55         { CS42L42_RSENSE_CTL1,                  0x40 },
  56         { CS42L42_RSENSE_CTL2,                  0x00 },
  57         { CS42L42_OSC_SWITCH,                   0x00 },
  58         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  59         { CS42L42_RSENSE_CTL3,                  0x1B },
  60         { CS42L42_TSENSE_CTL,                   0x1B },
  61         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  62         { CS42L42_TRSENSE_STATUS,               0x00 },
  63         { CS42L42_HSDET_CTL1,                   0x77 },
  64         { CS42L42_HSDET_CTL2,                   0x00 },
  65         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  66         { CS42L42_HS_DET_STATUS,                0x00 },
  67         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  68         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  69         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  70         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  71         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  72         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  73         { CS42L42_FSYNC_P_UPPER,                0x00 },
  74         { CS42L42_ASP_CLK_CFG,                  0x00 },
  75         { CS42L42_ASP_FRM_CFG,                  0x10 },
  76         { CS42L42_FS_RATE_EN,                   0x00 },
  77         { CS42L42_IN_ASRC_CLK,                  0x00 },
  78         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  79         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  80         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  81         { CS42L42_MIXER_STATUS,                 0x00 },
  82         { CS42L42_SRC_STATUS,                   0x00 },
  83         { CS42L42_ASP_RX_STATUS,                0x00 },
  84         { CS42L42_ASP_TX_STATUS,                0x00 },
  85         { CS42L42_CODEC_STATUS,                 0x00 },
  86         { CS42L42_DET_INT_STATUS1,              0x00 },
  87         { CS42L42_DET_INT_STATUS2,              0x00 },
  88         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  89         { CS42L42_VPMON_STATUS,                 0x00 },
  90         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  91         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  92         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  93         { CS42L42_MIXER_INT_MASK,               0x0F },
  94         { CS42L42_SRC_INT_MASK,                 0x0F },
  95         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  96         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  97         { CS42L42_CODEC_INT_MASK,               0x03 },
  98         { CS42L42_SRCPL_INT_MASK,               0xFF },
  99         { CS42L42_VPMON_INT_MASK,               0x01 },
 100         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
 101         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
 102         { CS42L42_PLL_CTL1,                     0x00 },
 103         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 104         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 105         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 106         { CS42L42_PLL_DIV_INT,                  0x40 },
 107         { CS42L42_PLL_CTL3,                     0x10 },
 108         { CS42L42_PLL_CAL_RATIO,                0x80 },
 109         { CS42L42_PLL_CTL4,                     0x03 },
 110         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 111         { CS42L42_LOAD_DET_DONE,                0x00 },
 112         { CS42L42_LOAD_DET_EN,                  0x00 },
 113         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 114         { CS42L42_WAKE_CTL,                     0xC0 },
 115         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 116         { CS42L42_TIPSENSE_CTL,                 0x02 },
 117         { CS42L42_MISC_DET_CTL,                 0x03 },
 118         { CS42L42_MIC_DET_CTL1,                 0x1F },
 119         { CS42L42_MIC_DET_CTL2,                 0x2F },
 120         { CS42L42_DET_STATUS1,                  0x00 },
 121         { CS42L42_DET_STATUS2,                  0x00 },
 122         { CS42L42_DET_INT1_MASK,                0xE0 },
 123         { CS42L42_DET_INT2_MASK,                0xFF },
 124         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 125         { CS42L42_ADC_CTL,                      0x00 },
 126         { CS42L42_ADC_VOLUME,                   0x00 },
 127         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 128         { CS42L42_DAC_CTL1,                     0x00 },
 129         { CS42L42_DAC_CTL2,                     0x02 },
 130         { CS42L42_HP_CTL,                       0x0D },
 131         { CS42L42_CLASSH_CTL,                   0x07 },
 132         { CS42L42_MIXER_CHA_VOL,                0x3F },
 133         { CS42L42_MIXER_ADC_VOL,                0x3F },
 134         { CS42L42_MIXER_CHB_VOL,                0x3F },
 135         { CS42L42_EQ_COEF_IN0,                  0x22 },
 136         { CS42L42_EQ_COEF_IN1,                  0x00 },
 137         { CS42L42_EQ_COEF_IN2,                  0x00 },
 138         { CS42L42_EQ_COEF_IN3,                  0x00 },
 139         { CS42L42_EQ_COEF_RW,                   0x00 },
 140         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 141         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 142         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 143         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 144         { CS42L42_EQ_INIT_STAT,                 0x00 },
 145         { CS42L42_EQ_START_FILT,                0x00 },
 146         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 147         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 148         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 149         { CS42L42_SP_RX_FS,                     0x8C },
 150         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 151         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 152         { CS42L42_SP_TX_FS,                     0xCC },
 153         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 154         { CS42L42_SRC_SDIN_FS,                  0x40 },
 155         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 156         { CS42L42_SPDIF_CTL1,                   0x01 },
 157         { CS42L42_SPDIF_CTL2,                   0x00 },
 158         { CS42L42_SPDIF_CTL3,                   0x00 },
 159         { CS42L42_SPDIF_CTL4,                   0x42 },
 160         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 161         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 162         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 163         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 164         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 165         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 166         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 167         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 168         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 169         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 170         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 172         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 173         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 174         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 175         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 176         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 177         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 178         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 179         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 180         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 181         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 182         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 183         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 184         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 185         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 186         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 187         { CS42L42_SUB_REVID,                    0x03 },
 188 };
 189
 190 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 191 {
 192         switch (reg) {
 193         case CS42L42_PAGE_REGISTER:
 194         case CS42L42_DEVID_AB:
 195         case CS42L42_DEVID_CD:
 196         case CS42L42_DEVID_E:
 197         case CS42L42_FABID:
 198         case CS42L42_REVID:
 199         case CS42L42_FRZ_CTL:
 200         case CS42L42_SRC_CTL:
 201         case CS42L42_MCLK_STATUS:
 202         case CS42L42_MCLK_CTL:
 203         case CS42L42_SFTRAMP_RATE:
 204         case CS42L42_I2C_DEBOUNCE:
 205         case CS42L42_I2C_STRETCH:
 206         case CS42L42_I2C_TIMEOUT:
 207         case CS42L42_PWR_CTL1:
 208         case CS42L42_PWR_CTL2:
 209         case CS42L42_PWR_CTL3:
 210         case CS42L42_RSENSE_CTL1:
 211         case CS42L42_RSENSE_CTL2:
 212         case CS42L42_OSC_SWITCH:
 213         case CS42L42_OSC_SWITCH_STATUS:
 214         case CS42L42_RSENSE_CTL3:
 215         case CS42L42_TSENSE_CTL:
 216         case CS42L42_TSRS_INT_DISABLE:
 217         case CS42L42_TRSENSE_STATUS:
 218         case CS42L42_HSDET_CTL1:
 219         case CS42L42_HSDET_CTL2:
 220         case CS42L42_HS_SWITCH_CTL:
 221         case CS42L42_HS_DET_STATUS:
 222         case CS42L42_HS_CLAMP_DISABLE:
 223         case CS42L42_MCLK_SRC_SEL:
 224         case CS42L42_SPDIF_CLK_CFG:
 225         case CS42L42_FSYNC_PW_LOWER:
 226         case CS42L42_FSYNC_PW_UPPER:
 227         case CS42L42_FSYNC_P_LOWER:
 228         case CS42L42_FSYNC_P_UPPER:
 229         case CS42L42_ASP_CLK_CFG:
 230         case CS42L42_ASP_FRM_CFG:
 231         case CS42L42_FS_RATE_EN:
 232         case CS42L42_IN_ASRC_CLK:
 233         case CS42L42_OUT_ASRC_CLK:
 234         case CS42L42_PLL_DIV_CFG1:
 235         case CS42L42_ADC_OVFL_STATUS:
 236         case CS42L42_MIXER_STATUS:
 237         case CS42L42_SRC_STATUS:
 238         case CS42L42_ASP_RX_STATUS:
 239         case CS42L42_ASP_TX_STATUS:
 240         case CS42L42_CODEC_STATUS:
 241         case CS42L42_DET_INT_STATUS1:
 242         case CS42L42_DET_INT_STATUS2:
 243         case CS42L42_SRCPL_INT_STATUS:
 244         case CS42L42_VPMON_STATUS:
 245         case CS42L42_PLL_LOCK_STATUS:
 246         case CS42L42_TSRS_PLUG_STATUS:
 247         case CS42L42_ADC_OVFL_INT_MASK:
 248         case CS42L42_MIXER_INT_MASK:
 249         case CS42L42_SRC_INT_MASK:
 250         case CS42L42_ASP_RX_INT_MASK:
 251         case CS42L42_ASP_TX_INT_MASK:
 252         case CS42L42_CODEC_INT_MASK:
 253         case CS42L42_SRCPL_INT_MASK:
 254         case CS42L42_VPMON_INT_MASK:
 255         case CS42L42_PLL_LOCK_INT_MASK:
 256         case CS42L42_TSRS_PLUG_INT_MASK:
 257         case CS42L42_PLL_CTL1:
 258         case CS42L42_PLL_DIV_FRAC0:
 259         case CS42L42_PLL_DIV_FRAC1:
 260         case CS42L42_PLL_DIV_FRAC2:
 261         case CS42L42_PLL_DIV_INT:
 262         case CS42L42_PLL_CTL3:
 263         case CS42L42_PLL_CAL_RATIO:
 264         case CS42L42_PLL_CTL4:
 265         case CS42L42_LOAD_DET_RCSTAT:
 266         case CS42L42_LOAD_DET_DONE:
 267         case CS42L42_LOAD_DET_EN:
 268         case CS42L42_HSBIAS_SC_AUTOCTL:
 269         case CS42L42_WAKE_CTL:
 270         case CS42L42_ADC_DISABLE_MUTE:
 271         case CS42L42_TIPSENSE_CTL:
 272         case CS42L42_MISC_DET_CTL:
 273         case CS42L42_MIC_DET_CTL1:
 274         case CS42L42_MIC_DET_CTL2:
 275         case CS42L42_DET_STATUS1:
 276         case CS42L42_DET_STATUS2:
 277         case CS42L42_DET_INT1_MASK:
 278         case CS42L42_DET_INT2_MASK:
 279         case CS42L42_HS_BIAS_CTL:
 280         case CS42L42_ADC_CTL:
 281         case CS42L42_ADC_VOLUME:
 282         case CS42L42_ADC_WNF_HPF_CTL:
 283         case CS42L42_DAC_CTL1:
 284         case CS42L42_DAC_CTL2:
 285         case CS42L42_HP_CTL:
 286         case CS42L42_CLASSH_CTL:
 287         case CS42L42_MIXER_CHA_VOL:
 288         case CS42L42_MIXER_ADC_VOL:
 289         case CS42L42_MIXER_CHB_VOL:
 290         case CS42L42_EQ_COEF_IN0:
 291         case CS42L42_EQ_COEF_IN1:
 292         case CS42L42_EQ_COEF_IN2:
 293         case CS42L42_EQ_COEF_IN3:
 294         case CS42L42_EQ_COEF_RW:
 295         case CS42L42_EQ_COEF_OUT0:
 296         case CS42L42_EQ_COEF_OUT1:
 297         case CS42L42_EQ_COEF_OUT2:
 298         case CS42L42_EQ_COEF_OUT3:
 299         case CS42L42_EQ_INIT_STAT:
 300         case CS42L42_EQ_START_FILT:
 301         case CS42L42_EQ_MUTE_CTL:
 302         case CS42L42_SP_RX_CH_SEL:
 303         case CS42L42_SP_RX_ISOC_CTL:
 304         case CS42L42_SP_RX_FS:
 305         case CS42l42_SPDIF_CH_SEL:
 306         case CS42L42_SP_TX_ISOC_CTL:
 307         case CS42L42_SP_TX_FS:
 308         case CS42L42_SPDIF_SW_CTL1:
 309         case CS42L42_SRC_SDIN_FS:
 310         case CS42L42_SRC_SDOUT_FS:
 311         case CS42L42_SPDIF_CTL1:
 312         case CS42L42_SPDIF_CTL2:
 313         case CS42L42_SPDIF_CTL3:
 314         case CS42L42_SPDIF_CTL4:
 315         case CS42L42_ASP_TX_SZ_EN:
 316         case CS42L42_ASP_TX_CH_EN:
 317         case CS42L42_ASP_TX_CH_AP_RES:
 318         case CS42L42_ASP_TX_CH1_BIT_MSB:
 319         case CS42L42_ASP_TX_CH1_BIT_LSB:
 320         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 321         case CS42L42_ASP_TX_CH2_BIT_MSB:
 322         case CS42L42_ASP_TX_CH2_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI0_EN:
 324         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 325         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 326         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 327         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 328         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 329         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 330         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 331         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 332         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 333         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 334         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 335         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 336         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 337         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 338         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 339         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 340         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 341         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 342         case CS42L42_SUB_REVID:
 343                 return true;
 344         default:
 345                 return false;
 346         }
 347 }
 348
 349 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 350 {
 351         switch (reg) {
 352         case CS42L42_DEVID_AB:
 353         case CS42L42_DEVID_CD:
 354         case CS42L42_DEVID_E:
 355         case CS42L42_MCLK_STATUS:
 356         case CS42L42_TRSENSE_STATUS:
 357         case CS42L42_HS_DET_STATUS:
 358         case CS42L42_ADC_OVFL_STATUS:
 359         case CS42L42_MIXER_STATUS:
 360         case CS42L42_SRC_STATUS:
 361         case CS42L42_ASP_RX_STATUS:
 362         case CS42L42_ASP_TX_STATUS:
 363         case CS42L42_CODEC_STATUS:
 364         case CS42L42_DET_INT_STATUS1:
 365         case CS42L42_DET_INT_STATUS2:
 366         case CS42L42_SRCPL_INT_STATUS:
 367         case CS42L42_VPMON_STATUS:
 368         case CS42L42_PLL_LOCK_STATUS:
 369         case CS42L42_TSRS_PLUG_STATUS:
 370         case CS42L42_LOAD_DET_RCSTAT:
 371         case CS42L42_LOAD_DET_DONE:
 372         case CS42L42_DET_STATUS1:
 373         case CS42L42_DET_STATUS2:
 374                 return true;
 375         default:
 376                 return false;
 377         }
 378 }
 379
 380 static const struct regmap_range_cfg cs42l42_page_range = {
 381         .name = "Pages",
 382         .range_min = 0,
 383         .range_max = CS42L42_MAX_REGISTER,
 384         .selector_reg = CS42L42_PAGE_REGISTER,
 385         .selector_mask = 0xff,
 386         .selector_shift = 0,
 387         .window_start = 0,
 388         .window_len = 256,
 389 };
 390
 391 static const struct regmap_config cs42l42_regmap = {
 392         .reg_bits = 8,
 393         .val_bits = 8,
 394
 395         .readable_reg = cs42l42_readable_register,
 396         .volatile_reg = cs42l42_volatile_register,
 397
 398         .ranges = &cs42l42_page_range,
 399         .num_ranges = 1,
 400
 401         .max_register = CS42L42_MAX_REGISTER,
 402         .reg_defaults = cs42l42_reg_defaults,
 403         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 404         .cache_type = REGCACHE_RBTREE,
 405 };
 406
 407 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false);
 408 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6200, 100, false);
 409
 410 static const char * const cs42l42_hpf_freq_text[] = {
 411         "1.86Hz", "120Hz", "235Hz", "466Hz"
 412 };
 413
 414 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 415                             CS42L42_ADC_HPF_CF_SHIFT,
 416                             cs42l42_hpf_freq_text);
 417
 418 static const char * const cs42l42_wnf3_freq_text[] = {
 419         "160Hz", "180Hz", "200Hz", "220Hz",
 420         "240Hz", "260Hz", "280Hz", "300Hz"
 421 };
 422
 423 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 424                             CS42L42_ADC_WNF_CF_SHIFT,
 425                             cs42l42_wnf3_freq_text);
 426
 427 static const char * const cs42l42_wnf05_freq_text[] = {
 428         "280Hz", "315Hz", "350Hz", "385Hz",
 429         "420Hz", "455Hz", "490Hz", "525Hz"
 430 };
 431
 432 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 433                             CS42L42_ADC_WNF_CF_SHIFT,
 434                             cs42l42_wnf05_freq_text);
 435
 436 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 437         /* ADC Volume and Filter Controls */
 438         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 439                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false),
 440         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 441                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 442         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 443                                 CS42L42_ADC_INV_SHIFT, true, false),
 444         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 445                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 446         SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME,
 447                                 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv),
 448         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 449                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 450         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 451                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 452         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 453         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 454         SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
 455
 456         /* DAC Volume and Filter Controls */
 457         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 458                                 CS42L42_DACA_INV_SHIFT, true, false),
 459         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 460                                 CS42L42_DACB_INV_SHIFT, true, false),
 461         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 462                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 463         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 464                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 465                                 0x3e, 1, mixer_tlv)
 466 };
 467
 468 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
 469                                 struct snd_kcontrol *kcontrol, int event)
 470 {
 471         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 472
 473         if (event & SND_SOC_DAPM_POST_PMU) {
 474                 /* Enable the channels */
 475                 snd_soc_update_bits(codec, CS42L42_ASP_RX_DAI0_EN,
 476                                 CS42L42_ASP_RX0_CH_EN_MASK,
 477                                 (CS42L42_ASP_RX0_CH1_EN |
 478                                 CS42L42_ASP_RX0_CH2_EN) <<
 479                                 CS42L42_ASP_RX0_CH_EN_SHIFT);
 480
 481                 /* Power up */
 482                 snd_soc_update_bits(codec, CS42L42_PWR_CTL1,
 483                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 484                                 CS42L42_HP_PDN_MASK, 0);
 485         } else if (event & SND_SOC_DAPM_PRE_PMD) {
 486                 /* Disable the channels */
 487                 snd_soc_update_bits(codec, CS42L42_ASP_RX_DAI0_EN,
 488                                 CS42L42_ASP_RX0_CH_EN_MASK, 0);
 489
 490                 /* Power down */
 491                 snd_soc_update_bits(codec, CS42L42_PWR_CTL1,
 492                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 493                                 CS42L42_HP_PDN_MASK,
 494                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 495                                 CS42L42_HP_PDN_MASK);
 496         } else {
 497                 dev_err(codec->dev, "Invalid event 0x%x\n", event);
 498         }
 499         return 0;
 500 }
 501
 502 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 503         SND_SOC_DAPM_OUTPUT("HP"),
 504         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
 505                                         CS42L42_ASP_SCLK_EN_SHIFT, false),
 506         SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
 507                                         0, NULL, 0, cs42l42_hpdrv_evt,
 508                                         SND_SOC_DAPM_POST_PMU |
 509                                         SND_SOC_DAPM_PRE_PMD)
 510 };
 511
 512 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 513         {"SDIN", NULL, "Playback"},
 514         {"HPDRV", NULL, "SDIN"},
 515         {"HP", NULL, "HPDRV"}
 516 };
 517
 518 static int cs42l42_set_bias_level(struct snd_soc_codec *codec,
 519                                         enum snd_soc_bias_level level)
 520 {
 521         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 522         int ret;
 523
 524         switch (level) {
 525         case SND_SOC_BIAS_ON:
 526                 break;
 527         case SND_SOC_BIAS_PREPARE:
 528                 break;
 529         case SND_SOC_BIAS_STANDBY:
 530                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 531                         regcache_cache_only(cs42l42->regmap, false);
 532                         regcache_sync(cs42l42->regmap);
 533                         ret = regulator_bulk_enable(
 534                                                 ARRAY_SIZE(cs42l42->supplies),
 535                                                 cs42l42->supplies);
 536                         if (ret != 0) {
 537                                 dev_err(codec->dev,
 538                                         "Failed to enable regulators: %d\n",
 539                                         ret);
 540                                 return ret;
 541                         }
 542                 }
 543                 break;
 544         case SND_SOC_BIAS_OFF:
 545
 546                 regcache_cache_only(cs42l42->regmap, true);
 547                 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
 548                                                     cs42l42->supplies);
 549                 break;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int cs42l42_codec_probe(struct snd_soc_codec *codec)
 556 {
 557         struct cs42l42_private *cs42l42 =
 558                 (struct cs42l42_private *)snd_soc_codec_get_drvdata(codec);
 559
 560         cs42l42->codec = codec;
 561
 562         return 0;
 563 }
 564
 565 static const struct snd_soc_codec_driver soc_codec_dev_cs42l42 = {
 566         .probe = cs42l42_codec_probe,
 567         .set_bias_level = cs42l42_set_bias_level,
 568         .ignore_pmdown_time = true,
 569
 570         .component_driver = {
 571                 .dapm_widgets = cs42l42_dapm_widgets,
 572                 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
 573                 .dapm_routes = cs42l42_audio_map,
 574                 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
 575
 576                 .controls = cs42l42_snd_controls,
 577                 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
 578         },
 579 };
 580
 581 struct cs42l42_pll_params {
 582         u32 sclk;
 583         u8 mclk_div;
 584         u8 mclk_src_sel;
 585         u8 sclk_prediv;
 586         u8 pll_div_int;
 587         u32 pll_div_frac;
 588         u8 pll_mode;
 589         u8 pll_divout;
 590         u32 mclk_int;
 591         u8 pll_cal_ratio;
 592 };
 593
 594 /*
 595  * Common PLL Settings for given SCLK
 596  * Table 4-5 from the Datasheet
 597  */
 598 static const struct cs42l42_pll_params pll_ratio_table[] = {
 599         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
 600         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 601         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 602         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 603         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
 604         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
 605         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 606         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 607         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 608         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
 609         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
 610         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
 611         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
 612         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
 613         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
 614 };
 615
 616 static int cs42l42_pll_config(struct snd_soc_codec *codec)
 617 {
 618         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 619         int i;
 620         u32 fsync;
 621
 622         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 623                 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
 624                         /* Configure the internal sample rate */
 625                         snd_soc_update_bits(codec, CS42L42_MCLK_CTL,
 626                                         CS42L42_INTERNAL_FS_MASK,
 627                                         ((pll_ratio_table[i].mclk_int !=
 628                                         12000000) &&
 629                                         (pll_ratio_table[i].mclk_int !=
 630                                         24000000)) <<
 631                                         CS42L42_INTERNAL_FS_SHIFT);
 632                         /* Set the MCLK src (PLL or SCLK) and the divide
 633                          * ratio
 634                          */
 635                         snd_soc_update_bits(codec, CS42L42_MCLK_SRC_SEL,
 636                                         CS42L42_MCLK_SRC_SEL_MASK |
 637                                         CS42L42_MCLKDIV_MASK,
 638                                         (pll_ratio_table[i].mclk_src_sel
 639                                         << CS42L42_MCLK_SRC_SEL_SHIFT) |
 640                                         (pll_ratio_table[i].mclk_div <<
 641                                         CS42L42_MCLKDIV_SHIFT));
 642                         /* Set up the LRCLK */
 643                         fsync = cs42l42->sclk / cs42l42->srate;
 644                         if (((fsync * cs42l42->srate) != cs42l42->sclk)
 645                                 || ((fsync % 2) != 0)) {
 646                                 dev_err(codec->dev,
 647                                         "Unsupported sclk %d/sample rate %d\n",
 648                                         cs42l42->sclk,
 649                                         cs42l42->srate);
 650                                 return -EINVAL;
 651                         }
 652                         /* Set the LRCLK period */
 653                         snd_soc_update_bits(codec,
 654                                         CS42L42_FSYNC_P_LOWER,
 655                                         CS42L42_FSYNC_PERIOD_MASK,
 656                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 657                                         CS42L42_FSYNC_PERIOD_SHIFT);
 658                         snd_soc_update_bits(codec,
 659                                         CS42L42_FSYNC_P_UPPER,
 660                                         CS42L42_FSYNC_PERIOD_MASK,
 661                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 662                                         CS42L42_FSYNC_PERIOD_SHIFT);
 663                         /* Set the LRCLK to 50% duty cycle */
 664                         fsync = fsync / 2;
 665                         snd_soc_update_bits(codec,
 666                                         CS42L42_FSYNC_PW_LOWER,
 667                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 668                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 669                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 670                         snd_soc_update_bits(codec,
 671                                         CS42L42_FSYNC_PW_UPPER,
 672                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 673                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 674                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 675                         snd_soc_update_bits(codec,
 676                                         CS42L42_ASP_FRM_CFG,
 677                                         CS42L42_ASP_5050_MASK,
 678                                         CS42L42_ASP_5050_MASK);
 679                         /* Set the frame delay to 1.0 SCLK clocks */
 680                         snd_soc_update_bits(codec, CS42L42_ASP_FRM_CFG,
 681                                         CS42L42_ASP_FSD_MASK,
 682                                         CS42L42_ASP_FSD_1_0 <<
 683                                         CS42L42_ASP_FSD_SHIFT);
 684                         /* Set the sample rates (96k or lower) */
 685                         snd_soc_update_bits(codec, CS42L42_FS_RATE_EN,
 686                                         CS42L42_FS_EN_MASK,
 687                                         (CS42L42_FS_EN_IASRC_96K |
 688                                         CS42L42_FS_EN_OASRC_96K) <<
 689                                         CS42L42_FS_EN_SHIFT);
 690                         /* Set the input/output internal MCLK clock ~12 MHz */
 691                         snd_soc_update_bits(codec, CS42L42_IN_ASRC_CLK,
 692                                         CS42L42_CLK_IASRC_SEL_MASK,
 693                                         CS42L42_CLK_IASRC_SEL_12 <<
 694                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 695                         snd_soc_update_bits(codec,
 696                                         CS42L42_OUT_ASRC_CLK,
 697                                         CS42L42_CLK_OASRC_SEL_MASK,
 698                                         CS42L42_CLK_OASRC_SEL_12 <<
 699                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 700                         /* channel 1 on low LRCLK, 32 bit */
 701                         snd_soc_update_bits(codec,
 702                                         CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 703                                         CS42L42_ASP_RX_CH_AP_MASK |
 704                                         CS42L42_ASP_RX_CH_RES_MASK,
 705                                         (CS42L42_ASP_RX_CH_AP_LOW <<
 706                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 707                                         (CS42L42_ASP_RX_CH_RES_32 <<
 708                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 709                         /* Channel 2 on high LRCLK, 32 bit */
 710                         snd_soc_update_bits(codec,
 711                                         CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 712                                         CS42L42_ASP_RX_CH_AP_MASK |
 713                                         CS42L42_ASP_RX_CH_RES_MASK,
 714                                         (CS42L42_ASP_RX_CH_AP_HI <<
 715                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 716                                         (CS42L42_ASP_RX_CH_RES_32 <<
 717                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 718                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 719                                 /* Pass the clock straight through */
 720                                 snd_soc_update_bits(codec,
 721                                         CS42L42_PLL_CTL1,
 722                                         CS42L42_PLL_START_MASK, 0);
 723                         } else {
 724                                 /* Configure PLL per table 4-5 */
 725                                 snd_soc_update_bits(codec,
 726                                         CS42L42_PLL_DIV_CFG1,
 727                                         CS42L42_SCLK_PREDIV_MASK,
 728                                         pll_ratio_table[i].sclk_prediv
 729                                         << CS42L42_SCLK_PREDIV_SHIFT);
 730                                 snd_soc_update_bits(codec,
 731                                         CS42L42_PLL_DIV_INT,
 732                                         CS42L42_PLL_DIV_INT_MASK,
 733                                         pll_ratio_table[i].pll_div_int
 734                                         << CS42L42_PLL_DIV_INT_SHIFT);
 735                                 snd_soc_update_bits(codec,
 736                                         CS42L42_PLL_DIV_FRAC0,
 737                                         CS42L42_PLL_DIV_FRAC_MASK,
 738                                         CS42L42_FRAC0_VAL(
 739                                         pll_ratio_table[i].pll_div_frac)
 740                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 741                                 snd_soc_update_bits(codec,
 742                                         CS42L42_PLL_DIV_FRAC1,
 743                                         CS42L42_PLL_DIV_FRAC_MASK,
 744                                         CS42L42_FRAC1_VAL(
 745                                         pll_ratio_table[i].pll_div_frac)
 746                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 747                                 snd_soc_update_bits(codec,
 748                                         CS42L42_PLL_DIV_FRAC2,
 749                                         CS42L42_PLL_DIV_FRAC_MASK,
 750                                         CS42L42_FRAC2_VAL(
 751                                         pll_ratio_table[i].pll_div_frac)
 752                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 753                                 snd_soc_update_bits(codec,
 754                                         CS42L42_PLL_CTL4,
 755                                         CS42L42_PLL_MODE_MASK,
 756                                         pll_ratio_table[i].pll_mode
 757                                         << CS42L42_PLL_MODE_SHIFT);
 758                                 snd_soc_update_bits(codec,
 759                                         CS42L42_PLL_CTL3,
 760                                         CS42L42_PLL_DIVOUT_MASK,
 761                                         pll_ratio_table[i].pll_divout
 762                                         << CS42L42_PLL_DIVOUT_SHIFT);
 763                                 snd_soc_update_bits(codec,
 764                                         CS42L42_PLL_CAL_RATIO,
 765                                         CS42L42_PLL_CAL_RATIO_MASK,
 766                                         pll_ratio_table[i].pll_cal_ratio
 767                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 768                         }
 769                         return 0;
 770                 }
 771         }
 772
 773         return -EINVAL;
 774 }
 775
 776 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 777 {
 778         struct snd_soc_codec *codec = codec_dai->codec;
 779         u32 asp_cfg_val = 0;
 780
 781         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 782         case SND_SOC_DAIFMT_CBS_CFM:
 783                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 784                                 CS42L42_ASP_MODE_SHIFT;
 785                 break;
 786         case SND_SOC_DAIFMT_CBS_CFS:
 787                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 788                                 CS42L42_ASP_MODE_SHIFT;
 789                 break;
 790         default:
 791                 return -EINVAL;
 792         }
 793
 794         /* interface format */
 795         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 796         case SND_SOC_DAIFMT_I2S:
 797         case SND_SOC_DAIFMT_LEFT_J:
 798                 break;
 799         default:
 800                 return -EINVAL;
 801         }
 802
 803         /* Bitclock/frame inversion */
 804         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 805         case SND_SOC_DAIFMT_NB_NF:
 806                 break;
 807         case SND_SOC_DAIFMT_NB_IF:
 808                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 809                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 810                 break;
 811         case SND_SOC_DAIFMT_IB_NF:
 812                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 813                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 814                 break;
 815         case SND_SOC_DAIFMT_IB_IF:
 816                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 817                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 818                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 819                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 820                 break;
 821         }
 822
 823         snd_soc_update_bits(codec, CS42L42_ASP_CLK_CFG,
 824                                 CS42L42_ASP_MODE_MASK |
 825                                 CS42L42_ASP_SCPOL_IN_DAC_MASK |
 826                                 CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val);
 827
 828         return 0;
 829 }
 830
 831 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 832                                 struct snd_pcm_hw_params *params,
 833                                 struct snd_soc_dai *dai)
 834 {
 835         struct snd_soc_codec *codec = dai->codec;
 836         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 837         int retval;
 838
 839         cs42l42->srate = params_rate(params);
 840         cs42l42->swidth = params_width(params);
 841
 842         retval = cs42l42_pll_config(codec);
 843
 844         return retval;
 845 }
 846
 847 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 848                                 int clk_id, unsigned int freq, int dir)
 849 {
 850         struct snd_soc_codec *codec = dai->codec;
 851         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 852
 853         cs42l42->sclk = freq;
 854
 855         return 0;
 856 }
 857
 858 static int cs42l42_digital_mute(struct snd_soc_dai *dai, int mute)
 859 {
 860         struct snd_soc_codec *codec = dai->codec;
 861         unsigned int regval;
 862         u8 fullScaleVol;
 863
 864         if (mute) {
 865                 /* Mark SCLK as not present to turn on the internal
 866                  * oscillator.
 867                  */
 868                 snd_soc_update_bits(codec, CS42L42_OSC_SWITCH,
 869                                                 CS42L42_SCLK_PRESENT_MASK, 0);
 870
 871                 snd_soc_update_bits(codec, CS42L42_PLL_CTL1,
 872                                 CS42L42_PLL_START_MASK,
 873                                 0 << CS42L42_PLL_START_SHIFT);
 874
 875                 /* Mute the headphone */
 876                 snd_soc_update_bits(codec, CS42L42_HP_CTL,
 877                                 CS42L42_HP_ANA_AMUTE_MASK |
 878                                 CS42L42_HP_ANA_BMUTE_MASK,
 879                                 CS42L42_HP_ANA_AMUTE_MASK |
 880                                 CS42L42_HP_ANA_BMUTE_MASK);
 881         } else {
 882                 snd_soc_update_bits(codec, CS42L42_PLL_CTL1,
 883                                 CS42L42_PLL_START_MASK,
 884                                 1 << CS42L42_PLL_START_SHIFT);
 885                 /* Read the headphone load */
 886                 regval = snd_soc_read(codec, CS42L42_LOAD_DET_RCSTAT);
 887                 if (((regval & CS42L42_RLA_STAT_MASK) >>
 888                         CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
 889                         fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
 890                 } else {
 891                         fullScaleVol = 0;
 892                 }
 893
 894                 /* Un-mute the headphone, set the full scale volume flag */
 895                 snd_soc_update_bits(codec, CS42L42_HP_CTL,
 896                                 CS42L42_HP_ANA_AMUTE_MASK |
 897                                 CS42L42_HP_ANA_BMUTE_MASK |
 898                                 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
 899
 900                 /* Mark SCLK as present, turn off internal oscillator */
 901                 snd_soc_update_bits(codec, CS42L42_OSC_SWITCH,
 902                                 CS42L42_SCLK_PRESENT_MASK,
 903                                 CS42L42_SCLK_PRESENT_MASK);
 904         }
 905
 906         return 0;
 907 }
 908
 909 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
 910                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
 911                         SNDRV_PCM_FMTBIT_S32_LE)
 912
 913
 914 static struct snd_soc_dai_ops cs42l42_ops = {
 915         .hw_params      = cs42l42_pcm_hw_params,
 916         .set_fmt        = cs42l42_set_dai_fmt,
 917         .set_sysclk     = cs42l42_set_sysclk,
 918         .digital_mute = cs42l42_digital_mute
 919 };
 920
 921 static struct snd_soc_dai_driver cs42l42_dai = {
 922                 .name = "cs42l42",
 923                 .playback = {
 924                         .stream_name = "Playback",
 925                         .channels_min = 1,
 926                         .channels_max = 2,
 927                         .rates = SNDRV_PCM_RATE_8000_192000,
 928                         .formats = CS42L42_FORMATS,
 929                 },
 930                 .capture = {
 931                         .stream_name = "Capture",
 932                         .channels_min = 1,
 933                         .channels_max = 2,
 934                         .rates = SNDRV_PCM_RATE_8000_192000,
 935                         .formats = CS42L42_FORMATS,
 936                 },
 937                 .ops = &cs42l42_ops,
 938 };
 939
 940 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
 941 {
 942         unsigned int hs_det_status;
 943         unsigned int int_status;
 944
 945         /* Mask the auto detect interrupt */
 946         regmap_update_bits(cs42l42->regmap,
 947                 CS42L42_CODEC_INT_MASK,
 948                 CS42L42_PDN_DONE_MASK |
 949                 CS42L42_HSDET_AUTO_DONE_MASK,
 950                 (1 << CS42L42_PDN_DONE_SHIFT) |
 951                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
 952
 953         /* Set hs detect to automatic, disabled mode */
 954         regmap_update_bits(cs42l42->regmap,
 955                 CS42L42_HSDET_CTL2,
 956                 CS42L42_HSDET_CTRL_MASK |
 957                 CS42L42_HSDET_SET_MASK |
 958                 CS42L42_HSBIAS_REF_MASK |
 959                 CS42L42_HSDET_AUTO_TIME_MASK,
 960                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
 961                 (2 << CS42L42_HSDET_SET_SHIFT) |
 962                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 963                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 964
 965         /* Read and save the hs detection result */
 966         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
 967
 968         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
 969                                 CS42L42_HSDET_TYPE_SHIFT;
 970
 971         /* Set up button detection */
 972         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
 973               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
 974                 /* Set auto HS bias settings to default */
 975                 regmap_update_bits(cs42l42->regmap,
 976                         CS42L42_HSBIAS_SC_AUTOCTL,
 977                         CS42L42_HSBIAS_SENSE_EN_MASK |
 978                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 979                         CS42L42_TIP_SENSE_EN_MASK |
 980                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 981                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 982                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 983                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 984                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 985
 986                 /* Set up hs detect level sensitivity */
 987                 regmap_update_bits(cs42l42->regmap,
 988                         CS42L42_MIC_DET_CTL1,
 989                         CS42L42_LATCH_TO_VP_MASK |
 990                         CS42L42_EVENT_STAT_SEL_MASK |
 991                         CS42L42_HS_DET_LEVEL_MASK,
 992                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
 993                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
 994                         (cs42l42->bias_thresholds[0] <<
 995                         CS42L42_HS_DET_LEVEL_SHIFT));
 996
 997                 /* Set auto HS bias settings to default */
 998                 regmap_update_bits(cs42l42->regmap,
 999                         CS42L42_HSBIAS_SC_AUTOCTL,
1000                         CS42L42_HSBIAS_SENSE_EN_MASK |
1001                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1002                         CS42L42_TIP_SENSE_EN_MASK |
1003                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1004                         (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1005                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1006                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1007                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1008
1009                 /* Turn on level detect circuitry */
1010                 regmap_update_bits(cs42l42->regmap,
1011                         CS42L42_MISC_DET_CTL,
1012                         CS42L42_DETECT_MODE_MASK |
1013                         CS42L42_HSBIAS_CTL_MASK |
1014                         CS42L42_PDN_MIC_LVL_DET_MASK,
1015                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1016                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1017                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1018
1019                 msleep(cs42l42->btn_det_init_dbnce);
1020
1021                 /* Clear any button interrupts before unmasking them */
1022                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1023                             &int_status);
1024
1025                 /* Unmask button detect interrupts */
1026                 regmap_update_bits(cs42l42->regmap,
1027                         CS42L42_DET_INT2_MASK,
1028                         CS42L42_M_DETECT_TF_MASK |
1029                         CS42L42_M_DETECT_FT_MASK |
1030                         CS42L42_M_HSBIAS_HIZ_MASK |
1031                         CS42L42_M_SHORT_RLS_MASK |
1032                         CS42L42_M_SHORT_DET_MASK,
1033                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1034                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1035                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1036                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1037                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1038         } else {
1039                 /* Make sure button detect and HS bias circuits are off */
1040                 regmap_update_bits(cs42l42->regmap,
1041                         CS42L42_MISC_DET_CTL,
1042                         CS42L42_DETECT_MODE_MASK |
1043                         CS42L42_HSBIAS_CTL_MASK |
1044                         CS42L42_PDN_MIC_LVL_DET_MASK,
1045                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1046                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1047                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1048         }
1049
1050         regmap_update_bits(cs42l42->regmap,
1051                                 CS42L42_DAC_CTL2,
1052                                 CS42L42_HPOUT_PULLDOWN_MASK |
1053                                 CS42L42_HPOUT_LOAD_MASK |
1054                                 CS42L42_HPOUT_CLAMP_MASK |
1055                                 CS42L42_DAC_HPF_EN_MASK |
1056                                 CS42L42_DAC_MON_EN_MASK,
1057                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1058                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1059                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1060                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1061                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1062
1063         /* Unmask tip sense interrupts */
1064         regmap_update_bits(cs42l42->regmap,
1065                 CS42L42_TSRS_PLUG_INT_MASK,
1066                 CS42L42_RS_PLUG_MASK |
1067                 CS42L42_RS_UNPLUG_MASK |
1068                 CS42L42_TS_PLUG_MASK |
1069                 CS42L42_TS_UNPLUG_MASK,
1070                 (1 << CS42L42_RS_PLUG_SHIFT) |
1071                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1072                 (0 << CS42L42_TS_PLUG_SHIFT) |
1073                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1074 }
1075
1076 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1077 {
1078         /* Mask tip sense interrupts */
1079         regmap_update_bits(cs42l42->regmap,
1080                                 CS42L42_TSRS_PLUG_INT_MASK,
1081                                 CS42L42_RS_PLUG_MASK |
1082                                 CS42L42_RS_UNPLUG_MASK |
1083                                 CS42L42_TS_PLUG_MASK |
1084                                 CS42L42_TS_UNPLUG_MASK,
1085                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1086                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1087                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1088                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1089
1090         /* Make sure button detect and HS bias circuits are off */
1091         regmap_update_bits(cs42l42->regmap,
1092                                 CS42L42_MISC_DET_CTL,
1093                                 CS42L42_DETECT_MODE_MASK |
1094                                 CS42L42_HSBIAS_CTL_MASK |
1095                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1096                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1097                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1098                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1099
1100         /* Set auto HS bias settings to default */
1101         regmap_update_bits(cs42l42->regmap,
1102                                 CS42L42_HSBIAS_SC_AUTOCTL,
1103                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1104                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1105                                 CS42L42_TIP_SENSE_EN_MASK |
1106                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1107                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1108                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1109                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1110                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1111
1112         /* Set hs detect to manual, disabled mode */
1113         regmap_update_bits(cs42l42->regmap,
1114                                 CS42L42_HSDET_CTL2,
1115                                 CS42L42_HSDET_CTRL_MASK |
1116                                 CS42L42_HSDET_SET_MASK |
1117                                 CS42L42_HSBIAS_REF_MASK |
1118                                 CS42L42_HSDET_AUTO_TIME_MASK,
1119                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1120                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1121                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1122                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1123
1124         regmap_update_bits(cs42l42->regmap,
1125                                 CS42L42_DAC_CTL2,
1126                                 CS42L42_HPOUT_PULLDOWN_MASK |
1127                                 CS42L42_HPOUT_LOAD_MASK |
1128                                 CS42L42_HPOUT_CLAMP_MASK |
1129                                 CS42L42_DAC_HPF_EN_MASK |
1130                                 CS42L42_DAC_MON_EN_MASK,
1131                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1132                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1133                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1134                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1135                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1136
1137         /* Power up HS bias to 2.7V */
1138         regmap_update_bits(cs42l42->regmap,
1139                                 CS42L42_MISC_DET_CTL,
1140                                 CS42L42_DETECT_MODE_MASK |
1141                                 CS42L42_HSBIAS_CTL_MASK |
1142                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1143                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1144                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1145                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1146
1147         /* Wait for HS bias to ramp up */
1148         msleep(cs42l42->hs_bias_ramp_time);
1149
1150         /* Unmask auto detect interrupt */
1151         regmap_update_bits(cs42l42->regmap,
1152                                 CS42L42_CODEC_INT_MASK,
1153                                 CS42L42_PDN_DONE_MASK |
1154                                 CS42L42_HSDET_AUTO_DONE_MASK,
1155                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1156                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1157
1158         /* Set hs detect to automatic, enabled mode */
1159         regmap_update_bits(cs42l42->regmap,
1160                                 CS42L42_HSDET_CTL2,
1161                                 CS42L42_HSDET_CTRL_MASK |
1162                                 CS42L42_HSDET_SET_MASK |
1163                                 CS42L42_HSBIAS_REF_MASK |
1164                                 CS42L42_HSDET_AUTO_TIME_MASK,
1165                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1166                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1167                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1168                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1169 }
1170
1171 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1172 {
1173         /* Mask button detect interrupts */
1174         regmap_update_bits(cs42l42->regmap,
1175                 CS42L42_DET_INT2_MASK,
1176                 CS42L42_M_DETECT_TF_MASK |
1177                 CS42L42_M_DETECT_FT_MASK |
1178                 CS42L42_M_HSBIAS_HIZ_MASK |
1179                 CS42L42_M_SHORT_RLS_MASK |
1180                 CS42L42_M_SHORT_DET_MASK,
1181                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1182                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1183                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1184                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1185                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1186
1187         /* Ground HS bias */
1188         regmap_update_bits(cs42l42->regmap,
1189                                 CS42L42_MISC_DET_CTL,
1190                                 CS42L42_DETECT_MODE_MASK |
1191                                 CS42L42_HSBIAS_CTL_MASK |
1192                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1193                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1194                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1195                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1196
1197         /* Set auto HS bias settings to default */
1198         regmap_update_bits(cs42l42->regmap,
1199                                 CS42L42_HSBIAS_SC_AUTOCTL,
1200                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1201                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1202                                 CS42L42_TIP_SENSE_EN_MASK |
1203                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1204                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1205                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1206                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1207                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1208
1209         /* Set hs detect to manual, disabled mode */
1210         regmap_update_bits(cs42l42->regmap,
1211                                 CS42L42_HSDET_CTL2,
1212                                 CS42L42_HSDET_CTRL_MASK |
1213                                 CS42L42_HSDET_SET_MASK |
1214                                 CS42L42_HSBIAS_REF_MASK |
1215                                 CS42L42_HSDET_AUTO_TIME_MASK,
1216                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1217                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1218                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1219                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1220 }
1221
1222 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1223 {
1224         int bias_level;
1225         unsigned int detect_status;
1226
1227         /* Mask button detect interrupts */
1228         regmap_update_bits(cs42l42->regmap,
1229                 CS42L42_DET_INT2_MASK,
1230                 CS42L42_M_DETECT_TF_MASK |
1231                 CS42L42_M_DETECT_FT_MASK |
1232                 CS42L42_M_HSBIAS_HIZ_MASK |
1233                 CS42L42_M_SHORT_RLS_MASK |
1234                 CS42L42_M_SHORT_DET_MASK,
1235                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1236                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1237                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1238                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1239                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1240
1241         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1242                      cs42l42->btn_det_event_dbnce * 2000);
1243
1244         /* Test all 4 level detect biases */
1245         bias_level = 1;
1246         do {
1247                 /* Adjust button detect level sensitivity */
1248                 regmap_update_bits(cs42l42->regmap,
1249                         CS42L42_MIC_DET_CTL1,
1250                         CS42L42_LATCH_TO_VP_MASK |
1251                         CS42L42_EVENT_STAT_SEL_MASK |
1252                         CS42L42_HS_DET_LEVEL_MASK,
1253                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1254                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1255                         (cs42l42->bias_thresholds[bias_level] <<
1256                         CS42L42_HS_DET_LEVEL_SHIFT));
1257
1258                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1259                                 &detect_status);
1260         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1261                 (++bias_level < CS42L42_NUM_BIASES));
1262
1263         switch (bias_level) {
1264         case 1: /* Function C button press */
1265                 dev_dbg(cs42l42->codec->dev, "Function C button press\n");
1266                 break;
1267         case 2: /* Function B button press */
1268                 dev_dbg(cs42l42->codec->dev, "Function B button press\n");
1269                 break;
1270         case 3: /* Function D button press */
1271                 dev_dbg(cs42l42->codec->dev, "Function D button press\n");
1272                 break;
1273         case 4: /* Function A button press */
1274                 dev_dbg(cs42l42->codec->dev, "Function A button press\n");
1275                 break;
1276         }
1277
1278         /* Set button detect level sensitivity back to default */
1279         regmap_update_bits(cs42l42->regmap,
1280                 CS42L42_MIC_DET_CTL1,
1281                 CS42L42_LATCH_TO_VP_MASK |
1282                 CS42L42_EVENT_STAT_SEL_MASK |
1283                 CS42L42_HS_DET_LEVEL_MASK,
1284                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1285                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1286                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1287
1288         /* Clear any button interrupts before unmasking them */
1289         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1290                     &detect_status);
1291
1292         /* Unmask button detect interrupts */
1293         regmap_update_bits(cs42l42->regmap,
1294                 CS42L42_DET_INT2_MASK,
1295                 CS42L42_M_DETECT_TF_MASK |
1296                 CS42L42_M_DETECT_FT_MASK |
1297                 CS42L42_M_HSBIAS_HIZ_MASK |
1298                 CS42L42_M_SHORT_RLS_MASK |
1299                 CS42L42_M_SHORT_DET_MASK,
1300                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1301                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1302                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1303                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1304                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1305 }
1306
1307 struct cs42l42_irq_params {
1308         u16 status_addr;
1309         u16 mask_addr;
1310         u8 mask;
1311 };
1312
1313 static const struct cs42l42_irq_params irq_params_table[] = {
1314         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1315                 CS42L42_ADC_OVFL_VAL_MASK},
1316         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1317                 CS42L42_MIXER_VAL_MASK},
1318         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1319                 CS42L42_SRC_VAL_MASK},
1320         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1321                 CS42L42_ASP_RX_VAL_MASK},
1322         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1323                 CS42L42_ASP_TX_VAL_MASK},
1324         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1325                 CS42L42_CODEC_VAL_MASK},
1326         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1327                 CS42L42_DET_INT_VAL1_MASK},
1328         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1329                 CS42L42_DET_INT_VAL2_MASK},
1330         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1331                 CS42L42_SRCPL_VAL_MASK},
1332         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1333                 CS42L42_VPMON_VAL_MASK},
1334         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1335                 CS42L42_PLL_LOCK_VAL_MASK},
1336         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1337                 CS42L42_TSRS_PLUG_VAL_MASK}
1338 };
1339
1340 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1341 {
1342         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1343         struct snd_soc_codec *codec = cs42l42->codec;
1344         unsigned int stickies[12];
1345         unsigned int masks[12];
1346         unsigned int current_plug_status;
1347         unsigned int current_button_status;
1348         unsigned int i;
1349
1350         /* Read sticky registers to clear interurpt */
1351         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1352                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1353                                 &(stickies[i]));
1354                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1355                                 &(masks[i]));
1356                 stickies[i] = stickies[i] & (~masks[i]) &
1357                                 irq_params_table[i].mask;
1358         }
1359
1360         /* Read tip sense status before handling type detect */
1361         current_plug_status = (stickies[11] &
1362                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1363                 CS42L42_TS_PLUG_SHIFT;
1364
1365         /* Read button sense status */
1366         current_button_status = stickies[7] &
1367                 (CS42L42_M_DETECT_TF_MASK |
1368                 CS42L42_M_DETECT_FT_MASK |
1369                 CS42L42_M_HSBIAS_HIZ_MASK);
1370
1371         /* Check auto-detect status */
1372         if ((~masks[5]) & irq_params_table[5].mask) {
1373                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1374                         cs42l42_process_hs_type_detect(cs42l42);
1375                         dev_dbg(codec->dev,
1376                                 "Auto detect done (%d)\n",
1377                                 cs42l42->hs_type);
1378                 }
1379         }
1380
1381         /* Check tip sense status */
1382         if ((~masks[11]) & irq_params_table[11].mask) {
1383                 switch (current_plug_status) {
1384                 case CS42L42_TS_PLUG:
1385                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1386                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1387                                 cs42l42_init_hs_type_detect(cs42l42);
1388                         }
1389                         break;
1390
1391                 case CS42L42_TS_UNPLUG:
1392                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1393                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1394                                 cs42l42_cancel_hs_type_detect(cs42l42);
1395                                 dev_dbg(codec->dev,
1396                                         "Unplug event\n");
1397                         }
1398                         break;
1399
1400                 default:
1401                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1402                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1403                 }
1404         }
1405
1406         /* Check button detect status */
1407         if ((~masks[7]) & irq_params_table[7].mask) {
1408                 if (!(current_button_status &
1409                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1410
1411                         if (current_button_status &
1412                                 CS42L42_M_DETECT_TF_MASK) {
1413                                 dev_dbg(codec->dev,
1414                                         "Button released\n");
1415                         } else if (current_button_status &
1416                                 CS42L42_M_DETECT_FT_MASK) {
1417                                 cs42l42_handle_button_press(cs42l42);
1418                         }
1419                 }
1420         }
1421
1422         return IRQ_HANDLED;
1423 }
1424
1425 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1426 {
1427         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1428                         CS42L42_ADC_OVFL_MASK,
1429                         (1 << CS42L42_ADC_OVFL_SHIFT));
1430
1431         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1432                         CS42L42_MIX_CHB_OVFL_MASK |
1433                         CS42L42_MIX_CHA_OVFL_MASK |
1434                         CS42L42_EQ_OVFL_MASK |
1435                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1436                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1437                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1438                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1439                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1440
1441         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1442                         CS42L42_SRC_ILK_MASK |
1443                         CS42L42_SRC_OLK_MASK |
1444                         CS42L42_SRC_IUNLK_MASK |
1445                         CS42L42_SRC_OUNLK_MASK,
1446                         (1 << CS42L42_SRC_ILK_SHIFT) |
1447                         (1 << CS42L42_SRC_OLK_SHIFT) |
1448                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1449                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1450
1451         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1452                         CS42L42_ASPRX_NOLRCK_MASK |
1453                         CS42L42_ASPRX_EARLY_MASK |
1454                         CS42L42_ASPRX_LATE_MASK |
1455                         CS42L42_ASPRX_ERROR_MASK |
1456                         CS42L42_ASPRX_OVLD_MASK,
1457                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1458                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1459                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1460                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1461                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1462
1463         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1464                         CS42L42_ASPTX_NOLRCK_MASK |
1465                         CS42L42_ASPTX_EARLY_MASK |
1466                         CS42L42_ASPTX_LATE_MASK |
1467                         CS42L42_ASPTX_SMERROR_MASK,
1468                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1469                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1470                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1471                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1472
1473         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1474                         CS42L42_PDN_DONE_MASK |
1475                         CS42L42_HSDET_AUTO_DONE_MASK,
1476                         (1 << CS42L42_PDN_DONE_SHIFT) |
1477                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1478
1479         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1480                         CS42L42_SRCPL_ADC_LK_MASK |
1481                         CS42L42_SRCPL_DAC_LK_MASK |
1482                         CS42L42_SRCPL_ADC_UNLK_MASK |
1483                         CS42L42_SRCPL_DAC_UNLK_MASK,
1484                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1485                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1486                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1487                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1488
1489         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1490                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1491                         CS42L42_TIP_SENSE_PLUG_MASK |
1492                         CS42L42_HSBIAS_SENSE_MASK,
1493                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1494                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1495                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1496
1497         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1498                         CS42L42_M_DETECT_TF_MASK |
1499                         CS42L42_M_DETECT_FT_MASK |
1500                         CS42L42_M_HSBIAS_HIZ_MASK |
1501                         CS42L42_M_SHORT_RLS_MASK |
1502                         CS42L42_M_SHORT_DET_MASK,
1503                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1504                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1505                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1506                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1507                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1508
1509         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1510                         CS42L42_VPMON_MASK,
1511                         (1 << CS42L42_VPMON_SHIFT));
1512
1513         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1514                         CS42L42_PLL_LOCK_MASK,
1515                         (1 << CS42L42_PLL_LOCK_SHIFT));
1516
1517         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1518                         CS42L42_RS_PLUG_MASK |
1519                         CS42L42_RS_UNPLUG_MASK |
1520                         CS42L42_TS_PLUG_MASK |
1521                         CS42L42_TS_UNPLUG_MASK,
1522                         (1 << CS42L42_RS_PLUG_SHIFT) |
1523                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1524                         (0 << CS42L42_TS_PLUG_SHIFT) |
1525                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1526 }
1527
1528 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1529 {
1530         unsigned int reg;
1531
1532         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1533
1534         /* Latch analog controls to VP power domain */
1535         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1536                         CS42L42_LATCH_TO_VP_MASK |
1537                         CS42L42_EVENT_STAT_SEL_MASK |
1538                         CS42L42_HS_DET_LEVEL_MASK,
1539                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1540                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1541                         (cs42l42->bias_thresholds[0] <<
1542                         CS42L42_HS_DET_LEVEL_SHIFT));
1543
1544         /* Remove ground noise-suppression clamps */
1545         regmap_update_bits(cs42l42->regmap,
1546                         CS42L42_HS_CLAMP_DISABLE,
1547                         CS42L42_HS_CLAMP_DISABLE_MASK,
1548                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1549
1550         /* Enable the tip sense circuit */
1551         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1552                         CS42L42_TIP_SENSE_CTRL_MASK |
1553                         CS42L42_TIP_SENSE_INV_MASK |
1554                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1555                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1556                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1557                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1558
1559         /* Save the initial status of the tip sense */
1560         regmap_read(cs42l42->regmap,
1561                           CS42L42_TSRS_PLUG_STATUS,
1562                           &reg);
1563         cs42l42->plug_state = (((char) reg) &
1564                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1565                       CS42L42_TS_PLUG_SHIFT;
1566 }
1567
1568 static const unsigned int threshold_defaults[] = {
1569         CS42L42_HS_DET_LEVEL_15,
1570         CS42L42_HS_DET_LEVEL_8,
1571         CS42L42_HS_DET_LEVEL_4,
1572         CS42L42_HS_DET_LEVEL_1
1573 };
1574
1575 static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1576                                         struct cs42l42_private *cs42l42)
1577 {
1578         struct device_node *np = i2c_client->dev.of_node;
1579         unsigned int val;
1580         unsigned int thresholds[CS42L42_NUM_BIASES];
1581         int ret;
1582         int i;
1583
1584         ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1585
1586         if (!ret) {
1587                 switch (val) {
1588                 case CS42L42_TS_INV_EN:
1589                 case CS42L42_TS_INV_DIS:
1590                         cs42l42->ts_inv = val;
1591                         break;
1592                 default:
1593                         dev_err(&i2c_client->dev,
1594                                 "Wrong cirrus,ts-inv DT value %d\n",
1595                                 val);
1596                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1597                 }
1598         } else {
1599                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1600         }
1601
1602         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1603                         CS42L42_TS_INV_MASK,
1604                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1605
1606         ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1607
1608         if (!ret) {
1609                 switch (val) {
1610                 case CS42L42_TS_DBNCE_0:
1611                 case CS42L42_TS_DBNCE_125:
1612                 case CS42L42_TS_DBNCE_250:
1613                 case CS42L42_TS_DBNCE_500:
1614                 case CS42L42_TS_DBNCE_750:
1615                 case CS42L42_TS_DBNCE_1000:
1616                 case CS42L42_TS_DBNCE_1250:
1617                 case CS42L42_TS_DBNCE_1500:
1618                         cs42l42->ts_dbnc_rise = val;
1619                         break;
1620                 default:
1621                         dev_err(&i2c_client->dev,
1622                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1623                                 val);
1624                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1625                 }
1626         } else {
1627                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1628         }
1629
1630         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1631                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1632                         (cs42l42->ts_dbnc_rise <<
1633                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1634
1635         ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1636
1637         if (!ret) {
1638                 switch (val) {
1639                 case CS42L42_TS_DBNCE_0:
1640                 case CS42L42_TS_DBNCE_125:
1641                 case CS42L42_TS_DBNCE_250:
1642                 case CS42L42_TS_DBNCE_500:
1643                 case CS42L42_TS_DBNCE_750:
1644                 case CS42L42_TS_DBNCE_1000:
1645                 case CS42L42_TS_DBNCE_1250:
1646                 case CS42L42_TS_DBNCE_1500:
1647                         cs42l42->ts_dbnc_fall = val;
1648                         break;
1649                 default:
1650                         dev_err(&i2c_client->dev,
1651                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1652                                 val);
1653                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1654                 }
1655         } else {
1656                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1657         }
1658
1659         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1660                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1661                         (cs42l42->ts_dbnc_fall <<
1662                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1663
1664         ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1665
1666         if (!ret) {
1667                 if ((val >= CS42L42_BTN_DET_INIT_DBNCE_MIN) &&
1668                         (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX))
1669                         cs42l42->btn_det_init_dbnce = val;
1670                 else {
1671                         dev_err(&i2c_client->dev,
1672                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1673                                 val);
1674                         cs42l42->btn_det_init_dbnce =
1675                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1676                 }
1677         } else {
1678                 cs42l42->btn_det_init_dbnce =
1679                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1680         }
1681
1682         ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1683
1684         if (!ret) {
1685                 if ((val >= CS42L42_BTN_DET_EVENT_DBNCE_MIN) &&
1686                         (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX))
1687                         cs42l42->btn_det_event_dbnce = val;
1688                 else {
1689                         dev_err(&i2c_client->dev,
1690                         "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1691                         cs42l42->btn_det_event_dbnce =
1692                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1693                 }
1694         } else {
1695                 cs42l42->btn_det_event_dbnce =
1696                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1697         }
1698
1699         ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1700                                    (u32 *)thresholds, CS42L42_NUM_BIASES);
1701
1702         if (!ret) {
1703                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1704                         if ((thresholds[i] >= CS42L42_HS_DET_LEVEL_MIN) &&
1705                                 (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX))
1706                                 cs42l42->bias_thresholds[i] = thresholds[i];
1707                         else {
1708                                 dev_err(&i2c_client->dev,
1709                                 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1710                                         thresholds[i]);
1711                                 cs42l42->bias_thresholds[i] =
1712                                         threshold_defaults[i];
1713                         }
1714                 }
1715         } else {
1716                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1717                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1718         }
1719
1720         ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1721
1722         if (!ret) {
1723                 switch (val) {
1724                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1725                         cs42l42->hs_bias_ramp_rate = val;
1726                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1727                         break;
1728                 case CS42L42_HSBIAS_RAMP_FAST:
1729                         cs42l42->hs_bias_ramp_rate = val;
1730                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1731                         break;
1732                 case CS42L42_HSBIAS_RAMP_SLOW:
1733                         cs42l42->hs_bias_ramp_rate = val;
1734                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1735                         break;
1736                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1737                         cs42l42->hs_bias_ramp_rate = val;
1738                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1739                         break;
1740                 default:
1741                         dev_err(&i2c_client->dev,
1742                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1743                                 val);
1744                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1745                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1746                 }
1747         } else {
1748                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1749                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1750         }
1751
1752         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1753                         CS42L42_HSBIAS_RAMP_MASK,
1754                         (cs42l42->hs_bias_ramp_rate <<
1755                         CS42L42_HSBIAS_RAMP_SHIFT));
1756
1757         return 0;
1758 }
1759
1760 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1761                                        const struct i2c_device_id *id)
1762 {
1763         struct cs42l42_private *cs42l42;
1764         int ret, i;
1765         unsigned int devid = 0;
1766         unsigned int reg;
1767
1768         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1769                                GFP_KERNEL);
1770         if (!cs42l42)
1771                 return -ENOMEM;
1772
1773         i2c_set_clientdata(i2c_client, cs42l42);
1774
1775         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1776         if (IS_ERR(cs42l42->regmap)) {
1777                 ret = PTR_ERR(cs42l42->regmap);
1778                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1779                 return ret;
1780         }
1781
1782         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1783                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1784
1785         ret = devm_regulator_bulk_get(&i2c_client->dev,
1786                                       ARRAY_SIZE(cs42l42->supplies),
1787                                       cs42l42->supplies);
1788         if (ret != 0) {
1789                 dev_err(&i2c_client->dev,
1790                         "Failed to request supplies: %d\n", ret);
1791                 return ret;
1792         }
1793
1794         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1795                                     cs42l42->supplies);
1796         if (ret != 0) {
1797                 dev_err(&i2c_client->dev,
1798                         "Failed to enable supplies: %d\n", ret);
1799                 return ret;
1800         }
1801
1802         /* Reset the Device */
1803         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1804                 "reset", GPIOD_OUT_LOW);
1805         if (IS_ERR(cs42l42->reset_gpio))
1806                 return PTR_ERR(cs42l42->reset_gpio);
1807
1808         if (cs42l42->reset_gpio) {
1809                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1810                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1811         }
1812         mdelay(3);
1813
1814         /* Request IRQ */
1815         ret = devm_request_threaded_irq(&i2c_client->dev,
1816                         i2c_client->irq,
1817                         NULL, cs42l42_irq_thread,
1818                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1819                         "cs42l42", cs42l42);
1820
1821         if (ret != 0)
1822                 dev_err(&i2c_client->dev,
1823                         "Failed to request IRQ: %d\n", ret);
1824
1825         /* initialize codec */
1826         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
1827         devid = (reg & 0xFF) << 12;
1828
1829         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
1830         devid |= (reg & 0xFF) << 4;
1831
1832         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
1833         devid |= (reg & 0xF0) >> 4;
1834
1835         if (devid != CS42L42_CHIP_ID) {
1836                 ret = -ENODEV;
1837                 dev_err(&i2c_client->dev,
1838                         "CS42L42 Device ID (%X). Expected %X\n",
1839                         devid, CS42L42_CHIP_ID);
1840                 return ret;
1841         }
1842
1843         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1844         if (ret < 0) {
1845                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1846                 return ret;
1847         }
1848
1849         dev_info(&i2c_client->dev,
1850                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1851
1852         /* Power up the codec */
1853         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1854                         CS42L42_ASP_DAO_PDN_MASK |
1855                         CS42L42_ASP_DAI_PDN_MASK |
1856                         CS42L42_MIXER_PDN_MASK |
1857                         CS42L42_EQ_PDN_MASK |
1858                         CS42L42_HP_PDN_MASK |
1859                         CS42L42_ADC_PDN_MASK |
1860                         CS42L42_PDN_ALL_MASK,
1861                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1862                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1863                         (1 << CS42L42_MIXER_PDN_SHIFT) |
1864                         (1 << CS42L42_EQ_PDN_SHIFT) |
1865                         (1 << CS42L42_HP_PDN_SHIFT) |
1866                         (1 << CS42L42_ADC_PDN_SHIFT) |
1867                         (0 << CS42L42_PDN_ALL_SHIFT));
1868
1869         if (i2c_client->dev.of_node) {
1870                 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1871                 if (ret != 0)
1872                         return ret;
1873         }
1874
1875         /* Setup headset detection */
1876         cs42l42_setup_hs_type_detect(cs42l42);
1877
1878         /* Mask/Unmask Interrupts */
1879         cs42l42_set_interrupt_masks(cs42l42);
1880
1881         /* Register codec for machine driver */
1882         ret =  snd_soc_register_codec(&i2c_client->dev,
1883                         &soc_codec_dev_cs42l42, &cs42l42_dai, 1);
1884         if (ret < 0)
1885                 goto err_disable;
1886         return 0;
1887
1888 err_disable:
1889         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1890                                 cs42l42->supplies);
1891         return ret;
1892 }
1893
1894 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1895 {
1896         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1897
1898         snd_soc_unregister_codec(&i2c_client->dev);
1899
1900         /* Hold down reset */
1901         if (cs42l42->reset_gpio)
1902                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1903
1904         return 0;
1905 }
1906
1907 #ifdef CONFIG_PM
1908 static int cs42l42_runtime_suspend(struct device *dev)
1909 {
1910         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1911
1912         regcache_cache_only(cs42l42->regmap, true);
1913         regcache_mark_dirty(cs42l42->regmap);
1914
1915         /* Hold down reset */
1916         if (cs42l42->reset_gpio)
1917                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1918
1919         /* remove power */
1920         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1921                                 cs42l42->supplies);
1922
1923         return 0;
1924 }
1925
1926 static int cs42l42_runtime_resume(struct device *dev)
1927 {
1928         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1929         int ret;
1930
1931         /* Enable power */
1932         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1933                                         cs42l42->supplies);
1934         if (ret != 0) {
1935                 dev_err(dev, "Failed to enable supplies: %d\n",
1936                         ret);
1937                 return ret;
1938         }
1939
1940         if (cs42l42->reset_gpio)
1941                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1942
1943         regcache_cache_only(cs42l42->regmap, false);
1944         regcache_sync(cs42l42->regmap);
1945
1946         return 0;
1947 }
1948 #endif
1949
1950 static const struct dev_pm_ops cs42l42_runtime_pm = {
1951         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1952                            NULL)
1953 };
1954
1955 static const struct of_device_id cs42l42_of_match[] = {
1956         { .compatible = "cirrus,cs42l42", },
1957         {},
1958 };
1959 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1960
1961
1962 static const struct i2c_device_id cs42l42_id[] = {
1963         {"cs42l42", 0},
1964         {}
1965 };
1966
1967 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1968
1969 static struct i2c_driver cs42l42_i2c_driver = {
1970         .driver = {
1971                 .name = "cs42l42",
1972                 .pm = &cs42l42_runtime_pm,
1973                 .of_match_table = cs42l42_of_match,
1974                 },
1975         .id_table = cs42l42_id,
1976         .probe = cs42l42_i2c_probe,
1977         .remove = cs42l42_i2c_remove,
1978 };
1979
1980 module_i2c_driver(cs42l42_i2c_driver);
1981
1982 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1983 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1984 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1985 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1986 MODULE_LICENSE("GPL");