2 * cs35l35.c -- CS35L35 ALSA SoC audio driver
4 * Copyright 2017 Cirrus Logic, Inc.
6 * Author: Brian Austin <brian.austin@cirrus.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/version.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/gpio/consumer.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/regmap.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <linux/gpio.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
36 #include <sound/cs35l35.h>
37 #include <linux/of_irq.h>
38 #include <linux/completion.h>
43 * Some fields take zero as a valid value so use a high bit flag that won't
44 * get written to the device to mark those.
46 #define CS35L35_VALID_PDATA 0x80000000
48 static const struct reg_default cs35l35_reg[] = {
49 {CS35L35_PWRCTL1, 0x01},
50 {CS35L35_PWRCTL2, 0x11},
51 {CS35L35_PWRCTL3, 0x00},
52 {CS35L35_CLK_CTL1, 0x04},
53 {CS35L35_CLK_CTL2, 0x12},
54 {CS35L35_CLK_CTL3, 0xCF},
55 {CS35L35_SP_FMT_CTL1, 0x20},
56 {CS35L35_SP_FMT_CTL2, 0x00},
57 {CS35L35_SP_FMT_CTL3, 0x02},
58 {CS35L35_MAG_COMP_CTL, 0x00},
59 {CS35L35_AMP_INP_DRV_CTL, 0x01},
60 {CS35L35_AMP_DIG_VOL_CTL, 0x12},
61 {CS35L35_AMP_DIG_VOL, 0x00},
62 {CS35L35_ADV_DIG_VOL, 0x00},
63 {CS35L35_PROTECT_CTL, 0x06},
64 {CS35L35_AMP_GAIN_AUD_CTL, 0x13},
65 {CS35L35_AMP_GAIN_PDM_CTL, 0x00},
66 {CS35L35_AMP_GAIN_ADV_CTL, 0x00},
67 {CS35L35_GPI_CTL, 0x00},
68 {CS35L35_BST_CVTR_V_CTL, 0x00},
69 {CS35L35_BST_PEAK_I, 0x07},
70 {CS35L35_BST_RAMP_CTL, 0x85},
71 {CS35L35_BST_CONV_COEF_1, 0x24},
72 {CS35L35_BST_CONV_COEF_2, 0x24},
73 {CS35L35_BST_CONV_SLOPE_COMP, 0x4E},
74 {CS35L35_BST_CONV_SW_FREQ, 0x04},
75 {CS35L35_CLASS_H_CTL, 0x0B},
76 {CS35L35_CLASS_H_HEADRM_CTL, 0x0B},
77 {CS35L35_CLASS_H_RELEASE_RATE, 0x08},
78 {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
79 {CS35L35_CLASS_H_VP_CTL, 0xC5},
80 {CS35L35_VPBR_CTL, 0x0A},
81 {CS35L35_VPBR_VOL_CTL, 0x90},
82 {CS35L35_VPBR_TIMING_CTL, 0x6A},
83 {CS35L35_VPBR_MODE_VOL_CTL, 0x00},
84 {CS35L35_SPKR_MON_CTL, 0xC0},
85 {CS35L35_IMON_SCALE_CTL, 0x30},
86 {CS35L35_AUDIN_RXLOC_CTL, 0x00},
87 {CS35L35_ADVIN_RXLOC_CTL, 0x80},
88 {CS35L35_VMON_TXLOC_CTL, 0x00},
89 {CS35L35_IMON_TXLOC_CTL, 0x80},
90 {CS35L35_VPMON_TXLOC_CTL, 0x04},
91 {CS35L35_VBSTMON_TXLOC_CTL, 0x84},
92 {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
93 {CS35L35_ZERO_FILL_LOC_CTL, 0x00},
94 {CS35L35_AUDIN_DEPTH_CTL, 0x0F},
95 {CS35L35_SPKMON_DEPTH_CTL, 0x0F},
96 {CS35L35_SUPMON_DEPTH_CTL, 0x0F},
97 {CS35L35_ZEROFILL_DEPTH_CTL, 0x00},
98 {CS35L35_MULT_DEV_SYNCH1, 0x02},
99 {CS35L35_MULT_DEV_SYNCH2, 0x80},
100 {CS35L35_PROT_RELEASE_CTL, 0x00},
101 {CS35L35_DIAG_MODE_REG_LOCK, 0x00},
102 {CS35L35_DIAG_MODE_CTL_1, 0x40},
103 {CS35L35_DIAG_MODE_CTL_2, 0x00},
104 {CS35L35_INT_MASK_1, 0xFF},
105 {CS35L35_INT_MASK_2, 0xFF},
106 {CS35L35_INT_MASK_3, 0xFF},
107 {CS35L35_INT_MASK_4, 0xFF},
111 static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
114 case CS35L35_INT_STATUS_1:
115 case CS35L35_INT_STATUS_2:
116 case CS35L35_INT_STATUS_3:
117 case CS35L35_INT_STATUS_4:
118 case CS35L35_PLL_STATUS:
119 case CS35L35_OTP_TRIM_STATUS:
126 static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
129 case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
130 case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
131 case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
132 case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
133 case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
134 case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
135 case CS35L35_CLASS_H_STATUS:
136 case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
137 case CS35L35_VPBR_ATTEN_STATUS:
138 case CS35L35_SPKR_MON_CTL:
139 case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
140 case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
141 case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
142 case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
143 case CS35L35_OTP_TRIM_STATUS:
150 static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
153 case CS35L35_INT_STATUS_1:
154 case CS35L35_INT_STATUS_2:
155 case CS35L35_INT_STATUS_3:
156 case CS35L35_INT_STATUS_4:
157 case CS35L35_PLL_STATUS:
158 case CS35L35_OTP_TRIM_STATUS:
165 static void cs35l35_reset(struct cs35l35_private *cs35l35)
167 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
168 usleep_range(2000, 2100);
169 gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
170 usleep_range(1000, 1100);
173 static int cs35l35_wait_for_pdn(struct cs35l35_private *cs35l35)
177 if (cs35l35->pdata.ext_bst) {
178 usleep_range(5000, 5500);
182 reinit_completion(&cs35l35->pdn_done);
184 ret = wait_for_completion_timeout(&cs35l35->pdn_done,
185 msecs_to_jiffies(100));
187 dev_err(cs35l35->dev, "PDN_DONE did not complete\n");
194 static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
195 struct snd_kcontrol *kcontrol, int event)
197 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
198 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
202 case SND_SOC_DAPM_PRE_PMU:
203 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
204 CS35L35_MCLK_DIS_MASK,
205 0 << CS35L35_MCLK_DIS_SHIFT);
206 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
207 CS35L35_DISCHG_FILT_MASK,
208 0 << CS35L35_DISCHG_FILT_SHIFT);
209 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
210 CS35L35_PDN_ALL_MASK, 0);
212 case SND_SOC_DAPM_POST_PMD:
213 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
214 CS35L35_DISCHG_FILT_MASK,
215 1 << CS35L35_DISCHG_FILT_SHIFT);
216 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
217 CS35L35_PDN_ALL_MASK, 1);
219 /* Already muted, so disable volume ramp for faster shutdown */
220 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
221 CS35L35_AMP_DIGSFT_MASK, 0);
223 ret = cs35l35_wait_for_pdn(cs35l35);
225 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
226 CS35L35_MCLK_DIS_MASK,
227 1 << CS35L35_MCLK_DIS_SHIFT);
229 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
230 CS35L35_AMP_DIGSFT_MASK,
231 1 << CS35L35_AMP_DIGSFT_SHIFT);
234 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
240 static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
241 struct snd_kcontrol *kcontrol, int event)
243 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
244 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
249 case SND_SOC_DAPM_PRE_PMU:
250 if (cs35l35->pdata.bst_pdn_fet_on)
251 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
252 CS35L35_PDN_BST_MASK,
253 0 << CS35L35_PDN_BST_FETON_SHIFT);
255 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
256 CS35L35_PDN_BST_MASK,
257 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
259 case SND_SOC_DAPM_POST_PMU:
260 usleep_range(5000, 5100);
261 /* If in PDM mode we must use VP for Voltage control */
262 if (cs35l35->pdm_mode)
263 regmap_update_bits(cs35l35->regmap,
264 CS35L35_BST_CVTR_V_CTL,
265 CS35L35_BST_CTL_MASK,
266 0 << CS35L35_BST_CTL_SHIFT);
268 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
269 CS35L35_AMP_MUTE_MASK, 0);
271 for (i = 0; i < 2; i++)
272 regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
273 ®, ARRAY_SIZE(reg));
276 case SND_SOC_DAPM_PRE_PMD:
277 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
278 CS35L35_AMP_MUTE_MASK,
279 1 << CS35L35_AMP_MUTE_SHIFT);
280 if (cs35l35->pdata.bst_pdn_fet_on)
281 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
282 CS35L35_PDN_BST_MASK,
283 1 << CS35L35_PDN_BST_FETON_SHIFT);
285 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
286 CS35L35_PDN_BST_MASK,
287 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
289 case SND_SOC_DAPM_POST_PMD:
290 usleep_range(5000, 5100);
292 * If PDM mode we should switch back to pdata value
293 * for Voltage control when we go down
295 if (cs35l35->pdm_mode)
296 regmap_update_bits(cs35l35->regmap,
297 CS35L35_BST_CVTR_V_CTL,
298 CS35L35_BST_CTL_MASK,
299 cs35l35->pdata.bst_vctl
300 << CS35L35_BST_CTL_SHIFT);
304 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
309 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
310 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
312 static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
313 SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
314 0, 0x34, 0xE4, dig_vol_tlv),
315 SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
317 SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
321 static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
322 SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
323 0, 0x34, 0xE4, dig_vol_tlv),
324 SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
328 static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
329 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
330 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
331 SND_SOC_DAPM_POST_PMD),
332 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
334 SND_SOC_DAPM_OUTPUT("SPK"),
336 SND_SOC_DAPM_INPUT("VP"),
337 SND_SOC_DAPM_INPUT("VBST"),
338 SND_SOC_DAPM_INPUT("ISENSE"),
339 SND_SOC_DAPM_INPUT("VSENSE"),
341 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
342 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
343 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
344 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
345 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
347 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
348 cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
349 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
350 SND_SOC_DAPM_PRE_PMD),
353 static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
354 {"VPMON ADC", NULL, "VP"},
355 {"VBSTMON ADC", NULL, "VBST"},
356 {"IMON ADC", NULL, "ISENSE"},
357 {"VMON ADC", NULL, "VSENSE"},
358 {"SDOUT", NULL, "IMON ADC"},
359 {"SDOUT", NULL, "VMON ADC"},
360 {"SDOUT", NULL, "VBSTMON ADC"},
361 {"SDOUT", NULL, "VPMON ADC"},
362 {"AMP Capture", NULL, "SDOUT"},
364 {"SDIN", NULL, "AMP Playback"},
365 {"CLASS H", NULL, "SDIN"},
366 {"Main AMP", NULL, "CLASS H"},
367 {"SPK", NULL, "Main AMP"},
370 static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
372 struct snd_soc_codec *codec = codec_dai->codec;
373 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
376 case SND_SOC_DAIFMT_CBM_CFM:
377 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
378 CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
379 cs35l35->slave_mode = false;
381 case SND_SOC_DAIFMT_CBS_CFS:
382 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
383 CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
384 cs35l35->slave_mode = true;
390 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
391 case SND_SOC_DAIFMT_I2S:
392 cs35l35->i2s_mode = true;
393 cs35l35->pdm_mode = false;
395 case SND_SOC_DAIFMT_PDM:
396 cs35l35->pdm_mode = true;
397 cs35l35->i2s_mode = false;
406 struct cs35l35_sysclk_config {
412 static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
414 /* SYSCLK, Sample Rate, Serial Port Cfg */
415 {5644800, 44100, 0x00},
416 {5644800, 88200, 0x40},
417 {6144000, 48000, 0x10},
418 {6144000, 96000, 0x50},
419 {11289600, 44100, 0x01},
420 {11289600, 88200, 0x41},
421 {11289600, 176400, 0x81},
422 {12000000, 44100, 0x03},
423 {12000000, 48000, 0x13},
424 {12000000, 88200, 0x43},
425 {12000000, 96000, 0x53},
426 {12000000, 176400, 0x83},
427 {12000000, 192000, 0x93},
428 {12288000, 48000, 0x11},
429 {12288000, 96000, 0x51},
430 {12288000, 192000, 0x91},
431 {13000000, 44100, 0x07},
432 {13000000, 48000, 0x17},
433 {13000000, 88200, 0x47},
434 {13000000, 96000, 0x57},
435 {13000000, 176400, 0x87},
436 {13000000, 192000, 0x97},
437 {22579200, 44100, 0x02},
438 {22579200, 88200, 0x42},
439 {22579200, 176400, 0x82},
440 {24000000, 44100, 0x0B},
441 {24000000, 48000, 0x1B},
442 {24000000, 88200, 0x4B},
443 {24000000, 96000, 0x5B},
444 {24000000, 176400, 0x8B},
445 {24000000, 192000, 0x9B},
446 {24576000, 48000, 0x12},
447 {24576000, 96000, 0x52},
448 {24576000, 192000, 0x92},
449 {26000000, 44100, 0x0F},
450 {26000000, 48000, 0x1F},
451 {26000000, 88200, 0x4F},
452 {26000000, 96000, 0x5F},
453 {26000000, 176400, 0x8F},
454 {26000000, 192000, 0x9F},
457 static int cs35l35_get_clk_config(int sysclk, int srate)
461 for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
462 if (cs35l35_clk_ctl[i].sysclk == sysclk &&
463 cs35l35_clk_ctl[i].srate == srate)
464 return cs35l35_clk_ctl[i].clk_cfg;
469 static int cs35l35_hw_params(struct snd_pcm_substream *substream,
470 struct snd_pcm_hw_params *params,
471 struct snd_soc_dai *dai)
473 struct snd_soc_codec *codec = dai->codec;
474 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
475 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
476 int srate = params_rate(params);
482 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
485 dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
486 cs35l35->sysclk, srate);
490 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
491 CS35L35_CLK_CTL2_MASK, clk_ctl);
493 dev_err(codec->dev, "Failed to set port config %d\n", ret);
499 * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
500 * the Class H algorithm does not enable weak-drive operation for
501 * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
503 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
505 if (classh->classh_wk_fet_disable == 0x00 &&
506 (errata_chk == 0x01 || errata_chk == 0x03)) {
507 ret = regmap_update_bits(cs35l35->regmap,
508 CS35L35_CLASS_H_FET_DRIVE_CTL,
509 CS35L35_CH_WKFET_DEL_MASK,
510 0 << CS35L35_CH_WKFET_DEL_SHIFT);
512 dev_err(codec->dev, "Failed to set fet config %d\n",
519 * You can pull more Monitor data from the SDOUT pin than going to SDIN
520 * Just make sure your SCLK is fast enough to fill the frame
522 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
523 switch (params_width(params)) {
525 audin_format = CS35L35_SDIN_DEPTH_8;
528 audin_format = CS35L35_SDIN_DEPTH_16;
531 audin_format = CS35L35_SDIN_DEPTH_24;
534 dev_err(codec->dev, "Unsupported Width %d\n",
535 params_width(params));
538 regmap_update_bits(cs35l35->regmap,
539 CS35L35_AUDIN_DEPTH_CTL,
540 CS35L35_AUDIN_DEPTH_MASK,
542 CS35L35_AUDIN_DEPTH_SHIFT);
543 if (cs35l35->pdata.stereo) {
544 regmap_update_bits(cs35l35->regmap,
545 CS35L35_AUDIN_DEPTH_CTL,
546 CS35L35_ADVIN_DEPTH_MASK,
548 CS35L35_ADVIN_DEPTH_SHIFT);
552 if (cs35l35->i2s_mode) {
553 /* We have to take the SCLK to derive num sclks
554 * to configure the CLOCK_CTL3 register correctly
556 if ((cs35l35->sclk / srate) % 4) {
557 dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n",
558 cs35l35->sclk, srate);
561 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
563 /* Only certain ratios are supported in I2S Slave Mode */
564 if (cs35l35->slave_mode) {
566 case CS35L35_SP_SCLKS_32FS:
567 case CS35L35_SP_SCLKS_48FS:
568 case CS35L35_SP_SCLKS_64FS:
571 dev_err(codec->dev, "ratio not supported\n");
575 /* Only certain ratios supported in I2S MASTER Mode */
577 case CS35L35_SP_SCLKS_32FS:
578 case CS35L35_SP_SCLKS_64FS:
581 dev_err(codec->dev, "ratio not supported\n");
585 ret = regmap_update_bits(cs35l35->regmap,
587 CS35L35_SP_SCLKS_MASK, sp_sclks <<
588 CS35L35_SP_SCLKS_SHIFT);
590 dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
598 static const unsigned int cs35l35_src_rates[] = {
599 44100, 48000, 88200, 96000, 176400, 192000
602 static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
603 .count = ARRAY_SIZE(cs35l35_src_rates),
604 .list = cs35l35_src_rates,
607 static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
608 struct snd_soc_dai *dai)
610 struct snd_soc_codec *codec = dai->codec;
611 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
613 if (!substream->runtime)
616 snd_pcm_hw_constraint_list(substream->runtime, 0,
617 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
619 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
620 CS35L35_PDM_MODE_MASK,
621 0 << CS35L35_PDM_MODE_SHIFT);
626 static const unsigned int cs35l35_pdm_rates[] = {
627 44100, 48000, 88200, 96000
630 static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
631 .count = ARRAY_SIZE(cs35l35_pdm_rates),
632 .list = cs35l35_pdm_rates,
635 static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
636 struct snd_soc_dai *dai)
638 struct snd_soc_codec *codec = dai->codec;
639 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
641 if (!substream->runtime)
644 snd_pcm_hw_constraint_list(substream->runtime, 0,
645 SNDRV_PCM_HW_PARAM_RATE,
646 &cs35l35_pdm_constraints);
648 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
649 CS35L35_PDM_MODE_MASK,
650 1 << CS35L35_PDM_MODE_SHIFT);
655 static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
656 int clk_id, unsigned int freq, int dir)
658 struct snd_soc_codec *codec = dai->codec;
659 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
661 /* Need the SCLK Frequency regardless of sysclk source for I2S */
662 cs35l35->sclk = freq;
667 static const struct snd_soc_dai_ops cs35l35_ops = {
668 .startup = cs35l35_pcm_startup,
669 .set_fmt = cs35l35_set_dai_fmt,
670 .hw_params = cs35l35_hw_params,
671 .set_sysclk = cs35l35_dai_set_sysclk,
674 static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
675 .startup = cs35l35_pdm_startup,
676 .set_fmt = cs35l35_set_dai_fmt,
677 .hw_params = cs35l35_hw_params,
680 static struct snd_soc_dai_driver cs35l35_dai[] = {
682 .name = "cs35l35-pcm",
685 .stream_name = "AMP Playback",
688 .rates = SNDRV_PCM_RATE_KNOT,
689 .formats = CS35L35_FORMATS,
692 .stream_name = "AMP Capture",
695 .rates = SNDRV_PCM_RATE_KNOT,
696 .formats = CS35L35_FORMATS,
699 .symmetric_rates = 1,
702 .name = "cs35l35-pdm",
705 .stream_name = "PDM Playback",
708 .rates = SNDRV_PCM_RATE_KNOT,
709 .formats = CS35L35_FORMATS,
711 .ops = &cs35l35_pdm_ops,
715 static int cs35l35_codec_set_sysclk(struct snd_soc_codec *codec,
716 int clk_id, int source, unsigned int freq,
719 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
725 clksrc = CS35L35_CLK_SOURCE_MCLK;
728 clksrc = CS35L35_CLK_SOURCE_SCLK;
731 clksrc = CS35L35_CLK_SOURCE_PDM;
734 dev_err(codec->dev, "Invalid CLK Source\n");
749 cs35l35->sysclk = freq;
752 dev_err(codec->dev, "Invalid CLK Frequency Input : %d\n", freq);
756 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
757 CS35L35_CLK_SOURCE_MASK,
758 clksrc << CS35L35_CLK_SOURCE_SHIFT);
760 dev_err(codec->dev, "Failed to set sysclk %d\n", ret);
767 static int cs35l35_codec_probe(struct snd_soc_codec *codec)
769 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
770 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
771 struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
774 /* Set Platform Data */
775 if (cs35l35->pdata.bst_vctl)
776 regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
777 CS35L35_BST_CTL_MASK,
778 cs35l35->pdata.bst_vctl);
780 if (cs35l35->pdata.bst_ipk)
781 regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
782 CS35L35_BST_IPK_MASK,
783 cs35l35->pdata.bst_ipk <<
784 CS35L35_BST_IPK_SHIFT);
786 if (cs35l35->pdata.gain_zc)
787 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
788 CS35L35_AMP_GAIN_ZC_MASK,
789 cs35l35->pdata.gain_zc <<
790 CS35L35_AMP_GAIN_ZC_SHIFT);
792 if (cs35l35->pdata.aud_channel)
793 regmap_update_bits(cs35l35->regmap,
794 CS35L35_AUDIN_RXLOC_CTL,
795 CS35L35_AUD_IN_LR_MASK,
796 cs35l35->pdata.aud_channel <<
797 CS35L35_AUD_IN_LR_SHIFT);
799 if (cs35l35->pdata.stereo) {
800 regmap_update_bits(cs35l35->regmap,
801 CS35L35_ADVIN_RXLOC_CTL,
802 CS35L35_ADV_IN_LR_MASK,
803 cs35l35->pdata.adv_channel <<
804 CS35L35_ADV_IN_LR_SHIFT);
805 if (cs35l35->pdata.shared_bst)
806 regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
807 CS35L35_CH_STEREO_MASK,
808 1 << CS35L35_CH_STEREO_SHIFT);
809 ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
810 ARRAY_SIZE(cs35l35_adv_controls));
815 if (cs35l35->pdata.sp_drv_str)
816 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
818 cs35l35->pdata.sp_drv_str <<
819 CS35L35_SP_DRV_SHIFT);
820 if (cs35l35->pdata.sp_drv_unused)
821 regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
822 CS35L35_SP_I2S_DRV_MASK,
823 cs35l35->pdata.sp_drv_unused <<
824 CS35L35_SP_I2S_DRV_SHIFT);
826 if (classh->classh_algo_enable) {
827 if (classh->classh_bst_override)
828 regmap_update_bits(cs35l35->regmap,
830 CS35L35_CH_BST_OVR_MASK,
831 classh->classh_bst_override <<
832 CS35L35_CH_BST_OVR_SHIFT);
833 if (classh->classh_bst_max_limit)
834 regmap_update_bits(cs35l35->regmap,
836 CS35L35_CH_BST_LIM_MASK,
837 classh->classh_bst_max_limit <<
838 CS35L35_CH_BST_LIM_SHIFT);
839 if (classh->classh_mem_depth)
840 regmap_update_bits(cs35l35->regmap,
842 CS35L35_CH_MEM_DEPTH_MASK,
843 classh->classh_mem_depth <<
844 CS35L35_CH_MEM_DEPTH_SHIFT);
845 if (classh->classh_headroom)
846 regmap_update_bits(cs35l35->regmap,
847 CS35L35_CLASS_H_HEADRM_CTL,
848 CS35L35_CH_HDRM_CTL_MASK,
849 classh->classh_headroom <<
850 CS35L35_CH_HDRM_CTL_SHIFT);
851 if (classh->classh_release_rate)
852 regmap_update_bits(cs35l35->regmap,
853 CS35L35_CLASS_H_RELEASE_RATE,
854 CS35L35_CH_REL_RATE_MASK,
855 classh->classh_release_rate <<
856 CS35L35_CH_REL_RATE_SHIFT);
857 if (classh->classh_wk_fet_disable)
858 regmap_update_bits(cs35l35->regmap,
859 CS35L35_CLASS_H_FET_DRIVE_CTL,
860 CS35L35_CH_WKFET_DIS_MASK,
861 classh->classh_wk_fet_disable <<
862 CS35L35_CH_WKFET_DIS_SHIFT);
863 if (classh->classh_wk_fet_delay)
864 regmap_update_bits(cs35l35->regmap,
865 CS35L35_CLASS_H_FET_DRIVE_CTL,
866 CS35L35_CH_WKFET_DEL_MASK,
867 classh->classh_wk_fet_delay <<
868 CS35L35_CH_WKFET_DEL_SHIFT);
869 if (classh->classh_wk_fet_thld)
870 regmap_update_bits(cs35l35->regmap,
871 CS35L35_CLASS_H_FET_DRIVE_CTL,
872 CS35L35_CH_WKFET_THLD_MASK,
873 classh->classh_wk_fet_thld <<
874 CS35L35_CH_WKFET_THLD_SHIFT);
875 if (classh->classh_vpch_auto)
876 regmap_update_bits(cs35l35->regmap,
877 CS35L35_CLASS_H_VP_CTL,
878 CS35L35_CH_VP_AUTO_MASK,
879 classh->classh_vpch_auto <<
880 CS35L35_CH_VP_AUTO_SHIFT);
881 if (classh->classh_vpch_rate)
882 regmap_update_bits(cs35l35->regmap,
883 CS35L35_CLASS_H_VP_CTL,
884 CS35L35_CH_VP_RATE_MASK,
885 classh->classh_vpch_rate <<
886 CS35L35_CH_VP_RATE_SHIFT);
887 if (classh->classh_vpch_man)
888 regmap_update_bits(cs35l35->regmap,
889 CS35L35_CLASS_H_VP_CTL,
890 CS35L35_CH_VP_MAN_MASK,
891 classh->classh_vpch_man <<
892 CS35L35_CH_VP_MAN_SHIFT);
895 if (monitor_config->is_present) {
896 if (monitor_config->vmon_specs) {
897 regmap_update_bits(cs35l35->regmap,
898 CS35L35_SPKMON_DEPTH_CTL,
899 CS35L35_VMON_DEPTH_MASK,
900 monitor_config->vmon_dpth <<
901 CS35L35_VMON_DEPTH_SHIFT);
902 regmap_update_bits(cs35l35->regmap,
903 CS35L35_VMON_TXLOC_CTL,
904 CS35L35_MON_TXLOC_MASK,
905 monitor_config->vmon_loc <<
906 CS35L35_MON_TXLOC_SHIFT);
907 regmap_update_bits(cs35l35->regmap,
908 CS35L35_VMON_TXLOC_CTL,
909 CS35L35_MON_FRM_MASK,
910 monitor_config->vmon_frm <<
911 CS35L35_MON_FRM_SHIFT);
913 if (monitor_config->imon_specs) {
914 regmap_update_bits(cs35l35->regmap,
915 CS35L35_SPKMON_DEPTH_CTL,
916 CS35L35_IMON_DEPTH_MASK,
917 monitor_config->imon_dpth <<
918 CS35L35_IMON_DEPTH_SHIFT);
919 regmap_update_bits(cs35l35->regmap,
920 CS35L35_IMON_TXLOC_CTL,
921 CS35L35_MON_TXLOC_MASK,
922 monitor_config->imon_loc <<
923 CS35L35_MON_TXLOC_SHIFT);
924 regmap_update_bits(cs35l35->regmap,
925 CS35L35_IMON_TXLOC_CTL,
926 CS35L35_MON_FRM_MASK,
927 monitor_config->imon_frm <<
928 CS35L35_MON_FRM_SHIFT);
929 regmap_update_bits(cs35l35->regmap,
930 CS35L35_IMON_SCALE_CTL,
931 CS35L35_IMON_SCALE_MASK,
932 monitor_config->imon_scale <<
933 CS35L35_IMON_SCALE_SHIFT);
935 if (monitor_config->vpmon_specs) {
936 regmap_update_bits(cs35l35->regmap,
937 CS35L35_SUPMON_DEPTH_CTL,
938 CS35L35_VPMON_DEPTH_MASK,
939 monitor_config->vpmon_dpth <<
940 CS35L35_VPMON_DEPTH_SHIFT);
941 regmap_update_bits(cs35l35->regmap,
942 CS35L35_VPMON_TXLOC_CTL,
943 CS35L35_MON_TXLOC_MASK,
944 monitor_config->vpmon_loc <<
945 CS35L35_MON_TXLOC_SHIFT);
946 regmap_update_bits(cs35l35->regmap,
947 CS35L35_VPMON_TXLOC_CTL,
948 CS35L35_MON_FRM_MASK,
949 monitor_config->vpmon_frm <<
950 CS35L35_MON_FRM_SHIFT);
952 if (monitor_config->vbstmon_specs) {
953 regmap_update_bits(cs35l35->regmap,
954 CS35L35_SUPMON_DEPTH_CTL,
955 CS35L35_VBSTMON_DEPTH_MASK,
956 monitor_config->vpmon_dpth <<
957 CS35L35_VBSTMON_DEPTH_SHIFT);
958 regmap_update_bits(cs35l35->regmap,
959 CS35L35_VBSTMON_TXLOC_CTL,
960 CS35L35_MON_TXLOC_MASK,
961 monitor_config->vbstmon_loc <<
962 CS35L35_MON_TXLOC_SHIFT);
963 regmap_update_bits(cs35l35->regmap,
964 CS35L35_VBSTMON_TXLOC_CTL,
965 CS35L35_MON_FRM_MASK,
966 monitor_config->vbstmon_frm <<
967 CS35L35_MON_FRM_SHIFT);
969 if (monitor_config->vpbrstat_specs) {
970 regmap_update_bits(cs35l35->regmap,
971 CS35L35_SUPMON_DEPTH_CTL,
972 CS35L35_VPBRSTAT_DEPTH_MASK,
973 monitor_config->vpbrstat_dpth <<
974 CS35L35_VPBRSTAT_DEPTH_SHIFT);
975 regmap_update_bits(cs35l35->regmap,
976 CS35L35_VPBR_STATUS_TXLOC_CTL,
977 CS35L35_MON_TXLOC_MASK,
978 monitor_config->vpbrstat_loc <<
979 CS35L35_MON_TXLOC_SHIFT);
980 regmap_update_bits(cs35l35->regmap,
981 CS35L35_VPBR_STATUS_TXLOC_CTL,
982 CS35L35_MON_FRM_MASK,
983 monitor_config->vpbrstat_frm <<
984 CS35L35_MON_FRM_SHIFT);
986 if (monitor_config->zerofill_specs) {
987 regmap_update_bits(cs35l35->regmap,
988 CS35L35_SUPMON_DEPTH_CTL,
989 CS35L35_ZEROFILL_DEPTH_MASK,
990 monitor_config->zerofill_dpth <<
991 CS35L35_ZEROFILL_DEPTH_SHIFT);
992 regmap_update_bits(cs35l35->regmap,
993 CS35L35_ZERO_FILL_LOC_CTL,
994 CS35L35_MON_TXLOC_MASK,
995 monitor_config->zerofill_loc <<
996 CS35L35_MON_TXLOC_SHIFT);
997 regmap_update_bits(cs35l35->regmap,
998 CS35L35_ZERO_FILL_LOC_CTL,
999 CS35L35_MON_FRM_MASK,
1000 monitor_config->zerofill_frm <<
1001 CS35L35_MON_FRM_SHIFT);
1008 static struct snd_soc_codec_driver soc_codec_dev_cs35l35 = {
1009 .probe = cs35l35_codec_probe,
1010 .set_sysclk = cs35l35_codec_set_sysclk,
1011 .component_driver = {
1012 .dapm_widgets = cs35l35_dapm_widgets,
1013 .num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets),
1015 .dapm_routes = cs35l35_audio_map,
1016 .num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map),
1018 .controls = cs35l35_aud_controls,
1019 .num_controls = ARRAY_SIZE(cs35l35_aud_controls),
1024 static struct regmap_config cs35l35_regmap = {
1028 .max_register = CS35L35_MAX_REGISTER,
1029 .reg_defaults = cs35l35_reg,
1030 .num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
1031 .volatile_reg = cs35l35_volatile_register,
1032 .readable_reg = cs35l35_readable_register,
1033 .precious_reg = cs35l35_precious_register,
1034 .cache_type = REGCACHE_RBTREE,
1037 static irqreturn_t cs35l35_irq(int irq, void *data)
1039 struct cs35l35_private *cs35l35 = data;
1040 unsigned int sticky1, sticky2, sticky3, sticky4;
1041 unsigned int mask1, mask2, mask3, mask4, current1;
1043 /* ack the irq by reading all status registers */
1044 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
1045 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
1046 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
1047 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
1049 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
1050 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
1051 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
1052 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
1054 /* Check to see if unmasked bits are active */
1055 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
1056 && !(sticky4 & ~mask4))
1059 if (sticky2 & CS35L35_PDN_DONE)
1060 complete(&cs35l35->pdn_done);
1062 /* read the current values */
1063 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, ¤t1);
1065 /* handle the interrupts */
1066 if (sticky1 & CS35L35_CAL_ERR) {
1067 dev_crit(cs35l35->dev, "Calibration Error\n");
1069 /* error is no longer asserted; safe to reset */
1070 if (!(current1 & CS35L35_CAL_ERR)) {
1071 pr_debug("%s : Cal error release\n", __func__);
1072 regmap_update_bits(cs35l35->regmap,
1073 CS35L35_PROT_RELEASE_CTL,
1074 CS35L35_CAL_ERR_RLS, 0);
1075 regmap_update_bits(cs35l35->regmap,
1076 CS35L35_PROT_RELEASE_CTL,
1077 CS35L35_CAL_ERR_RLS,
1078 CS35L35_CAL_ERR_RLS);
1079 regmap_update_bits(cs35l35->regmap,
1080 CS35L35_PROT_RELEASE_CTL,
1081 CS35L35_CAL_ERR_RLS, 0);
1085 if (sticky1 & CS35L35_AMP_SHORT) {
1086 dev_crit(cs35l35->dev, "AMP Short Error\n");
1087 /* error is no longer asserted; safe to reset */
1088 if (!(current1 & CS35L35_AMP_SHORT)) {
1089 dev_dbg(cs35l35->dev, "Amp short error release\n");
1090 regmap_update_bits(cs35l35->regmap,
1091 CS35L35_PROT_RELEASE_CTL,
1092 CS35L35_SHORT_RLS, 0);
1093 regmap_update_bits(cs35l35->regmap,
1094 CS35L35_PROT_RELEASE_CTL,
1097 regmap_update_bits(cs35l35->regmap,
1098 CS35L35_PROT_RELEASE_CTL,
1099 CS35L35_SHORT_RLS, 0);
1103 if (sticky1 & CS35L35_OTW) {
1104 dev_warn(cs35l35->dev, "Over temperature warning\n");
1106 /* error is no longer asserted; safe to reset */
1107 if (!(current1 & CS35L35_OTW)) {
1108 dev_dbg(cs35l35->dev, "Over temperature warn release\n");
1109 regmap_update_bits(cs35l35->regmap,
1110 CS35L35_PROT_RELEASE_CTL,
1111 CS35L35_OTW_RLS, 0);
1112 regmap_update_bits(cs35l35->regmap,
1113 CS35L35_PROT_RELEASE_CTL,
1116 regmap_update_bits(cs35l35->regmap,
1117 CS35L35_PROT_RELEASE_CTL,
1118 CS35L35_OTW_RLS, 0);
1122 if (sticky1 & CS35L35_OTE) {
1123 dev_crit(cs35l35->dev, "Over temperature error\n");
1124 /* error is no longer asserted; safe to reset */
1125 if (!(current1 & CS35L35_OTE)) {
1126 dev_dbg(cs35l35->dev, "Over temperature error release\n");
1127 regmap_update_bits(cs35l35->regmap,
1128 CS35L35_PROT_RELEASE_CTL,
1129 CS35L35_OTE_RLS, 0);
1130 regmap_update_bits(cs35l35->regmap,
1131 CS35L35_PROT_RELEASE_CTL,
1134 regmap_update_bits(cs35l35->regmap,
1135 CS35L35_PROT_RELEASE_CTL,
1136 CS35L35_OTE_RLS, 0);
1140 if (sticky3 & CS35L35_BST_HIGH) {
1141 dev_crit(cs35l35->dev, "VBST error: powering off!\n");
1142 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1143 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1144 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1145 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1148 if (sticky3 & CS35L35_LBST_SHORT) {
1149 dev_crit(cs35l35->dev, "LBST error: powering off!\n");
1150 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1151 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1152 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1153 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1156 if (sticky2 & CS35L35_VPBR_ERR)
1157 dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n");
1159 if (sticky4 & CS35L35_VMON_OVFL)
1160 dev_dbg(cs35l35->dev, "Error: VMON overflow\n");
1162 if (sticky4 & CS35L35_IMON_OVFL)
1163 dev_dbg(cs35l35->dev, "Error: IMON overflow\n");
1169 static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
1170 struct cs35l35_platform_data *pdata)
1172 struct device_node *np = i2c_client->dev.of_node;
1173 struct device_node *classh, *signal_format;
1174 struct classh_cfg *classh_config = &pdata->classh_algo;
1175 struct monitor_cfg *monitor_config = &pdata->mon_cfg;
1176 unsigned int val32 = 0;
1177 u8 monitor_array[4];
1178 const int imon_array_size = ARRAY_SIZE(monitor_array);
1179 const int mon_array_size = imon_array_size - 1;
1185 pdata->bst_pdn_fet_on = of_property_read_bool(np,
1186 "cirrus,boost-pdn-fet-on");
1188 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
1190 if (val32 < 2600 || val32 > 9000) {
1191 dev_err(&i2c_client->dev,
1192 "Invalid Boost Voltage %d mV\n", val32);
1195 pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
1198 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
1200 if (val32 < 1680 || val32 > 4480) {
1201 dev_err(&i2c_client->dev,
1202 "Invalid Boost Peak Current %u mA\n", val32);
1206 pdata->bst_ipk = (val32 - 1680) / 110;
1209 if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
1210 pdata->sp_drv_str = val32;
1211 if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
1212 pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
1214 pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
1216 if (pdata->stereo) {
1217 ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
1219 pdata->aud_channel = val32;
1221 ret = of_property_read_u32(np, "cirrus,advisory-channel",
1224 pdata->adv_channel = val32;
1226 pdata->shared_bst = of_property_read_bool(np,
1227 "cirrus,shared-boost");
1230 pdata->ext_bst = of_property_read_bool(np, "cirrus,external-boost");
1232 pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
1234 classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
1235 classh_config->classh_algo_enable = classh ? true : false;
1237 if (classh_config->classh_algo_enable) {
1238 classh_config->classh_bst_override =
1239 of_property_read_bool(np, "cirrus,classh-bst-overide");
1241 ret = of_property_read_u32(classh,
1242 "cirrus,classh-bst-max-limit",
1245 val32 |= CS35L35_VALID_PDATA;
1246 classh_config->classh_bst_max_limit = val32;
1249 ret = of_property_read_u32(classh,
1250 "cirrus,classh-bst-max-limit",
1253 val32 |= CS35L35_VALID_PDATA;
1254 classh_config->classh_bst_max_limit = val32;
1257 ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
1260 val32 |= CS35L35_VALID_PDATA;
1261 classh_config->classh_mem_depth = val32;
1264 ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
1267 classh_config->classh_release_rate = val32;
1269 ret = of_property_read_u32(classh, "cirrus,classh-headroom",
1272 val32 |= CS35L35_VALID_PDATA;
1273 classh_config->classh_headroom = val32;
1276 ret = of_property_read_u32(classh,
1277 "cirrus,classh-wk-fet-disable",
1280 classh_config->classh_wk_fet_disable = val32;
1282 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
1285 val32 |= CS35L35_VALID_PDATA;
1286 classh_config->classh_wk_fet_delay = val32;
1289 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
1292 classh_config->classh_wk_fet_thld = val32;
1294 ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
1297 val32 |= CS35L35_VALID_PDATA;
1298 classh_config->classh_vpch_auto = val32;
1301 ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
1304 val32 |= CS35L35_VALID_PDATA;
1305 classh_config->classh_vpch_rate = val32;
1308 ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
1311 classh_config->classh_vpch_man = val32;
1313 of_node_put(classh);
1315 /* frame depth location */
1316 signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
1317 monitor_config->is_present = signal_format ? true : false;
1318 if (monitor_config->is_present) {
1319 ret = of_property_read_u8_array(signal_format, "cirrus,imon",
1320 monitor_array, imon_array_size);
1322 monitor_config->imon_specs = true;
1323 monitor_config->imon_dpth = monitor_array[0];
1324 monitor_config->imon_loc = monitor_array[1];
1325 monitor_config->imon_frm = monitor_array[2];
1326 monitor_config->imon_scale = monitor_array[3];
1328 ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
1329 monitor_array, mon_array_size);
1331 monitor_config->vmon_specs = true;
1332 monitor_config->vmon_dpth = monitor_array[0];
1333 monitor_config->vmon_loc = monitor_array[1];
1334 monitor_config->vmon_frm = monitor_array[2];
1336 ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
1337 monitor_array, mon_array_size);
1339 monitor_config->vpmon_specs = true;
1340 monitor_config->vpmon_dpth = monitor_array[0];
1341 monitor_config->vpmon_loc = monitor_array[1];
1342 monitor_config->vpmon_frm = monitor_array[2];
1344 ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
1345 monitor_array, mon_array_size);
1347 monitor_config->vbstmon_specs = true;
1348 monitor_config->vbstmon_dpth = monitor_array[0];
1349 monitor_config->vbstmon_loc = monitor_array[1];
1350 monitor_config->vbstmon_frm = monitor_array[2];
1352 ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
1353 monitor_array, mon_array_size);
1355 monitor_config->vpbrstat_specs = true;
1356 monitor_config->vpbrstat_dpth = monitor_array[0];
1357 monitor_config->vpbrstat_loc = monitor_array[1];
1358 monitor_config->vpbrstat_frm = monitor_array[2];
1360 ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
1361 monitor_array, mon_array_size);
1363 monitor_config->zerofill_specs = true;
1364 monitor_config->zerofill_dpth = monitor_array[0];
1365 monitor_config->zerofill_loc = monitor_array[1];
1366 monitor_config->zerofill_frm = monitor_array[2];
1369 of_node_put(signal_format);
1375 static const struct reg_sequence cs35l35_errata_patch[] = {
1390 static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
1391 const struct i2c_device_id *id)
1393 struct cs35l35_private *cs35l35;
1394 struct device *dev = &i2c_client->dev;
1395 struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
1398 unsigned int devid = 0;
1401 cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
1407 i2c_set_clientdata(i2c_client, cs35l35);
1408 cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
1409 if (IS_ERR(cs35l35->regmap)) {
1410 ret = PTR_ERR(cs35l35->regmap);
1411 dev_err(dev, "regmap_init() failed: %d\n", ret);
1415 for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
1416 cs35l35->supplies[i].supply = cs35l35_supplies[i];
1418 cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
1420 ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
1423 dev_err(dev, "Failed to request core supplies: %d\n", ret);
1428 cs35l35->pdata = *pdata;
1430 pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
1434 if (i2c_client->dev.of_node) {
1435 ret = cs35l35_handle_of_data(i2c_client, pdata);
1440 cs35l35->pdata = *pdata;
1443 ret = regulator_bulk_enable(cs35l35->num_supplies,
1446 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1450 /* returning NULL can be valid if in stereo mode */
1451 cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1453 if (IS_ERR(cs35l35->reset_gpio)) {
1454 ret = PTR_ERR(cs35l35->reset_gpio);
1455 cs35l35->reset_gpio = NULL;
1456 if (ret == -EBUSY) {
1458 "Reset line busy, assuming shared reset\n");
1460 dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1465 cs35l35_reset(cs35l35);
1467 init_completion(&cs35l35->pdn_done);
1469 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
1470 IRQF_ONESHOT | IRQF_TRIGGER_LOW |
1471 IRQF_SHARED, "cs35l35", cs35l35);
1473 dev_err(dev, "Failed to request IRQ: %d\n", ret);
1476 /* initialize codec */
1477 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®);
1479 devid = (reg & 0xFF) << 12;
1480 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®);
1481 devid |= (reg & 0xFF) << 4;
1482 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®);
1483 devid |= (reg & 0xF0) >> 4;
1485 if (devid != CS35L35_CHIP_ID) {
1486 dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
1487 devid, CS35L35_CHIP_ID);
1492 ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®);
1494 dev_err(dev, "Get Revision ID failed: %d\n", ret);
1498 ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
1499 ARRAY_SIZE(cs35l35_errata_patch));
1501 dev_err(dev, "Failed to apply errata patch: %d\n", ret);
1505 dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
1508 /* Set the INT Masks for critical errors */
1509 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
1510 CS35L35_INT1_CRIT_MASK);
1511 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
1512 CS35L35_INT2_CRIT_MASK);
1513 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
1514 CS35L35_INT3_CRIT_MASK);
1515 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
1516 CS35L35_INT4_CRIT_MASK);
1518 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1519 CS35L35_PWR2_PDN_MASK,
1520 CS35L35_PWR2_PDN_MASK);
1522 if (cs35l35->pdata.bst_pdn_fet_on)
1523 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1524 CS35L35_PDN_BST_MASK,
1525 1 << CS35L35_PDN_BST_FETON_SHIFT);
1527 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1528 CS35L35_PDN_BST_MASK,
1529 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
1531 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
1532 CS35L35_PWR3_PDN_MASK,
1533 CS35L35_PWR3_PDN_MASK);
1535 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
1536 CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
1538 ret = snd_soc_register_codec(dev, &soc_codec_dev_cs35l35, cs35l35_dai,
1539 ARRAY_SIZE(cs35l35_dai));
1541 dev_err(dev, "Failed to register codec: %d\n", ret);
1548 regulator_bulk_disable(cs35l35->num_supplies,
1550 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1555 static int cs35l35_i2c_remove(struct i2c_client *client)
1557 snd_soc_unregister_codec(&client->dev);
1561 static const struct of_device_id cs35l35_of_match[] = {
1562 {.compatible = "cirrus,cs35l35"},
1565 MODULE_DEVICE_TABLE(of, cs35l35_of_match);
1567 static const struct i2c_device_id cs35l35_id[] = {
1572 MODULE_DEVICE_TABLE(i2c, cs35l35_id);
1574 static struct i2c_driver cs35l35_i2c_driver = {
1577 .of_match_table = cs35l35_of_match,
1579 .id_table = cs35l35_id,
1580 .probe = cs35l35_i2c_probe,
1581 .remove = cs35l35_i2c_remove,
1584 module_i2c_driver(cs35l35_i2c_driver);
1586 MODULE_DESCRIPTION("ASoC CS35L35 driver");
1587 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1588 MODULE_LICENSE("GPL");