sound/soc/codecs/cs35l33.c

   1 /*
   2  * cs35l33.c -- CS35L33 ALSA SoC audio driver
   3  *
   4  * Copyright 2016 Cirrus Logic, Inc.
   5  *
   6  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/slab.h>
  20 #include <linux/workqueue.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <linux/gpio.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <sound/cs35l33.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/regulator/machine.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/of_irq.h>
  39
  40 #include "cs35l33.h"
  41
  42 #define CS35L33_BOOT_DELAY      50
  43
  44 struct cs35l33_private {
  45         struct snd_soc_codec *codec;
  46         struct cs35l33_pdata pdata;
  47         struct regmap *regmap;
  48         struct gpio_desc *reset_gpio;
  49         bool amp_cal;
  50         int mclk_int;
  51         struct regulator_bulk_data core_supplies[2];
  52         int num_core_supplies;
  53         bool is_tdm_mode;
  54         bool enable_soft_ramp;
  55 };
  56
  57 static const struct reg_default cs35l33_reg[] = {
  58         {CS35L33_PWRCTL1, 0x85},
  59         {CS35L33_PWRCTL2, 0xFE},
  60         {CS35L33_CLK_CTL, 0x0C},
  61         {CS35L33_BST_PEAK_CTL, 0x90},
  62         {CS35L33_PROTECT_CTL, 0x55},
  63         {CS35L33_BST_CTL1, 0x00},
  64         {CS35L33_BST_CTL2, 0x01},
  65         {CS35L33_ADSP_CTL, 0x00},
  66         {CS35L33_ADC_CTL, 0xC8},
  67         {CS35L33_DAC_CTL, 0x14},
  68         {CS35L33_DIG_VOL_CTL, 0x00},
  69         {CS35L33_CLASSD_CTL, 0x04},
  70         {CS35L33_AMP_CTL, 0x90},
  71         {CS35L33_INT_MASK_1, 0xFF},
  72         {CS35L33_INT_MASK_2, 0xFF},
  73         {CS35L33_DIAG_LOCK, 0x00},
  74         {CS35L33_DIAG_CTRL_1, 0x40},
  75         {CS35L33_DIAG_CTRL_2, 0x00},
  76         {CS35L33_HG_MEMLDO_CTL, 0x62},
  77         {CS35L33_HG_REL_RATE, 0x03},
  78         {CS35L33_LDO_DEL, 0x12},
  79         {CS35L33_HG_HEAD, 0x0A},
  80         {CS35L33_HG_EN, 0x05},
  81         {CS35L33_TX_VMON, 0x00},
  82         {CS35L33_TX_IMON, 0x03},
  83         {CS35L33_TX_VPMON, 0x02},
  84         {CS35L33_TX_VBSTMON, 0x05},
  85         {CS35L33_TX_FLAG, 0x06},
  86         {CS35L33_TX_EN1, 0x00},
  87         {CS35L33_TX_EN2, 0x00},
  88         {CS35L33_TX_EN3, 0x00},
  89         {CS35L33_TX_EN4, 0x00},
  90         {CS35L33_RX_AUD, 0x40},
  91         {CS35L33_RX_SPLY, 0x03},
  92         {CS35L33_RX_ALIVE, 0x04},
  93         {CS35L33_BST_CTL4, 0x63},
  94 };
  95
  96 static const struct reg_sequence cs35l33_patch[] = {
  97         { 0x00,  0x99, 0 },
  98         { 0x59,  0x02, 0 },
  99         { 0x52,  0x30, 0 },
 100         { 0x39,  0x45, 0 },
 101         { 0x57,  0x30, 0 },
 102         { 0x2C,  0x68, 0 },
 103         { 0x00,  0x00, 0 },
 104 };
 105
 106 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
 107 {
 108         switch (reg) {
 109         case CS35L33_DEVID_AB:
 110         case CS35L33_DEVID_CD:
 111         case CS35L33_DEVID_E:
 112         case CS35L33_REV_ID:
 113         case CS35L33_INT_STATUS_1:
 114         case CS35L33_INT_STATUS_2:
 115         case CS35L33_HG_STATUS:
 116                 return true;
 117         default:
 118                 return false;
 119         }
 120 }
 121
 122 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
 123 {
 124         switch (reg) {
 125         /* these are read only registers */
 126         case CS35L33_DEVID_AB:
 127         case CS35L33_DEVID_CD:
 128         case CS35L33_DEVID_E:
 129         case CS35L33_REV_ID:
 130         case CS35L33_INT_STATUS_1:
 131         case CS35L33_INT_STATUS_2:
 132         case CS35L33_HG_STATUS:
 133                 return false;
 134         default:
 135                 return true;
 136         }
 137 }
 138
 139 static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
 140 {
 141         switch (reg) {
 142         case CS35L33_DEVID_AB:
 143         case CS35L33_DEVID_CD:
 144         case CS35L33_DEVID_E:
 145         case CS35L33_REV_ID:
 146         case CS35L33_PWRCTL1:
 147         case CS35L33_PWRCTL2:
 148         case CS35L33_CLK_CTL:
 149         case CS35L33_BST_PEAK_CTL:
 150         case CS35L33_PROTECT_CTL:
 151         case CS35L33_BST_CTL1:
 152         case CS35L33_BST_CTL2:
 153         case CS35L33_ADSP_CTL:
 154         case CS35L33_ADC_CTL:
 155         case CS35L33_DAC_CTL:
 156         case CS35L33_DIG_VOL_CTL:
 157         case CS35L33_CLASSD_CTL:
 158         case CS35L33_AMP_CTL:
 159         case CS35L33_INT_MASK_1:
 160         case CS35L33_INT_MASK_2:
 161         case CS35L33_INT_STATUS_1:
 162         case CS35L33_INT_STATUS_2:
 163         case CS35L33_DIAG_LOCK:
 164         case CS35L33_DIAG_CTRL_1:
 165         case CS35L33_DIAG_CTRL_2:
 166         case CS35L33_HG_MEMLDO_CTL:
 167         case CS35L33_HG_REL_RATE:
 168         case CS35L33_LDO_DEL:
 169         case CS35L33_HG_HEAD:
 170         case CS35L33_HG_EN:
 171         case CS35L33_TX_VMON:
 172         case CS35L33_TX_IMON:
 173         case CS35L33_TX_VPMON:
 174         case CS35L33_TX_VBSTMON:
 175         case CS35L33_TX_FLAG:
 176         case CS35L33_TX_EN1:
 177         case CS35L33_TX_EN2:
 178         case CS35L33_TX_EN3:
 179         case CS35L33_TX_EN4:
 180         case CS35L33_RX_AUD:
 181         case CS35L33_RX_SPLY:
 182         case CS35L33_RX_ALIVE:
 183         case CS35L33_BST_CTL4:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
 191 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
 192
 193 static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
 194
 195         SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
 196                        4, 0x09, 0, classd_ctl_tlv),
 197         SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
 198                         0, 0x34, 0xE4, dac_tlv),
 199 };
 200
 201 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
 202         struct snd_kcontrol *kcontrol, int event)
 203 {
 204         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 205         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 206
 207         switch (event) {
 208         case SND_SOC_DAPM_POST_PMU:
 209                 if (!priv->amp_cal) {
 210                         usleep_range(8000, 9000);
 211                         priv->amp_cal = true;
 212                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
 213                                     CS35L33_AMP_CAL, 0);
 214                         dev_dbg(codec->dev, "Amp calibration done\n");
 215                 }
 216                 dev_dbg(codec->dev, "Amp turned on\n");
 217                 break;
 218         case SND_SOC_DAPM_POST_PMD:
 219                 dev_dbg(codec->dev, "Amp turned off\n");
 220                 break;
 221         default:
 222                 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
 223                 break;
 224         }
 225
 226         return 0;
 227 }
 228
 229 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
 230         struct snd_kcontrol *kcontrol, int event)
 231 {
 232         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 233         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 234         unsigned int val;
 235
 236         switch (event) {
 237         case SND_SOC_DAPM_PRE_PMU:
 238                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 239                                     CS35L33_PDN_BST, 0);
 240                 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
 241                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 242                                     CS35L33_PDN_TDM, val);
 243                 dev_dbg(codec->dev, "BST turned on\n");
 244                 break;
 245         case SND_SOC_DAPM_POST_PMU:
 246                 dev_dbg(codec->dev, "SDIN turned on\n");
 247                 if (!priv->amp_cal) {
 248                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
 249                                     CS35L33_AMP_CAL, CS35L33_AMP_CAL);
 250                         dev_dbg(codec->dev, "Amp calibration started\n");
 251                         usleep_range(10000, 11000);
 252                 }
 253                 break;
 254         case SND_SOC_DAPM_POST_PMD:
 255                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 256                                     CS35L33_PDN_TDM, CS35L33_PDN_TDM);
 257                 usleep_range(4000, 4100);
 258                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 259                                     CS35L33_PDN_BST, CS35L33_PDN_BST);
 260                 dev_dbg(codec->dev, "BST and SDIN turned off\n");
 261                 break;
 262         default:
 263                 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
 264
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
 271         struct snd_kcontrol *kcontrol, int event)
 272 {
 273         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 274         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 275         unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
 276         unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
 277         unsigned int val, val2;
 278
 279         switch (event) {
 280         case SND_SOC_DAPM_PRE_PMU:
 281                 if (priv->is_tdm_mode) {
 282                         /* set sdout_3st_i2s and reset pdn_tdm */
 283                         val = CS35L33_SDOUT_3ST_I2S;
 284                         /* reset sdout_3st_tdm */
 285                         val2 = 0;
 286                 } else {
 287                         /* reset sdout_3st_i2s and set pdn_tdm */
 288                         val = CS35L33_PDN_TDM;
 289                         /* set sdout_3st_tdm */
 290                         val2 = CS35L33_SDOUT_3ST_TDM;
 291                 }
 292                 dev_dbg(codec->dev, "SDOUT turned on\n");
 293                 break;
 294         case SND_SOC_DAPM_PRE_PMD:
 295                 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
 296                 val2 = CS35L33_SDOUT_3ST_TDM;
 297                 dev_dbg(codec->dev, "SDOUT turned off\n");
 298                 break;
 299         default:
 300                 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
 301                 return 0;
 302         }
 303
 304         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 305                 mask, val);
 306         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 307                 mask2, val2);
 308
 309         return 0;
 310 }
 311
 312 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
 313
 314         SND_SOC_DAPM_OUTPUT("SPK"),
 315         SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
 316                 cs35l33_spkrdrv_event,
 317                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 318         SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
 319                 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
 320                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 321
 322         SND_SOC_DAPM_INPUT("MON"),
 323
 324         SND_SOC_DAPM_ADC("VMON", NULL,
 325                 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
 326         SND_SOC_DAPM_ADC("IMON", NULL,
 327                 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
 328         SND_SOC_DAPM_ADC("VPMON", NULL,
 329                 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
 330         SND_SOC_DAPM_ADC("VBSTMON", NULL,
 331                 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
 332
 333         SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
 334                 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
 335                 SND_SOC_DAPM_PRE_PMD),
 336 };
 337
 338 static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
 339         {"SDIN", NULL, "CS35L33 Playback"},
 340         {"SPKDRV", NULL, "SDIN"},
 341         {"SPK", NULL, "SPKDRV"},
 342
 343         {"VMON", NULL, "MON"},
 344         {"IMON", NULL, "MON"},
 345
 346         {"SDOUT", NULL, "VMON"},
 347         {"SDOUT", NULL, "IMON"},
 348         {"CS35L33 Capture", NULL, "SDOUT"},
 349 };
 350
 351 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
 352         {"SPKDRV", NULL, "VPMON"},
 353         {"VPMON", NULL, "CS35L33 Playback"},
 354 };
 355
 356 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
 357         {"SDOUT", NULL, "VPMON"},
 358         {"VPMON", NULL, "MON"},
 359         {"SDOUT", NULL, "VBSTMON"},
 360         {"VBSTMON", NULL, "MON"},
 361 };
 362
 363 static int cs35l33_set_bias_level(struct snd_soc_codec *codec,
 364                                   enum snd_soc_bias_level level)
 365 {
 366         unsigned int val;
 367         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 368
 369         switch (level) {
 370         case SND_SOC_BIAS_ON:
 371                 break;
 372         case SND_SOC_BIAS_PREPARE:
 373                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 374                                     CS35L33_PDN_ALL, 0);
 375                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 376                                     CS35L33_MCLKDIS, 0);
 377                 break;
 378         case SND_SOC_BIAS_STANDBY:
 379                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 380                                     CS35L33_PDN_ALL, CS35L33_PDN_ALL);
 381                 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
 382                 usleep_range(1000, 1100);
 383                 if (val & CS35L33_PDN_DONE)
 384                         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 385                                             CS35L33_MCLKDIS, CS35L33_MCLKDIS);
 386                 break;
 387         case SND_SOC_BIAS_OFF:
 388                 break;
 389         default:
 390                 return -EINVAL;
 391         }
 392
 393         return 0;
 394 }
 395
 396 struct cs35l33_mclk_div {
 397         int mclk;
 398         int srate;
 399         u8 adsp_rate;
 400         u8 int_fs_ratio;
 401 };
 402
 403 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
 404         /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
 405         {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
 406         {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
 407         {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
 408
 409         {6000000,  8000, 0x1, 0},
 410         {6000000, 11025, 0x2, 0},
 411         {6000000, 11029, 0x3, 0},
 412         {6000000, 12000, 0x4, 0},
 413         {6000000, 16000, 0x5, 0},
 414         {6000000, 22050, 0x6, 0},
 415         {6000000, 22059, 0x7, 0},
 416         {6000000, 24000, 0x8, 0},
 417         {6000000, 32000, 0x9, 0},
 418         {6000000, 44100, 0xA, 0},
 419         {6000000, 44118, 0xB, 0},
 420         {6000000, 48000, 0xC, 0},
 421
 422         {6144000,  8000, 0x1, CS35L33_INT_FS_RATE},
 423         {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
 424         {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
 425         {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
 426         {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
 427         {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
 428 };
 429
 430 static int cs35l33_get_mclk_coeff(int mclk, int srate)
 431 {
 432         int i;
 433
 434         for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
 435                 if (cs35l33_mclk_coeffs[i].mclk == mclk &&
 436                         cs35l33_mclk_coeffs[i].srate == srate)
 437                         return i;
 438         }
 439         return -EINVAL;
 440 }
 441
 442 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 443 {
 444         struct snd_soc_codec *codec = codec_dai->codec;
 445         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 446
 447         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 448         case SND_SOC_DAIFMT_CBM_CFM:
 449                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
 450                         CS35L33_MS_MASK, CS35L33_MS_MASK);
 451                 dev_dbg(codec->dev, "Audio port in master mode\n");
 452                 break;
 453         case SND_SOC_DAIFMT_CBS_CFS:
 454                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
 455                         CS35L33_MS_MASK, 0);
 456                 dev_dbg(codec->dev, "Audio port in slave mode\n");
 457                 break;
 458         default:
 459                 return -EINVAL;
 460         }
 461
 462         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 463         case SND_SOC_DAIFMT_DSP_A:
 464                 /*
 465                  * tdm mode in cs35l33 resembles dsp-a mode very
 466                  * closely, it is dsp-a with fsync shifted left by half bclk
 467                  */
 468                 priv->is_tdm_mode = true;
 469                 dev_dbg(codec->dev, "Audio port in TDM mode\n");
 470                 break;
 471         case SND_SOC_DAIFMT_I2S:
 472                 priv->is_tdm_mode = false;
 473                 dev_dbg(codec->dev, "Audio port in I2S mode\n");
 474                 break;
 475         default:
 476                 return -EINVAL;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
 483                                  struct snd_pcm_hw_params *params,
 484                                  struct snd_soc_dai *dai)
 485 {
 486         struct snd_soc_codec *codec = dai->codec;
 487         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 488         int sample_size = params_width(params);
 489         int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
 490
 491         if (coeff < 0)
 492                 return coeff;
 493
 494         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 495                 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
 496                 cs35l33_mclk_coeffs[coeff].int_fs_ratio
 497                 | cs35l33_mclk_coeffs[coeff].adsp_rate);
 498
 499         if (priv->is_tdm_mode) {
 500                 sample_size = (sample_size / 8) - 1;
 501                 if (sample_size > 2)
 502                         sample_size = 2;
 503                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
 504                         CS35L33_AUDIN_RX_DEPTH,
 505                         sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
 506         }
 507
 508         dev_dbg(codec->dev, "sample rate=%d, bits per sample=%d\n",
 509                 params_rate(params), params_width(params));
 510
 511         return 0;
 512 }
 513
 514 static const unsigned int cs35l33_src_rates[] = {
 515         8000, 11025, 11029, 12000, 16000, 22050,
 516         22059, 24000, 32000, 44100, 44118, 48000
 517 };
 518
 519 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
 520         .count  = ARRAY_SIZE(cs35l33_src_rates),
 521         .list   = cs35l33_src_rates,
 522 };
 523
 524 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
 525                                struct snd_soc_dai *dai)
 526 {
 527         snd_pcm_hw_constraint_list(substream->runtime, 0,
 528                                         SNDRV_PCM_HW_PARAM_RATE,
 529                                         &cs35l33_constraints);
 530         return 0;
 531 }
 532
 533 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
 534 {
 535         struct snd_soc_codec *codec = dai->codec;
 536         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 537
 538         if (tristate) {
 539                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 540                         CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
 541                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 542                         CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
 543         } else {
 544                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 545                         CS35L33_SDOUT_3ST_I2S, 0);
 546                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 547                         CS35L33_SDOUT_3ST_TDM, 0);
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 554                                 unsigned int rx_mask, int slots, int slot_width)
 555 {
 556         struct snd_soc_codec *codec = dai->codec;
 557         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 558         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 559         unsigned int reg, bit_pos, i;
 560         int slot, slot_num;
 561
 562         if (slot_width != 8)
 563                 return -EINVAL;
 564
 565         /* scan rx_mask for aud slot */
 566         slot = ffs(rx_mask) - 1;
 567         if (slot >= 0) {
 568                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
 569                         CS35L33_X_LOC, slot);
 570                 dev_dbg(codec->dev, "Audio starts from slots %d", slot);
 571         }
 572
 573         /*
 574          * scan tx_mask: vmon(2 slots); imon (2 slots);
 575          * vpmon (1 slot) vbstmon (1 slot)
 576          */
 577         slot = ffs(tx_mask) - 1;
 578         slot_num = 0;
 579
 580         for (i = 0; i < 2 ; i++) {
 581                 /* disable vpmon/vbstmon: enable later if set in tx_mask */
 582                 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
 583                         CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
 584                         | CS35L33_X_LOC);
 585         }
 586
 587         /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
 588         snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
 589                 ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
 590
 591         while (slot >= 0) {
 592                 /* configure VMON_TX_LOC */
 593                 if (slot_num == 0) {
 594                         regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
 595                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 596                         dev_dbg(codec->dev, "VMON enabled in slots %d-%d",
 597                                 slot, slot + 1);
 598                 }
 599
 600                 /* configure IMON_TX_LOC */
 601                 if (slot_num == 3) {
 602                         regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
 603                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 604                         dev_dbg(codec->dev, "IMON enabled in slots %d-%d",
 605                                 slot, slot + 1);
 606                 }
 607
 608                 /* configure VPMON_TX_LOC */
 609                 if (slot_num == 4) {
 610                         regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
 611                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 612                         snd_soc_dapm_add_routes(dapm,
 613                                 &cs35l33_vp_vbst_mon_route[0], 2);
 614                         dev_dbg(codec->dev, "VPMON enabled in slots %d", slot);
 615                 }
 616
 617                 /* configure VBSTMON_TX_LOC */
 618                 if (slot_num == 5) {
 619                         regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
 620                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 621                         snd_soc_dapm_add_routes(dapm,
 622                                 &cs35l33_vp_vbst_mon_route[2], 2);
 623                         dev_dbg(codec->dev,
 624                                 "VBSTMON enabled in slots %d", slot);
 625                 }
 626
 627                 /* Enable the relevant tx slot */
 628                 reg = CS35L33_TX_EN4 - (slot/8);
 629                 bit_pos = slot - ((slot / 8) * (8));
 630                 regmap_update_bits(priv->regmap, reg,
 631                         1 << bit_pos, 1 << bit_pos);
 632
 633                 tx_mask &= ~(1 << slot);
 634                 slot = ffs(tx_mask) - 1;
 635                 slot_num++;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int cs35l33_codec_set_sysclk(struct snd_soc_codec *codec,
 642                 int clk_id, int source, unsigned int freq, int dir)
 643 {
 644         struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
 645
 646         switch (freq) {
 647         case CS35L33_MCLK_5644:
 648         case CS35L33_MCLK_6:
 649         case CS35L33_MCLK_6144:
 650                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
 651                         CS35L33_MCLKDIV2, 0);
 652                 cs35l33->mclk_int = freq;
 653                 break;
 654         case CS35L33_MCLK_11289:
 655         case CS35L33_MCLK_12:
 656         case CS35L33_MCLK_12288:
 657                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
 658                         CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
 659                 cs35l33->mclk_int = freq/2;
 660                 break;
 661         default:
 662                 cs35l33->mclk_int = 0;
 663                 return -EINVAL;
 664         }
 665
 666         dev_dbg(codec->dev, "external mclk freq=%d, internal mclk freq=%d\n",
 667                 freq, cs35l33->mclk_int);
 668
 669         return 0;
 670 }
 671
 672 static const struct snd_soc_dai_ops cs35l33_ops = {
 673         .startup = cs35l33_pcm_startup,
 674         .set_tristate = cs35l33_set_tristate,
 675         .set_fmt = cs35l33_set_dai_fmt,
 676         .hw_params = cs35l33_pcm_hw_params,
 677         .set_tdm_slot = cs35l33_set_tdm_slot,
 678 };
 679
 680 static struct snd_soc_dai_driver cs35l33_dai = {
 681                 .name = "cs35l33-dai",
 682                 .id = 0,
 683                 .playback = {
 684                         .stream_name = "CS35L33 Playback",
 685                         .channels_min = 1,
 686                         .channels_max = 1,
 687                         .rates = CS35L33_RATES,
 688                         .formats = CS35L33_FORMATS,
 689                 },
 690                 .capture = {
 691                         .stream_name = "CS35L33 Capture",
 692                         .channels_min = 2,
 693                         .channels_max = 2,
 694                         .rates = CS35L33_RATES,
 695                         .formats = CS35L33_FORMATS,
 696                 },
 697                 .ops = &cs35l33_ops,
 698                 .symmetric_rates = 1,
 699 };
 700
 701 static int cs35l33_set_hg_data(struct snd_soc_codec *codec,
 702                                struct cs35l33_pdata *pdata)
 703 {
 704         struct cs35l33_hg *hg_config = &pdata->hg_config;
 705         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 706         struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
 707
 708         if (hg_config->enable_hg_algo) {
 709                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 710                         CS35L33_MEM_DEPTH_MASK,
 711                         hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
 712                 regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
 713                         hg_config->release_rate);
 714                 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
 715                         CS35L33_HD_RM_MASK,
 716                         hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
 717                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 718                         CS35L33_LDO_THLD_MASK,
 719                         hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
 720                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 721                         CS35L33_LDO_DISABLE_MASK,
 722                         hg_config->ldo_path_disable <<
 723                                 CS35L33_LDO_DISABLE_SHIFT);
 724                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 725                         CS35L33_LDO_ENTRY_DELAY_MASK,
 726                         hg_config->ldo_entry_delay <<
 727                                 CS35L33_LDO_ENTRY_DELAY_SHIFT);
 728                 if (hg_config->vp_hg_auto) {
 729                         regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 730                                 CS35L33_VP_HG_AUTO_MASK,
 731                                 CS35L33_VP_HG_AUTO_MASK);
 732                         snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
 733                                 ARRAY_SIZE(cs35l33_vphg_auto_route));
 734                 }
 735                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 736                         CS35L33_VP_HG_MASK,
 737                         hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
 738                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 739                         CS35L33_VP_HG_RATE_MASK,
 740                         hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
 741                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 742                         CS35L33_VP_HG_VA_MASK,
 743                         hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
 744                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 745                         CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
 746         }
 747         return 0;
 748 }
 749
 750 static int cs35l33_set_bst_ipk(struct snd_soc_codec *codec, unsigned int bst)
 751 {
 752         struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
 753         int ret = 0, steps = 0;
 754
 755         /* Boost current in uA */
 756         if (bst > 3600000 || bst < 1850000) {
 757                 dev_err(codec->dev, "Invalid boost current %d\n", bst);
 758                 ret = -EINVAL;
 759                 goto err;
 760         }
 761
 762         if (bst % 15625) {
 763                 dev_err(codec->dev, "Current not a multiple of 15625uA (%d)\n",
 764                         bst);
 765                 ret = -EINVAL;
 766                 goto err;
 767         }
 768
 769         while (bst > 1850000) {
 770                 bst -= 15625;
 771                 steps++;
 772         }
 773
 774         regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
 775                 steps+0x70);
 776
 777 err:
 778         return ret;
 779 }
 780
 781 static int cs35l33_probe(struct snd_soc_codec *codec)
 782 {
 783         struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
 784
 785         cs35l33->codec = codec;
 786         pm_runtime_get_sync(codec->dev);
 787
 788         regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
 789                 CS35L33_ALIVE_WD_DIS, 0x8);
 790         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
 791                                 CS35L33_ALIVE_WD_DIS2,
 792                                 CS35L33_ALIVE_WD_DIS2);
 793
 794         /* Set Platform Data */
 795         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
 796                 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
 797         regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
 798                 CS35L33_AMP_DRV_SEL_MASK,
 799                 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
 800
 801         if (cs35l33->pdata.boost_ipk)
 802                 cs35l33_set_bst_ipk(codec, cs35l33->pdata.boost_ipk);
 803
 804         if (cs35l33->enable_soft_ramp) {
 805                 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
 806                         CS35L33_DIGSFT, CS35L33_DIGSFT);
 807                 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
 808                         CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
 809         } else {
 810                 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
 811                         CS35L33_DIGSFT, 0);
 812         }
 813
 814         /* update IMON scaling rate if different from default of 0x8 */
 815         if (cs35l33->pdata.imon_adc_scale != 0x8)
 816                 snd_soc_update_bits(codec, CS35L33_ADC_CTL,
 817                         CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
 818
 819         cs35l33_set_hg_data(codec, &(cs35l33->pdata));
 820
 821         /*
 822          * unmask important interrupts that causes the chip to enter
 823          * speaker safe mode and hence deserves user attention
 824          */
 825         regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
 826                 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
 827                 CS35L33_M_CAL_ERR, 0);
 828
 829         pm_runtime_put_sync(codec->dev);
 830
 831         return 0;
 832 }
 833
 834 static struct snd_soc_codec_driver soc_codec_dev_cs35l33 = {
 835         .probe = cs35l33_probe,
 836
 837         .set_bias_level = cs35l33_set_bias_level,
 838         .set_sysclk = cs35l33_codec_set_sysclk,
 839
 840         .component_driver = {
 841                 .controls               = cs35l33_snd_controls,
 842                 .num_controls           = ARRAY_SIZE(cs35l33_snd_controls),
 843                 .dapm_widgets           = cs35l33_dapm_widgets,
 844                 .num_dapm_widgets       = ARRAY_SIZE(cs35l33_dapm_widgets),
 845                 .dapm_routes            = cs35l33_audio_map,
 846                 .num_dapm_routes        = ARRAY_SIZE(cs35l33_audio_map),
 847         },
 848         .idle_bias_off = true,
 849 };
 850
 851 static const struct regmap_config cs35l33_regmap = {
 852         .reg_bits = 8,
 853         .val_bits = 8,
 854
 855         .max_register = CS35L33_MAX_REGISTER,
 856         .reg_defaults = cs35l33_reg,
 857         .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
 858         .volatile_reg = cs35l33_volatile_register,
 859         .readable_reg = cs35l33_readable_register,
 860         .writeable_reg = cs35l33_writeable_register,
 861         .cache_type = REGCACHE_RBTREE,
 862         .use_single_rw = true,
 863 };
 864
 865 static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
 866 {
 867         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
 868         int ret;
 869
 870         dev_dbg(dev, "%s\n", __func__);
 871
 872         if (cs35l33->reset_gpio)
 873                 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
 874
 875         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
 876                 cs35l33->core_supplies);
 877         if (ret != 0) {
 878                 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
 879                 return ret;
 880         }
 881
 882         regcache_cache_only(cs35l33->regmap, false);
 883
 884         if (cs35l33->reset_gpio)
 885                 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
 886
 887         msleep(CS35L33_BOOT_DELAY);
 888
 889         ret = regcache_sync(cs35l33->regmap);
 890         if (ret != 0) {
 891                 dev_err(dev, "Failed to restore register cache\n");
 892                 goto err;
 893         }
 894
 895         return 0;
 896
 897 err:
 898         regcache_cache_only(cs35l33->regmap, true);
 899         regulator_bulk_disable(cs35l33->num_core_supplies,
 900                 cs35l33->core_supplies);
 901
 902         return ret;
 903 }
 904
 905 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
 906 {
 907         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
 908
 909         dev_dbg(dev, "%s\n", __func__);
 910
 911         /* redo the calibration in next power up */
 912         cs35l33->amp_cal = false;
 913
 914         regcache_cache_only(cs35l33->regmap, true);
 915         regcache_mark_dirty(cs35l33->regmap);
 916         regulator_bulk_disable(cs35l33->num_core_supplies,
 917                 cs35l33->core_supplies);
 918
 919         return 0;
 920 }
 921
 922 static const struct dev_pm_ops cs35l33_pm_ops = {
 923         SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
 924                            cs35l33_runtime_resume,
 925                            NULL)
 926 };
 927
 928 static int cs35l33_get_hg_data(const struct device_node *np,
 929                                struct cs35l33_pdata *pdata)
 930 {
 931         struct device_node *hg;
 932         struct cs35l33_hg *hg_config = &pdata->hg_config;
 933         u32 val32;
 934
 935         hg = of_get_child_by_name(np, "cirrus,hg-algo");
 936         hg_config->enable_hg_algo = hg ? true : false;
 937
 938         if (hg_config->enable_hg_algo) {
 939                 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
 940                         hg_config->mem_depth = val32;
 941                 if (of_property_read_u32(hg, "cirrus,release-rate",
 942                                 &val32) >= 0)
 943                         hg_config->release_rate = val32;
 944                 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
 945                         hg_config->ldo_thld = val32;
 946                 if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
 947                                 &val32) >= 0)
 948                         hg_config->ldo_path_disable = val32;
 949                 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
 950                                 &val32) >= 0)
 951                         hg_config->ldo_entry_delay = val32;
 952
 953                 hg_config->vp_hg_auto = of_property_read_bool(hg,
 954                         "cirrus,vp-hg-auto");
 955
 956                 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
 957                         hg_config->vp_hg = val32;
 958                 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
 959                         hg_config->vp_hg_rate = val32;
 960                 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
 961                         hg_config->vp_hg_va = val32;
 962         }
 963
 964         of_node_put(hg);
 965
 966         return 0;
 967 }
 968
 969 static irqreturn_t cs35l33_irq_thread(int irq, void *data)
 970 {
 971         struct cs35l33_private *cs35l33 = data;
 972         struct snd_soc_codec *codec = cs35l33->codec;
 973         unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
 974
 975         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
 976                 &sticky_val2);
 977         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
 978                 &sticky_val1);
 979         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
 980         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
 981
 982         /* Check to see if the unmasked bits are active,
 983          *  if not then exit.
 984          */
 985         if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
 986                 return IRQ_NONE;
 987
 988         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
 989                 &current_val);
 990
 991         /* handle the interrupts */
 992
 993         if (sticky_val1 & CS35L33_AMP_SHORT) {
 994                 dev_crit(codec->dev, "Amp short error\n");
 995                 if (!(current_val & CS35L33_AMP_SHORT)) {
 996                         dev_dbg(codec->dev,
 997                                 "Amp short error release\n");
 998                         regmap_update_bits(cs35l33->regmap,
 999                                 CS35L33_AMP_CTL,
1000                                 CS35L33_AMP_SHORT_RLS, 0);
1001                         regmap_update_bits(cs35l33->regmap,
1002                                 CS35L33_AMP_CTL,
1003                                 CS35L33_AMP_SHORT_RLS,
1004                                 CS35L33_AMP_SHORT_RLS);
1005                         regmap_update_bits(cs35l33->regmap,
1006                                 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
1007                                 0);
1008                 }
1009         }
1010
1011         if (sticky_val1 & CS35L33_CAL_ERR) {
1012                 dev_err(codec->dev, "Cal error\n");
1013
1014                 /* redo the calibration in next power up */
1015                 cs35l33->amp_cal = false;
1016
1017                 if (!(current_val & CS35L33_CAL_ERR)) {
1018                         dev_dbg(codec->dev, "Cal error release\n");
1019                         regmap_update_bits(cs35l33->regmap,
1020                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1021                                 0);
1022                         regmap_update_bits(cs35l33->regmap,
1023                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1024                                 CS35L33_CAL_ERR_RLS);
1025                         regmap_update_bits(cs35l33->regmap,
1026                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1027                                 0);
1028                 }
1029         }
1030
1031         if (sticky_val1 & CS35L33_OTE) {
1032                 dev_crit(codec->dev, "Over temperature error\n");
1033                 if (!(current_val & CS35L33_OTE)) {
1034                         dev_dbg(codec->dev,
1035                                 "Over temperature error release\n");
1036                         regmap_update_bits(cs35l33->regmap,
1037                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1038                         regmap_update_bits(cs35l33->regmap,
1039                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1040                                 CS35L33_OTE_RLS);
1041                         regmap_update_bits(cs35l33->regmap,
1042                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1043                 }
1044         }
1045
1046         if (sticky_val1 & CS35L33_OTW) {
1047                 dev_err(codec->dev, "Over temperature warning\n");
1048                 if (!(current_val & CS35L33_OTW)) {
1049                         dev_dbg(codec->dev,
1050                                 "Over temperature warning release\n");
1051                         regmap_update_bits(cs35l33->regmap,
1052                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1053                         regmap_update_bits(cs35l33->regmap,
1054                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1055                                 CS35L33_OTW_RLS);
1056                         regmap_update_bits(cs35l33->regmap,
1057                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1058                 }
1059         }
1060         if (CS35L33_ALIVE_ERR & sticky_val1)
1061                 dev_err(codec->dev, "ERROR: ADSPCLK Interrupt\n");
1062
1063         if (CS35L33_MCLK_ERR & sticky_val1)
1064                 dev_err(codec->dev, "ERROR: MCLK Interrupt\n");
1065
1066         if (CS35L33_VMON_OVFL & sticky_val2)
1067                 dev_err(codec->dev,
1068                         "ERROR: VMON Overflow Interrupt\n");
1069
1070         if (CS35L33_IMON_OVFL & sticky_val2)
1071                 dev_err(codec->dev,
1072                         "ERROR: IMON Overflow Interrupt\n");
1073
1074         if (CS35L33_VPMON_OVFL & sticky_val2)
1075                 dev_err(codec->dev,
1076                         "ERROR: VPMON Overflow Interrupt\n");
1077
1078         return IRQ_HANDLED;
1079 }
1080
1081 static const char * const cs35l33_core_supplies[] = {
1082         "VA",
1083         "VP",
1084 };
1085
1086 static int cs35l33_of_get_pdata(struct device *dev,
1087                                 struct cs35l33_private *cs35l33)
1088 {
1089         struct device_node *np = dev->of_node;
1090         struct cs35l33_pdata *pdata = &cs35l33->pdata;
1091         u32 val32;
1092
1093         if (!np)
1094                 return 0;
1095
1096         if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1097                 pdata->boost_ctl = val32;
1098                 pdata->amp_drv_sel = 1;
1099         }
1100
1101         if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1102                 pdata->ramp_rate = val32;
1103                 cs35l33->enable_soft_ramp = true;
1104         }
1105
1106         if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1107                 pdata->boost_ipk = val32;
1108
1109         if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1110                 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1111                         pdata->imon_adc_scale = val32;
1112                 else
1113                         /* use default value */
1114                         pdata->imon_adc_scale = 0x8;
1115         } else {
1116                 /* use default value */
1117                 pdata->imon_adc_scale = 0x8;
1118         }
1119
1120         cs35l33_get_hg_data(np, pdata);
1121
1122         return 0;
1123 }
1124
1125 static int cs35l33_i2c_probe(struct i2c_client *i2c_client,
1126                                        const struct i2c_device_id *id)
1127 {
1128         struct cs35l33_private *cs35l33;
1129         struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1130         int ret, devid, i;
1131         unsigned int reg;
1132
1133         cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1134                                GFP_KERNEL);
1135         if (!cs35l33)
1136                 return -ENOMEM;
1137
1138         i2c_set_clientdata(i2c_client, cs35l33);
1139         cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1140         if (IS_ERR(cs35l33->regmap)) {
1141                 ret = PTR_ERR(cs35l33->regmap);
1142                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1143                 return ret;
1144         }
1145
1146         regcache_cache_only(cs35l33->regmap, true);
1147
1148         for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1149                 cs35l33->core_supplies[i].supply
1150                         = cs35l33_core_supplies[i];
1151         cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1152
1153         ret = devm_regulator_bulk_get(&i2c_client->dev,
1154                         cs35l33->num_core_supplies,
1155                         cs35l33->core_supplies);
1156         if (ret != 0) {
1157                 dev_err(&i2c_client->dev,
1158                         "Failed to request core supplies: %d\n",
1159                         ret);
1160                 return ret;
1161         }
1162
1163         if (pdata) {
1164                 cs35l33->pdata = *pdata;
1165         } else {
1166                 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1167                 pdata = &cs35l33->pdata;
1168         }
1169
1170         ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1171                         cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1172                         "cs35l33", cs35l33);
1173         if (ret != 0)
1174                 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1175
1176         /* We could issue !RST or skip it based on AMP topology */
1177         cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1178                         "reset-gpios", GPIOD_OUT_HIGH);
1179         if (IS_ERR(cs35l33->reset_gpio)) {
1180                 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1181                         __func__);
1182                 return PTR_ERR(cs35l33->reset_gpio);
1183         }
1184
1185         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1186                                         cs35l33->core_supplies);
1187         if (ret != 0) {
1188                 dev_err(&i2c_client->dev,
1189                         "Failed to enable core supplies: %d\n",
1190                         ret);
1191                 return ret;
1192         }
1193
1194         if (cs35l33->reset_gpio)
1195                 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1196
1197         msleep(CS35L33_BOOT_DELAY);
1198         regcache_cache_only(cs35l33->regmap, false);
1199
1200         /* initialize codec */
1201         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, &reg);
1202         devid = (reg & 0xFF) << 12;
1203         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, &reg);
1204         devid |= (reg & 0xFF) << 4;
1205         ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, &reg);
1206         devid |= (reg & 0xF0) >> 4;
1207
1208         if (devid != CS35L33_CHIP_ID) {
1209                 dev_err(&i2c_client->dev,
1210                         "CS35L33 Device ID (%X). Expected ID %X\n",
1211                         devid, CS35L33_CHIP_ID);
1212                 goto err_enable;
1213         }
1214
1215         ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1216         if (ret < 0) {
1217                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1218                 goto err_enable;
1219         }
1220
1221         dev_info(&i2c_client->dev,
1222                  "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
1223
1224         ret = regmap_register_patch(cs35l33->regmap,
1225                         cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1226         if (ret < 0) {
1227                 dev_err(&i2c_client->dev,
1228                         "Error in applying regmap patch: %d\n", ret);
1229                 goto err_enable;
1230         }
1231
1232         /* disable mclk and tdm */
1233         regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1234                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1235                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1236
1237         pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1238         pm_runtime_use_autosuspend(&i2c_client->dev);
1239         pm_runtime_set_active(&i2c_client->dev);
1240         pm_runtime_enable(&i2c_client->dev);
1241
1242         ret =  snd_soc_register_codec(&i2c_client->dev,
1243                         &soc_codec_dev_cs35l33, &cs35l33_dai, 1);
1244         if (ret < 0) {
1245                 dev_err(&i2c_client->dev, "%s: Register codec failed\n",
1246                         __func__);
1247                 goto err_enable;
1248         }
1249
1250         return 0;
1251
1252 err_enable:
1253         regulator_bulk_disable(cs35l33->num_core_supplies,
1254                                cs35l33->core_supplies);
1255
1256         return ret;
1257 }
1258
1259 static int cs35l33_i2c_remove(struct i2c_client *client)
1260 {
1261         struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1262
1263         snd_soc_unregister_codec(&client->dev);
1264
1265         if (cs35l33->reset_gpio)
1266                 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1267
1268         pm_runtime_disable(&client->dev);
1269         regulator_bulk_disable(cs35l33->num_core_supplies,
1270                 cs35l33->core_supplies);
1271
1272         return 0;
1273 }
1274
1275 static const struct of_device_id cs35l33_of_match[] = {
1276         { .compatible = "cirrus,cs35l33", },
1277         {},
1278 };
1279 MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1280
1281 static const struct i2c_device_id cs35l33_id[] = {
1282         {"cs35l33", 0},
1283         {}
1284 };
1285
1286 MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1287
1288 static struct i2c_driver cs35l33_i2c_driver = {
1289         .driver = {
1290                 .name = "cs35l33",
1291                 .pm = &cs35l33_pm_ops,
1292                 .of_match_table = cs35l33_of_match,
1293
1294                 },
1295         .id_table = cs35l33_id,
1296         .probe = cs35l33_i2c_probe,
1297         .remove = cs35l33_i2c_remove,
1298
1299 };
1300 module_i2c_driver(cs35l33_i2c_driver);
1301
1302 MODULE_DESCRIPTION("ASoC CS35L33 driver");
1303 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1304 MODULE_LICENSE("GPL");