sound/soc/codecs/arizona.c

   1 /*
   2  * arizona.c - Wolfson Arizona class device shared support
   3  *
   4  * Copyright 2012 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/gcd.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/tlv.h>
  20
  21 #include <linux/mfd/arizona/core.h>
  22 #include <linux/mfd/arizona/gpio.h>
  23 #include <linux/mfd/arizona/registers.h>
  24
  25 #include "arizona.h"
  26
  27 #define ARIZONA_AIF_BCLK_CTRL                   0x00
  28 #define ARIZONA_AIF_TX_PIN_CTRL                 0x01
  29 #define ARIZONA_AIF_RX_PIN_CTRL                 0x02
  30 #define ARIZONA_AIF_RATE_CTRL                   0x03
  31 #define ARIZONA_AIF_FORMAT                      0x04
  32 #define ARIZONA_AIF_TX_BCLK_RATE                0x05
  33 #define ARIZONA_AIF_RX_BCLK_RATE                0x06
  34 #define ARIZONA_AIF_FRAME_CTRL_1                0x07
  35 #define ARIZONA_AIF_FRAME_CTRL_2                0x08
  36 #define ARIZONA_AIF_FRAME_CTRL_3                0x09
  37 #define ARIZONA_AIF_FRAME_CTRL_4                0x0A
  38 #define ARIZONA_AIF_FRAME_CTRL_5                0x0B
  39 #define ARIZONA_AIF_FRAME_CTRL_6                0x0C
  40 #define ARIZONA_AIF_FRAME_CTRL_7                0x0D
  41 #define ARIZONA_AIF_FRAME_CTRL_8                0x0E
  42 #define ARIZONA_AIF_FRAME_CTRL_9                0x0F
  43 #define ARIZONA_AIF_FRAME_CTRL_10               0x10
  44 #define ARIZONA_AIF_FRAME_CTRL_11               0x11
  45 #define ARIZONA_AIF_FRAME_CTRL_12               0x12
  46 #define ARIZONA_AIF_FRAME_CTRL_13               0x13
  47 #define ARIZONA_AIF_FRAME_CTRL_14               0x14
  48 #define ARIZONA_AIF_FRAME_CTRL_15               0x15
  49 #define ARIZONA_AIF_FRAME_CTRL_16               0x16
  50 #define ARIZONA_AIF_FRAME_CTRL_17               0x17
  51 #define ARIZONA_AIF_FRAME_CTRL_18               0x18
  52 #define ARIZONA_AIF_TX_ENABLES                  0x19
  53 #define ARIZONA_AIF_RX_ENABLES                  0x1A
  54 #define ARIZONA_AIF_FORCE_WRITE                 0x1B
  55
  56 #define ARIZONA_FLL_VCO_CORNER 141900000
  57 #define ARIZONA_FLL_MAX_FREF   13500000
  58 #define ARIZONA_FLL_MIN_FVCO   90000000
  59 #define ARIZONA_FLL_MAX_FRATIO 16
  60 #define ARIZONA_FLL_MAX_REFDIV 8
  61 #define ARIZONA_FLL_MIN_OUTDIV 2
  62 #define ARIZONA_FLL_MAX_OUTDIV 7
  63
  64 #define arizona_fll_err(_fll, fmt, ...) \
  65         dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  66 #define arizona_fll_warn(_fll, fmt, ...) \
  67         dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  68 #define arizona_fll_dbg(_fll, fmt, ...) \
  69         dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  70
  71 #define arizona_aif_err(_dai, fmt, ...) \
  72         dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  73 #define arizona_aif_warn(_dai, fmt, ...) \
  74         dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  75 #define arizona_aif_dbg(_dai, fmt, ...) \
  76         dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  77
  78 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
  79                           struct snd_kcontrol *kcontrol,
  80                           int event)
  81 {
  82         struct snd_soc_codec *codec = w->codec;
  83         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
  84         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
  85         bool manual_ena = false;
  86         int val;
  87
  88         switch (arizona->type) {
  89         case WM5102:
  90                 switch (arizona->rev) {
  91                 case 0:
  92                         break;
  93                 default:
  94                         manual_ena = true;
  95                         break;
  96                 }
  97         default:
  98                 break;
  99         }
 100
 101         switch (event) {
 102         case SND_SOC_DAPM_PRE_PMU:
 103                 if (!priv->spk_ena && manual_ena) {
 104                         regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
 105                         priv->spk_ena_pending = true;
 106                 }
 107                 break;
 108         case SND_SOC_DAPM_POST_PMU:
 109                 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
 110                 if (val & ARIZONA_SPK_SHUTDOWN_STS) {
 111                         dev_crit(arizona->dev,
 112                                  "Speaker not enabled due to temperature\n");
 113                         return -EBUSY;
 114                 }
 115
 116                 regmap_update_bits_async(arizona->regmap,
 117                                          ARIZONA_OUTPUT_ENABLES_1,
 118                                          1 << w->shift, 1 << w->shift);
 119
 120                 if (priv->spk_ena_pending) {
 121                         msleep(75);
 122                         regmap_write_async(arizona->regmap, 0x4f5, 0xda);
 123                         priv->spk_ena_pending = false;
 124                         priv->spk_ena++;
 125                 }
 126                 break;
 127         case SND_SOC_DAPM_PRE_PMD:
 128                 if (manual_ena) {
 129                         priv->spk_ena--;
 130                         if (!priv->spk_ena)
 131                                 regmap_write_async(arizona->regmap,
 132                                                    0x4f5, 0x25a);
 133                 }
 134
 135                 regmap_update_bits_async(arizona->regmap,
 136                                          ARIZONA_OUTPUT_ENABLES_1,
 137                                          1 << w->shift, 0);
 138                 break;
 139         case SND_SOC_DAPM_POST_PMD:
 140                 if (manual_ena) {
 141                         if (!priv->spk_ena)
 142                                 regmap_write_async(arizona->regmap,
 143                                                    0x4f5, 0x0da);
 144                 }
 145                 break;
 146         }
 147
 148         return 0;
 149 }
 150
 151 static irqreturn_t arizona_thermal_warn(int irq, void *data)
 152 {
 153         struct arizona *arizona = data;
 154         unsigned int val;
 155         int ret;
 156
 157         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 158                           &val);
 159         if (ret != 0) {
 160                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 161                         ret);
 162         } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) {
 163                 dev_crit(arizona->dev, "Thermal warning\n");
 164         }
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
 170 {
 171         struct arizona *arizona = data;
 172         unsigned int val;
 173         int ret;
 174
 175         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 176                           &val);
 177         if (ret != 0) {
 178                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 179                         ret);
 180         } else if (val & ARIZONA_SPK_SHUTDOWN_STS) {
 181                 dev_crit(arizona->dev, "Thermal shutdown\n");
 182                 ret = regmap_update_bits(arizona->regmap,
 183                                          ARIZONA_OUTPUT_ENABLES_1,
 184                                          ARIZONA_OUT4L_ENA |
 185                                          ARIZONA_OUT4R_ENA, 0);
 186                 if (ret != 0)
 187                         dev_crit(arizona->dev,
 188                                  "Failed to disable speaker outputs: %d\n",
 189                                  ret);
 190         }
 191
 192         return IRQ_HANDLED;
 193 }
 194
 195 static const struct snd_soc_dapm_widget arizona_spkl =
 196         SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
 197                            ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 198                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 199
 200 static const struct snd_soc_dapm_widget arizona_spkr =
 201         SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
 202                            ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 203                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 204
 205 int arizona_init_spk(struct snd_soc_codec *codec)
 206 {
 207         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 208         struct arizona *arizona = priv->arizona;
 209         int ret;
 210
 211         ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
 212         if (ret != 0)
 213                 return ret;
 214
 215         switch (arizona->type) {
 216         case WM8997:
 217                 break;
 218         default:
 219                 ret = snd_soc_dapm_new_controls(&codec->dapm,
 220                                                 &arizona_spkr, 1);
 221                 if (ret != 0)
 222                         return ret;
 223                 break;
 224         }
 225
 226         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN,
 227                                   "Thermal warning", arizona_thermal_warn,
 228                                   arizona);
 229         if (ret != 0)
 230                 dev_err(arizona->dev,
 231                         "Failed to get thermal warning IRQ: %d\n",
 232                         ret);
 233
 234         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN,
 235                                   "Thermal shutdown", arizona_thermal_shutdown,
 236                                   arizona);
 237         if (ret != 0)
 238                 dev_err(arizona->dev,
 239                         "Failed to get thermal shutdown IRQ: %d\n",
 240                         ret);
 241
 242         return 0;
 243 }
 244 EXPORT_SYMBOL_GPL(arizona_init_spk);
 245
 246 int arizona_init_gpio(struct snd_soc_codec *codec)
 247 {
 248         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 249         struct arizona *arizona = priv->arizona;
 250         int i;
 251
 252         switch (arizona->type) {
 253         case WM5110:
 254                 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
 255                 break;
 256         default:
 257                 break;
 258         }
 259
 260         snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
 261
 262         for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
 263                 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
 264                 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
 265                         snd_soc_dapm_enable_pin(&codec->dapm,
 266                                                 "DRC1 Signal Activity");
 267                         break;
 268                 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
 269                         snd_soc_dapm_enable_pin(&codec->dapm,
 270                                                 "DRC2 Signal Activity");
 271                         break;
 272                 default:
 273                         break;
 274                 }
 275         }
 276
 277         return 0;
 278 }
 279 EXPORT_SYMBOL_GPL(arizona_init_gpio);
 280
 281 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
 282         "None",
 283         "Tone Generator 1",
 284         "Tone Generator 2",
 285         "Haptics",
 286         "AEC",
 287         "Mic Mute Mixer",
 288         "Noise Generator",
 289         "IN1L",
 290         "IN1R",
 291         "IN2L",
 292         "IN2R",
 293         "IN3L",
 294         "IN3R",
 295         "IN4L",
 296         "IN4R",
 297         "AIF1RX1",
 298         "AIF1RX2",
 299         "AIF1RX3",
 300         "AIF1RX4",
 301         "AIF1RX5",
 302         "AIF1RX6",
 303         "AIF1RX7",
 304         "AIF1RX8",
 305         "AIF2RX1",
 306         "AIF2RX2",
 307         "AIF2RX3",
 308         "AIF2RX4",
 309         "AIF2RX5",
 310         "AIF2RX6",
 311         "AIF3RX1",
 312         "AIF3RX2",
 313         "SLIMRX1",
 314         "SLIMRX2",
 315         "SLIMRX3",
 316         "SLIMRX4",
 317         "SLIMRX5",
 318         "SLIMRX6",
 319         "SLIMRX7",
 320         "SLIMRX8",
 321         "EQ1",
 322         "EQ2",
 323         "EQ3",
 324         "EQ4",
 325         "DRC1L",
 326         "DRC1R",
 327         "DRC2L",
 328         "DRC2R",
 329         "LHPF1",
 330         "LHPF2",
 331         "LHPF3",
 332         "LHPF4",
 333         "DSP1.1",
 334         "DSP1.2",
 335         "DSP1.3",
 336         "DSP1.4",
 337         "DSP1.5",
 338         "DSP1.6",
 339         "DSP2.1",
 340         "DSP2.2",
 341         "DSP2.3",
 342         "DSP2.4",
 343         "DSP2.5",
 344         "DSP2.6",
 345         "DSP3.1",
 346         "DSP3.2",
 347         "DSP3.3",
 348         "DSP3.4",
 349         "DSP3.5",
 350         "DSP3.6",
 351         "DSP4.1",
 352         "DSP4.2",
 353         "DSP4.3",
 354         "DSP4.4",
 355         "DSP4.5",
 356         "DSP4.6",
 357         "ASRC1L",
 358         "ASRC1R",
 359         "ASRC2L",
 360         "ASRC2R",
 361         "ISRC1INT1",
 362         "ISRC1INT2",
 363         "ISRC1INT3",
 364         "ISRC1INT4",
 365         "ISRC1DEC1",
 366         "ISRC1DEC2",
 367         "ISRC1DEC3",
 368         "ISRC1DEC4",
 369         "ISRC2INT1",
 370         "ISRC2INT2",
 371         "ISRC2INT3",
 372         "ISRC2INT4",
 373         "ISRC2DEC1",
 374         "ISRC2DEC2",
 375         "ISRC2DEC3",
 376         "ISRC2DEC4",
 377         "ISRC3INT1",
 378         "ISRC3INT2",
 379         "ISRC3INT3",
 380         "ISRC3INT4",
 381         "ISRC3DEC1",
 382         "ISRC3DEC2",
 383         "ISRC3DEC3",
 384         "ISRC3DEC4",
 385 };
 386 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
 387
 388 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
 389         0x00,  /* None */
 390         0x04,  /* Tone */
 391         0x05,
 392         0x06,  /* Haptics */
 393         0x08,  /* AEC */
 394         0x0c,  /* Noise mixer */
 395         0x0d,  /* Comfort noise */
 396         0x10,  /* IN1L */
 397         0x11,
 398         0x12,
 399         0x13,
 400         0x14,
 401         0x15,
 402         0x16,
 403         0x17,
 404         0x20,  /* AIF1RX1 */
 405         0x21,
 406         0x22,
 407         0x23,
 408         0x24,
 409         0x25,
 410         0x26,
 411         0x27,
 412         0x28,  /* AIF2RX1 */
 413         0x29,
 414         0x2a,
 415         0x2b,
 416         0x2c,
 417         0x2d,
 418         0x30,  /* AIF3RX1 */
 419         0x31,
 420         0x38,  /* SLIMRX1 */
 421         0x39,
 422         0x3a,
 423         0x3b,
 424         0x3c,
 425         0x3d,
 426         0x3e,
 427         0x3f,
 428         0x50,  /* EQ1 */
 429         0x51,
 430         0x52,
 431         0x53,
 432         0x58,  /* DRC1L */
 433         0x59,
 434         0x5a,
 435         0x5b,
 436         0x60,  /* LHPF1 */
 437         0x61,
 438         0x62,
 439         0x63,
 440         0x68,  /* DSP1.1 */
 441         0x69,
 442         0x6a,
 443         0x6b,
 444         0x6c,
 445         0x6d,
 446         0x70,  /* DSP2.1 */
 447         0x71,
 448         0x72,
 449         0x73,
 450         0x74,
 451         0x75,
 452         0x78,  /* DSP3.1 */
 453         0x79,
 454         0x7a,
 455         0x7b,
 456         0x7c,
 457         0x7d,
 458         0x80,  /* DSP4.1 */
 459         0x81,
 460         0x82,
 461         0x83,
 462         0x84,
 463         0x85,
 464         0x90,  /* ASRC1L */
 465         0x91,
 466         0x92,
 467         0x93,
 468         0xa0,  /* ISRC1INT1 */
 469         0xa1,
 470         0xa2,
 471         0xa3,
 472         0xa4,  /* ISRC1DEC1 */
 473         0xa5,
 474         0xa6,
 475         0xa7,
 476         0xa8,  /* ISRC2DEC1 */
 477         0xa9,
 478         0xaa,
 479         0xab,
 480         0xac,  /* ISRC2INT1 */
 481         0xad,
 482         0xae,
 483         0xaf,
 484         0xb0,  /* ISRC3DEC1 */
 485         0xb1,
 486         0xb2,
 487         0xb3,
 488         0xb4,  /* ISRC3INT1 */
 489         0xb5,
 490         0xb6,
 491         0xb7,
 492 };
 493 EXPORT_SYMBOL_GPL(arizona_mixer_values);
 494
 495 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
 496 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
 497
 498 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
 499         "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
 500 };
 501 EXPORT_SYMBOL_GPL(arizona_rate_text);
 502
 503 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
 504         0, 1, 2, 8,
 505 };
 506 EXPORT_SYMBOL_GPL(arizona_rate_val);
 507
 508
 509 const struct soc_enum arizona_isrc_fsh[] = {
 510         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
 511                               ARIZONA_ISRC1_FSH_SHIFT, 0xf,
 512                               ARIZONA_RATE_ENUM_SIZE,
 513                               arizona_rate_text, arizona_rate_val),
 514         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
 515                               ARIZONA_ISRC2_FSH_SHIFT, 0xf,
 516                               ARIZONA_RATE_ENUM_SIZE,
 517                               arizona_rate_text, arizona_rate_val),
 518         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
 519                               ARIZONA_ISRC3_FSH_SHIFT, 0xf,
 520                               ARIZONA_RATE_ENUM_SIZE,
 521                               arizona_rate_text, arizona_rate_val),
 522 };
 523 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
 524
 525 const struct soc_enum arizona_isrc_fsl[] = {
 526         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
 527                               ARIZONA_ISRC1_FSL_SHIFT, 0xf,
 528                               ARIZONA_RATE_ENUM_SIZE,
 529                               arizona_rate_text, arizona_rate_val),
 530         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
 531                               ARIZONA_ISRC2_FSL_SHIFT, 0xf,
 532                               ARIZONA_RATE_ENUM_SIZE,
 533                               arizona_rate_text, arizona_rate_val),
 534         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
 535                               ARIZONA_ISRC3_FSL_SHIFT, 0xf,
 536                               ARIZONA_RATE_ENUM_SIZE,
 537                               arizona_rate_text, arizona_rate_val),
 538 };
 539 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
 540
 541 const struct soc_enum arizona_asrc_rate1 =
 542         SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
 543                               ARIZONA_ASRC_RATE1_SHIFT, 0xf,
 544                               ARIZONA_RATE_ENUM_SIZE - 1,
 545                               arizona_rate_text, arizona_rate_val);
 546 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
 547
 548 static const char *arizona_vol_ramp_text[] = {
 549         "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
 550         "15ms/6dB", "30ms/6dB",
 551 };
 552
 553 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
 554                      ARIZONA_INPUT_VOLUME_RAMP,
 555                      ARIZONA_IN_VD_RAMP_SHIFT,
 556                      arizona_vol_ramp_text);
 557 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
 558
 559 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
 560                      ARIZONA_INPUT_VOLUME_RAMP,
 561                      ARIZONA_IN_VI_RAMP_SHIFT,
 562                      arizona_vol_ramp_text);
 563 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
 564
 565 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
 566                      ARIZONA_OUTPUT_VOLUME_RAMP,
 567                      ARIZONA_OUT_VD_RAMP_SHIFT,
 568                      arizona_vol_ramp_text);
 569 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
 570
 571 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
 572                      ARIZONA_OUTPUT_VOLUME_RAMP,
 573                      ARIZONA_OUT_VI_RAMP_SHIFT,
 574                      arizona_vol_ramp_text);
 575 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
 576
 577 static const char *arizona_lhpf_mode_text[] = {
 578         "Low-pass", "High-pass"
 579 };
 580
 581 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
 582                      ARIZONA_HPLPF1_1,
 583                      ARIZONA_LHPF1_MODE_SHIFT,
 584                      arizona_lhpf_mode_text);
 585 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
 586
 587 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
 588                      ARIZONA_HPLPF2_1,
 589                      ARIZONA_LHPF2_MODE_SHIFT,
 590                      arizona_lhpf_mode_text);
 591 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
 592
 593 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
 594                      ARIZONA_HPLPF3_1,
 595                      ARIZONA_LHPF3_MODE_SHIFT,
 596                      arizona_lhpf_mode_text);
 597 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
 598
 599 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
 600                      ARIZONA_HPLPF4_1,
 601                      ARIZONA_LHPF4_MODE_SHIFT,
 602                      arizona_lhpf_mode_text);
 603 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
 604
 605 static const char *arizona_ng_hold_text[] = {
 606         "30ms", "120ms", "250ms", "500ms",
 607 };
 608
 609 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
 610                      ARIZONA_NOISE_GATE_CONTROL,
 611                      ARIZONA_NGATE_HOLD_SHIFT,
 612                      arizona_ng_hold_text);
 613 EXPORT_SYMBOL_GPL(arizona_ng_hold);
 614
 615 static const char * const arizona_in_hpf_cut_text[] = {
 616         "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
 617 };
 618
 619 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
 620                      ARIZONA_HPF_CONTROL,
 621                      ARIZONA_IN_HPF_CUT_SHIFT,
 622                      arizona_in_hpf_cut_text);
 623 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
 624
 625 static const char * const arizona_in_dmic_osr_text[] = {
 626         "1.536MHz", "3.072MHz", "6.144MHz",
 627 };
 628
 629 const struct soc_enum arizona_in_dmic_osr[] = {
 630         SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
 631                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 632                         arizona_in_dmic_osr_text),
 633         SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
 634                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 635                         arizona_in_dmic_osr_text),
 636         SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
 637                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 638                         arizona_in_dmic_osr_text),
 639         SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
 640                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 641                         arizona_in_dmic_osr_text),
 642 };
 643 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
 644
 645 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
 646 {
 647         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 648         unsigned int val;
 649         int i;
 650
 651         if (ena)
 652                 val = ARIZONA_IN_VU;
 653         else
 654                 val = 0;
 655
 656         for (i = 0; i < priv->num_inputs; i++)
 657                 snd_soc_update_bits(codec,
 658                                     ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
 659                                     ARIZONA_IN_VU, val);
 660 }
 661
 662 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
 663                   int event)
 664 {
 665         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
 666         unsigned int reg;
 667
 668         if (w->shift % 2)
 669                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
 670         else
 671                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
 672
 673         switch (event) {
 674         case SND_SOC_DAPM_PRE_PMU:
 675                 priv->in_pending++;
 676                 break;
 677         case SND_SOC_DAPM_POST_PMU:
 678                 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
 679
 680                 /* If this is the last input pending then allow VU */
 681                 priv->in_pending--;
 682                 if (priv->in_pending == 0) {
 683                         msleep(1);
 684                         arizona_in_set_vu(w->codec, 1);
 685                 }
 686                 break;
 687         case SND_SOC_DAPM_PRE_PMD:
 688                 snd_soc_update_bits(w->codec, reg,
 689                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
 690                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
 691                 break;
 692         case SND_SOC_DAPM_POST_PMD:
 693                 /* Disable volume updates if no inputs are enabled */
 694                 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
 695                 if (reg == 0)
 696                         arizona_in_set_vu(w->codec, 0);
 697         }
 698
 699         return 0;
 700 }
 701 EXPORT_SYMBOL_GPL(arizona_in_ev);
 702
 703 int arizona_out_ev(struct snd_soc_dapm_widget *w,
 704                    struct snd_kcontrol *kcontrol,
 705                    int event)
 706 {
 707         switch (event) {
 708         case SND_SOC_DAPM_POST_PMU:
 709                 switch (w->shift) {
 710                 case ARIZONA_OUT1L_ENA_SHIFT:
 711                 case ARIZONA_OUT1R_ENA_SHIFT:
 712                 case ARIZONA_OUT2L_ENA_SHIFT:
 713                 case ARIZONA_OUT2R_ENA_SHIFT:
 714                 case ARIZONA_OUT3L_ENA_SHIFT:
 715                 case ARIZONA_OUT3R_ENA_SHIFT:
 716                         msleep(17);
 717                         break;
 718
 719                 default:
 720                         break;
 721                 }
 722                 break;
 723         }
 724
 725         return 0;
 726 }
 727 EXPORT_SYMBOL_GPL(arizona_out_ev);
 728
 729 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
 730                    struct snd_kcontrol *kcontrol,
 731                    int event)
 732 {
 733         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
 734         struct arizona *arizona = priv->arizona;
 735         unsigned int mask = 1 << w->shift;
 736         unsigned int val;
 737
 738         switch (event) {
 739         case SND_SOC_DAPM_POST_PMU:
 740                 val = mask;
 741                 break;
 742         case SND_SOC_DAPM_PRE_PMD:
 743                 val = 0;
 744                 break;
 745         default:
 746                 return -EINVAL;
 747         }
 748
 749         /* Store the desired state for the HP outputs */
 750         priv->arizona->hp_ena &= ~mask;
 751         priv->arizona->hp_ena |= val;
 752
 753         /* Force off if HPDET magic is active */
 754         if (priv->arizona->hpdet_magic)
 755                 val = 0;
 756
 757         regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
 758                                  mask, val);
 759
 760         return arizona_out_ev(w, kcontrol, event);
 761 }
 762 EXPORT_SYMBOL_GPL(arizona_hp_ev);
 763
 764 static unsigned int arizona_sysclk_48k_rates[] = {
 765         6144000,
 766         12288000,
 767         24576000,
 768         49152000,
 769         73728000,
 770         98304000,
 771         147456000,
 772 };
 773
 774 static unsigned int arizona_sysclk_44k1_rates[] = {
 775         5644800,
 776         11289600,
 777         22579200,
 778         45158400,
 779         67737600,
 780         90316800,
 781         135475200,
 782 };
 783
 784 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
 785                              unsigned int freq)
 786 {
 787         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 788         unsigned int reg;
 789         unsigned int *rates;
 790         int ref, div, refclk;
 791
 792         switch (clk) {
 793         case ARIZONA_CLK_OPCLK:
 794                 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
 795                 refclk = priv->sysclk;
 796                 break;
 797         case ARIZONA_CLK_ASYNC_OPCLK:
 798                 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
 799                 refclk = priv->asyncclk;
 800                 break;
 801         default:
 802                 return -EINVAL;
 803         }
 804
 805         if (refclk % 8000)
 806                 rates = arizona_sysclk_44k1_rates;
 807         else
 808                 rates = arizona_sysclk_48k_rates;
 809
 810         for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
 811                      rates[ref] <= refclk; ref++) {
 812                 div = 1;
 813                 while (rates[ref] / div >= freq && div < 32) {
 814                         if (rates[ref] / div == freq) {
 815                                 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
 816                                         freq);
 817                                 snd_soc_update_bits(codec, reg,
 818                                                     ARIZONA_OPCLK_DIV_MASK |
 819                                                     ARIZONA_OPCLK_SEL_MASK,
 820                                                     (div <<
 821                                                      ARIZONA_OPCLK_DIV_SHIFT) |
 822                                                     ref);
 823                                 return 0;
 824                         }
 825                         div++;
 826                 }
 827         }
 828
 829         dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
 830         return -EINVAL;
 831 }
 832
 833 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
 834                        int source, unsigned int freq, int dir)
 835 {
 836         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 837         struct arizona *arizona = priv->arizona;
 838         char *name;
 839         unsigned int reg;
 840         unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
 841         unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
 842         unsigned int *clk;
 843
 844         switch (clk_id) {
 845         case ARIZONA_CLK_SYSCLK:
 846                 name = "SYSCLK";
 847                 reg = ARIZONA_SYSTEM_CLOCK_1;
 848                 clk = &priv->sysclk;
 849                 mask |= ARIZONA_SYSCLK_FRAC;
 850                 break;
 851         case ARIZONA_CLK_ASYNCCLK:
 852                 name = "ASYNCCLK";
 853                 reg = ARIZONA_ASYNC_CLOCK_1;
 854                 clk = &priv->asyncclk;
 855                 break;
 856         case ARIZONA_CLK_OPCLK:
 857         case ARIZONA_CLK_ASYNC_OPCLK:
 858                 return arizona_set_opclk(codec, clk_id, freq);
 859         default:
 860                 return -EINVAL;
 861         }
 862
 863         switch (freq) {
 864         case  5644800:
 865         case  6144000:
 866                 break;
 867         case 11289600:
 868         case 12288000:
 869                 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 870                 break;
 871         case 22579200:
 872         case 24576000:
 873                 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 874                 break;
 875         case 45158400:
 876         case 49152000:
 877                 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 878                 break;
 879         case 67737600:
 880         case 73728000:
 881                 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 882                 break;
 883         case 90316800:
 884         case 98304000:
 885                 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 886                 break;
 887         case 135475200:
 888         case 147456000:
 889                 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 890                 break;
 891         case 0:
 892                 dev_dbg(arizona->dev, "%s cleared\n", name);
 893                 *clk = freq;
 894                 return 0;
 895         default:
 896                 return -EINVAL;
 897         }
 898
 899         *clk = freq;
 900
 901         if (freq % 6144000)
 902                 val |= ARIZONA_SYSCLK_FRAC;
 903
 904         dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
 905
 906         return regmap_update_bits(arizona->regmap, reg, mask, val);
 907 }
 908 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
 909
 910 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 911 {
 912         struct snd_soc_codec *codec = dai->codec;
 913         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 914         struct arizona *arizona = priv->arizona;
 915         int lrclk, bclk, mode, base;
 916
 917         base = dai->driver->base;
 918
 919         lrclk = 0;
 920         bclk = 0;
 921
 922         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 923         case SND_SOC_DAIFMT_DSP_A:
 924                 mode = 0;
 925                 break;
 926         case SND_SOC_DAIFMT_I2S:
 927                 mode = 2;
 928                 break;
 929         default:
 930                 arizona_aif_err(dai, "Unsupported DAI format %d\n",
 931                                 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 932                 return -EINVAL;
 933         }
 934
 935         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 936         case SND_SOC_DAIFMT_CBS_CFS:
 937                 break;
 938         case SND_SOC_DAIFMT_CBS_CFM:
 939                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
 940                 break;
 941         case SND_SOC_DAIFMT_CBM_CFS:
 942                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
 943                 break;
 944         case SND_SOC_DAIFMT_CBM_CFM:
 945                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
 946                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
 947                 break;
 948         default:
 949                 arizona_aif_err(dai, "Unsupported master mode %d\n",
 950                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 951                 return -EINVAL;
 952         }
 953
 954         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 955         case SND_SOC_DAIFMT_NB_NF:
 956                 break;
 957         case SND_SOC_DAIFMT_IB_IF:
 958                 bclk |= ARIZONA_AIF1_BCLK_INV;
 959                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
 960                 break;
 961         case SND_SOC_DAIFMT_IB_NF:
 962                 bclk |= ARIZONA_AIF1_BCLK_INV;
 963                 break;
 964         case SND_SOC_DAIFMT_NB_IF:
 965                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
 966                 break;
 967         default:
 968                 return -EINVAL;
 969         }
 970
 971         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
 972                                  ARIZONA_AIF1_BCLK_INV |
 973                                  ARIZONA_AIF1_BCLK_MSTR,
 974                                  bclk);
 975         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
 976                                  ARIZONA_AIF1TX_LRCLK_INV |
 977                                  ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
 978         regmap_update_bits_async(arizona->regmap,
 979                                  base + ARIZONA_AIF_RX_PIN_CTRL,
 980                                  ARIZONA_AIF1RX_LRCLK_INV |
 981                                  ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
 982         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
 983                            ARIZONA_AIF1_FMT_MASK, mode);
 984
 985         return 0;
 986 }
 987
 988 static const int arizona_48k_bclk_rates[] = {
 989         -1,
 990         48000,
 991         64000,
 992         96000,
 993         128000,
 994         192000,
 995         256000,
 996         384000,
 997         512000,
 998         768000,
 999         1024000,
1000         1536000,
1001         2048000,
1002         3072000,
1003         4096000,
1004         6144000,
1005         8192000,
1006         12288000,
1007         24576000,
1008 };
1009
1010 static const unsigned int arizona_48k_rates[] = {
1011         12000,
1012         24000,
1013         48000,
1014         96000,
1015         192000,
1016         384000,
1017         768000,
1018         4000,
1019         8000,
1020         16000,
1021         32000,
1022         64000,
1023         128000,
1024         256000,
1025         512000,
1026 };
1027
1028 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1029         .count  = ARRAY_SIZE(arizona_48k_rates),
1030         .list   = arizona_48k_rates,
1031 };
1032
1033 static const int arizona_44k1_bclk_rates[] = {
1034         -1,
1035         44100,
1036         58800,
1037         88200,
1038         117600,
1039         177640,
1040         235200,
1041         352800,
1042         470400,
1043         705600,
1044         940800,
1045         1411200,
1046         1881600,
1047         2822400,
1048         3763200,
1049         5644800,
1050         7526400,
1051         11289600,
1052         22579200,
1053 };
1054
1055 static const unsigned int arizona_44k1_rates[] = {
1056         11025,
1057         22050,
1058         44100,
1059         88200,
1060         176400,
1061         352800,
1062         705600,
1063 };
1064
1065 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1066         .count  = ARRAY_SIZE(arizona_44k1_rates),
1067         .list   = arizona_44k1_rates,
1068 };
1069
1070 static int arizona_sr_vals[] = {
1071         0,
1072         12000,
1073         24000,
1074         48000,
1075         96000,
1076         192000,
1077         384000,
1078         768000,
1079         0,
1080         11025,
1081         22050,
1082         44100,
1083         88200,
1084         176400,
1085         352800,
1086         705600,
1087         4000,
1088         8000,
1089         16000,
1090         32000,
1091         64000,
1092         128000,
1093         256000,
1094         512000,
1095 };
1096
1097 static int arizona_startup(struct snd_pcm_substream *substream,
1098                            struct snd_soc_dai *dai)
1099 {
1100         struct snd_soc_codec *codec = dai->codec;
1101         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1102         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1103         const struct snd_pcm_hw_constraint_list *constraint;
1104         unsigned int base_rate;
1105
1106         switch (dai_priv->clk) {
1107         case ARIZONA_CLK_SYSCLK:
1108                 base_rate = priv->sysclk;
1109                 break;
1110         case ARIZONA_CLK_ASYNCCLK:
1111                 base_rate = priv->asyncclk;
1112                 break;
1113         default:
1114                 return 0;
1115         }
1116
1117         if (base_rate == 0)
1118                 return 0;
1119
1120         if (base_rate % 8000)
1121                 constraint = &arizona_44k1_constraint;
1122         else
1123                 constraint = &arizona_48k_constraint;
1124
1125         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1126                                           SNDRV_PCM_HW_PARAM_RATE,
1127                                           constraint);
1128 }
1129
1130 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec,
1131                                         unsigned int rate)
1132 {
1133         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1134         struct arizona *arizona = priv->arizona;
1135         struct reg_default dac_comp[] = {
1136                 { 0x80, 0x3 },
1137                 { ARIZONA_DAC_COMP_1, 0 },
1138                 { ARIZONA_DAC_COMP_2, 0 },
1139                 { 0x80, 0x0 },
1140         };
1141
1142         mutex_lock(&codec->mutex);
1143
1144         dac_comp[1].def = arizona->dac_comp_coeff;
1145         if (rate >= 176400)
1146                 dac_comp[2].def = arizona->dac_comp_enabled;
1147
1148         mutex_unlock(&codec->mutex);
1149
1150         regmap_multi_reg_write(arizona->regmap,
1151                                dac_comp,
1152                                ARRAY_SIZE(dac_comp));
1153 }
1154
1155 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1156                                   struct snd_pcm_hw_params *params,
1157                                   struct snd_soc_dai *dai)
1158 {
1159         struct snd_soc_codec *codec = dai->codec;
1160         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1161         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1162         int base = dai->driver->base;
1163         int i, sr_val;
1164
1165         /*
1166          * We will need to be more flexible than this in future,
1167          * currently we use a single sample rate for SYSCLK.
1168          */
1169         for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1170                 if (arizona_sr_vals[i] == params_rate(params))
1171                         break;
1172         if (i == ARRAY_SIZE(arizona_sr_vals)) {
1173                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1174                                 params_rate(params));
1175                 return -EINVAL;
1176         }
1177         sr_val = i;
1178
1179         switch (dai_priv->clk) {
1180         case ARIZONA_CLK_SYSCLK:
1181                 switch (priv->arizona->type) {
1182                 case WM5102:
1183                         arizona_wm5102_set_dac_comp(codec,
1184                                                     params_rate(params));
1185                         break;
1186                 default:
1187                         break;
1188                 }
1189
1190                 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1191                                     ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1192                 if (base)
1193                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1194                                             ARIZONA_AIF1_RATE_MASK, 0);
1195                 break;
1196         case ARIZONA_CLK_ASYNCCLK:
1197                 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1198                                     ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1199                 if (base)
1200                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1201                                             ARIZONA_AIF1_RATE_MASK,
1202                                             8 << ARIZONA_AIF1_RATE_SHIFT);
1203                 break;
1204         default:
1205                 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1206                 return -EINVAL;
1207         }
1208
1209         return 0;
1210 }
1211
1212 static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec,
1213                                     int base, int bclk, int lrclk, int frame)
1214 {
1215         int val;
1216
1217         val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL);
1218         if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
1219                 return true;
1220
1221         val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE);
1222         if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK))
1223                 return true;
1224
1225         val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1);
1226         if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
1227                              ARIZONA_AIF1TX_SLOT_LEN_MASK)))
1228                 return true;
1229
1230         return false;
1231 }
1232
1233 static int arizona_hw_params(struct snd_pcm_substream *substream,
1234                              struct snd_pcm_hw_params *params,
1235                              struct snd_soc_dai *dai)
1236 {
1237         struct snd_soc_codec *codec = dai->codec;
1238         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1239         struct arizona *arizona = priv->arizona;
1240         int base = dai->driver->base;
1241         const int *rates;
1242         int i, ret, val;
1243         int channels = params_channels(params);
1244         int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1245         int tdm_width = arizona->tdm_width[dai->id - 1];
1246         int tdm_slots = arizona->tdm_slots[dai->id - 1];
1247         int bclk, lrclk, wl, frame, bclk_target;
1248         bool reconfig;
1249         unsigned int aif_tx_state, aif_rx_state;
1250
1251         if (params_rate(params) % 8000)
1252                 rates = &arizona_44k1_bclk_rates[0];
1253         else
1254                 rates = &arizona_48k_bclk_rates[0];
1255
1256         if (tdm_slots) {
1257                 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
1258                                 tdm_slots, tdm_width);
1259                 bclk_target = tdm_slots * tdm_width * params_rate(params);
1260                 channels = tdm_slots;
1261         } else {
1262                 bclk_target = snd_soc_params_to_bclk(params);
1263         }
1264
1265         if (chan_limit && chan_limit < channels) {
1266                 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1267                 bclk_target /= channels;
1268                 bclk_target *= chan_limit;
1269         }
1270
1271         /* Force multiple of 2 channels for I2S mode */
1272         val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1273         if ((channels & 1) && (val & ARIZONA_AIF1_FMT_MASK)) {
1274                 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1275                 bclk_target /= channels;
1276                 bclk_target *= channels + 1;
1277         }
1278
1279         for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1280                 if (rates[i] >= bclk_target &&
1281                     rates[i] % params_rate(params) == 0) {
1282                         bclk = i;
1283                         break;
1284                 }
1285         }
1286         if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1287                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1288                                 params_rate(params));
1289                 return -EINVAL;
1290         }
1291
1292         lrclk = rates[bclk] / params_rate(params);
1293
1294         arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1295                         rates[bclk], rates[bclk] / lrclk);
1296
1297         wl = snd_pcm_format_width(params_format(params));
1298         frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1299
1300         reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame);
1301
1302         if (reconfig) {
1303                 /* Save AIF TX/RX state */
1304                 aif_tx_state = snd_soc_read(codec,
1305                                             base + ARIZONA_AIF_TX_ENABLES);
1306                 aif_rx_state = snd_soc_read(codec,
1307                                             base + ARIZONA_AIF_RX_ENABLES);
1308                 /* Disable AIF TX/RX before reconfiguring it */
1309                 regmap_update_bits_async(arizona->regmap,
1310                                     base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0);
1311                 regmap_update_bits(arizona->regmap,
1312                                     base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
1313         }
1314
1315         ret = arizona_hw_params_rate(substream, params, dai);
1316         if (ret != 0)
1317                 goto restore_aif;
1318
1319         if (reconfig) {
1320                 regmap_update_bits_async(arizona->regmap,
1321                                          base + ARIZONA_AIF_BCLK_CTRL,
1322                                          ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1323                 regmap_update_bits_async(arizona->regmap,
1324                                          base + ARIZONA_AIF_TX_BCLK_RATE,
1325                                          ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1326                 regmap_update_bits_async(arizona->regmap,
1327                                          base + ARIZONA_AIF_RX_BCLK_RATE,
1328                                          ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1329                 regmap_update_bits_async(arizona->regmap,
1330                                          base + ARIZONA_AIF_FRAME_CTRL_1,
1331                                          ARIZONA_AIF1TX_WL_MASK |
1332                                          ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1333                 regmap_update_bits(arizona->regmap,
1334                                    base + ARIZONA_AIF_FRAME_CTRL_2,
1335                                    ARIZONA_AIF1RX_WL_MASK |
1336                                    ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1337         }
1338
1339 restore_aif:
1340         if (reconfig) {
1341                 /* Restore AIF TX/RX state */
1342                 regmap_update_bits_async(arizona->regmap,
1343                                          base + ARIZONA_AIF_TX_ENABLES,
1344                                          0xff, aif_tx_state);
1345                 regmap_update_bits(arizona->regmap,
1346                                    base + ARIZONA_AIF_RX_ENABLES,
1347                                    0xff, aif_rx_state);
1348         }
1349         return ret;
1350 }
1351
1352 static const char *arizona_dai_clk_str(int clk_id)
1353 {
1354         switch (clk_id) {
1355         case ARIZONA_CLK_SYSCLK:
1356                 return "SYSCLK";
1357         case ARIZONA_CLK_ASYNCCLK:
1358                 return "ASYNCCLK";
1359         default:
1360                 return "Unknown clock";
1361         }
1362 }
1363
1364 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1365                                   int clk_id, unsigned int freq, int dir)
1366 {
1367         struct snd_soc_codec *codec = dai->codec;
1368         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1369         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1370         struct snd_soc_dapm_route routes[2];
1371
1372         switch (clk_id) {
1373         case ARIZONA_CLK_SYSCLK:
1374         case ARIZONA_CLK_ASYNCCLK:
1375                 break;
1376         default:
1377                 return -EINVAL;
1378         }
1379
1380         if (clk_id == dai_priv->clk)
1381                 return 0;
1382
1383         if (dai->active) {
1384                 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1385                         dai->id);
1386                 return -EBUSY;
1387         }
1388
1389         dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1390                 arizona_dai_clk_str(clk_id));
1391
1392         memset(&routes, 0, sizeof(routes));
1393         routes[0].sink = dai->driver->capture.stream_name;
1394         routes[1].sink = dai->driver->playback.stream_name;
1395
1396         routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1397         routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1398         snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1399
1400         routes[0].source = arizona_dai_clk_str(clk_id);
1401         routes[1].source = arizona_dai_clk_str(clk_id);
1402         snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1403
1404         dai_priv->clk = clk_id;
1405
1406         return snd_soc_dapm_sync(&codec->dapm);
1407 }
1408
1409 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1410 {
1411         struct snd_soc_codec *codec = dai->codec;
1412         int base = dai->driver->base;
1413         unsigned int reg;
1414
1415         if (tristate)
1416                 reg = ARIZONA_AIF1_TRI;
1417         else
1418                 reg = 0;
1419
1420         return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1421                                    ARIZONA_AIF1_TRI, reg);
1422 }
1423
1424 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
1425                                          unsigned int base,
1426                                          int channels, unsigned int mask)
1427 {
1428         struct snd_soc_codec *codec = dai->codec;
1429         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1430         struct arizona *arizona = priv->arizona;
1431         int slot, i;
1432
1433         for (i = 0; i < channels; ++i) {
1434                 slot = ffs(mask) - 1;
1435                 if (slot < 0)
1436                         return;
1437
1438                 regmap_write(arizona->regmap, base + i, slot);
1439
1440                 mask &= ~(1 << slot);
1441         }
1442
1443         if (mask)
1444                 arizona_aif_warn(dai, "Too many channels in TDM mask\n");
1445 }
1446
1447 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1448                                 unsigned int rx_mask, int slots, int slot_width)
1449 {
1450         struct snd_soc_codec *codec = dai->codec;
1451         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1452         struct arizona *arizona = priv->arizona;
1453         int base = dai->driver->base;
1454         int rx_max_chan = dai->driver->playback.channels_max;
1455         int tx_max_chan = dai->driver->capture.channels_max;
1456
1457         /* Only support TDM for the physical AIFs */
1458         if (dai->id > ARIZONA_MAX_AIF)
1459                 return -ENOTSUPP;
1460
1461         if (slots == 0) {
1462                 tx_mask = (1 << tx_max_chan) - 1;
1463                 rx_mask = (1 << rx_max_chan) - 1;
1464         }
1465
1466         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
1467                                      tx_max_chan, tx_mask);
1468         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
1469                                      rx_max_chan, rx_mask);
1470
1471         arizona->tdm_width[dai->id - 1] = slot_width;
1472         arizona->tdm_slots[dai->id - 1] = slots;
1473
1474         return 0;
1475 }
1476
1477 const struct snd_soc_dai_ops arizona_dai_ops = {
1478         .startup = arizona_startup,
1479         .set_fmt = arizona_set_fmt,
1480         .set_tdm_slot = arizona_set_tdm_slot,
1481         .hw_params = arizona_hw_params,
1482         .set_sysclk = arizona_dai_set_sysclk,
1483         .set_tristate = arizona_set_tristate,
1484 };
1485 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1486
1487 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1488         .startup = arizona_startup,
1489         .hw_params = arizona_hw_params_rate,
1490         .set_sysclk = arizona_dai_set_sysclk,
1491 };
1492 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1493
1494 int arizona_init_dai(struct arizona_priv *priv, int id)
1495 {
1496         struct arizona_dai_priv *dai_priv = &priv->dai[id];
1497
1498         dai_priv->clk = ARIZONA_CLK_SYSCLK;
1499
1500         return 0;
1501 }
1502 EXPORT_SYMBOL_GPL(arizona_init_dai);
1503
1504 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1505 {
1506         struct arizona_fll *fll = data;
1507
1508         arizona_fll_dbg(fll, "clock OK\n");
1509
1510         complete(&fll->ok);
1511
1512         return IRQ_HANDLED;
1513 }
1514
1515 static struct {
1516         unsigned int min;
1517         unsigned int max;
1518         u16 fratio;
1519         int ratio;
1520 } fll_fratios[] = {
1521         {       0,    64000, 4, 16 },
1522         {   64000,   128000, 3,  8 },
1523         {  128000,   256000, 2,  4 },
1524         {  256000,  1000000, 1,  2 },
1525         { 1000000, 13500000, 0,  1 },
1526 };
1527
1528 static struct {
1529         unsigned int min;
1530         unsigned int max;
1531         u16 gain;
1532 } fll_gains[] = {
1533         {       0,   256000, 0 },
1534         {  256000,  1000000, 2 },
1535         { 1000000, 13500000, 4 },
1536 };
1537
1538 struct arizona_fll_cfg {
1539         int n;
1540         int theta;
1541         int lambda;
1542         int refdiv;
1543         int outdiv;
1544         int fratio;
1545         int gain;
1546 };
1547
1548 static int arizona_validate_fll(struct arizona_fll *fll,
1549                                 unsigned int Fref,
1550                                 unsigned int Fout)
1551 {
1552         unsigned int Fvco_min;
1553
1554         if (fll->fout && Fout != fll->fout) {
1555                 arizona_fll_err(fll,
1556                                 "Can't change output on active FLL\n");
1557                 return -EINVAL;
1558         }
1559
1560         if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1561                 arizona_fll_err(fll,
1562                                 "Can't scale %dMHz in to <=13.5MHz\n",
1563                                 Fref);
1564                 return -EINVAL;
1565         }
1566
1567         Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1568         if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1569                 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1570                                 Fout);
1571                 return -EINVAL;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1578 {
1579         int i;
1580
1581         /* Find an appropriate FLL_FRATIO */
1582         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1583                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1584                         if (fratio)
1585                                 *fratio = fll_fratios[i].fratio;
1586                         return fll_fratios[i].ratio;
1587                 }
1588         }
1589
1590         return -EINVAL;
1591 }
1592
1593 static int arizona_calc_fratio(struct arizona_fll *fll,
1594                                struct arizona_fll_cfg *cfg,
1595                                unsigned int target,
1596                                unsigned int Fref, bool sync)
1597 {
1598         int init_ratio, ratio;
1599         int refdiv, div;
1600
1601         /* Fref must be <=13.5MHz, find initial refdiv */
1602         div = 1;
1603         cfg->refdiv = 0;
1604         while (Fref > ARIZONA_FLL_MAX_FREF) {
1605                 div *= 2;
1606                 Fref /= 2;
1607                 cfg->refdiv++;
1608
1609                 if (div > ARIZONA_FLL_MAX_REFDIV)
1610                         return -EINVAL;
1611         }
1612
1613         /* Find an appropriate FLL_FRATIO */
1614         init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1615         if (init_ratio < 0) {
1616                 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1617                                 Fref);
1618                 return init_ratio;
1619         }
1620
1621         switch (fll->arizona->type) {
1622         case WM5110:
1623                 if (fll->arizona->rev < 3 || sync)
1624                         return init_ratio;
1625                 break;
1626         default:
1627                 return init_ratio;
1628         }
1629
1630         cfg->fratio = init_ratio - 1;
1631
1632         /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1633         refdiv = cfg->refdiv;
1634
1635         while (div <= ARIZONA_FLL_MAX_REFDIV) {
1636                 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1637                      ratio++) {
1638                         if ((ARIZONA_FLL_VCO_CORNER / 2) /
1639                             (fll->vco_mult * ratio) < Fref)
1640                                 break;
1641
1642                         if (target % (ratio * Fref)) {
1643                                 cfg->refdiv = refdiv;
1644                                 cfg->fratio = ratio - 1;
1645                                 return ratio;
1646                         }
1647                 }
1648
1649                 for (ratio = init_ratio - 1; ratio > 0; ratio--) {
1650                         if (target % (ratio * Fref)) {
1651                                 cfg->refdiv = refdiv;
1652                                 cfg->fratio = ratio - 1;
1653                                 return ratio;
1654                         }
1655                 }
1656
1657                 div *= 2;
1658                 Fref /= 2;
1659                 refdiv++;
1660                 init_ratio = arizona_find_fratio(Fref, NULL);
1661         }
1662
1663         arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1664         return cfg->fratio + 1;
1665 }
1666
1667 static int arizona_calc_fll(struct arizona_fll *fll,
1668                             struct arizona_fll_cfg *cfg,
1669                             unsigned int Fref, bool sync)
1670 {
1671         unsigned int target, div, gcd_fll;
1672         int i, ratio;
1673
1674         arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1675
1676         /* Fvco should be over the targt; don't check the upper bound */
1677         div = ARIZONA_FLL_MIN_OUTDIV;
1678         while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1679                 div++;
1680                 if (div > ARIZONA_FLL_MAX_OUTDIV)
1681                         return -EINVAL;
1682         }
1683         target = fll->fout * div / fll->vco_mult;
1684         cfg->outdiv = div;
1685
1686         arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1687
1688         /* Find an appropriate FLL_FRATIO and refdiv */
1689         ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1690         if (ratio < 0)
1691                 return ratio;
1692
1693         /* Apply the division for our remaining calculations */
1694         Fref = Fref / (1 << cfg->refdiv);
1695
1696         cfg->n = target / (ratio * Fref);
1697
1698         if (target % (ratio * Fref)) {
1699                 gcd_fll = gcd(target, ratio * Fref);
1700                 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1701
1702                 cfg->theta = (target - (cfg->n * ratio * Fref))
1703                         / gcd_fll;
1704                 cfg->lambda = (ratio * Fref) / gcd_fll;
1705         } else {
1706                 cfg->theta = 0;
1707                 cfg->lambda = 0;
1708         }
1709
1710         /* Round down to 16bit range with cost of accuracy lost.
1711          * Denominator must be bigger than numerator so we only
1712          * take care of it.
1713          */
1714         while (cfg->lambda >= (1 << 16)) {
1715                 cfg->theta >>= 1;
1716                 cfg->lambda >>= 1;
1717         }
1718
1719         for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1720                 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1721                         cfg->gain = fll_gains[i].gain;
1722                         break;
1723                 }
1724         }
1725         if (i == ARRAY_SIZE(fll_gains)) {
1726                 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1727                                 Fref);
1728                 return -EINVAL;
1729         }
1730
1731         arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1732                         cfg->n, cfg->theta, cfg->lambda);
1733         arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1734                         cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1735         arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1736
1737         return 0;
1738
1739 }
1740
1741 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1742                               struct arizona_fll_cfg *cfg, int source,
1743                               bool sync)
1744 {
1745         regmap_update_bits_async(arizona->regmap, base + 3,
1746                                  ARIZONA_FLL1_THETA_MASK, cfg->theta);
1747         regmap_update_bits_async(arizona->regmap, base + 4,
1748                                  ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1749         regmap_update_bits_async(arizona->regmap, base + 5,
1750                                  ARIZONA_FLL1_FRATIO_MASK,
1751                                  cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1752         regmap_update_bits_async(arizona->regmap, base + 6,
1753                                  ARIZONA_FLL1_CLK_REF_DIV_MASK |
1754                                  ARIZONA_FLL1_CLK_REF_SRC_MASK,
1755                                  cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1756                                  source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1757
1758         if (sync) {
1759                 regmap_update_bits(arizona->regmap, base + 0x7,
1760                                    ARIZONA_FLL1_GAIN_MASK,
1761                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1762         } else {
1763                 regmap_update_bits(arizona->regmap, base + 0x5,
1764                                    ARIZONA_FLL1_OUTDIV_MASK,
1765                                    cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1766                 regmap_update_bits(arizona->regmap, base + 0x9,
1767                                    ARIZONA_FLL1_GAIN_MASK,
1768                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1769         }
1770
1771         regmap_update_bits_async(arizona->regmap, base + 2,
1772                                  ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1773                                  ARIZONA_FLL1_CTRL_UPD | cfg->n);
1774 }
1775
1776 static int arizona_is_enabled_fll(struct arizona_fll *fll)
1777 {
1778         struct arizona *arizona = fll->arizona;
1779         unsigned int reg;
1780         int ret;
1781
1782         ret = regmap_read(arizona->regmap, fll->base + 1, &reg);
1783         if (ret != 0) {
1784                 arizona_fll_err(fll, "Failed to read current state: %d\n",
1785                                 ret);
1786                 return ret;
1787         }
1788
1789         return reg & ARIZONA_FLL1_ENA;
1790 }
1791
1792 static int arizona_enable_fll(struct arizona_fll *fll)
1793 {
1794         struct arizona *arizona = fll->arizona;
1795         int ret;
1796         bool use_sync = false;
1797         int already_enabled = arizona_is_enabled_fll(fll);
1798         struct arizona_fll_cfg cfg;
1799
1800         if (already_enabled < 0)
1801                 return already_enabled;
1802
1803         if (already_enabled) {
1804                 /* Facilitate smooth refclk across the transition */
1805                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,
1806                                          ARIZONA_FLL1_GAIN_MASK, 0);
1807                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
1808                                          ARIZONA_FLL1_FREERUN,
1809                                          ARIZONA_FLL1_FREERUN);
1810         }
1811
1812         /*
1813          * If we have both REFCLK and SYNCCLK then enable both,
1814          * otherwise apply the SYNCCLK settings to REFCLK.
1815          */
1816         if (fll->ref_src >= 0 && fll->ref_freq &&
1817             fll->ref_src != fll->sync_src) {
1818                 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
1819
1820                 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
1821                                   false);
1822                 if (fll->sync_src >= 0) {
1823                         arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
1824
1825                         arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
1826                                           fll->sync_src, true);
1827                         use_sync = true;
1828                 }
1829         } else if (fll->sync_src >= 0) {
1830                 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
1831
1832                 arizona_apply_fll(arizona, fll->base, &cfg,
1833                                   fll->sync_src, false);
1834
1835                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1836                                          ARIZONA_FLL1_SYNC_ENA, 0);
1837         } else {
1838                 arizona_fll_err(fll, "No clocks provided\n");
1839                 return -EINVAL;
1840         }
1841
1842         /*
1843          * Increase the bandwidth if we're not using a low frequency
1844          * sync source.
1845          */
1846         if (use_sync && fll->sync_freq > 100000)
1847                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1848                                          ARIZONA_FLL1_SYNC_BW, 0);
1849         else
1850                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1851                                          ARIZONA_FLL1_SYNC_BW,
1852                                          ARIZONA_FLL1_SYNC_BW);
1853
1854         if (!already_enabled)
1855                 pm_runtime_get(arizona->dev);
1856
1857         /* Clear any pending completions */
1858         try_wait_for_completion(&fll->ok);
1859
1860         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1861                                  ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1862         if (use_sync)
1863                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1864                                          ARIZONA_FLL1_SYNC_ENA,
1865                                          ARIZONA_FLL1_SYNC_ENA);
1866
1867         if (already_enabled)
1868                 regmap_update_bits_async(arizona->regmap, fll->base + 1,
1869                                          ARIZONA_FLL1_FREERUN, 0);
1870
1871         ret = wait_for_completion_timeout(&fll->ok,
1872                                           msecs_to_jiffies(250));
1873         if (ret == 0)
1874                 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1875
1876         return 0;
1877 }
1878
1879 static void arizona_disable_fll(struct arizona_fll *fll)
1880 {
1881         struct arizona *arizona = fll->arizona;
1882         bool change;
1883
1884         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1885                                  ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
1886         regmap_update_bits_check(arizona->regmap, fll->base + 1,
1887                                  ARIZONA_FLL1_ENA, 0, &change);
1888         regmap_update_bits(arizona->regmap, fll->base + 0x11,
1889                            ARIZONA_FLL1_SYNC_ENA, 0);
1890         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1891                                  ARIZONA_FLL1_FREERUN, 0);
1892
1893         if (change)
1894                 pm_runtime_put_autosuspend(arizona->dev);
1895 }
1896
1897 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1898                            unsigned int Fref, unsigned int Fout)
1899 {
1900         int ret = 0;
1901
1902         if (fll->ref_src == source && fll->ref_freq == Fref)
1903                 return 0;
1904
1905         if (fll->fout && Fref > 0) {
1906                 ret = arizona_validate_fll(fll, Fref, fll->fout);
1907                 if (ret != 0)
1908                         return ret;
1909         }
1910
1911         fll->ref_src = source;
1912         fll->ref_freq = Fref;
1913
1914         if (fll->fout && Fref > 0) {
1915                 ret = arizona_enable_fll(fll);
1916         }
1917
1918         return ret;
1919 }
1920 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1921
1922 int arizona_set_fll(struct arizona_fll *fll, int source,
1923                     unsigned int Fref, unsigned int Fout)
1924 {
1925         int ret = 0;
1926
1927         if (fll->sync_src == source &&
1928             fll->sync_freq == Fref && fll->fout == Fout)
1929                 return 0;
1930
1931         if (Fout) {
1932                 if (fll->ref_src >= 0) {
1933                         ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
1934                         if (ret != 0)
1935                                 return ret;
1936                 }
1937
1938                 ret = arizona_validate_fll(fll, Fref, Fout);
1939                 if (ret != 0)
1940                         return ret;
1941         }
1942
1943         fll->sync_src = source;
1944         fll->sync_freq = Fref;
1945         fll->fout = Fout;
1946
1947         if (Fout)
1948                 ret = arizona_enable_fll(fll);
1949         else
1950                 arizona_disable_fll(fll);
1951
1952         return ret;
1953 }
1954 EXPORT_SYMBOL_GPL(arizona_set_fll);
1955
1956 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1957                      int ok_irq, struct arizona_fll *fll)
1958 {
1959         int ret;
1960         unsigned int val;
1961
1962         init_completion(&fll->ok);
1963
1964         fll->id = id;
1965         fll->base = base;
1966         fll->arizona = arizona;
1967         fll->sync_src = ARIZONA_FLL_SRC_NONE;
1968
1969         /* Configure default refclk to 32kHz if we have one */
1970         regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1971         switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1972         case ARIZONA_CLK_SRC_MCLK1:
1973         case ARIZONA_CLK_SRC_MCLK2:
1974                 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
1975                 break;
1976         default:
1977                 fll->ref_src = ARIZONA_FLL_SRC_NONE;
1978         }
1979         fll->ref_freq = 32768;
1980
1981         snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1982         snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1983                  "FLL%d clock OK", id);
1984
1985         ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1986                                   arizona_fll_clock_ok, fll);
1987         if (ret != 0) {
1988                 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1989                         id, ret);
1990         }
1991
1992         regmap_update_bits(arizona->regmap, fll->base + 1,
1993                            ARIZONA_FLL1_FREERUN, 0);
1994
1995         return 0;
1996 }
1997 EXPORT_SYMBOL_GPL(arizona_init_fll);
1998
1999 /**
2000  * arizona_set_output_mode - Set the mode of the specified output
2001  *
2002  * @codec: Device to configure
2003  * @output: Output number
2004  * @diff: True to set the output to differential mode
2005  *
2006  * Some systems use external analogue switches to connect more
2007  * analogue devices to the CODEC than are supported by the device.  In
2008  * some systems this requires changing the switched output from single
2009  * ended to differential mode dynamically at runtime, an operation
2010  * supported using this function.
2011  *
2012  * Most systems have a single static configuration and should use
2013  * platform data instead.
2014  */
2015 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
2016 {
2017         unsigned int reg, val;
2018
2019         if (output < 1 || output > 6)
2020                 return -EINVAL;
2021
2022         reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
2023
2024         if (diff)
2025                 val = ARIZONA_OUT1_MONO;
2026         else
2027                 val = 0;
2028
2029         return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
2030 }
2031 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
2032
2033 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2034 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2035 MODULE_LICENSE("GPL");