29e198f57d4cd711f56c90fa640c807edbee414a
[sfrench/cifs-2.6.git] / sound / soc / codecs / arizona.c
1 /*
2  * arizona.c - Wolfson Arizona class device shared support
3  *
4  * Copyright 2012 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
20
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/gpio.h>
23 #include <linux/mfd/arizona/registers.h>
24
25 #include "arizona.h"
26
27 #define ARIZONA_AIF_BCLK_CTRL                   0x00
28 #define ARIZONA_AIF_TX_PIN_CTRL                 0x01
29 #define ARIZONA_AIF_RX_PIN_CTRL                 0x02
30 #define ARIZONA_AIF_RATE_CTRL                   0x03
31 #define ARIZONA_AIF_FORMAT                      0x04
32 #define ARIZONA_AIF_TX_BCLK_RATE                0x05
33 #define ARIZONA_AIF_RX_BCLK_RATE                0x06
34 #define ARIZONA_AIF_FRAME_CTRL_1                0x07
35 #define ARIZONA_AIF_FRAME_CTRL_2                0x08
36 #define ARIZONA_AIF_FRAME_CTRL_3                0x09
37 #define ARIZONA_AIF_FRAME_CTRL_4                0x0A
38 #define ARIZONA_AIF_FRAME_CTRL_5                0x0B
39 #define ARIZONA_AIF_FRAME_CTRL_6                0x0C
40 #define ARIZONA_AIF_FRAME_CTRL_7                0x0D
41 #define ARIZONA_AIF_FRAME_CTRL_8                0x0E
42 #define ARIZONA_AIF_FRAME_CTRL_9                0x0F
43 #define ARIZONA_AIF_FRAME_CTRL_10               0x10
44 #define ARIZONA_AIF_FRAME_CTRL_11               0x11
45 #define ARIZONA_AIF_FRAME_CTRL_12               0x12
46 #define ARIZONA_AIF_FRAME_CTRL_13               0x13
47 #define ARIZONA_AIF_FRAME_CTRL_14               0x14
48 #define ARIZONA_AIF_FRAME_CTRL_15               0x15
49 #define ARIZONA_AIF_FRAME_CTRL_16               0x16
50 #define ARIZONA_AIF_FRAME_CTRL_17               0x17
51 #define ARIZONA_AIF_FRAME_CTRL_18               0x18
52 #define ARIZONA_AIF_TX_ENABLES                  0x19
53 #define ARIZONA_AIF_RX_ENABLES                  0x1A
54 #define ARIZONA_AIF_FORCE_WRITE                 0x1B
55
56 #define ARIZONA_FLL_VCO_CORNER 141900000
57 #define ARIZONA_FLL_MAX_FREF   13500000
58 #define ARIZONA_FLL_MIN_FVCO   90000000
59 #define ARIZONA_FLL_MAX_FRATIO 16
60 #define ARIZONA_FLL_MAX_REFDIV 8
61 #define ARIZONA_FLL_MIN_OUTDIV 2
62 #define ARIZONA_FLL_MAX_OUTDIV 7
63
64 #define arizona_fll_err(_fll, fmt, ...) \
65         dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
66 #define arizona_fll_warn(_fll, fmt, ...) \
67         dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
68 #define arizona_fll_dbg(_fll, fmt, ...) \
69         dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
70
71 #define arizona_aif_err(_dai, fmt, ...) \
72         dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
73 #define arizona_aif_warn(_dai, fmt, ...) \
74         dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
75 #define arizona_aif_dbg(_dai, fmt, ...) \
76         dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
77
78 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
79                           struct snd_kcontrol *kcontrol,
80                           int event)
81 {
82         struct snd_soc_codec *codec = w->codec;
83         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
84         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
85         bool manual_ena = false;
86         int val;
87
88         switch (arizona->type) {
89         case WM5102:
90                 switch (arizona->rev) {
91                 case 0:
92                         break;
93                 default:
94                         manual_ena = true;
95                         break;
96                 }
97         default:
98                 break;
99         }
100
101         switch (event) {
102         case SND_SOC_DAPM_PRE_PMU:
103                 if (!priv->spk_ena && manual_ena) {
104                         regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
105                         priv->spk_ena_pending = true;
106                 }
107                 break;
108         case SND_SOC_DAPM_POST_PMU:
109                 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
110                 if (val & ARIZONA_SPK_SHUTDOWN_STS) {
111                         dev_crit(arizona->dev,
112                                  "Speaker not enabled due to temperature\n");
113                         return -EBUSY;
114                 }
115
116                 regmap_update_bits_async(arizona->regmap,
117                                          ARIZONA_OUTPUT_ENABLES_1,
118                                          1 << w->shift, 1 << w->shift);
119
120                 if (priv->spk_ena_pending) {
121                         msleep(75);
122                         regmap_write_async(arizona->regmap, 0x4f5, 0xda);
123                         priv->spk_ena_pending = false;
124                         priv->spk_ena++;
125                 }
126                 break;
127         case SND_SOC_DAPM_PRE_PMD:
128                 if (manual_ena) {
129                         priv->spk_ena--;
130                         if (!priv->spk_ena)
131                                 regmap_write_async(arizona->regmap,
132                                                    0x4f5, 0x25a);
133                 }
134
135                 regmap_update_bits_async(arizona->regmap,
136                                          ARIZONA_OUTPUT_ENABLES_1,
137                                          1 << w->shift, 0);
138                 break;
139         case SND_SOC_DAPM_POST_PMD:
140                 if (manual_ena) {
141                         if (!priv->spk_ena)
142                                 regmap_write_async(arizona->regmap,
143                                                    0x4f5, 0x0da);
144                 }
145                 break;
146         }
147
148         return 0;
149 }
150
151 static irqreturn_t arizona_thermal_warn(int irq, void *data)
152 {
153         struct arizona *arizona = data;
154         unsigned int val;
155         int ret;
156
157         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
158                           &val);
159         if (ret != 0) {
160                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
161                         ret);
162         } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) {
163                 dev_crit(arizona->dev, "Thermal warning\n");
164         }
165
166         return IRQ_HANDLED;
167 }
168
169 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
170 {
171         struct arizona *arizona = data;
172         unsigned int val;
173         int ret;
174
175         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
176                           &val);
177         if (ret != 0) {
178                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
179                         ret);
180         } else if (val & ARIZONA_SPK_SHUTDOWN_STS) {
181                 dev_crit(arizona->dev, "Thermal shutdown\n");
182                 ret = regmap_update_bits(arizona->regmap,
183                                          ARIZONA_OUTPUT_ENABLES_1,
184                                          ARIZONA_OUT4L_ENA |
185                                          ARIZONA_OUT4R_ENA, 0);
186                 if (ret != 0)
187                         dev_crit(arizona->dev,
188                                  "Failed to disable speaker outputs: %d\n",
189                                  ret);
190         }
191
192         return IRQ_HANDLED;
193 }
194
195 static const struct snd_soc_dapm_widget arizona_spkl =
196         SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
197                            ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
198                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
199
200 static const struct snd_soc_dapm_widget arizona_spkr =
201         SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
202                            ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
203                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
204
205 int arizona_init_spk(struct snd_soc_codec *codec)
206 {
207         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
208         struct arizona *arizona = priv->arizona;
209         int ret;
210
211         ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
212         if (ret != 0)
213                 return ret;
214
215         switch (arizona->type) {
216         case WM8997:
217                 break;
218         default:
219                 ret = snd_soc_dapm_new_controls(&codec->dapm,
220                                                 &arizona_spkr, 1);
221                 if (ret != 0)
222                         return ret;
223                 break;
224         }
225
226         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN,
227                                   "Thermal warning", arizona_thermal_warn,
228                                   arizona);
229         if (ret != 0)
230                 dev_err(arizona->dev,
231                         "Failed to get thermal warning IRQ: %d\n",
232                         ret);
233
234         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN,
235                                   "Thermal shutdown", arizona_thermal_shutdown,
236                                   arizona);
237         if (ret != 0)
238                 dev_err(arizona->dev,
239                         "Failed to get thermal shutdown IRQ: %d\n",
240                         ret);
241
242         return 0;
243 }
244 EXPORT_SYMBOL_GPL(arizona_init_spk);
245
246 int arizona_init_gpio(struct snd_soc_codec *codec)
247 {
248         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
249         struct arizona *arizona = priv->arizona;
250         int i;
251
252         switch (arizona->type) {
253         case WM5110:
254                 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
255                 break;
256         default:
257                 break;
258         }
259
260         snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
261
262         for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
263                 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
264                 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
265                         snd_soc_dapm_enable_pin(&codec->dapm,
266                                                 "DRC1 Signal Activity");
267                         break;
268                 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
269                         snd_soc_dapm_enable_pin(&codec->dapm,
270                                                 "DRC2 Signal Activity");
271                         break;
272                 default:
273                         break;
274                 }
275         }
276
277         return 0;
278 }
279 EXPORT_SYMBOL_GPL(arizona_init_gpio);
280
281 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
282         "None",
283         "Tone Generator 1",
284         "Tone Generator 2",
285         "Haptics",
286         "AEC",
287         "Mic Mute Mixer",
288         "Noise Generator",
289         "IN1L",
290         "IN1R",
291         "IN2L",
292         "IN2R",
293         "IN3L",
294         "IN3R",
295         "IN4L",
296         "IN4R",
297         "AIF1RX1",
298         "AIF1RX2",
299         "AIF1RX3",
300         "AIF1RX4",
301         "AIF1RX5",
302         "AIF1RX6",
303         "AIF1RX7",
304         "AIF1RX8",
305         "AIF2RX1",
306         "AIF2RX2",
307         "AIF2RX3",
308         "AIF2RX4",
309         "AIF2RX5",
310         "AIF2RX6",
311         "AIF3RX1",
312         "AIF3RX2",
313         "SLIMRX1",
314         "SLIMRX2",
315         "SLIMRX3",
316         "SLIMRX4",
317         "SLIMRX5",
318         "SLIMRX6",
319         "SLIMRX7",
320         "SLIMRX8",
321         "EQ1",
322         "EQ2",
323         "EQ3",
324         "EQ4",
325         "DRC1L",
326         "DRC1R",
327         "DRC2L",
328         "DRC2R",
329         "LHPF1",
330         "LHPF2",
331         "LHPF3",
332         "LHPF4",
333         "DSP1.1",
334         "DSP1.2",
335         "DSP1.3",
336         "DSP1.4",
337         "DSP1.5",
338         "DSP1.6",
339         "DSP2.1",
340         "DSP2.2",
341         "DSP2.3",
342         "DSP2.4",
343         "DSP2.5",
344         "DSP2.6",
345         "DSP3.1",
346         "DSP3.2",
347         "DSP3.3",
348         "DSP3.4",
349         "DSP3.5",
350         "DSP3.6",
351         "DSP4.1",
352         "DSP4.2",
353         "DSP4.3",
354         "DSP4.4",
355         "DSP4.5",
356         "DSP4.6",
357         "ASRC1L",
358         "ASRC1R",
359         "ASRC2L",
360         "ASRC2R",
361         "ISRC1INT1",
362         "ISRC1INT2",
363         "ISRC1INT3",
364         "ISRC1INT4",
365         "ISRC1DEC1",
366         "ISRC1DEC2",
367         "ISRC1DEC3",
368         "ISRC1DEC4",
369         "ISRC2INT1",
370         "ISRC2INT2",
371         "ISRC2INT3",
372         "ISRC2INT4",
373         "ISRC2DEC1",
374         "ISRC2DEC2",
375         "ISRC2DEC3",
376         "ISRC2DEC4",
377         "ISRC3INT1",
378         "ISRC3INT2",
379         "ISRC3INT3",
380         "ISRC3INT4",
381         "ISRC3DEC1",
382         "ISRC3DEC2",
383         "ISRC3DEC3",
384         "ISRC3DEC4",
385 };
386 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
387
388 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
389         0x00,  /* None */
390         0x04,  /* Tone */
391         0x05,
392         0x06,  /* Haptics */
393         0x08,  /* AEC */
394         0x0c,  /* Noise mixer */
395         0x0d,  /* Comfort noise */
396         0x10,  /* IN1L */
397         0x11,
398         0x12,
399         0x13,
400         0x14,
401         0x15,
402         0x16,
403         0x17,
404         0x20,  /* AIF1RX1 */
405         0x21,
406         0x22,
407         0x23,
408         0x24,
409         0x25,
410         0x26,
411         0x27,
412         0x28,  /* AIF2RX1 */
413         0x29,
414         0x2a,
415         0x2b,
416         0x2c,
417         0x2d,
418         0x30,  /* AIF3RX1 */
419         0x31,
420         0x38,  /* SLIMRX1 */
421         0x39,
422         0x3a,
423         0x3b,
424         0x3c,
425         0x3d,
426         0x3e,
427         0x3f,
428         0x50,  /* EQ1 */
429         0x51,
430         0x52,
431         0x53,
432         0x58,  /* DRC1L */
433         0x59,
434         0x5a,
435         0x5b,
436         0x60,  /* LHPF1 */
437         0x61,
438         0x62,
439         0x63,
440         0x68,  /* DSP1.1 */
441         0x69,
442         0x6a,
443         0x6b,
444         0x6c,
445         0x6d,
446         0x70,  /* DSP2.1 */
447         0x71,
448         0x72,
449         0x73,
450         0x74,
451         0x75,
452         0x78,  /* DSP3.1 */
453         0x79,
454         0x7a,
455         0x7b,
456         0x7c,
457         0x7d,
458         0x80,  /* DSP4.1 */
459         0x81,
460         0x82,
461         0x83,
462         0x84,
463         0x85,
464         0x90,  /* ASRC1L */
465         0x91,
466         0x92,
467         0x93,
468         0xa0,  /* ISRC1INT1 */
469         0xa1,
470         0xa2,
471         0xa3,
472         0xa4,  /* ISRC1DEC1 */
473         0xa5,
474         0xa6,
475         0xa7,
476         0xa8,  /* ISRC2DEC1 */
477         0xa9,
478         0xaa,
479         0xab,
480         0xac,  /* ISRC2INT1 */
481         0xad,
482         0xae,
483         0xaf,
484         0xb0,  /* ISRC3DEC1 */
485         0xb1,
486         0xb2,
487         0xb3,
488         0xb4,  /* ISRC3INT1 */
489         0xb5,
490         0xb6,
491         0xb7,
492 };
493 EXPORT_SYMBOL_GPL(arizona_mixer_values);
494
495 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
496 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
497
498 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
499         "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
500 };
501 EXPORT_SYMBOL_GPL(arizona_rate_text);
502
503 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
504         0, 1, 2, 8,
505 };
506 EXPORT_SYMBOL_GPL(arizona_rate_val);
507
508
509 const struct soc_enum arizona_isrc_fsh[] = {
510         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
511                               ARIZONA_ISRC1_FSH_SHIFT, 0xf,
512                               ARIZONA_RATE_ENUM_SIZE,
513                               arizona_rate_text, arizona_rate_val),
514         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
515                               ARIZONA_ISRC2_FSH_SHIFT, 0xf,
516                               ARIZONA_RATE_ENUM_SIZE,
517                               arizona_rate_text, arizona_rate_val),
518         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
519                               ARIZONA_ISRC3_FSH_SHIFT, 0xf,
520                               ARIZONA_RATE_ENUM_SIZE,
521                               arizona_rate_text, arizona_rate_val),
522 };
523 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
524
525 const struct soc_enum arizona_isrc_fsl[] = {
526         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
527                               ARIZONA_ISRC1_FSL_SHIFT, 0xf,
528                               ARIZONA_RATE_ENUM_SIZE,
529                               arizona_rate_text, arizona_rate_val),
530         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
531                               ARIZONA_ISRC2_FSL_SHIFT, 0xf,
532                               ARIZONA_RATE_ENUM_SIZE,
533                               arizona_rate_text, arizona_rate_val),
534         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
535                               ARIZONA_ISRC3_FSL_SHIFT, 0xf,
536                               ARIZONA_RATE_ENUM_SIZE,
537                               arizona_rate_text, arizona_rate_val),
538 };
539 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
540
541 const struct soc_enum arizona_asrc_rate1 =
542         SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
543                               ARIZONA_ASRC_RATE1_SHIFT, 0xf,
544                               ARIZONA_RATE_ENUM_SIZE - 1,
545                               arizona_rate_text, arizona_rate_val);
546 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
547
548 static const char *arizona_vol_ramp_text[] = {
549         "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
550         "15ms/6dB", "30ms/6dB",
551 };
552
553 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
554                      ARIZONA_INPUT_VOLUME_RAMP,
555                      ARIZONA_IN_VD_RAMP_SHIFT,
556                      arizona_vol_ramp_text);
557 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
558
559 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
560                      ARIZONA_INPUT_VOLUME_RAMP,
561                      ARIZONA_IN_VI_RAMP_SHIFT,
562                      arizona_vol_ramp_text);
563 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
564
565 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
566                      ARIZONA_OUTPUT_VOLUME_RAMP,
567                      ARIZONA_OUT_VD_RAMP_SHIFT,
568                      arizona_vol_ramp_text);
569 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
570
571 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
572                      ARIZONA_OUTPUT_VOLUME_RAMP,
573                      ARIZONA_OUT_VI_RAMP_SHIFT,
574                      arizona_vol_ramp_text);
575 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
576
577 static const char *arizona_lhpf_mode_text[] = {
578         "Low-pass", "High-pass"
579 };
580
581 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
582                      ARIZONA_HPLPF1_1,
583                      ARIZONA_LHPF1_MODE_SHIFT,
584                      arizona_lhpf_mode_text);
585 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
586
587 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
588                      ARIZONA_HPLPF2_1,
589                      ARIZONA_LHPF2_MODE_SHIFT,
590                      arizona_lhpf_mode_text);
591 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
592
593 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
594                      ARIZONA_HPLPF3_1,
595                      ARIZONA_LHPF3_MODE_SHIFT,
596                      arizona_lhpf_mode_text);
597 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
598
599 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
600                      ARIZONA_HPLPF4_1,
601                      ARIZONA_LHPF4_MODE_SHIFT,
602                      arizona_lhpf_mode_text);
603 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
604
605 static const char *arizona_ng_hold_text[] = {
606         "30ms", "120ms", "250ms", "500ms",
607 };
608
609 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
610                      ARIZONA_NOISE_GATE_CONTROL,
611                      ARIZONA_NGATE_HOLD_SHIFT,
612                      arizona_ng_hold_text);
613 EXPORT_SYMBOL_GPL(arizona_ng_hold);
614
615 static const char * const arizona_in_hpf_cut_text[] = {
616         "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
617 };
618
619 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
620                      ARIZONA_HPF_CONTROL,
621                      ARIZONA_IN_HPF_CUT_SHIFT,
622                      arizona_in_hpf_cut_text);
623 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
624
625 static const char * const arizona_in_dmic_osr_text[] = {
626         "1.536MHz", "3.072MHz", "6.144MHz",
627 };
628
629 const struct soc_enum arizona_in_dmic_osr[] = {
630         SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
631                         ARRAY_SIZE(arizona_in_dmic_osr_text),
632                         arizona_in_dmic_osr_text),
633         SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
634                         ARRAY_SIZE(arizona_in_dmic_osr_text),
635                         arizona_in_dmic_osr_text),
636         SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
637                         ARRAY_SIZE(arizona_in_dmic_osr_text),
638                         arizona_in_dmic_osr_text),
639         SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
640                         ARRAY_SIZE(arizona_in_dmic_osr_text),
641                         arizona_in_dmic_osr_text),
642 };
643 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
644
645 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
646 {
647         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
648         unsigned int val;
649         int i;
650
651         if (ena)
652                 val = ARIZONA_IN_VU;
653         else
654                 val = 0;
655
656         for (i = 0; i < priv->num_inputs; i++)
657                 snd_soc_update_bits(codec,
658                                     ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
659                                     ARIZONA_IN_VU, val);
660 }
661
662 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
663                   int event)
664 {
665         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
666         unsigned int reg;
667
668         if (w->shift % 2)
669                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
670         else
671                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
672
673         switch (event) {
674         case SND_SOC_DAPM_PRE_PMU:
675                 priv->in_pending++;
676                 break;
677         case SND_SOC_DAPM_POST_PMU:
678                 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
679
680                 /* If this is the last input pending then allow VU */
681                 priv->in_pending--;
682                 if (priv->in_pending == 0) {
683                         msleep(1);
684                         arizona_in_set_vu(w->codec, 1);
685                 }
686                 break;
687         case SND_SOC_DAPM_PRE_PMD:
688                 snd_soc_update_bits(w->codec, reg,
689                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
690                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
691                 break;
692         case SND_SOC_DAPM_POST_PMD:
693                 /* Disable volume updates if no inputs are enabled */
694                 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
695                 if (reg == 0)
696                         arizona_in_set_vu(w->codec, 0);
697         }
698
699         return 0;
700 }
701 EXPORT_SYMBOL_GPL(arizona_in_ev);
702
703 int arizona_out_ev(struct snd_soc_dapm_widget *w,
704                    struct snd_kcontrol *kcontrol,
705                    int event)
706 {
707         switch (event) {
708         case SND_SOC_DAPM_POST_PMU:
709                 switch (w->shift) {
710                 case ARIZONA_OUT1L_ENA_SHIFT:
711                 case ARIZONA_OUT1R_ENA_SHIFT:
712                 case ARIZONA_OUT2L_ENA_SHIFT:
713                 case ARIZONA_OUT2R_ENA_SHIFT:
714                 case ARIZONA_OUT3L_ENA_SHIFT:
715                 case ARIZONA_OUT3R_ENA_SHIFT:
716                         msleep(17);
717                         break;
718
719                 default:
720                         break;
721                 }
722                 break;
723         }
724
725         return 0;
726 }
727 EXPORT_SYMBOL_GPL(arizona_out_ev);
728
729 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
730                    struct snd_kcontrol *kcontrol,
731                    int event)
732 {
733         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
734         struct arizona *arizona = priv->arizona;
735         unsigned int mask = 1 << w->shift;
736         unsigned int val;
737
738         switch (event) {
739         case SND_SOC_DAPM_POST_PMU:
740                 val = mask;
741                 break;
742         case SND_SOC_DAPM_PRE_PMD:
743                 val = 0;
744                 break;
745         default:
746                 return -EINVAL;
747         }
748
749         /* Store the desired state for the HP outputs */
750         priv->arizona->hp_ena &= ~mask;
751         priv->arizona->hp_ena |= val;
752
753         /* Force off if HPDET magic is active */
754         if (priv->arizona->hpdet_magic)
755                 val = 0;
756
757         regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
758                                  mask, val);
759
760         return arizona_out_ev(w, kcontrol, event);
761 }
762 EXPORT_SYMBOL_GPL(arizona_hp_ev);
763
764 static unsigned int arizona_sysclk_48k_rates[] = {
765         6144000,
766         12288000,
767         24576000,
768         49152000,
769         73728000,
770         98304000,
771         147456000,
772 };
773
774 static unsigned int arizona_sysclk_44k1_rates[] = {
775         5644800,
776         11289600,
777         22579200,
778         45158400,
779         67737600,
780         90316800,
781         135475200,
782 };
783
784 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
785                              unsigned int freq)
786 {
787         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
788         unsigned int reg;
789         unsigned int *rates;
790         int ref, div, refclk;
791
792         switch (clk) {
793         case ARIZONA_CLK_OPCLK:
794                 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
795                 refclk = priv->sysclk;
796                 break;
797         case ARIZONA_CLK_ASYNC_OPCLK:
798                 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
799                 refclk = priv->asyncclk;
800                 break;
801         default:
802                 return -EINVAL;
803         }
804
805         if (refclk % 8000)
806                 rates = arizona_sysclk_44k1_rates;
807         else
808                 rates = arizona_sysclk_48k_rates;
809
810         for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
811                      rates[ref] <= refclk; ref++) {
812                 div = 1;
813                 while (rates[ref] / div >= freq && div < 32) {
814                         if (rates[ref] / div == freq) {
815                                 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
816                                         freq);
817                                 snd_soc_update_bits(codec, reg,
818                                                     ARIZONA_OPCLK_DIV_MASK |
819                                                     ARIZONA_OPCLK_SEL_MASK,
820                                                     (div <<
821                                                      ARIZONA_OPCLK_DIV_SHIFT) |
822                                                     ref);
823                                 return 0;
824                         }
825                         div++;
826                 }
827         }
828
829         dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
830         return -EINVAL;
831 }
832
833 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
834                        int source, unsigned int freq, int dir)
835 {
836         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
837         struct arizona *arizona = priv->arizona;
838         char *name;
839         unsigned int reg;
840         unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
841         unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
842         unsigned int *clk;
843
844         switch (clk_id) {
845         case ARIZONA_CLK_SYSCLK:
846                 name = "SYSCLK";
847                 reg = ARIZONA_SYSTEM_CLOCK_1;
848                 clk = &priv->sysclk;
849                 mask |= ARIZONA_SYSCLK_FRAC;
850                 break;
851         case ARIZONA_CLK_ASYNCCLK:
852                 name = "ASYNCCLK";
853                 reg = ARIZONA_ASYNC_CLOCK_1;
854                 clk = &priv->asyncclk;
855                 break;
856         case ARIZONA_CLK_OPCLK:
857         case ARIZONA_CLK_ASYNC_OPCLK:
858                 return arizona_set_opclk(codec, clk_id, freq);
859         default:
860                 return -EINVAL;
861         }
862
863         switch (freq) {
864         case  5644800:
865         case  6144000:
866                 break;
867         case 11289600:
868         case 12288000:
869                 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
870                 break;
871         case 22579200:
872         case 24576000:
873                 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
874                 break;
875         case 45158400:
876         case 49152000:
877                 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
878                 break;
879         case 67737600:
880         case 73728000:
881                 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
882                 break;
883         case 90316800:
884         case 98304000:
885                 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
886                 break;
887         case 135475200:
888         case 147456000:
889                 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
890                 break;
891         case 0:
892                 dev_dbg(arizona->dev, "%s cleared\n", name);
893                 *clk = freq;
894                 return 0;
895         default:
896                 return -EINVAL;
897         }
898
899         *clk = freq;
900
901         if (freq % 6144000)
902                 val |= ARIZONA_SYSCLK_FRAC;
903
904         dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
905
906         return regmap_update_bits(arizona->regmap, reg, mask, val);
907 }
908 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
909
910 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
911 {
912         struct snd_soc_codec *codec = dai->codec;
913         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
914         struct arizona *arizona = priv->arizona;
915         int lrclk, bclk, mode, base;
916
917         base = dai->driver->base;
918
919         lrclk = 0;
920         bclk = 0;
921
922         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
923         case SND_SOC_DAIFMT_DSP_A:
924                 mode = 0;
925                 break;
926         case SND_SOC_DAIFMT_I2S:
927                 mode = 2;
928                 break;
929         default:
930                 arizona_aif_err(dai, "Unsupported DAI format %d\n",
931                                 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
932                 return -EINVAL;
933         }
934
935         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
936         case SND_SOC_DAIFMT_CBS_CFS:
937                 break;
938         case SND_SOC_DAIFMT_CBS_CFM:
939                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
940                 break;
941         case SND_SOC_DAIFMT_CBM_CFS:
942                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
943                 break;
944         case SND_SOC_DAIFMT_CBM_CFM:
945                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
946                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
947                 break;
948         default:
949                 arizona_aif_err(dai, "Unsupported master mode %d\n",
950                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
951                 return -EINVAL;
952         }
953
954         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
955         case SND_SOC_DAIFMT_NB_NF:
956                 break;
957         case SND_SOC_DAIFMT_IB_IF:
958                 bclk |= ARIZONA_AIF1_BCLK_INV;
959                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
960                 break;
961         case SND_SOC_DAIFMT_IB_NF:
962                 bclk |= ARIZONA_AIF1_BCLK_INV;
963                 break;
964         case SND_SOC_DAIFMT_NB_IF:
965                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
966                 break;
967         default:
968                 return -EINVAL;
969         }
970
971         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
972                                  ARIZONA_AIF1_BCLK_INV |
973                                  ARIZONA_AIF1_BCLK_MSTR,
974                                  bclk);
975         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
976                                  ARIZONA_AIF1TX_LRCLK_INV |
977                                  ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
978         regmap_update_bits_async(arizona->regmap,
979                                  base + ARIZONA_AIF_RX_PIN_CTRL,
980                                  ARIZONA_AIF1RX_LRCLK_INV |
981                                  ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
982         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
983                            ARIZONA_AIF1_FMT_MASK, mode);
984
985         return 0;
986 }
987
988 static const int arizona_48k_bclk_rates[] = {
989         -1,
990         48000,
991         64000,
992         96000,
993         128000,
994         192000,
995         256000,
996         384000,
997         512000,
998         768000,
999         1024000,
1000         1536000,
1001         2048000,
1002         3072000,
1003         4096000,
1004         6144000,
1005         8192000,
1006         12288000,
1007         24576000,
1008 };
1009
1010 static const unsigned int arizona_48k_rates[] = {
1011         12000,
1012         24000,
1013         48000,
1014         96000,
1015         192000,
1016         384000,
1017         768000,
1018         4000,
1019         8000,
1020         16000,
1021         32000,
1022         64000,
1023         128000,
1024         256000,
1025         512000,
1026 };
1027
1028 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1029         .count  = ARRAY_SIZE(arizona_48k_rates),
1030         .list   = arizona_48k_rates,
1031 };
1032
1033 static const int arizona_44k1_bclk_rates[] = {
1034         -1,
1035         44100,
1036         58800,
1037         88200,
1038         117600,
1039         177640,
1040         235200,
1041         352800,
1042         470400,
1043         705600,
1044         940800,
1045         1411200,
1046         1881600,
1047         2822400,
1048         3763200,
1049         5644800,
1050         7526400,
1051         11289600,
1052         22579200,
1053 };
1054
1055 static const unsigned int arizona_44k1_rates[] = {
1056         11025,
1057         22050,
1058         44100,
1059         88200,
1060         176400,
1061         352800,
1062         705600,
1063 };
1064
1065 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1066         .count  = ARRAY_SIZE(arizona_44k1_rates),
1067         .list   = arizona_44k1_rates,
1068 };
1069
1070 static int arizona_sr_vals[] = {
1071         0,
1072         12000,
1073         24000,
1074         48000,
1075         96000,
1076         192000,
1077         384000,
1078         768000,
1079         0,
1080         11025,
1081         22050,
1082         44100,
1083         88200,
1084         176400,
1085         352800,
1086         705600,
1087         4000,
1088         8000,
1089         16000,
1090         32000,
1091         64000,
1092         128000,
1093         256000,
1094         512000,
1095 };
1096
1097 static int arizona_startup(struct snd_pcm_substream *substream,
1098                            struct snd_soc_dai *dai)
1099 {
1100         struct snd_soc_codec *codec = dai->codec;
1101         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1102         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1103         const struct snd_pcm_hw_constraint_list *constraint;
1104         unsigned int base_rate;
1105
1106         switch (dai_priv->clk) {
1107         case ARIZONA_CLK_SYSCLK:
1108                 base_rate = priv->sysclk;
1109                 break;
1110         case ARIZONA_CLK_ASYNCCLK:
1111                 base_rate = priv->asyncclk;
1112                 break;
1113         default:
1114                 return 0;
1115         }
1116
1117         if (base_rate == 0)
1118                 return 0;
1119
1120         if (base_rate % 8000)
1121                 constraint = &arizona_44k1_constraint;
1122         else
1123                 constraint = &arizona_48k_constraint;
1124
1125         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1126                                           SNDRV_PCM_HW_PARAM_RATE,
1127                                           constraint);
1128 }
1129
1130 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1131                                   struct snd_pcm_hw_params *params,
1132                                   struct snd_soc_dai *dai)
1133 {
1134         struct snd_soc_codec *codec = dai->codec;
1135         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1136         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1137         int base = dai->driver->base;
1138         int i, sr_val;
1139
1140         /*
1141          * We will need to be more flexible than this in future,
1142          * currently we use a single sample rate for SYSCLK.
1143          */
1144         for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1145                 if (arizona_sr_vals[i] == params_rate(params))
1146                         break;
1147         if (i == ARRAY_SIZE(arizona_sr_vals)) {
1148                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1149                                 params_rate(params));
1150                 return -EINVAL;
1151         }
1152         sr_val = i;
1153
1154         switch (dai_priv->clk) {
1155         case ARIZONA_CLK_SYSCLK:
1156                 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1157                                     ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1158                 if (base)
1159                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1160                                             ARIZONA_AIF1_RATE_MASK, 0);
1161                 break;
1162         case ARIZONA_CLK_ASYNCCLK:
1163                 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1164                                     ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1165                 if (base)
1166                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1167                                             ARIZONA_AIF1_RATE_MASK,
1168                                             8 << ARIZONA_AIF1_RATE_SHIFT);
1169                 break;
1170         default:
1171                 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1172                 return -EINVAL;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int arizona_hw_params(struct snd_pcm_substream *substream,
1179                              struct snd_pcm_hw_params *params,
1180                              struct snd_soc_dai *dai)
1181 {
1182         struct snd_soc_codec *codec = dai->codec;
1183         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1184         struct arizona *arizona = priv->arizona;
1185         int base = dai->driver->base;
1186         const int *rates;
1187         int i, ret, val;
1188         int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1189         int bclk, lrclk, wl, frame, bclk_target;
1190
1191         if (params_rate(params) % 8000)
1192                 rates = &arizona_44k1_bclk_rates[0];
1193         else
1194                 rates = &arizona_48k_bclk_rates[0];
1195
1196         bclk_target = snd_soc_params_to_bclk(params);
1197         if (chan_limit && chan_limit < params_channels(params)) {
1198                 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1199                 bclk_target /= params_channels(params);
1200                 bclk_target *= chan_limit;
1201         }
1202
1203         /* Force stereo for I2S mode */
1204         val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1205         if (params_channels(params) == 1 && (val & ARIZONA_AIF1_FMT_MASK)) {
1206                 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1207                 bclk_target *= 2;
1208         }
1209
1210         for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1211                 if (rates[i] >= bclk_target &&
1212                     rates[i] % params_rate(params) == 0) {
1213                         bclk = i;
1214                         break;
1215                 }
1216         }
1217         if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1218                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1219                                 params_rate(params));
1220                 return -EINVAL;
1221         }
1222
1223         lrclk = rates[bclk] / params_rate(params);
1224
1225         arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1226                         rates[bclk], rates[bclk] / lrclk);
1227
1228         wl = snd_pcm_format_width(params_format(params));
1229         frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1230
1231         ret = arizona_hw_params_rate(substream, params, dai);
1232         if (ret != 0)
1233                 return ret;
1234
1235         regmap_update_bits_async(arizona->regmap,
1236                                  base + ARIZONA_AIF_BCLK_CTRL,
1237                                  ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1238         regmap_update_bits_async(arizona->regmap,
1239                                  base + ARIZONA_AIF_TX_BCLK_RATE,
1240                                  ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1241         regmap_update_bits_async(arizona->regmap,
1242                                  base + ARIZONA_AIF_RX_BCLK_RATE,
1243                                  ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1244         regmap_update_bits_async(arizona->regmap,
1245                                  base + ARIZONA_AIF_FRAME_CTRL_1,
1246                                  ARIZONA_AIF1TX_WL_MASK |
1247                                  ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1248         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FRAME_CTRL_2,
1249                            ARIZONA_AIF1RX_WL_MASK |
1250                            ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1251
1252         return 0;
1253 }
1254
1255 static const char *arizona_dai_clk_str(int clk_id)
1256 {
1257         switch (clk_id) {
1258         case ARIZONA_CLK_SYSCLK:
1259                 return "SYSCLK";
1260         case ARIZONA_CLK_ASYNCCLK:
1261                 return "ASYNCCLK";
1262         default:
1263                 return "Unknown clock";
1264         }
1265 }
1266
1267 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1268                                   int clk_id, unsigned int freq, int dir)
1269 {
1270         struct snd_soc_codec *codec = dai->codec;
1271         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1272         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1273         struct snd_soc_dapm_route routes[2];
1274
1275         switch (clk_id) {
1276         case ARIZONA_CLK_SYSCLK:
1277         case ARIZONA_CLK_ASYNCCLK:
1278                 break;
1279         default:
1280                 return -EINVAL;
1281         }
1282
1283         if (clk_id == dai_priv->clk)
1284                 return 0;
1285
1286         if (dai->active) {
1287                 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1288                         dai->id);
1289                 return -EBUSY;
1290         }
1291
1292         dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1293                 arizona_dai_clk_str(clk_id));
1294
1295         memset(&routes, 0, sizeof(routes));
1296         routes[0].sink = dai->driver->capture.stream_name;
1297         routes[1].sink = dai->driver->playback.stream_name;
1298
1299         routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1300         routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1301         snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1302
1303         routes[0].source = arizona_dai_clk_str(clk_id);
1304         routes[1].source = arizona_dai_clk_str(clk_id);
1305         snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1306
1307         dai_priv->clk = clk_id;
1308
1309         return snd_soc_dapm_sync(&codec->dapm);
1310 }
1311
1312 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1313 {
1314         struct snd_soc_codec *codec = dai->codec;
1315         int base = dai->driver->base;
1316         unsigned int reg;
1317
1318         if (tristate)
1319                 reg = ARIZONA_AIF1_TRI;
1320         else
1321                 reg = 0;
1322
1323         return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1324                                    ARIZONA_AIF1_TRI, reg);
1325 }
1326
1327 const struct snd_soc_dai_ops arizona_dai_ops = {
1328         .startup = arizona_startup,
1329         .set_fmt = arizona_set_fmt,
1330         .hw_params = arizona_hw_params,
1331         .set_sysclk = arizona_dai_set_sysclk,
1332         .set_tristate = arizona_set_tristate,
1333 };
1334 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1335
1336 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1337         .startup = arizona_startup,
1338         .hw_params = arizona_hw_params_rate,
1339         .set_sysclk = arizona_dai_set_sysclk,
1340 };
1341 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1342
1343 int arizona_init_dai(struct arizona_priv *priv, int id)
1344 {
1345         struct arizona_dai_priv *dai_priv = &priv->dai[id];
1346
1347         dai_priv->clk = ARIZONA_CLK_SYSCLK;
1348
1349         return 0;
1350 }
1351 EXPORT_SYMBOL_GPL(arizona_init_dai);
1352
1353 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1354 {
1355         struct arizona_fll *fll = data;
1356
1357         arizona_fll_dbg(fll, "clock OK\n");
1358
1359         complete(&fll->ok);
1360
1361         return IRQ_HANDLED;
1362 }
1363
1364 static struct {
1365         unsigned int min;
1366         unsigned int max;
1367         u16 fratio;
1368         int ratio;
1369 } fll_fratios[] = {
1370         {       0,    64000, 4, 16 },
1371         {   64000,   128000, 3,  8 },
1372         {  128000,   256000, 2,  4 },
1373         {  256000,  1000000, 1,  2 },
1374         { 1000000, 13500000, 0,  1 },
1375 };
1376
1377 static struct {
1378         unsigned int min;
1379         unsigned int max;
1380         u16 gain;
1381 } fll_gains[] = {
1382         {       0,   256000, 0 },
1383         {  256000,  1000000, 2 },
1384         { 1000000, 13500000, 4 },
1385 };
1386
1387 struct arizona_fll_cfg {
1388         int n;
1389         int theta;
1390         int lambda;
1391         int refdiv;
1392         int outdiv;
1393         int fratio;
1394         int gain;
1395 };
1396
1397 static int arizona_validate_fll(struct arizona_fll *fll,
1398                                 unsigned int Fref,
1399                                 unsigned int Fout)
1400 {
1401         unsigned int Fvco_min;
1402
1403         if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1404                 arizona_fll_err(fll,
1405                                 "Can't scale %dMHz in to <=13.5MHz\n",
1406                                 Fref);
1407                 return -EINVAL;
1408         }
1409
1410         Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1411         if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1412                 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1413                                 Fout);
1414                 return -EINVAL;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1421 {
1422         int i;
1423
1424         /* Find an appropriate FLL_FRATIO */
1425         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1426                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1427                         if (fratio)
1428                                 *fratio = fll_fratios[i].fratio;
1429                         return fll_fratios[i].ratio;
1430                 }
1431         }
1432
1433         return -EINVAL;
1434 }
1435
1436 static int arizona_calc_fratio(struct arizona_fll *fll,
1437                                struct arizona_fll_cfg *cfg,
1438                                unsigned int target,
1439                                unsigned int Fref, bool sync)
1440 {
1441         int init_ratio, ratio;
1442         int refdiv, div;
1443
1444         /* Fref must be <=13.5MHz, find initial refdiv */
1445         div = 1;
1446         cfg->refdiv = 0;
1447         while (Fref > ARIZONA_FLL_MAX_FREF) {
1448                 div *= 2;
1449                 Fref /= 2;
1450                 cfg->refdiv++;
1451
1452                 if (div > ARIZONA_FLL_MAX_REFDIV)
1453                         return -EINVAL;
1454         }
1455
1456         /* Find an appropriate FLL_FRATIO */
1457         init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1458         if (init_ratio < 0) {
1459                 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1460                                 Fref);
1461                 return init_ratio;
1462         }
1463
1464         switch (fll->arizona->type) {
1465         case WM5110:
1466                 if (fll->arizona->rev < 3 || sync)
1467                         return init_ratio;
1468                 break;
1469         default:
1470                 return init_ratio;
1471         }
1472
1473         cfg->fratio = init_ratio - 1;
1474
1475         /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1476         refdiv = cfg->refdiv;
1477
1478         while (div <= ARIZONA_FLL_MAX_REFDIV) {
1479                 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1480                      ratio++) {
1481                         if (target % (ratio * Fref)) {
1482                                 cfg->refdiv = refdiv;
1483                                 cfg->fratio = ratio - 1;
1484                                 return ratio;
1485                         }
1486                 }
1487
1488                 for (ratio = init_ratio - 1; ratio >= 0; ratio--) {
1489                         if (ARIZONA_FLL_VCO_CORNER / (fll->vco_mult * ratio) <
1490                             Fref)
1491                                 break;
1492
1493                         if (target % (ratio * Fref)) {
1494                                 cfg->refdiv = refdiv;
1495                                 cfg->fratio = ratio - 1;
1496                                 return ratio;
1497                         }
1498                 }
1499
1500                 div *= 2;
1501                 Fref /= 2;
1502                 refdiv++;
1503                 init_ratio = arizona_find_fratio(Fref, NULL);
1504         }
1505
1506         arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1507         return cfg->fratio + 1;
1508 }
1509
1510 static int arizona_calc_fll(struct arizona_fll *fll,
1511                             struct arizona_fll_cfg *cfg,
1512                             unsigned int Fref, bool sync)
1513 {
1514         unsigned int target, div, gcd_fll;
1515         int i, ratio;
1516
1517         arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1518
1519         /* Fvco should be over the targt; don't check the upper bound */
1520         div = ARIZONA_FLL_MIN_OUTDIV;
1521         while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1522                 div++;
1523                 if (div > ARIZONA_FLL_MAX_OUTDIV)
1524                         return -EINVAL;
1525         }
1526         target = fll->fout * div / fll->vco_mult;
1527         cfg->outdiv = div;
1528
1529         arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1530
1531         /* Find an appropriate FLL_FRATIO and refdiv */
1532         ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1533         if (ratio < 0)
1534                 return ratio;
1535
1536         /* Apply the division for our remaining calculations */
1537         Fref = Fref / (1 << cfg->refdiv);
1538
1539         cfg->n = target / (ratio * Fref);
1540
1541         if (target % (ratio * Fref)) {
1542                 gcd_fll = gcd(target, ratio * Fref);
1543                 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1544
1545                 cfg->theta = (target - (cfg->n * ratio * Fref))
1546                         / gcd_fll;
1547                 cfg->lambda = (ratio * Fref) / gcd_fll;
1548         } else {
1549                 cfg->theta = 0;
1550                 cfg->lambda = 0;
1551         }
1552
1553         /* Round down to 16bit range with cost of accuracy lost.
1554          * Denominator must be bigger than numerator so we only
1555          * take care of it.
1556          */
1557         while (cfg->lambda >= (1 << 16)) {
1558                 cfg->theta >>= 1;
1559                 cfg->lambda >>= 1;
1560         }
1561
1562         for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1563                 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1564                         cfg->gain = fll_gains[i].gain;
1565                         break;
1566                 }
1567         }
1568         if (i == ARRAY_SIZE(fll_gains)) {
1569                 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1570                                 Fref);
1571                 return -EINVAL;
1572         }
1573
1574         arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1575                         cfg->n, cfg->theta, cfg->lambda);
1576         arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1577                         cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1578         arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1579
1580         return 0;
1581
1582 }
1583
1584 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1585                               struct arizona_fll_cfg *cfg, int source,
1586                               bool sync)
1587 {
1588         regmap_update_bits_async(arizona->regmap, base + 3,
1589                                  ARIZONA_FLL1_THETA_MASK, cfg->theta);
1590         regmap_update_bits_async(arizona->regmap, base + 4,
1591                                  ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1592         regmap_update_bits_async(arizona->regmap, base + 5,
1593                                  ARIZONA_FLL1_FRATIO_MASK,
1594                                  cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1595         regmap_update_bits_async(arizona->regmap, base + 6,
1596                                  ARIZONA_FLL1_CLK_REF_DIV_MASK |
1597                                  ARIZONA_FLL1_CLK_REF_SRC_MASK,
1598                                  cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1599                                  source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1600
1601         if (sync) {
1602                 regmap_update_bits(arizona->regmap, base + 0x7,
1603                                    ARIZONA_FLL1_GAIN_MASK,
1604                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1605         } else {
1606                 regmap_update_bits(arizona->regmap, base + 0x5,
1607                                    ARIZONA_FLL1_OUTDIV_MASK,
1608                                    cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1609                 regmap_update_bits(arizona->regmap, base + 0x9,
1610                                    ARIZONA_FLL1_GAIN_MASK,
1611                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1612         }
1613
1614         regmap_update_bits_async(arizona->regmap, base + 2,
1615                                  ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1616                                  ARIZONA_FLL1_CTRL_UPD | cfg->n);
1617 }
1618
1619 static bool arizona_is_enabled_fll(struct arizona_fll *fll)
1620 {
1621         struct arizona *arizona = fll->arizona;
1622         unsigned int reg;
1623         int ret;
1624
1625         ret = regmap_read(arizona->regmap, fll->base + 1, &reg);
1626         if (ret != 0) {
1627                 arizona_fll_err(fll, "Failed to read current state: %d\n",
1628                                 ret);
1629                 return ret;
1630         }
1631
1632         return reg & ARIZONA_FLL1_ENA;
1633 }
1634
1635 static void arizona_enable_fll(struct arizona_fll *fll)
1636 {
1637         struct arizona *arizona = fll->arizona;
1638         int ret;
1639         bool use_sync = false;
1640         struct arizona_fll_cfg cfg;
1641
1642         /*
1643          * If we have both REFCLK and SYNCCLK then enable both,
1644          * otherwise apply the SYNCCLK settings to REFCLK.
1645          */
1646         if (fll->ref_src >= 0 && fll->ref_freq &&
1647             fll->ref_src != fll->sync_src) {
1648                 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
1649
1650                 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
1651                                   false);
1652                 if (fll->sync_src >= 0) {
1653                         arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
1654
1655                         arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
1656                                           fll->sync_src, true);
1657                         use_sync = true;
1658                 }
1659         } else if (fll->sync_src >= 0) {
1660                 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
1661
1662                 arizona_apply_fll(arizona, fll->base, &cfg,
1663                                   fll->sync_src, false);
1664
1665                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1666                                          ARIZONA_FLL1_SYNC_ENA, 0);
1667         } else {
1668                 arizona_fll_err(fll, "No clocks provided\n");
1669                 return;
1670         }
1671
1672         /*
1673          * Increase the bandwidth if we're not using a low frequency
1674          * sync source.
1675          */
1676         if (use_sync && fll->sync_freq > 100000)
1677                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1678                                          ARIZONA_FLL1_SYNC_BW, 0);
1679         else
1680                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1681                                          ARIZONA_FLL1_SYNC_BW,
1682                                          ARIZONA_FLL1_SYNC_BW);
1683
1684         if (!arizona_is_enabled_fll(fll))
1685                 pm_runtime_get(arizona->dev);
1686
1687         /* Clear any pending completions */
1688         try_wait_for_completion(&fll->ok);
1689
1690         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1691                                  ARIZONA_FLL1_FREERUN, 0);
1692         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1693                                  ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1694         if (use_sync)
1695                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1696                                          ARIZONA_FLL1_SYNC_ENA,
1697                                          ARIZONA_FLL1_SYNC_ENA);
1698
1699         ret = wait_for_completion_timeout(&fll->ok,
1700                                           msecs_to_jiffies(250));
1701         if (ret == 0)
1702                 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1703 }
1704
1705 static void arizona_disable_fll(struct arizona_fll *fll)
1706 {
1707         struct arizona *arizona = fll->arizona;
1708         bool change;
1709
1710         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1711                                  ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
1712         regmap_update_bits_check(arizona->regmap, fll->base + 1,
1713                                  ARIZONA_FLL1_ENA, 0, &change);
1714         regmap_update_bits(arizona->regmap, fll->base + 0x11,
1715                            ARIZONA_FLL1_SYNC_ENA, 0);
1716
1717         if (change)
1718                 pm_runtime_put_autosuspend(arizona->dev);
1719 }
1720
1721 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1722                            unsigned int Fref, unsigned int Fout)
1723 {
1724         int ret;
1725
1726         if (fll->ref_src == source && fll->ref_freq == Fref)
1727                 return 0;
1728
1729         if (fll->fout && Fref > 0) {
1730                 ret = arizona_validate_fll(fll, Fref, fll->fout);
1731                 if (ret != 0)
1732                         return ret;
1733         }
1734
1735         fll->ref_src = source;
1736         fll->ref_freq = Fref;
1737
1738         if (fll->fout && Fref > 0) {
1739                 arizona_enable_fll(fll);
1740         }
1741
1742         return 0;
1743 }
1744 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1745
1746 int arizona_set_fll(struct arizona_fll *fll, int source,
1747                     unsigned int Fref, unsigned int Fout)
1748 {
1749         int ret;
1750
1751         if (fll->sync_src == source &&
1752             fll->sync_freq == Fref && fll->fout == Fout)
1753                 return 0;
1754
1755         if (Fout) {
1756                 if (fll->ref_src >= 0) {
1757                         ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
1758                         if (ret != 0)
1759                                 return ret;
1760                 }
1761
1762                 ret = arizona_validate_fll(fll, Fref, Fout);
1763                 if (ret != 0)
1764                         return ret;
1765         }
1766
1767         fll->sync_src = source;
1768         fll->sync_freq = Fref;
1769         fll->fout = Fout;
1770
1771         if (Fout) {
1772                 arizona_enable_fll(fll);
1773         } else {
1774                 arizona_disable_fll(fll);
1775         }
1776
1777         return 0;
1778 }
1779 EXPORT_SYMBOL_GPL(arizona_set_fll);
1780
1781 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1782                      int ok_irq, struct arizona_fll *fll)
1783 {
1784         int ret;
1785         unsigned int val;
1786
1787         init_completion(&fll->ok);
1788
1789         fll->id = id;
1790         fll->base = base;
1791         fll->arizona = arizona;
1792         fll->sync_src = ARIZONA_FLL_SRC_NONE;
1793
1794         /* Configure default refclk to 32kHz if we have one */
1795         regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1796         switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1797         case ARIZONA_CLK_SRC_MCLK1:
1798         case ARIZONA_CLK_SRC_MCLK2:
1799                 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
1800                 break;
1801         default:
1802                 fll->ref_src = ARIZONA_FLL_SRC_NONE;
1803         }
1804         fll->ref_freq = 32768;
1805
1806         snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1807         snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1808                  "FLL%d clock OK", id);
1809
1810         ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1811                                   arizona_fll_clock_ok, fll);
1812         if (ret != 0) {
1813                 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1814                         id, ret);
1815         }
1816
1817         regmap_update_bits(arizona->regmap, fll->base + 1,
1818                            ARIZONA_FLL1_FREERUN, 0);
1819
1820         return 0;
1821 }
1822 EXPORT_SYMBOL_GPL(arizona_init_fll);
1823
1824 /**
1825  * arizona_set_output_mode - Set the mode of the specified output
1826  *
1827  * @codec: Device to configure
1828  * @output: Output number
1829  * @diff: True to set the output to differential mode
1830  *
1831  * Some systems use external analogue switches to connect more
1832  * analogue devices to the CODEC than are supported by the device.  In
1833  * some systems this requires changing the switched output from single
1834  * ended to differential mode dynamically at runtime, an operation
1835  * supported using this function.
1836  *
1837  * Most systems have a single static configuration and should use
1838  * platform data instead.
1839  */
1840 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
1841 {
1842         unsigned int reg, val;
1843
1844         if (output < 1 || output > 6)
1845                 return -EINVAL;
1846
1847         reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
1848
1849         if (diff)
1850                 val = ARIZONA_OUT1_MONO;
1851         else
1852                 val = 0;
1853
1854         return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
1855 }
1856 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
1857
1858 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1859 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1860 MODULE_LICENSE("GPL");