2 * Copyright (C) 2014-2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dai.h>
26 #include "cygnus-ssp.h"
28 #define DEFAULT_VCO 1354750204
30 #define CAPTURE_FCI_ID_BASE 0x180
31 #define CYGNUS_SSP_TRISTATE_MASK 0x001fff
32 #define CYGNUS_PLLCLKSEL_MASK 0xf
34 /* Used with stream_on field to indicate which streams are active */
35 #define PLAYBACK_STREAM_MASK BIT(0)
36 #define CAPTURE_STREAM_MASK BIT(1)
38 #define I2S_STREAM_CFG_MASK 0xff003ff
39 #define I2S_CAP_STREAM_CFG_MASK 0xf0
40 #define SPDIF_STREAM_CFG_MASK 0x3ff
41 #define CH_GRP_STEREO 0x1
43 /* Begin register offset defines */
44 #define AUD_MISC_SEROUT_OE_REG_BASE 0x01c
45 #define AUD_MISC_SEROUT_SPDIF_OE 12
46 #define AUD_MISC_SEROUT_MCLK_OE 3
47 #define AUD_MISC_SEROUT_LRCK_OE 2
48 #define AUD_MISC_SEROUT_SCLK_OE 1
49 #define AUD_MISC_SEROUT_SDAT_OE 0
51 /* AUD_FMM_BF_CTRL_xxx regs */
52 #define BF_DST_CFG0_OFFSET 0x100
53 #define BF_DST_CFG1_OFFSET 0x104
54 #define BF_DST_CFG2_OFFSET 0x108
56 #define BF_DST_CTRL0_OFFSET 0x130
57 #define BF_DST_CTRL1_OFFSET 0x134
58 #define BF_DST_CTRL2_OFFSET 0x138
60 #define BF_SRC_CFG0_OFFSET 0x148
61 #define BF_SRC_CFG1_OFFSET 0x14c
62 #define BF_SRC_CFG2_OFFSET 0x150
63 #define BF_SRC_CFG3_OFFSET 0x154
65 #define BF_SRC_CTRL0_OFFSET 0x1c0
66 #define BF_SRC_CTRL1_OFFSET 0x1c4
67 #define BF_SRC_CTRL2_OFFSET 0x1c8
68 #define BF_SRC_CTRL3_OFFSET 0x1cc
70 #define BF_SRC_GRP0_OFFSET 0x1fc
71 #define BF_SRC_GRP1_OFFSET 0x200
72 #define BF_SRC_GRP2_OFFSET 0x204
73 #define BF_SRC_GRP3_OFFSET 0x208
75 #define BF_SRC_GRP_EN_OFFSET 0x320
76 #define BF_SRC_GRP_FLOWON_OFFSET 0x324
77 #define BF_SRC_GRP_SYNC_DIS_OFFSET 0x328
79 /* AUD_FMM_IOP_OUT_I2S_xxx regs */
80 #define OUT_I2S_0_STREAM_CFG_OFFSET 0xa00
81 #define OUT_I2S_0_CFG_OFFSET 0xa04
82 #define OUT_I2S_0_MCLK_CFG_OFFSET 0xa0c
84 #define OUT_I2S_1_STREAM_CFG_OFFSET 0xa40
85 #define OUT_I2S_1_CFG_OFFSET 0xa44
86 #define OUT_I2S_1_MCLK_CFG_OFFSET 0xa4c
88 #define OUT_I2S_2_STREAM_CFG_OFFSET 0xa80
89 #define OUT_I2S_2_CFG_OFFSET 0xa84
90 #define OUT_I2S_2_MCLK_CFG_OFFSET 0xa8c
92 /* AUD_FMM_IOP_OUT_SPDIF_xxx regs */
93 #define SPDIF_STREAM_CFG_OFFSET 0xac0
94 #define SPDIF_CTRL_OFFSET 0xac4
95 #define SPDIF_FORMAT_CFG_OFFSET 0xad8
96 #define SPDIF_MCLK_CFG_OFFSET 0xadc
98 /* AUD_FMM_IOP_PLL_0_xxx regs */
99 #define IOP_PLL_0_MACRO_OFFSET 0xb00
100 #define IOP_PLL_0_MDIV_Ch0_OFFSET 0xb14
101 #define IOP_PLL_0_MDIV_Ch1_OFFSET 0xb18
102 #define IOP_PLL_0_MDIV_Ch2_OFFSET 0xb1c
104 #define IOP_PLL_0_ACTIVE_MDIV_Ch0_OFFSET 0xb30
105 #define IOP_PLL_0_ACTIVE_MDIV_Ch1_OFFSET 0xb34
106 #define IOP_PLL_0_ACTIVE_MDIV_Ch2_OFFSET 0xb38
108 /* AUD_FMM_IOP_xxx regs */
109 #define IOP_PLL_0_CONTROL_OFFSET 0xb04
110 #define IOP_PLL_0_USER_NDIV_OFFSET 0xb08
111 #define IOP_PLL_0_ACTIVE_NDIV_OFFSET 0xb20
112 #define IOP_PLL_0_RESET_OFFSET 0xb5c
114 /* AUD_FMM_IOP_IN_I2S_xxx regs */
115 #define IN_I2S_0_STREAM_CFG_OFFSET 0x00
116 #define IN_I2S_0_CFG_OFFSET 0x04
117 #define IN_I2S_1_STREAM_CFG_OFFSET 0x40
118 #define IN_I2S_1_CFG_OFFSET 0x44
119 #define IN_I2S_2_STREAM_CFG_OFFSET 0x80
120 #define IN_I2S_2_CFG_OFFSET 0x84
122 /* AUD_FMM_IOP_MISC_xxx regs */
123 #define IOP_SW_INIT_LOGIC 0x1c0
125 /* End register offset defines */
128 /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_0_REG */
129 #define I2S_OUT_MCLKRATE_SHIFT 16
131 /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_REG */
132 #define I2S_OUT_PLLCLKSEL_SHIFT 0
134 /* AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG */
135 #define I2S_OUT_STREAM_ENA 31
136 #define I2S_OUT_STREAM_CFG_GROUP_ID 20
137 #define I2S_OUT_STREAM_CFG_CHANNEL_GROUPING 24
139 /* AUD_FMM_IOP_IN_I2S_x_CAP */
140 #define I2S_IN_STREAM_CFG_CAP_ENA 31
141 #define I2S_IN_STREAM_CFG_0_GROUP_ID 4
143 /* AUD_FMM_IOP_OUT_I2S_x_I2S_CFG_REG */
144 #define I2S_OUT_CFGX_CLK_ENA 0
145 #define I2S_OUT_CFGX_DATA_ENABLE 1
146 #define I2S_OUT_CFGX_DATA_ALIGNMENT 6
147 #define I2S_OUT_CFGX_BITS_PER_SLOT 13
148 #define I2S_OUT_CFGX_VALID_SLOT 14
149 #define I2S_OUT_CFGX_FSYNC_WIDTH 18
150 #define I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32 26
151 #define I2S_OUT_CFGX_SLAVE_MODE 30
152 #define I2S_OUT_CFGX_TDM_MODE 31
154 /* AUD_FMM_BF_CTRL_SOURCECH_CFGx_REG */
155 #define BF_SRC_CFGX_SFIFO_ENA 0
156 #define BF_SRC_CFGX_BUFFER_PAIR_ENABLE 1
157 #define BF_SRC_CFGX_SAMPLE_CH_MODE 2
158 #define BF_SRC_CFGX_SFIFO_SZ_DOUBLE 5
159 #define BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY 10
160 #define BF_SRC_CFGX_BIT_RES 20
161 #define BF_SRC_CFGX_PROCESS_SEQ_ID_VALID 31
163 /* AUD_FMM_BF_CTRL_DESTCH_CFGx_REG */
164 #define BF_DST_CFGX_CAP_ENA 0
165 #define BF_DST_CFGX_BUFFER_PAIR_ENABLE 1
166 #define BF_DST_CFGX_DFIFO_SZ_DOUBLE 2
167 #define BF_DST_CFGX_NOT_PAUSE_WHEN_FULL 11
168 #define BF_DST_CFGX_FCI_ID 12
169 #define BF_DST_CFGX_CAP_MODE 24
170 #define BF_DST_CFGX_PROC_SEQ_ID_VALID 31
172 /* AUD_FMM_IOP_OUT_SPDIF_xxx */
173 #define SPDIF_0_OUT_DITHER_ENA 3
174 #define SPDIF_0_OUT_STREAM_ENA 31
176 /* AUD_FMM_IOP_PLL_0_USER */
177 #define IOP_PLL_0_USER_NDIV_FRAC 10
179 /* AUD_FMM_IOP_PLL_0_ACTIVE */
180 #define IOP_PLL_0_ACTIVE_NDIV_FRAC 10
183 #define INIT_SSP_REGS(num) (struct cygnus_ssp_regs){ \
184 .i2s_stream_cfg = OUT_I2S_ ##num## _STREAM_CFG_OFFSET, \
185 .i2s_cap_stream_cfg = IN_I2S_ ##num## _STREAM_CFG_OFFSET, \
186 .i2s_cfg = OUT_I2S_ ##num## _CFG_OFFSET, \
187 .i2s_cap_cfg = IN_I2S_ ##num## _CFG_OFFSET, \
188 .i2s_mclk_cfg = OUT_I2S_ ##num## _MCLK_CFG_OFFSET, \
189 .bf_destch_ctrl = BF_DST_CTRL ##num## _OFFSET, \
190 .bf_destch_cfg = BF_DST_CFG ##num## _OFFSET, \
191 .bf_sourcech_ctrl = BF_SRC_CTRL ##num## _OFFSET, \
192 .bf_sourcech_cfg = BF_SRC_CFG ##num## _OFFSET, \
193 .bf_sourcech_grp = BF_SRC_GRP ##num## _OFFSET \
196 struct pll_macro_entry {
202 * PLL has 3 output channels (1x, 2x, and 4x). Below are
203 * the common MCLK frequencies used by audio driver
205 static const struct pll_macro_entry pll_predef_mclk[] = {
231 #define CYGNUS_RATE_MIN 8000
232 #define CYGNUS_RATE_MAX 384000
234 /* List of valid frame sizes for tdm mode */
235 static const int ssp_valid_tdm_framesize[] = {32, 64, 128, 256, 512};
237 static const unsigned int cygnus_rates[] = {
238 8000, 11025, 16000, 22050, 32000, 44100, 48000,
239 88200, 96000, 176400, 192000, 352800, 384000
242 static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = {
243 .count = ARRAY_SIZE(cygnus_rates),
244 .list = cygnus_rates,
247 static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai)
249 struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
251 return &cygaud->portinfo[dai->id];
254 static int audio_ssp_init_portregs(struct cygnus_aio_port *aio)
259 switch (aio->port_type) {
261 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
262 value &= ~I2S_STREAM_CFG_MASK;
266 aio->cygaud->audio + aio->regs.bf_sourcech_grp);
268 /* Configure the AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG reg */
269 value |= aio->portnum << I2S_OUT_STREAM_CFG_GROUP_ID;
270 value |= aio->portnum; /* FCI ID is the port num */
271 value |= CH_GRP_STEREO << I2S_OUT_STREAM_CFG_CHANNEL_GROUPING;
272 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
274 /* Configure the AUD_FMM_BF_CTRL_SOURCECH_CFGX reg */
275 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
276 value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
277 value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
278 value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
279 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
281 /* Configure the AUD_FMM_IOP_IN_I2S_x_CAP_STREAM_CFG_0 reg */
282 value = readl(aio->cygaud->i2s_in +
283 aio->regs.i2s_cap_stream_cfg);
284 value &= ~I2S_CAP_STREAM_CFG_MASK;
285 value |= aio->portnum << I2S_IN_STREAM_CFG_0_GROUP_ID;
286 writel(value, aio->cygaud->i2s_in +
287 aio->regs.i2s_cap_stream_cfg);
289 /* Configure the AUD_FMM_BF_CTRL_DESTCH_CFGX_REG_BASE reg */
290 fci_id = CAPTURE_FCI_ID_BASE + aio->portnum;
292 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
293 value |= BIT(BF_DST_CFGX_DFIFO_SZ_DOUBLE);
294 value &= ~BIT(BF_DST_CFGX_NOT_PAUSE_WHEN_FULL);
295 value |= (fci_id << BF_DST_CFGX_FCI_ID);
296 value |= BIT(BF_DST_CFGX_PROC_SEQ_ID_VALID);
297 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
299 /* Enable the transmit pin for this port */
300 value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
301 value &= ~BIT((aio->portnum * 4) + AUD_MISC_SEROUT_SDAT_OE);
302 writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
305 writel(aio->portnum, aio->cygaud->audio + BF_SRC_GRP3_OFFSET);
307 value = readl(aio->cygaud->audio + SPDIF_CTRL_OFFSET);
308 value |= BIT(SPDIF_0_OUT_DITHER_ENA);
309 writel(value, aio->cygaud->audio + SPDIF_CTRL_OFFSET);
311 /* Enable and set the FCI ID for the SPDIF channel */
312 value = readl(aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
313 value &= ~SPDIF_STREAM_CFG_MASK;
314 value |= aio->portnum; /* FCI ID is the port num */
315 value |= BIT(SPDIF_0_OUT_STREAM_ENA);
316 writel(value, aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
318 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
319 value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
320 value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
321 value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
322 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
324 /* Enable the spdif output pin */
325 value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
326 value &= ~BIT(AUD_MISC_SEROUT_SPDIF_OE);
327 writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
330 dev_err(aio->cygaud->dev, "Port not supported\n");
337 static void audio_ssp_in_enable(struct cygnus_aio_port *aio)
341 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
342 value |= BIT(BF_DST_CFGX_CAP_ENA);
343 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
345 writel(0x1, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
347 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
348 value |= BIT(I2S_OUT_CFGX_CLK_ENA);
349 value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
350 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
352 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
353 value |= BIT(I2S_IN_STREAM_CFG_CAP_ENA);
354 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
356 aio->streams_on |= CAPTURE_STREAM_MASK;
359 static void audio_ssp_in_disable(struct cygnus_aio_port *aio)
363 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
364 value &= ~BIT(I2S_IN_STREAM_CFG_CAP_ENA);
365 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
367 aio->streams_on &= ~CAPTURE_STREAM_MASK;
369 /* If both playback and capture are off */
370 if (!aio->streams_on) {
371 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
372 value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
373 value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
374 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
377 writel(0x0, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
379 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
380 value &= ~BIT(BF_DST_CFGX_CAP_ENA);
381 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
384 static int audio_ssp_out_enable(struct cygnus_aio_port *aio)
389 switch (aio->port_type) {
391 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
392 value |= BIT(I2S_OUT_STREAM_ENA);
393 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
395 writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
397 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
398 value |= BIT(I2S_OUT_CFGX_CLK_ENA);
399 value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
400 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
402 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
403 value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
404 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
406 aio->streams_on |= PLAYBACK_STREAM_MASK;
409 value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
411 writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
413 writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
415 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
416 value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
417 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
420 dev_err(aio->cygaud->dev,
421 "Port not supported %d\n", aio->portnum);
428 static int audio_ssp_out_disable(struct cygnus_aio_port *aio)
433 switch (aio->port_type) {
435 aio->streams_on &= ~PLAYBACK_STREAM_MASK;
437 /* If both playback and capture are off */
438 if (!aio->streams_on) {
439 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
440 value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
441 value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
442 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
445 /* set group_sync_dis = 1 */
446 value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
447 value |= BIT(aio->portnum);
448 writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
450 writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
452 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
453 value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
454 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
456 /* set group_sync_dis = 0 */
457 value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
458 value &= ~BIT(aio->portnum);
459 writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
461 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
462 value &= ~BIT(I2S_OUT_STREAM_ENA);
463 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
465 /* IOP SW INIT on OUT_I2S_x */
466 value = readl(aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
467 value |= BIT(aio->portnum);
468 writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
469 value &= ~BIT(aio->portnum);
470 writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
473 value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
475 writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
476 writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
478 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
479 value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
480 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
483 dev_err(aio->cygaud->dev,
484 "Port not supported %d\n", aio->portnum);
491 static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk,
492 struct cygnus_aio_port *aio)
496 const struct pll_macro_entry *p_entry;
499 for (i = 0; i < ARRAY_SIZE(pll_predef_mclk); i++) {
500 p_entry = &pll_predef_mclk[i];
501 if (p_entry->mclk == mclk) {
508 "%s No valid mclk freq (%u) found!\n", __func__, mclk);
512 ch_clk = cygaud->audio_clk[p_entry->pll_ch_num];
514 if ((aio->clk_trace.cap_en) && (!aio->clk_trace.cap_clk_en)) {
515 error = clk_prepare_enable(ch_clk);
517 dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
521 aio->clk_trace.cap_clk_en = true;
524 if ((aio->clk_trace.play_en) && (!aio->clk_trace.play_clk_en)) {
525 error = clk_prepare_enable(ch_clk);
527 dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
531 aio->clk_trace.play_clk_en = true;
534 error = clk_set_rate(ch_clk, mclk);
536 dev_err(cygaud->dev, "%s Set MCLK rate failed: %d\n",
541 return p_entry->pll_ch_num;
544 static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio)
550 unsigned int bit_rate;
553 bit_rate = aio->bit_per_frame * aio->lrclk;
556 * Check if the bit clock can be generated from the given MCLK.
557 * MCLK must be a perfect multiple of bit clock and must be one of the
558 * following values... (2,4,6,8,10,12,14)
560 if ((aio->mclk % bit_rate) != 0)
563 ratio = aio->mclk / bit_rate;
572 mclk_rate = ratio / 2;
576 dev_err(aio->cygaud->dev,
577 "Invalid combination of MCLK and BCLK\n");
578 dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n",
579 aio->lrclk, aio->bit_per_frame, aio->mclk);
584 switch (aio->port_type) {
586 sclk = aio->bit_per_frame;
590 /* sclks_per_1fs_div = sclk cycles/32 */
593 /* Set number of bitclks per frame */
594 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
595 value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
596 value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32;
597 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
598 dev_dbg(aio->cygaud->dev,
599 "SCLKS_PER_1FS_DIV32 = 0x%x\n", value);
604 dev_err(aio->cygaud->dev, "Unknown port type\n");
608 /* Set MCLK_RATE ssp port (spdif and ssp are the same) */
609 value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
610 value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
611 value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
612 writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
614 dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
615 dev_dbg(aio->cygaud->dev, "bits per frame = %u, mclk = %u Hz, lrclk = %u Hz\n",
616 aio->bit_per_frame, aio->mclk, aio->lrclk);
620 static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
621 struct snd_pcm_hw_params *params,
622 struct snd_soc_dai *dai)
624 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
630 dev_dbg(aio->cygaud->dev, "%s port = %d\n", __func__, aio->portnum);
631 dev_dbg(aio->cygaud->dev, "params_channels %d\n",
632 params_channels(params));
633 dev_dbg(aio->cygaud->dev, "rate %d\n", params_rate(params));
634 dev_dbg(aio->cygaud->dev, "format %d\n", params_format(params));
636 rate = params_rate(params);
639 case CYGNUS_SSPMODE_TDM:
640 if ((rate == 192000) && (params_channels(params) > 4)) {
641 dev_err(aio->cygaud->dev, "Cannot run %d channels at %dHz\n",
642 params_channels(params), rate);
646 case CYGNUS_SSPMODE_I2S:
647 aio->bit_per_frame = 64; /* I2S must be 64 bit per frame */
650 dev_err(aio->cygaud->dev,
651 "%s port running in unknown mode\n", __func__);
655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
656 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
657 value &= ~BIT(BF_SRC_CFGX_BUFFER_PAIR_ENABLE);
658 /* Configure channels as mono or stereo/TDM */
659 if (params_channels(params) == 1)
660 value |= BIT(BF_SRC_CFGX_SAMPLE_CH_MODE);
662 value &= ~BIT(BF_SRC_CFGX_SAMPLE_CH_MODE);
663 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
665 switch (params_format(params)) {
666 case SNDRV_PCM_FORMAT_S8:
667 if (aio->port_type == PORT_SPDIF) {
668 dev_err(aio->cygaud->dev,
669 "SPDIF does not support 8bit format\n");
675 case SNDRV_PCM_FORMAT_S16_LE:
679 case SNDRV_PCM_FORMAT_S32_LE:
680 /* 32 bit mode is coded as 0 */
688 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
689 value &= ~(mask << BF_SRC_CFGX_BIT_RES);
690 value |= (bitres << BF_SRC_CFGX_BIT_RES);
691 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
695 switch (params_format(params)) {
696 case SNDRV_PCM_FORMAT_S16_LE:
697 value = readl(aio->cygaud->audio +
698 aio->regs.bf_destch_cfg);
699 value |= BIT(BF_DST_CFGX_CAP_MODE);
700 writel(value, aio->cygaud->audio +
701 aio->regs.bf_destch_cfg);
704 case SNDRV_PCM_FORMAT_S32_LE:
705 value = readl(aio->cygaud->audio +
706 aio->regs.bf_destch_cfg);
707 value &= ~BIT(BF_DST_CFGX_CAP_MODE);
708 writel(value, aio->cygaud->audio +
709 aio->regs.bf_destch_cfg);
720 ret = cygnus_ssp_set_clocks(aio);
726 * This function sets the mclk frequency for pll clock
728 static int cygnus_ssp_set_sysclk(struct snd_soc_dai *dai,
729 int clk_id, unsigned int freq, int dir)
733 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
734 struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
736 dev_dbg(aio->cygaud->dev,
737 "%s Enter port = %d\n", __func__, aio->portnum);
738 sel = pll_configure_mclk(cygaud, freq, aio);
740 dev_err(aio->cygaud->dev,
741 "%s Setting mclk failed.\n", __func__);
747 dev_dbg(aio->cygaud->dev, "%s Setting MCLKSEL to %d\n", __func__, sel);
748 value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
749 value &= ~(0xf << I2S_OUT_PLLCLKSEL_SHIFT);
750 value |= (sel << I2S_OUT_PLLCLKSEL_SHIFT);
751 writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
756 static int cygnus_ssp_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *dai)
759 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
761 snd_soc_dai_set_dma_data(dai, substream, aio);
762 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
763 aio->clk_trace.play_en = true;
765 aio->clk_trace.cap_en = true;
767 substream->runtime->hw.rate_min = CYGNUS_RATE_MIN;
768 substream->runtime->hw.rate_max = CYGNUS_RATE_MAX;
770 snd_pcm_hw_constraint_list(substream->runtime, 0,
771 SNDRV_PCM_HW_PARAM_RATE, &cygnus_rate_constraint);
775 static void cygnus_ssp_shutdown(struct snd_pcm_substream *substream,
776 struct snd_soc_dai *dai)
778 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
781 aio->clk_trace.play_en = false;
783 aio->clk_trace.cap_en = false;
785 if (!aio->is_slave) {
788 val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
789 val &= CYGNUS_PLLCLKSEL_MASK;
790 if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
791 dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
796 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
797 if (aio->clk_trace.play_clk_en) {
798 clk_disable_unprepare(aio->cygaud->
800 aio->clk_trace.play_clk_en = false;
803 if (aio->clk_trace.cap_clk_en) {
804 clk_disable_unprepare(aio->cygaud->
806 aio->clk_trace.cap_clk_en = false;
814 * 31 Yes TDM Mode (1 = TDM, 0 = i2s)
815 * 30 Yes Slave Mode (1 = Slave, 0 = Master)
816 * 29:26 No Sclks per frame
818 * 17:14 No Valid Slots
819 * 13 No Bits (1 = 16 bits, 0 = 32 bits)
820 * 12:08 No Bits per samp
821 * 07 Yes Justifcation (1 = LSB, 0 = MSB)
822 * 06 Yes Alignment (1 = Delay 1 clk, 0 = no delay
823 * 05 Yes SCLK polarity (1 = Rising, 0 = Falling)
824 * 04 Yes LRCLK Polarity (1 = High for left, 0 = Low for left)
825 * 03:02 Yes Reserved - write as zero
829 #define I2S_OUT_CFG_REG_UPDATE_MASK 0x3C03FF03
831 /* Input cfg is same as output, but the FS width is not a valid field */
832 #define I2S_IN_CFG_REG_UPDATE_MASK (I2S_OUT_CFG_REG_UPDATE_MASK | 0x03FC0000)
834 int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, int len)
836 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
838 if ((len > 0) && (len < 256)) {
839 aio->fsync_width = len;
846 static int cygnus_ssp_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
848 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
856 dev_dbg(aio->cygaud->dev, "%s Enter fmt: %x\n", __func__, fmt);
858 if (aio->port_type == PORT_SPDIF)
863 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
864 case SND_SOC_DAIFMT_CBM_CFM:
865 ssp_newcfg |= BIT(I2S_OUT_CFGX_SLAVE_MODE);
868 case SND_SOC_DAIFMT_CBS_CFS:
869 ssp_newcfg &= ~BIT(I2S_OUT_CFGX_SLAVE_MODE);
876 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
877 case SND_SOC_DAIFMT_I2S:
878 ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
879 ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
880 aio->mode = CYGNUS_SSPMODE_I2S;
883 case SND_SOC_DAIFMT_DSP_A:
884 case SND_SOC_DAIFMT_DSP_B:
885 ssp_newcfg |= BIT(I2S_OUT_CFGX_TDM_MODE);
887 /* DSP_A = data after FS, DSP_B = data during FS */
888 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A)
889 ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
891 if ((aio->fsync_width > 0) && (aio->fsync_width < 256))
893 (aio->fsync_width << I2S_OUT_CFGX_FSYNC_WIDTH);
895 ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
897 aio->mode = CYGNUS_SSPMODE_TDM;
906 * Retain bits we do not want to update, then OR in new bits
908 ssp_curcfg = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
909 ssp_outcfg = (ssp_curcfg & I2S_OUT_CFG_REG_UPDATE_MASK) | ssp_newcfg;
910 writel(ssp_outcfg, aio->cygaud->audio + aio->regs.i2s_cfg);
914 * Retain bits we do not want to update, then OR in new bits
916 ssp_curcfg = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
917 ssp_incfg = (ssp_curcfg & I2S_IN_CFG_REG_UPDATE_MASK) | ssp_newcfg;
918 writel(ssp_incfg, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
920 val = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
923 * Configure the word clk and bit clk as output or tristate
924 * Each port has 4 bits for controlling its pins.
925 * Shift the mask based upon port number.
927 mask = BIT(AUD_MISC_SEROUT_LRCK_OE)
928 | BIT(AUD_MISC_SEROUT_SCLK_OE)
929 | BIT(AUD_MISC_SEROUT_MCLK_OE);
930 mask = mask << (aio->portnum * 4);
932 /* Set bit for tri-state */
935 /* Clear bit for drive */
938 dev_dbg(aio->cygaud->dev, "%s Set OE bits 0x%x\n", __func__, val);
939 writel(val, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
944 static int cygnus_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
945 struct snd_soc_dai *dai)
947 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
948 struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
950 dev_dbg(aio->cygaud->dev,
951 "%s cmd %d at port = %d\n", __func__, cmd, aio->portnum);
954 case SNDRV_PCM_TRIGGER_START:
955 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
956 case SNDRV_PCM_TRIGGER_RESUME:
957 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
958 audio_ssp_out_enable(aio);
960 audio_ssp_in_enable(aio);
961 cygaud->active_ports++;
965 case SNDRV_PCM_TRIGGER_STOP:
966 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
967 case SNDRV_PCM_TRIGGER_SUSPEND:
968 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
969 audio_ssp_out_disable(aio);
971 audio_ssp_in_disable(aio);
972 cygaud->active_ports--;
982 static int cygnus_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
983 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
985 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
987 int bits_per_slot = 0; /* default to 32-bits per slot */
989 unsigned int active_slots;
993 if (tx_mask != rx_mask) {
994 dev_err(aio->cygaud->dev,
995 "%s tx_mask must equal rx_mask\n", __func__);
999 active_slots = hweight32(tx_mask);
1001 if ((active_slots < 0) || (active_slots > 16))
1004 /* Slot value must be even */
1005 if (active_slots % 2)
1008 /* We encode 16 slots as 0 in the reg */
1009 if (active_slots == 16)
1012 /* Slot Width is either 16 or 32 */
1013 switch (slot_width) {
1022 dev_warn(aio->cygaud->dev,
1023 "%s Defaulting Slot Width to 32\n", __func__);
1026 frame_bits = slots * slot_width;
1028 for (i = 0; i < ARRAY_SIZE(ssp_valid_tdm_framesize); i++) {
1029 if (ssp_valid_tdm_framesize[i] == frame_bits) {
1036 dev_err(aio->cygaud->dev,
1037 "%s In TDM mode, frame bits INVALID (%d)\n",
1038 __func__, frame_bits);
1042 aio->bit_per_frame = frame_bits;
1044 dev_dbg(aio->cygaud->dev, "%s active_slots %u, bits per frame %d\n",
1045 __func__, active_slots, frame_bits);
1047 /* Set capture side of ssp port */
1048 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
1049 value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
1050 value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
1051 value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
1052 value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
1053 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
1055 /* Set playback side of ssp port */
1056 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
1057 value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
1058 value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
1059 value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
1060 value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
1061 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
1066 #ifdef CONFIG_PM_SLEEP
1067 static int cygnus_ssp_suspend(struct snd_soc_dai *cpu_dai)
1069 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
1071 if (!aio->is_slave) {
1074 val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
1075 val &= CYGNUS_PLLCLKSEL_MASK;
1076 if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
1077 dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
1082 if (aio->clk_trace.cap_clk_en)
1083 clk_disable_unprepare(aio->cygaud->audio_clk[val]);
1084 if (aio->clk_trace.play_clk_en)
1085 clk_disable_unprepare(aio->cygaud->audio_clk[val]);
1087 aio->pll_clk_num = val;
1093 static int cygnus_ssp_resume(struct snd_soc_dai *cpu_dai)
1095 struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
1098 if (!aio->is_slave) {
1099 if (aio->clk_trace.cap_clk_en) {
1100 error = clk_prepare_enable(aio->cygaud->
1101 audio_clk[aio->pll_clk_num]);
1103 dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
1108 if (aio->clk_trace.play_clk_en) {
1109 error = clk_prepare_enable(aio->cygaud->
1110 audio_clk[aio->pll_clk_num]);
1112 if (aio->clk_trace.cap_clk_en)
1113 clk_disable_unprepare(aio->cygaud->
1114 audio_clk[aio->pll_clk_num]);
1115 dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
1125 #define cygnus_ssp_suspend NULL
1126 #define cygnus_ssp_resume NULL
1129 static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
1130 .startup = cygnus_ssp_startup,
1131 .shutdown = cygnus_ssp_shutdown,
1132 .trigger = cygnus_ssp_trigger,
1133 .hw_params = cygnus_ssp_hw_params,
1134 .set_fmt = cygnus_ssp_set_fmt,
1135 .set_sysclk = cygnus_ssp_set_sysclk,
1136 .set_tdm_slot = cygnus_set_dai_tdm_slot,
1140 #define INIT_CPU_DAI(num) { \
1141 .name = "cygnus-ssp" #num, \
1143 .channels_min = 1, \
1144 .channels_max = 16, \
1145 .rates = SNDRV_PCM_RATE_KNOT, \
1146 .formats = SNDRV_PCM_FMTBIT_S8 | \
1147 SNDRV_PCM_FMTBIT_S16_LE | \
1148 SNDRV_PCM_FMTBIT_S32_LE, \
1151 .channels_min = 2, \
1152 .channels_max = 16, \
1153 .rates = SNDRV_PCM_RATE_KNOT, \
1154 .formats = SNDRV_PCM_FMTBIT_S16_LE | \
1155 SNDRV_PCM_FMTBIT_S32_LE, \
1157 .ops = &cygnus_ssp_dai_ops, \
1158 .suspend = cygnus_ssp_suspend, \
1159 .resume = cygnus_ssp_resume, \
1162 static const struct snd_soc_dai_driver cygnus_ssp_dai_info[] = {
1168 static const struct snd_soc_dai_driver cygnus_spdif_dai_info = {
1169 .name = "cygnus-spdif",
1173 .rates = SNDRV_PCM_RATE_KNOT,
1174 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1175 SNDRV_PCM_FMTBIT_S32_LE,
1177 .ops = &cygnus_ssp_dai_ops,
1178 .suspend = cygnus_ssp_suspend,
1179 .resume = cygnus_ssp_resume,
1182 static struct snd_soc_dai_driver cygnus_ssp_dai[CYGNUS_MAX_PORTS];
1184 static const struct snd_soc_component_driver cygnus_ssp_component = {
1185 .name = "cygnus-audio",
1189 * Return < 0 if error
1190 * Return 0 if disabled
1191 * Return 1 if enabled and node is parsed successfully
1193 static int parse_ssp_child_node(struct platform_device *pdev,
1194 struct device_node *dn,
1195 struct cygnus_audio *cygaud,
1196 struct snd_soc_dai_driver *p_dai)
1198 struct cygnus_aio_port *aio;
1199 struct cygnus_ssp_regs ssp_regs[3];
1202 enum cygnus_audio_port_type port_type;
1204 if (of_property_read_u32(dn, "reg", &rawval)) {
1205 dev_err(&pdev->dev, "Missing reg property\n");
1212 ssp_regs[0] = INIT_SSP_REGS(0);
1213 port_type = PORT_TDM;
1216 ssp_regs[1] = INIT_SSP_REGS(1);
1217 port_type = PORT_TDM;
1220 ssp_regs[2] = INIT_SSP_REGS(2);
1221 port_type = PORT_TDM;
1224 port_type = PORT_SPDIF;
1227 dev_err(&pdev->dev, "Bad value for reg %u\n", rawval);
1231 aio = &cygaud->portinfo[portnum];
1232 aio->cygaud = cygaud;
1233 aio->portnum = portnum;
1234 aio->port_type = port_type;
1235 aio->fsync_width = -1;
1237 switch (port_type) {
1239 aio->regs = ssp_regs[portnum];
1240 *p_dai = cygnus_ssp_dai_info[portnum];
1241 aio->mode = CYGNUS_SSPMODE_UNKNOWN;
1245 aio->regs.bf_sourcech_cfg = BF_SRC_CFG3_OFFSET;
1246 aio->regs.bf_sourcech_ctrl = BF_SRC_CTRL3_OFFSET;
1247 aio->regs.i2s_mclk_cfg = SPDIF_MCLK_CFG_OFFSET;
1248 aio->regs.i2s_stream_cfg = SPDIF_STREAM_CFG_OFFSET;
1249 *p_dai = cygnus_spdif_dai_info;
1251 /* For the purposes of this code SPDIF can be I2S mode */
1252 aio->mode = CYGNUS_SSPMODE_I2S;
1255 dev_err(&pdev->dev, "Bad value for port_type %d\n", port_type);
1259 dev_dbg(&pdev->dev, "%s portnum = %d\n", __func__, aio->portnum);
1260 aio->streams_on = 0;
1261 aio->cygaud->dev = &pdev->dev;
1262 aio->clk_trace.play_en = false;
1263 aio->clk_trace.cap_en = false;
1265 audio_ssp_init_portregs(aio);
1269 static int audio_clk_init(struct platform_device *pdev,
1270 struct cygnus_audio *cygaud)
1273 char clk_name[PROP_LEN_MAX];
1275 for (i = 0; i < ARRAY_SIZE(cygaud->audio_clk); i++) {
1276 snprintf(clk_name, PROP_LEN_MAX, "ch%d_audio", i);
1278 cygaud->audio_clk[i] = devm_clk_get(&pdev->dev, clk_name);
1279 if (IS_ERR(cygaud->audio_clk[i]))
1280 return PTR_ERR(cygaud->audio_clk[i]);
1286 static int cygnus_ssp_probe(struct platform_device *pdev)
1288 struct device *dev = &pdev->dev;
1289 struct device_node *child_node;
1290 struct resource *res = pdev->resource;
1291 struct cygnus_audio *cygaud;
1294 int active_port_count;
1296 cygaud = devm_kzalloc(dev, sizeof(struct cygnus_audio), GFP_KERNEL);
1300 dev_set_drvdata(dev, cygaud);
1302 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud");
1303 cygaud->audio = devm_ioremap_resource(dev, res);
1304 if (IS_ERR(cygaud->audio))
1305 return PTR_ERR(cygaud->audio);
1307 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "i2s_in");
1308 cygaud->i2s_in = devm_ioremap_resource(dev, res);
1309 if (IS_ERR(cygaud->i2s_in))
1310 return PTR_ERR(cygaud->i2s_in);
1312 /* Tri-state all controlable pins until we know that we need them */
1313 writel(CYGNUS_SSP_TRISTATE_MASK,
1314 cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
1316 node_count = of_get_child_count(pdev->dev.of_node);
1317 if ((node_count < 1) || (node_count > CYGNUS_MAX_PORTS)) {
1318 dev_err(dev, "child nodes is %d. Must be between 1 and %d\n",
1319 node_count, CYGNUS_MAX_PORTS);
1323 active_port_count = 0;
1325 for_each_available_child_of_node(pdev->dev.of_node, child_node) {
1326 err = parse_ssp_child_node(pdev, child_node, cygaud,
1327 &cygnus_ssp_dai[active_port_count]);
1329 /* negative is err, 0 is active and good, 1 is disabled */
1333 dev_dbg(dev, "Activating DAI: %s\n",
1334 cygnus_ssp_dai[active_port_count].name);
1335 active_port_count++;
1340 cygaud->active_ports = 0;
1342 dev_dbg(dev, "Registering %d DAIs\n", active_port_count);
1343 err = snd_soc_register_component(dev, &cygnus_ssp_component,
1344 cygnus_ssp_dai, active_port_count);
1346 dev_err(dev, "snd_soc_register_dai failed\n");
1350 cygaud->irq_num = platform_get_irq(pdev, 0);
1351 if (cygaud->irq_num <= 0) {
1352 dev_err(dev, "platform_get_irq failed\n");
1353 err = cygaud->irq_num;
1357 err = audio_clk_init(pdev, cygaud);
1359 dev_err(dev, "audio clock initialization failed\n");
1363 err = cygnus_soc_platform_register(dev, cygaud);
1365 dev_err(dev, "platform reg error %d\n", err);
1372 snd_soc_unregister_component(dev);
1376 static int cygnus_ssp_remove(struct platform_device *pdev)
1378 cygnus_soc_platform_unregister(&pdev->dev);
1379 snd_soc_unregister_component(&pdev->dev);
1384 static const struct of_device_id cygnus_ssp_of_match[] = {
1385 { .compatible = "brcm,cygnus-audio" },
1388 MODULE_DEVICE_TABLE(of, cygnus_ssp_of_match);
1390 static struct platform_driver cygnus_ssp_driver = {
1391 .probe = cygnus_ssp_probe,
1392 .remove = cygnus_ssp_remove,
1394 .name = "cygnus-ssp",
1395 .of_match_table = cygnus_ssp_of_match,
1399 module_platform_driver(cygnus_ssp_driver);
1401 MODULE_ALIAS("platform:cygnus-ssp");
1402 MODULE_LICENSE("GPL v2");
1403 MODULE_AUTHOR("Broadcom");
1404 MODULE_DESCRIPTION("Cygnus ASoC SSP Interface");