2 * at91-i2s.c -- ALSA SoC I2S Audio Layer Platform driver
4 * Author: Frank Mandarino <fmandarino@endrelia.com>
5 * Endrelia Technologies Inc.
7 * Based on pxa2xx Platform drivers by
8 * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 * 3rd Mar 2006 Initial version.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <sound/driver.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_ssc.h>
34 #include <asm/arch/at91_pdc.h>
39 #define DBG(x...) printk(KERN_DEBUG "at91-i2s:" x)
44 #if defined(CONFIG_ARCH_AT91SAM9260)
45 #define NUM_SSC_DEVICES 1
47 #define NUM_SSC_DEVICES 3
51 #define AT91_I2S_DAIFMT \
52 (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF)
54 #define AT91_I2S_DIR \
55 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
57 /* priv is (SSC_CMR.DIV << 16 | SSC_TCMR.PERIOD ) */
58 static struct snd_soc_dai_mode at91_i2s[] = {
60 /* 8k: BCLK = (MCLK/10) = (60MHz/50) = 1.2MHz */
62 .fmt = AT91_I2S_DAIFMT,
63 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
64 .pcmrate = SNDRV_PCM_RATE_8000,
65 .pcmdir = AT91_I2S_DIR,
66 .flags = SND_SOC_DAI_BFS_DIV,
68 .bfs = SND_SOC_FSBD(10),
69 .priv = (25 << 16 | 74),
72 /* 16k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
74 .fmt = AT91_I2S_DAIFMT,
75 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
76 .pcmrate = SNDRV_PCM_RATE_16000,
77 .pcmdir = AT91_I2S_DIR,
78 .flags = SND_SOC_DAI_BFS_DIV,
80 .bfs = SND_SOC_FSBD(3),
81 .priv = (7 << 16 | 133),
84 /* 32k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
86 .fmt = AT91_I2S_DAIFMT,
87 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
88 .pcmrate = SNDRV_PCM_RATE_32000,
89 .pcmdir = AT91_I2S_DIR,
90 .flags = SND_SOC_DAI_BFS_DIV,
92 .bfs = SND_SOC_FSBD(3),
93 .priv = (7 << 16 | 66),
96 /* 48k: BCLK = (MCLK/5) ~= (60MHz/26) = 2.3076923MHz */
98 .fmt = AT91_I2S_DAIFMT,
99 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
100 .pcmrate = SNDRV_PCM_RATE_48000,
101 .pcmdir = AT91_I2S_DIR,
102 .flags = SND_SOC_DAI_BFS_DIV,
104 .bfs = SND_SOC_FSBD(5),
105 .priv = (13 << 16 | 23),
111 * SSC PDC registers required by the PCM DMA engine.
113 static struct at91_pdc_regs pdc_tx_reg = {
116 .xnpr = AT91_PDC_TNPR,
117 .xncr = AT91_PDC_TNCR,
120 static struct at91_pdc_regs pdc_rx_reg = {
123 .xnpr = AT91_PDC_RNPR,
124 .xncr = AT91_PDC_RNCR,
128 * SSC & PDC status bits for transmit and receive.
130 static struct at91_ssc_mask ssc_tx_mask = {
131 .ssc_enable = AT91_SSC_TXEN,
132 .ssc_disable = AT91_SSC_TXDIS,
133 .ssc_endx = AT91_SSC_ENDTX,
134 .ssc_endbuf = AT91_SSC_TXBUFE,
135 .pdc_enable = AT91_PDC_TXTEN,
136 .pdc_disable = AT91_PDC_TXTDIS,
139 static struct at91_ssc_mask ssc_rx_mask = {
140 .ssc_enable = AT91_SSC_RXEN,
141 .ssc_disable = AT91_SSC_RXDIS,
142 .ssc_endx = AT91_SSC_ENDRX,
143 .ssc_endbuf = AT91_SSC_RXBUFF,
144 .pdc_enable = AT91_PDC_RXTEN,
145 .pdc_disable = AT91_PDC_RXTDIS,
152 static struct at91_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
154 .name = "SSC0/I2S PCM Stereo out",
156 .mask = &ssc_tx_mask,
159 .name = "SSC0/I2S PCM Stereo in",
161 .mask = &ssc_rx_mask,
163 #if NUM_SSC_DEVICES == 3
165 .name = "SSC1/I2S PCM Stereo out",
167 .mask = &ssc_tx_mask,
170 .name = "SSC1/I2S PCM Stereo in",
172 .mask = &ssc_rx_mask,
175 .name = "SSC2/I2S PCM Stereo out",
177 .mask = &ssc_tx_mask,
180 .name = "SSC1/I2S PCM Stereo in",
182 .mask = &ssc_rx_mask,
189 * A MUTEX is used to protect an SSC initialzed flag which allows
190 * the substream hw_params() call to initialize the SSC only if
191 * there are no other substreams open. If there are other
192 * substreams open, the hw_param() call can only check that
193 * it is using the same format and rate.
195 static DECLARE_MUTEX(ssc0_mutex);
196 #if NUM_SSC_DEVICES == 3
197 static DECLARE_MUTEX(ssc1_mutex);
198 static DECLARE_MUTEX(ssc2_mutex);
202 struct at91_ssc_state {
213 static struct at91_ssc_info {
215 struct at91_ssc_periph ssc;
216 spinlock_t lock; /* lock for dir_mask */
217 int dir_mask; /* 0=unused, 1=playback, 2=capture */
218 struct semaphore *mutex;
222 struct at91_pcm_dma_params *dma_params[2];
223 struct at91_ssc_state ssc_state;
225 } ssc_info[NUM_SSC_DEVICES] = {
228 .lock = SPIN_LOCK_UNLOCKED,
230 .mutex = &ssc0_mutex,
233 #if NUM_SSC_DEVICES == 3
236 .lock = SPIN_LOCK_UNLOCKED,
238 .mutex = &ssc1_mutex,
243 .lock = SPIN_LOCK_UNLOCKED,
245 .mutex = &ssc2_mutex,
252 static irqreturn_t at91_i2s_interrupt(int irq, void *dev_id)
254 struct at91_ssc_info *ssc_p = dev_id;
255 struct at91_pcm_dma_params *dma_params;
259 ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)
260 & at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
263 * Loop through the substreams attached to this SSC. If
264 * a DMA-related interrupt occurred on that substream, call
265 * the DMA interrupt handler function, if one has been
266 * registered in the dma_params structure by the PCM driver.
268 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
269 dma_params = ssc_p->dma_params[i];
271 if (dma_params != NULL && dma_params->dma_intr_handler != NULL &&
273 (dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf)))
275 dma_params->dma_intr_handler(ssc_sr, dma_params->substream);
281 static int at91_i2s_startup(struct snd_pcm_substream *substream)
283 struct snd_soc_pcm_runtime *rtd = substream->private_data;
284 struct at91_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
287 DBG("i2s_startup: SSC_SR=0x%08lx\n",
288 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
289 dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2;
291 spin_lock_irq(&ssc_p->lock);
292 if (ssc_p->dir_mask & dir_mask) {
293 spin_unlock_irq(&ssc_p->lock);
296 ssc_p->dir_mask |= dir_mask;
297 spin_unlock_irq(&ssc_p->lock);
300 * dma_data is not set until hw_params() is called and
301 * shutdown() depends on this value being NULL if hw_params()
304 rtd->cpu_dai->dma_data = NULL;
309 static void at91_i2s_shutdown(struct snd_pcm_substream *substream)
311 struct snd_soc_pcm_runtime *rtd = substream->private_data;
312 struct at91_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
313 struct at91_pcm_dma_params *dma_params = rtd->cpu_dai->dma_data;
316 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
318 if (dma_params != NULL) {
319 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
320 dma_params->mask->ssc_disable);
321 DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"),
322 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
324 dma_params->ssc_base = NULL;
325 dma_params->substream = NULL;
326 ssc_p->dma_params[dir] = NULL;
331 spin_lock_irq(&ssc_p->lock);
332 ssc_p->dir_mask &= ~dir_mask;
333 if (!ssc_p->dir_mask) {
334 /* Shutdown the SSC clock. */
335 DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
336 at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid);
338 if (ssc_p->initialized)
339 free_irq(ssc_p->ssc.pid, ssc_p);
342 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
344 /* Force a re-init on the next hw_params() call. */
345 ssc_p->initialized = 0;
347 spin_unlock_irq(&ssc_p->lock);
351 static int at91_i2s_suspend(struct platform_device *pdev,
352 struct snd_soc_cpu_dai *dai)
354 struct at91_ssc_info *ssc_p;
359 ssc_p = &ssc_info[dai->id];
361 /* Save the status register before disabling transmit and receive. */
362 ssc_p->ssc_state.ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR);
363 at91_ssc_write(ssc_p->ssc.base +
364 AT91_SSC_CR, AT91_SSC_TXDIS | AT91_SSC_RXDIS);
366 /* Save the current interrupt mask, then disable unmasked interrupts. */
367 ssc_p->ssc_state.ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
368 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->ssc_state.ssc_imr);
370 ssc_p->ssc_state.ssc_cmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR);
371 ssc_p->ssc_state.ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
372 ssc_p->ssc_state.ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
373 ssc_p->ssc_state.ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
374 ssc_p->ssc_state.ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
379 static int at91_i2s_resume(struct platform_device *pdev,
380 struct snd_soc_cpu_dai *dai)
382 struct at91_ssc_info *ssc_p;
388 ssc_p = &ssc_info[dai->id];
390 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_tfmr);
391 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_tcmr);
392 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_rfmr);
393 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_rcmr);
394 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->ssc_state.ssc_cmr);
396 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IER, ssc_p->ssc_state.ssc_imr);
398 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
399 ((ssc_p->ssc_state.ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) |
400 ((ssc_p->ssc_state.ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0));
406 #define at91_i2s_suspend NULL
407 #define at91_i2s_resume NULL
410 static unsigned int at91_i2s_config_sysclk(
411 struct snd_soc_cpu_dai *iface, struct snd_soc_clock_info *info,
414 /* Currently, there is only support for USB (12Mhz) mode */
420 static int at91_i2s_hw_params(struct snd_pcm_substream *substream,
421 struct snd_pcm_hw_params *params)
423 struct snd_soc_pcm_runtime *rtd = substream->private_data;
424 int id = rtd->cpu_dai->id;
425 struct at91_ssc_info *ssc_p = &ssc_info[id];
426 struct at91_pcm_dma_params *dma_params;
427 unsigned int pcmfmt, rate;
428 int dir, channels, bits;
430 u32 div, period, tfmr, rfmr, tcmr, rcmr;
434 * Currently, there is only one set of dma params for
435 * each direction. If more are added, this code will
436 * have to be changed to select the proper set.
438 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
440 dma_params = &ssc_dma_params[id][dir];
441 dma_params->ssc_base = ssc_p->ssc.base;
442 dma_params->substream = substream;
444 ssc_p->dma_params[dir] = dma_params;
445 rtd->cpu_dai->dma_data = dma_params;
447 rate = params_rate(params);
448 channels = params_channels(params);
450 pcmfmt = rtd->cpu_dai->dai_runtime.pcmfmt;
452 case SNDRV_PCM_FMTBIT_S16_LE:
453 /* likely this is all we'll ever support, but ... */
455 dma_params->pdc_xfer_size = 2;
458 printk(KERN_WARNING "at91-i2s: unsupported format %x\n",
463 /* Don't allow both SSC substreams to initialize at the same time. */
467 * If this SSC is alreadly initialized, then this substream must use
468 * the same format and rate.
470 if (ssc_p->initialized) {
471 if (pcmfmt != ssc_p->pcmfmt || rate != ssc_p->rate) {
472 printk(KERN_WARNING "at91-i2s: "
473 "incompatible substream in other direction\n");
478 /* Enable PMC peripheral clock for this SSC */
479 DBG("Starting pid %d clock\n", ssc_p->ssc.pid);
480 at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
483 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
485 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RPR, 0);
486 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RCR, 0);
487 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RNPR, 0);
488 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RNCR, 0);
489 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TPR, 0);
490 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TCR, 0);
491 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TNPR, 0);
492 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TNCR, 0);
494 div = rtd->cpu_dai->dai_runtime.priv >> 16;
495 period = rtd->cpu_dai->dai_runtime.priv & 0xffff;
497 mck_clk = clk_get(NULL, "mck");
499 DBG("mck %lu fsbd %u bfs %llu bfs_real %u bclk %lu div %u period %u\n",
500 clk_get_rate(mck_clk),
502 rtd->cpu_dai->dai_runtime.bfs,
503 SND_SOC_FSBD_REAL(rtd->cpu_dai->dai_runtime.bfs),
504 clk_get_rate(mck_clk) / (2 * div),
510 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, div);
513 * Setup the TFMR and RFMR for the proper data format.
516 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
517 | (( 0 << 23) & AT91_SSC_FSDEN)
518 | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
519 | (((bits - 1) << 16) & AT91_SSC_FSLEN)
520 | (((channels - 1) << 8) & AT91_SSC_DATNB)
521 | (( 1 << 7) & AT91_SSC_MSBF)
522 | (( 0 << 5) & AT91_SSC_DATDEF)
523 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
524 DBG("SSC_TFMR=0x%08x\n", tfmr);
525 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr);
528 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
529 | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
530 | (( 0 << 16) & AT91_SSC_FSLEN)
531 | (((channels - 1) << 8) & AT91_SSC_DATNB)
532 | (( 1 << 7) & AT91_SSC_MSBF)
533 | (( 0 << 5) & AT91_SSC_LOOP)
534 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
536 DBG("SSC_RFMR=0x%08x\n", rfmr);
537 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr);
540 * Setup the TCMR and RCMR to generate the proper BCLK
544 (( period << 24) & AT91_SSC_PERIOD)
545 | (( 1 << 16) & AT91_SSC_STTDLY)
546 | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
547 | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
548 | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
549 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
551 DBG("SSC_TCMR=0x%08x\n", tcmr);
552 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr);
555 (( 0 << 24) & AT91_SSC_PERIOD)
556 | (( 1 << 16) & AT91_SSC_STTDLY)
557 | (( AT91_SSC_START_TX_RX ) & AT91_SSC_START)
558 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
559 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
560 | (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS);
562 DBG("SSC_RCMR=0x%08x\n", rcmr);
563 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr);
565 if ((ret = request_irq(ssc_p->ssc.pid, at91_i2s_interrupt,
566 0, ssc_p->name, ssc_p)) < 0) {
567 printk(KERN_WARNING "at91-i2s: request_irq failure\n");
572 * Save the current substream parameters in order to check
573 * that the substream in the opposite direction uses the
576 ssc_p->pcmfmt = pcmfmt;
578 ssc_p->initialized = 1;
580 DBG("hw_params: SSC initialized\n");
589 static int at91_i2s_prepare(struct snd_pcm_substream *substream)
591 struct snd_soc_pcm_runtime *rtd = substream->private_data;
592 struct at91_pcm_dma_params *dma_params = rtd->cpu_dai->dma_data;
594 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
595 dma_params->mask->ssc_enable);
597 DBG("%s enabled SSC_SR=0x%08lx\n",
598 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "transmit" : "receive",
599 at91_ssc_read(ssc_info[rtd->cpu_dai->id].ssc.base + AT91_SSC_SR));
604 struct snd_soc_cpu_dai at91_i2s_dai[NUM_SSC_DEVICES] = {
605 { .name = "at91_ssc0/i2s",
607 .type = SND_SOC_DAI_I2S,
608 .suspend = at91_i2s_suspend,
609 .resume = at91_i2s_resume,
610 .config_sysclk = at91_i2s_config_sysclk,
618 .startup = at91_i2s_startup,
619 .shutdown = at91_i2s_shutdown,
620 .prepare = at91_i2s_prepare,
621 .hw_params = at91_i2s_hw_params,},
623 .mode = &at91_i2s[0],
624 .num_modes = ARRAY_SIZE(at91_i2s),},
625 .private_data = &ssc_info[0].ssc,
627 #if NUM_SSC_DEVICES == 3
628 { .name = "at91_ssc1/i2s",
630 .type = SND_SOC_DAI_I2S,
631 .suspend = at91_i2s_suspend,
632 .resume = at91_i2s_resume,
633 .config_sysclk = at91_i2s_config_sysclk,
641 .startup = at91_i2s_startup,
642 .shutdown = at91_i2s_shutdown,
643 .prepare = at91_i2s_prepare,
644 .hw_params = at91_i2s_hw_params,},
646 .mode = &at91_i2s[0],
647 .num_modes = ARRAY_SIZE(at91_i2s),},
648 .private_data = &ssc_info[1].ssc,
650 { .name = "at91_ssc2/i2s",
652 .type = SND_SOC_DAI_I2S,
653 .suspend = at91_i2s_suspend,
654 .resume = at91_i2s_resume,
655 .config_sysclk = at91_i2s_config_sysclk,
663 .startup = at91_i2s_startup,
664 .shutdown = at91_i2s_shutdown,
665 .prepare = at91_i2s_prepare,
666 .hw_params = at91_i2s_hw_params,},
668 .mode = &at91_i2s[0],
669 .num_modes = ARRAY_SIZE(at91_i2s),},
670 .private_data = &ssc_info[2].ssc,
675 EXPORT_SYMBOL_GPL(at91_i2s_dai);
677 /* Module information */
678 MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
679 MODULE_DESCRIPTION("AT91 I2S ASoC Interface");
680 MODULE_LICENSE("GPL");