[ALSA] Clean up with common snd_ctl_boolean_*_info callbacks
[sfrench/cifs-2.6.git] / sound / pci / rme9652 / hdspm.c
1 /*   -*- linux-c -*-
2  *
3  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4  *
5  *      Copyright (c) 2003 Winfried Ritsch (IEM)
6  *      code based on hdsp.c   Paul Davis
7  *                             Marcus Andersson
8  *                             Thomas Charbonnel
9  *      Modified 2006-06-01 for AES32 support by Remy Bruno
10  *                                               <remy.bruno@trinnov.com>
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
25  *
26  */
27 #include <sound/driver.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/moduleparam.h>
32 #include <linux/slab.h>
33 #include <linux/pci.h>
34 #include <asm/io.h>
35
36 #include <sound/core.h>
37 #include <sound/control.h>
38 #include <sound/pcm.h>
39 #include <sound/info.h>
40 #include <sound/asoundef.h>
41 #include <sound/rawmidi.h>
42 #include <sound/hwdep.h>
43 #include <sound/initval.h>
44
45 #include <sound/hdspm.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
50
51 /* Disable precise pointer at start */
52 static int precise_ptr[SNDRV_CARDS];
53
54 /* Send all playback to line outs */
55 static int line_outs_monitor[SNDRV_CARDS];
56
57 /* Enable Analog Outs on Channel 63/64 by default */
58 static int enable_monitor[SNDRV_CARDS];
59
60 module_param_array(index, int, NULL, 0444);
61 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
62
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
65
66 module_param_array(enable, bool, NULL, 0444);
67 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
68
69 module_param_array(precise_ptr, bool, NULL, 0444);
70 MODULE_PARM_DESC(precise_ptr, "Enable or disable precise pointer.");
71
72 module_param_array(line_outs_monitor, bool, NULL, 0444);
73 MODULE_PARM_DESC(line_outs_monitor,
74                  "Send playback streams to analog outs by default.");
75
76 module_param_array(enable_monitor, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable_monitor,
78                  "Enable Analog Out on Channel 63/64 by default.");
79
80 MODULE_AUTHOR
81       ("Winfried Ritsch <ritsch_AT_iem.at>, Paul Davis <paul@linuxaudiosystems.com>, "
82        "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
83        "Remy Bruno <remy.bruno@trinnov.com>");
84 MODULE_DESCRIPTION("RME HDSPM");
85 MODULE_LICENSE("GPL");
86 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
87
88 /* --- Write registers. --- 
89   These are defined as byte-offsets from the iobase value.  */
90
91 #define HDSPM_controlRegister        64
92 #define HDSPM_interruptConfirmation  96
93 #define HDSPM_control2Reg            256  /* not in specs ???????? */
94 #define HDSPM_freqReg                256  /* for AES32 */
95 #define HDSPM_midiDataOut0           352  /* just believe in old code */
96 #define HDSPM_midiDataOut1           356
97 #define HDSPM_eeprom_wr              384  /* for AES32 */
98
99 /* DMA enable for 64 channels, only Bit 0 is relevant */
100 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */ 
101 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
102
103 /* 16 page addresses for each of the 64 channels DMA buffer in and out 
104    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
105 #define HDSPM_pageAddressBufferOut       8192
106 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
107
108 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
109
110 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
111
112 /* --- Read registers. ---
113    These are defined as byte-offsets from the iobase value */
114 #define HDSPM_statusRegister    0
115 /*#define HDSPM_statusRegister2  96 */
116 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
117  * offset 192, for AES32 *and* MADI
118  * => need to check that offset 192 is working on MADI */
119 #define HDSPM_statusRegister2  192
120 #define HDSPM_timecodeRegister 128
121
122 #define HDSPM_midiDataIn0     360
123 #define HDSPM_midiDataIn1     364
124
125 /* status is data bytes in MIDI-FIFO (0-128) */
126 #define HDSPM_midiStatusOut0  384       
127 #define HDSPM_midiStatusOut1  388       
128 #define HDSPM_midiStatusIn0   392       
129 #define HDSPM_midiStatusIn1   396       
130
131
132 /* the meters are regular i/o-mapped registers, but offset
133    considerably from the rest. the peak registers are reset
134    when read; the least-significant 4 bits are full-scale counters; 
135    the actual peak value is in the most-significant 24 bits.
136 */
137 #define HDSPM_MADI_peakrmsbase  4096    /* 4096-8191 2x64x32Bit Meters */
138
139 /* --- Control Register bits --------- */
140 #define HDSPM_Start                (1<<0) /* start engine */
141
142 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
143 #define HDSPM_Latency1             (1<<2) /* where n is defined */
144 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
145
146 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Slave/Autosync */
147
148 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
149
150 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
151 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
152 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
153 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
154
155 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
156 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
157                                      56channelMODE=0 */ /* MADI ONLY*/
158 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
159
160 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode, 
161                                      0=off, 1=on  */ /* MADI ONLY */
162 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
163
164 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax */ /* MADI ONLY*/
165 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
166
167 #define HDSPM_SyncRef0     (1<<16) /* 0=WOrd, 1=MADI */
168 #define HDSPM_SyncRef1     (1<<17) /* for AES32: SyncRefN codes the AES # */
169 #define HDSPM_SyncRef2     (1<<13)
170 #define HDSPM_SyncRef3     (1<<25)
171
172 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
173 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use 
174                                       AES additional bits in
175                                       lower 5 Audiodatabits ??? */
176 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
177 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
178
179 #define HDSPM_Midi0InterruptEnable (1<<22)
180 #define HDSPM_Midi1InterruptEnable (1<<23)
181
182 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
183
184 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
185 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
186 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
187
188 #define HDSPM_wclk_sel (1<<30)
189
190 /* --- bit helper defines */
191 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
192 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
193 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
194 #define HDSPM_InputOptical   0
195 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
196 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|HDSPM_SyncRef2|HDSPM_SyncRef3)
197 #define HDSPM_SyncRef_Word   0
198 #define HDSPM_SyncRef_MADI   (HDSPM_SyncRef0)
199
200 #define HDSPM_SYNC_FROM_WORD 0  /* Preferred sync reference */
201 #define HDSPM_SYNC_FROM_MADI 1  /* choices - used by "pref_sync_ref" */
202
203 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
204 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
205 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
206 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
207 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
208 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|HDSPM_Frequency0)
209 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
210 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
211 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|HDSPM_Frequency0)
212
213 /* --- for internal discrimination */
214 #define HDSPM_CLOCK_SOURCE_AUTOSYNC          0  /* Sample Clock Sources */
215 #define HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ    1
216 #define HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ  2
217 #define HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ    3
218 #define HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ    4
219 #define HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ  5
220 #define HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ    6
221 #define HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ   7
222 #define HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
223 #define HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ   9
224
225 /* Synccheck Status */
226 #define HDSPM_SYNC_CHECK_NO_LOCK 0
227 #define HDSPM_SYNC_CHECK_LOCK    1
228 #define HDSPM_SYNC_CHECK_SYNC    2
229
230 /* AutoSync References - used by "autosync_ref" control switch */
231 #define HDSPM_AUTOSYNC_FROM_WORD      0
232 #define HDSPM_AUTOSYNC_FROM_MADI      1
233 #define HDSPM_AUTOSYNC_FROM_NONE      2
234
235 /* Possible sources of MADI input */
236 #define HDSPM_OPTICAL 0         /* optical   */
237 #define HDSPM_COAXIAL 1         /* BNC */
238
239 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
240 #define hdspm_decode_latency(x)       (((x) & HDSPM_LatencyMask)>>1)
241
242 #define hdspm_encode_in(x) (((x)&0x3)<<14)
243 #define hdspm_decode_in(x) (((x)>>14)&0x3)
244
245 /* --- control2 register bits --- */
246 #define HDSPM_TMS             (1<<0)
247 #define HDSPM_TCK             (1<<1)
248 #define HDSPM_TDI             (1<<2)
249 #define HDSPM_JTAG            (1<<3)
250 #define HDSPM_PWDN            (1<<4)
251 #define HDSPM_PROGRAM         (1<<5)
252 #define HDSPM_CONFIG_MODE_0   (1<<6)
253 #define HDSPM_CONFIG_MODE_1   (1<<7)
254 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
255 #define HDSPM_BIGENDIAN_MODE  (1<<9)
256 #define HDSPM_RD_MULTIPLE     (1<<10)
257
258 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
259      that do not conflict with specific bits for AES32 seem to be valid also for the AES32 */
260 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
261 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn. MODE=0 */
262 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1 (like inp0) */
263 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
264
265 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
266                                            /* since 64byte accurate last 6 bits 
267                                               are not used */
268
269 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
270 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
271
272 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
273 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
274 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
275 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
276
277 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with Interrupt */
278 #define HDSPM_midi0IRQPending   (1<<30) /* MIDI IRQ is pending  */
279 #define HDSPM_midi1IRQPending   (1<<31) /* and aktiv */
280
281 /* --- status bit helpers */
282 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2|HDSPM_madiFreq3)
283 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
284 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
285 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
286 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
287 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
288 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
289 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
290 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
291 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
292
293 /* Status2 Register bits */ /* MADI ONLY */
294
295 #define HDSPM_version0 (1<<0)   /* not realy defined but I guess */
296 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
297 #define HDSPM_version2 (1<<2)
298
299 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
300 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
301
302 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
303 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
304 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
305 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
306
307 #define HDSPM_SelSyncRef0 (1<<8)        /* Sync Source in slave mode */
308 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
309 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
310
311 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
312
313 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
314 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
315 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
316 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
317 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
318 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
319 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
320
321
322 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|HDSPM_SelSyncRef2)
323 #define HDSPM_SelSyncRef_WORD      0
324 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
325 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|HDSPM_SelSyncRef2)
326
327 /*
328    For AES32, bits for status, status2 and timecode are different
329 */
330 /* status */
331 #define HDSPM_AES32_wcLock      0x0200000
332 #define HDSPM_AES32_wcFreq_bit  22
333 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 
334   HDSPM_bit2freq */
335 #define HDSPM_AES32_syncref_bit  16
336 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
337
338 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
339 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
340 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
341 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
342 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
343 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
344 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
345 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
346 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
347 #define HDSPM_AES32_AUTOSYNC_FROM_NONE -1
348
349 /*  status2 */
350 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
351 #define HDSPM_LockAES   0x80
352 #define HDSPM_LockAES1  0x80
353 #define HDSPM_LockAES2  0x40
354 #define HDSPM_LockAES3  0x20
355 #define HDSPM_LockAES4  0x10
356 #define HDSPM_LockAES5  0x8
357 #define HDSPM_LockAES6  0x4
358 #define HDSPM_LockAES7  0x2
359 #define HDSPM_LockAES8  0x1
360 /*
361    Timecode
362    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
363    AES i+1
364  bits 3210
365       0001  32kHz
366       0010  44.1kHz
367       0011  48kHz
368       0100  64kHz
369       0101  88.2kHz
370       0110  96kHz
371       0111  128kHz
372       1000  176.4kHz
373       1001  192kHz
374   NB: Timecode register doesn't seem to work on AES32 card revision 230
375 */
376
377 /* Mixer Values */
378 #define UNITY_GAIN          32768       /* = 65536/2 */
379 #define MINUS_INFINITY_GAIN 0
380
381 /* Number of channels for different Speed Modes */
382 #define MADI_SS_CHANNELS       64
383 #define MADI_DS_CHANNELS       32
384 #define MADI_QS_CHANNELS       16
385
386 /* the size of a substream (1 mono data stream) */
387 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
388 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
389
390 /* the size of the area we need to allocate for DMA transfers. the
391    size is the same regardless of the number of channels, and
392    also the latency to use. 
393    for one direction !!!
394 */
395 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
396 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
397
398 /* revisions >= 230 indicate AES32 card */
399 #define HDSPM_AESREVISION 230
400
401 struct hdspm_midi {
402         struct hdspm *hdspm;
403         int id;
404         struct snd_rawmidi *rmidi;
405         struct snd_rawmidi_substream *input;
406         struct snd_rawmidi_substream *output;
407         char istimer;           /* timer in use */
408         struct timer_list timer;
409         spinlock_t lock;
410         int pending;
411 };
412
413 struct hdspm {
414         spinlock_t lock;
415         struct snd_pcm_substream *capture_substream;     /* only one playback */
416         struct snd_pcm_substream *playback_substream; /* and/or capture stream */
417
418         char *card_name;             /* for procinfo */
419         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
420
421         unsigned char is_aes32;    /* indicates if card is AES32 */
422
423         int precise_ptr;        /* use precise pointers, to be tested */
424         int monitor_outs;       /* set up monitoring outs init flag */
425
426         u32 control_register;   /* cached value */
427         u32 control2_register;  /* cached value */
428
429         struct hdspm_midi midi[2];
430         struct tasklet_struct midi_tasklet;
431
432         size_t period_bytes;
433         unsigned char ss_channels;      /* channels of card in single speed */
434         unsigned char ds_channels;      /* Double Speed */
435         unsigned char qs_channels;      /* Quad Speed */
436
437         unsigned char *playback_buffer; /* suitably aligned address */
438         unsigned char *capture_buffer;  /* suitably aligned address */
439
440         pid_t capture_pid;      /* process id which uses capture */
441         pid_t playback_pid;     /* process id which uses capture */
442         int running;            /* running status */
443
444         int last_external_sample_rate;  /* samplerate mystic ... */
445         int last_internal_sample_rate;
446         int system_sample_rate;
447
448         char *channel_map;      /* channel map for DS and Quadspeed */
449
450         int dev;                /* Hardware vars... */
451         int irq;
452         unsigned long port;
453         void __iomem *iobase;
454
455         int irq_count;          /* for debug */
456
457         struct snd_card *card;  /* one card */
458         struct snd_pcm *pcm;            /* has one pcm */
459         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
460         struct pci_dev *pci;    /* and an pci info */
461
462         /* Mixer vars */
463         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];   /* fast alsa mixer */
464         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];      /* but input to much, so not used */
465         struct hdspm_mixer *mixer;      /* full mixer accessable over mixer ioctl or hwdep-device */
466
467 };
468
469 /* These tables map the ALSA channels 1..N to the channels that we
470    need to use in order to find the relevant channel buffer. RME
471    refer to this kind of mapping as between "the ADAT channel and
472    the DMA channel." We index it using the logical audio channel,
473    and the value is the DMA channel (i.e. channel buffer number)
474    where the data for that channel can be read/written from/to.
475 */
476
477 static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = {
478    0, 1, 2, 3, 4, 5, 6, 7,
479    8, 9, 10, 11, 12, 13, 14, 15,
480    16, 17, 18, 19, 20, 21, 22, 23,
481    24, 25, 26, 27, 28, 29, 30, 31,
482    32, 33, 34, 35, 36, 37, 38, 39,
483    40, 41, 42, 43, 44, 45, 46, 47,
484    48, 49, 50, 51, 52, 53, 54, 55,
485    56, 57, 58, 59, 60, 61, 62, 63
486 };
487
488
489 static struct pci_device_id snd_hdspm_ids[] __devinitdata = {
490         {
491          .vendor = PCI_VENDOR_ID_XILINX,
492          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
493          .subvendor = PCI_ANY_ID,
494          .subdevice = PCI_ANY_ID,
495          .class = 0,
496          .class_mask = 0,
497          .driver_data = 0},
498         {0,}
499 };
500
501 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
502
503 /* prototypes */
504 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
505                                                    struct hdspm * hdspm);
506 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
507                                           struct hdspm * hdspm);
508
509 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm);
510 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm);
511 static int hdspm_autosync_ref(struct hdspm * hdspm);
512 static int snd_hdspm_set_defaults(struct hdspm * hdspm);
513 static void hdspm_set_sgbuf(struct hdspm * hdspm, struct snd_sg_buf *sgbuf,
514                              unsigned int reg, int channels);
515
516 static inline int HDSPM_bit2freq(int n)
517 {
518         static int bit2freq_tab[] = { 0, 32000, 44100, 48000, 64000, 88200,
519                 96000, 128000, 176400, 192000 };
520         if (n < 1 || n > 9)
521                 return 0;
522         return bit2freq_tab[n];
523 }
524
525 /* Write/read to/from HDSPM with Adresses in Bytes
526    not words but only 32Bit writes are allowed */
527
528 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
529                                unsigned int val)
530 {
531         writel(val, hdspm->iobase + reg);
532 }
533
534 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
535 {
536         return readl(hdspm->iobase + reg);
537 }
538
539 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 
540    mixer is write only on hardware so we have to cache him for read 
541    each fader is a u32, but uses only the first 16 bit */
542
543 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
544                                      unsigned int in)
545 {
546         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
547                 return 0;
548
549         return hdspm->mixer->ch[chan].in[in];
550 }
551
552 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
553                                      unsigned int pb)
554 {
555         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
556                 return 0;
557         return hdspm->mixer->ch[chan].pb[pb];
558 }
559
560 static inline int hdspm_write_in_gain(struct hdspm * hdspm, unsigned int chan,
561                                       unsigned int in, unsigned short data)
562 {
563         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
564                 return -1;
565
566         hdspm_write(hdspm,
567                     HDSPM_MADI_mixerBase +
568                     ((in + 128 * chan) * sizeof(u32)),
569                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
570         return 0;
571 }
572
573 static inline int hdspm_write_pb_gain(struct hdspm * hdspm, unsigned int chan,
574                                       unsigned int pb, unsigned short data)
575 {
576         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
577                 return -1;
578
579         hdspm_write(hdspm,
580                     HDSPM_MADI_mixerBase +
581                     ((64 + pb + 128 * chan) * sizeof(u32)),
582                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
583         return 0;
584 }
585
586
587 /* enable DMA for specific channels, now available for DSP-MADI */
588 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
589 {
590         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
591 }
592
593 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
594 {
595         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
596 }
597
598 /* check if same process is writing and reading */
599 static inline int snd_hdspm_use_is_exclusive(struct hdspm * hdspm)
600 {
601         unsigned long flags;
602         int ret = 1;
603
604         spin_lock_irqsave(&hdspm->lock, flags);
605         if ((hdspm->playback_pid != hdspm->capture_pid) &&
606             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
607                 ret = 0;
608         }
609         spin_unlock_irqrestore(&hdspm->lock, flags);
610         return ret;
611 }
612
613 /* check for external sample rate */
614 static inline int hdspm_external_sample_rate(struct hdspm * hdspm)
615 {
616         if (hdspm->is_aes32) {
617                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
618                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
619                 unsigned int timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
620
621                 int syncref = hdspm_autosync_ref(hdspm);
622
623                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
624                                 status & HDSPM_AES32_wcLock)
625                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
626                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
627                         syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
628                         status2 & (HDSPM_LockAES >>
629                                   (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
630                         return HDSPM_bit2freq((timecode >>
631                           (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
632                 return 0;
633         } else {
634                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
635                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
636                 unsigned int rate_bits;
637                 int rate = 0;
638
639                 /* if wordclock has synced freq and wordclock is valid */
640                 if ((status2 & HDSPM_wcLock) != 0 &&
641                                 (status & HDSPM_SelSyncRef0) == 0) {
642
643                         rate_bits = status2 & HDSPM_wcFreqMask;
644
645                         switch (rate_bits) {
646                         case HDSPM_wcFreq32:
647                                 rate = 32000;
648                                 break;
649                         case HDSPM_wcFreq44_1:
650                                 rate = 44100;
651                                 break;
652                         case HDSPM_wcFreq48:
653                                 rate = 48000;
654                                 break;
655                         case HDSPM_wcFreq64:
656                                 rate = 64000;
657                                 break;
658                         case HDSPM_wcFreq88_2:
659                                 rate = 88200;
660                                 break;
661                         case HDSPM_wcFreq96:
662                                 rate = 96000;
663                                 break;
664                                 /* Quadspeed Bit missing ???? */
665                         default:
666                                 rate = 0;
667                                 break;
668                         }
669                 }
670
671                 /* if rate detected and Syncref is Word than have it, word has priority to MADI */
672                 if (rate != 0 &&
673                     (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
674                         return rate;
675
676                 /* maby a madi input (which is taken if sel sync is madi) */
677                 if (status & HDSPM_madiLock) {
678                         rate_bits = status & HDSPM_madiFreqMask;
679
680                         switch (rate_bits) {
681                         case HDSPM_madiFreq32:
682                                 rate = 32000;
683                                 break;
684                         case HDSPM_madiFreq44_1:
685                                 rate = 44100;
686                                 break;
687                         case HDSPM_madiFreq48:
688                                 rate = 48000;
689                                 break;
690                         case HDSPM_madiFreq64:
691                                 rate = 64000;
692                                 break;
693                         case HDSPM_madiFreq88_2:
694                                 rate = 88200;
695                                 break;
696                         case HDSPM_madiFreq96:
697                                 rate = 96000;
698                                 break;
699                         case HDSPM_madiFreq128:
700                                 rate = 128000;
701                                 break;
702                         case HDSPM_madiFreq176_4:
703                                 rate = 176400;
704                                 break;
705                         case HDSPM_madiFreq192:
706                                 rate = 192000;
707                                 break;
708                         default:
709                                 rate = 0;
710                                 break;
711                         }
712                 }
713                 return rate;
714         }
715 }
716
717 /* Latency function */
718 static inline void hdspm_compute_period_size(struct hdspm * hdspm)
719 {
720         hdspm->period_bytes =
721             1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
722 }
723
724 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm * hdspm)
725 {
726         int position;
727
728         position = hdspm_read(hdspm, HDSPM_statusRegister);
729
730         if (!hdspm->precise_ptr) {
731                 return (position & HDSPM_BufferID) ? (hdspm->period_bytes /
732                                                       4) : 0;
733         }
734
735         /* hwpointer comes in bytes and is 64Bytes accurate (by docu since PCI Burst)
736            i have experimented that it is at most 64 Byte to much for playing 
737            so substraction of 64 byte should be ok for ALSA, but use it only
738            for application where you know what you do since if you come to
739            near with record pointer it can be a disaster */
740
741         position &= HDSPM_BufferPositionMask;
742         position = ((position - 64) % (2 * hdspm->period_bytes)) / 4;
743
744         return position;
745 }
746
747
748 static inline void hdspm_start_audio(struct hdspm * s)
749 {
750         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
751         hdspm_write(s, HDSPM_controlRegister, s->control_register);
752 }
753
754 static inline void hdspm_stop_audio(struct hdspm * s)
755 {
756         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
757         hdspm_write(s, HDSPM_controlRegister, s->control_register);
758 }
759
760 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
761 static inline void hdspm_silence_playback(struct hdspm * hdspm)
762 {
763         int i;
764         int n = hdspm->period_bytes;
765         void *buf = hdspm->playback_buffer;
766
767         if (buf == NULL)
768                 return;
769
770         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
771                 memset(buf, 0, n);
772                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
773         }
774 }
775
776 static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
777 {
778         int n;
779
780         spin_lock_irq(&s->lock);
781
782         frames >>= 7;
783         n = 0;
784         while (frames) {
785                 n++;
786                 frames >>= 1;
787         }
788         s->control_register &= ~HDSPM_LatencyMask;
789         s->control_register |= hdspm_encode_latency(n);
790
791         hdspm_write(s, HDSPM_controlRegister, s->control_register);
792
793         hdspm_compute_period_size(s);
794
795         spin_unlock_irq(&s->lock);
796
797         return 0;
798 }
799
800 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
801 {
802         u64 n;
803         u32 r;
804         
805         if (rate >= 112000)
806                 rate /= 4;
807         else if (rate >= 56000)
808                 rate /= 2;
809
810         /* RME says n = 104857600000000, but in the windows MADI driver, I see:
811 //      return 104857600000000 / rate; // 100 MHz
812         return 110100480000000 / rate; // 105 MHz
813         */         
814         //n = 104857600000000ULL;  /*  =  2^20 * 10^8 */
815         n = 110100480000000ULL;    /* Value checked for AES32 and MADI */
816         div64_32(&n, rate, &r);
817         /* n should be less than 2^32 for being written to FREQ register */
818         snd_assert((n >> 32) == 0);
819         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
820 }
821
822 /* dummy set rate lets see what happens */
823 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
824 {
825         int reject_if_open = 0;
826         int current_rate;
827         int rate_bits;
828         int not_set = 0;
829         int is_single, is_double, is_quad;
830
831         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
832            it (e.g. during module initialization).
833          */
834
835         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
836
837                 /* SLAVE --- */ 
838                 if (called_internally) {
839
840                   /* request from ctl or card initialization 
841                      just make a warning an remember setting 
842                      for future master mode switching */
843     
844                         snd_printk
845                             (KERN_WARNING "HDSPM: Warning: device is not running as a clock master.\n");
846                         not_set = 1;
847                 } else {
848
849                         /* hw_param request while in AutoSync mode */
850                         int external_freq =
851                             hdspm_external_sample_rate(hdspm);
852
853                         if ((hdspm_autosync_ref(hdspm) ==
854                              HDSPM_AUTOSYNC_FROM_NONE)) {
855
856                                 snd_printk(KERN_WARNING "HDSPM: Detected no Externel Sync \n");
857                                 not_set = 1;
858
859                         } else if (rate != external_freq) {
860
861                                 snd_printk
862                                     (KERN_WARNING "HDSPM: Warning: No AutoSync source for requested rate\n");
863                                 not_set = 1;
864                         }
865                 }
866         }
867
868         current_rate = hdspm->system_sample_rate;
869
870         /* Changing between Singe, Double and Quad speed is not
871            allowed if any substreams are open. This is because such a change
872            causes a shift in the location of the DMA buffers and a reduction
873            in the number of available buffers.
874
875            Note that a similar but essentially insoluble problem exists for
876            externally-driven rate changes. All we can do is to flag rate
877            changes in the read/write routines.  
878          */
879
880         is_single = (current_rate <= 48000);
881         is_double = (current_rate > 48000 && current_rate <= 96000);
882         is_quad = (current_rate > 96000);
883
884         switch (rate) {
885         case 32000:
886                 if (!is_single)
887                         reject_if_open = 1;
888                 rate_bits = HDSPM_Frequency32KHz;
889                 break;
890         case 44100:
891                 if (!is_single)
892                         reject_if_open = 1;
893                 rate_bits = HDSPM_Frequency44_1KHz;
894                 break;
895         case 48000:
896                 if (!is_single)
897                         reject_if_open = 1;
898                 rate_bits = HDSPM_Frequency48KHz;
899                 break;
900         case 64000:
901                 if (!is_double)
902                         reject_if_open = 1;
903                 rate_bits = HDSPM_Frequency64KHz;
904                 break;
905         case 88200:
906                 if (!is_double)
907                         reject_if_open = 1;
908                 rate_bits = HDSPM_Frequency88_2KHz;
909                 break;
910         case 96000:
911                 if (!is_double)
912                         reject_if_open = 1;
913                 rate_bits = HDSPM_Frequency96KHz;
914                 break;
915         case 128000:
916                 if (!is_quad)
917                         reject_if_open = 1;
918                 rate_bits = HDSPM_Frequency128KHz;
919                 break;
920         case 176400:
921                 if (!is_quad)
922                         reject_if_open = 1;
923                 rate_bits = HDSPM_Frequency176_4KHz;
924                 break;
925         case 192000:
926                 if (!is_quad)
927                         reject_if_open = 1;
928                 rate_bits = HDSPM_Frequency192KHz;
929                 break;
930         default:
931                 return -EINVAL;
932         }
933
934         if (reject_if_open
935             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
936                 snd_printk
937                     (KERN_ERR "HDSPM: cannot change between single- and double-speed mode (capture PID = %d, playback PID = %d)\n",
938                      hdspm->capture_pid, hdspm->playback_pid);
939                 return -EBUSY;
940         }
941
942         hdspm->control_register &= ~HDSPM_FrequencyMask;
943         hdspm->control_register |= rate_bits;
944         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
945
946         /* For AES32, need to set DDS value in FREQ register
947            For MADI, also apparently */
948         hdspm_set_dds_value(hdspm, rate);
949         
950         if (hdspm->is_aes32 && rate != current_rate)
951                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
952         
953         /* For AES32 and for MADI (at least rev 204), channel_map needs to
954          * always be channel_map_madi_ss, whatever the sample rate */
955         hdspm->channel_map = channel_map_madi_ss;
956
957         hdspm->system_sample_rate = rate;
958
959         if (not_set != 0)
960                 return -1;
961
962         return 0;
963 }
964
965 /* mainly for init to 0 on load */
966 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
967 {
968         int i, j;
969         unsigned int gain =
970             (sgain > UNITY_GAIN) ? UNITY_GAIN : (sgain < 0) ? 0 : sgain;
971
972         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
973                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
974                         hdspm_write_in_gain(hdspm, i, j, gain);
975                         hdspm_write_pb_gain(hdspm, i, j, gain);
976                 }
977 }
978
979 /*----------------------------------------------------------------------------
980    MIDI
981   ----------------------------------------------------------------------------*/
982
983 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, int id)
984 {
985         /* the hardware already does the relevant bit-mask with 0xff */
986         if (id)
987                 return hdspm_read(hdspm, HDSPM_midiDataIn1);
988         else
989                 return hdspm_read(hdspm, HDSPM_midiDataIn0);
990 }
991
992 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, int val)
993 {
994         /* the hardware already does the relevant bit-mask with 0xff */
995         if (id)
996                 return hdspm_write(hdspm, HDSPM_midiDataOut1, val);
997         else
998                 return hdspm_write(hdspm, HDSPM_midiDataOut0, val);
999 }
1000
1001 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1002 {
1003         if (id)
1004                 return (hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff);
1005         else
1006                 return (hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff);
1007 }
1008
1009 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1010 {
1011         int fifo_bytes_used;
1012
1013         if (id)
1014                 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xff;
1015         else
1016                 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xff;
1017
1018         if (fifo_bytes_used < 128)
1019                 return  128 - fifo_bytes_used;
1020         else
1021                 return 0;
1022 }
1023
1024 static inline void snd_hdspm_flush_midi_input (struct hdspm *hdspm, int id)
1025 {
1026         while (snd_hdspm_midi_input_available (hdspm, id))
1027                 snd_hdspm_midi_read_byte (hdspm, id);
1028 }
1029
1030 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1031 {
1032         unsigned long flags;
1033         int n_pending;
1034         int to_write;
1035         int i;
1036         unsigned char buf[128];
1037
1038         /* Output is not interrupt driven */
1039                 
1040         spin_lock_irqsave (&hmidi->lock, flags);
1041         if (hmidi->output) {
1042                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1043                         if ((n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, hmidi->id)) > 0) {
1044                                 if (n_pending > (int)sizeof (buf))
1045                                         n_pending = sizeof (buf);
1046                                 
1047                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1048                                         for (i = 0; i < to_write; ++i) 
1049                                                 snd_hdspm_midi_write_byte (hmidi->hdspm, hmidi->id, buf[i]);
1050                                 }
1051                         }
1052                 }
1053         }
1054         spin_unlock_irqrestore (&hmidi->lock, flags);
1055         return 0;
1056 }
1057
1058 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1059 {
1060         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1061         unsigned long flags;
1062         int n_pending;
1063         int i;
1064
1065         spin_lock_irqsave (&hmidi->lock, flags);
1066         if ((n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id)) > 0) {
1067                 if (hmidi->input) {
1068                         if (n_pending > (int)sizeof (buf)) {
1069                                 n_pending = sizeof (buf);
1070                         }
1071                         for (i = 0; i < n_pending; ++i) {
1072                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, hmidi->id);
1073                         }
1074                         if (n_pending) {
1075                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1076                         }
1077                 } else {
1078                         /* flush the MIDI input FIFO */
1079                         while (n_pending--) {
1080                                 snd_hdspm_midi_read_byte (hmidi->hdspm, hmidi->id);
1081                         }
1082                 }
1083         }
1084         hmidi->pending = 0;
1085         if (hmidi->id) {
1086                 hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable;
1087         } else {
1088                 hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable;
1089         }
1090         hdspm_write(hmidi->hdspm, HDSPM_controlRegister, hmidi->hdspm->control_register);
1091         spin_unlock_irqrestore (&hmidi->lock, flags);
1092         return snd_hdspm_midi_output_write (hmidi);
1093 }
1094
1095 static void snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1096 {
1097         struct hdspm *hdspm;
1098         struct hdspm_midi *hmidi;
1099         unsigned long flags;
1100         u32 ie;
1101
1102         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1103         hdspm = hmidi->hdspm;
1104         ie = hmidi->id ? HDSPM_Midi1InterruptEnable : HDSPM_Midi0InterruptEnable;
1105         spin_lock_irqsave (&hdspm->lock, flags);
1106         if (up) {
1107                 if (!(hdspm->control_register & ie)) {
1108                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1109                         hdspm->control_register |= ie;
1110                 }
1111         } else {
1112                 hdspm->control_register &= ~ie;
1113         }
1114
1115         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1116         spin_unlock_irqrestore (&hdspm->lock, flags);
1117 }
1118
1119 static void snd_hdspm_midi_output_timer(unsigned long data)
1120 {
1121         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1122         unsigned long flags;
1123         
1124         snd_hdspm_midi_output_write(hmidi);
1125         spin_lock_irqsave (&hmidi->lock, flags);
1126
1127         /* this does not bump hmidi->istimer, because the
1128            kernel automatically removed the timer when it
1129            expired, and we are now adding it back, thus
1130            leaving istimer wherever it was set before.  
1131         */
1132
1133         if (hmidi->istimer) {
1134                 hmidi->timer.expires = 1 + jiffies;
1135                 add_timer(&hmidi->timer);
1136         }
1137
1138         spin_unlock_irqrestore (&hmidi->lock, flags);
1139 }
1140
1141 static void snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1142 {
1143         struct hdspm_midi *hmidi;
1144         unsigned long flags;
1145
1146         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1147         spin_lock_irqsave (&hmidi->lock, flags);
1148         if (up) {
1149                 if (!hmidi->istimer) {
1150                         init_timer(&hmidi->timer);
1151                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1152                         hmidi->timer.data = (unsigned long) hmidi;
1153                         hmidi->timer.expires = 1 + jiffies;
1154                         add_timer(&hmidi->timer);
1155                         hmidi->istimer++;
1156                 }
1157         } else {
1158                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1159                         del_timer (&hmidi->timer);
1160                 }
1161         }
1162         spin_unlock_irqrestore (&hmidi->lock, flags);
1163         if (up)
1164                 snd_hdspm_midi_output_write(hmidi);
1165 }
1166
1167 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1168 {
1169         struct hdspm_midi *hmidi;
1170
1171         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1172         spin_lock_irq (&hmidi->lock);
1173         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1174         hmidi->input = substream;
1175         spin_unlock_irq (&hmidi->lock);
1176
1177         return 0;
1178 }
1179
1180 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1181 {
1182         struct hdspm_midi *hmidi;
1183
1184         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1185         spin_lock_irq (&hmidi->lock);
1186         hmidi->output = substream;
1187         spin_unlock_irq (&hmidi->lock);
1188
1189         return 0;
1190 }
1191
1192 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1193 {
1194         struct hdspm_midi *hmidi;
1195
1196         snd_hdspm_midi_input_trigger (substream, 0);
1197
1198         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1199         spin_lock_irq (&hmidi->lock);
1200         hmidi->input = NULL;
1201         spin_unlock_irq (&hmidi->lock);
1202
1203         return 0;
1204 }
1205
1206 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1207 {
1208         struct hdspm_midi *hmidi;
1209
1210         snd_hdspm_midi_output_trigger (substream, 0);
1211
1212         hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
1213         spin_lock_irq (&hmidi->lock);
1214         hmidi->output = NULL;
1215         spin_unlock_irq (&hmidi->lock);
1216
1217         return 0;
1218 }
1219
1220 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1221 {
1222         .open =         snd_hdspm_midi_output_open,
1223         .close =        snd_hdspm_midi_output_close,
1224         .trigger =      snd_hdspm_midi_output_trigger,
1225 };
1226
1227 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1228 {
1229         .open =         snd_hdspm_midi_input_open,
1230         .close =        snd_hdspm_midi_input_close,
1231         .trigger =      snd_hdspm_midi_input_trigger,
1232 };
1233
1234 static int __devinit snd_hdspm_create_midi (struct snd_card *card, struct hdspm *hdspm, int id)
1235 {
1236         int err;
1237         char buf[32];
1238
1239         hdspm->midi[id].id = id;
1240         hdspm->midi[id].rmidi = NULL;
1241         hdspm->midi[id].input = NULL;
1242         hdspm->midi[id].output = NULL;
1243         hdspm->midi[id].hdspm = hdspm;
1244         hdspm->midi[id].istimer = 0;
1245         hdspm->midi[id].pending = 0;
1246         spin_lock_init (&hdspm->midi[id].lock);
1247
1248         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1249         if ((err = snd_rawmidi_new (card, buf, id, 1, 1, &hdspm->midi[id].rmidi)) < 0)
1250                 return err;
1251
1252         sprintf (hdspm->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1253         hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1254
1255         snd_rawmidi_set_ops (hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdspm_midi_output);
1256         snd_rawmidi_set_ops (hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdspm_midi_input);
1257
1258         hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1259                 SNDRV_RAWMIDI_INFO_INPUT |
1260                 SNDRV_RAWMIDI_INFO_DUPLEX;
1261
1262         return 0;
1263 }
1264
1265
1266 static void hdspm_midi_tasklet(unsigned long arg)
1267 {
1268         struct hdspm *hdspm = (struct hdspm *)arg;
1269         
1270         if (hdspm->midi[0].pending)
1271                 snd_hdspm_midi_input_read (&hdspm->midi[0]);
1272         if (hdspm->midi[1].pending)
1273                 snd_hdspm_midi_input_read (&hdspm->midi[1]);
1274
1275
1276
1277 /*-----------------------------------------------------------------------------
1278   Status Interface
1279   ----------------------------------------------------------------------------*/
1280
1281 /* get the system sample rate which is set */
1282
1283 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1284 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1285   .name = xname, \
1286   .index = xindex, \
1287   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1288   .info = snd_hdspm_info_system_sample_rate, \
1289   .get = snd_hdspm_get_system_sample_rate \
1290 }
1291
1292 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1293                                              struct snd_ctl_elem_info *uinfo)
1294 {
1295         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1296         uinfo->count = 1;
1297         return 0;
1298 }
1299
1300 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1301                                             struct snd_ctl_elem_value *
1302                                             ucontrol)
1303 {
1304         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1305
1306         ucontrol->value.enumerated.item[0] = hdspm->system_sample_rate;
1307         return 0;
1308 }
1309
1310 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1311 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1312   .name = xname, \
1313   .index = xindex, \
1314   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1315   .info = snd_hdspm_info_autosync_sample_rate, \
1316   .get = snd_hdspm_get_autosync_sample_rate \
1317 }
1318
1319 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1320                                                struct snd_ctl_elem_info *uinfo)
1321 {
1322         static char *texts[] = { "32000", "44100", "48000",
1323                 "64000", "88200", "96000",
1324                 "128000", "176400", "192000",
1325                 "None"
1326         };
1327         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1328         uinfo->count = 1;
1329         uinfo->value.enumerated.items = 10;
1330         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1331                 uinfo->value.enumerated.item =
1332                     uinfo->value.enumerated.items - 1;
1333         strcpy(uinfo->value.enumerated.name,
1334                texts[uinfo->value.enumerated.item]);
1335         return 0;
1336 }
1337
1338 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1339                                               struct snd_ctl_elem_value *
1340                                               ucontrol)
1341 {
1342         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1343
1344         switch (hdspm_external_sample_rate(hdspm)) {
1345         case 32000:
1346                 ucontrol->value.enumerated.item[0] = 0;
1347                 break;
1348         case 44100:
1349                 ucontrol->value.enumerated.item[0] = 1;
1350                 break;
1351         case 48000:
1352                 ucontrol->value.enumerated.item[0] = 2;
1353                 break;
1354         case 64000:
1355                 ucontrol->value.enumerated.item[0] = 3;
1356                 break;
1357         case 88200:
1358                 ucontrol->value.enumerated.item[0] = 4;
1359                 break;
1360         case 96000:
1361                 ucontrol->value.enumerated.item[0] = 5;
1362                 break;
1363         case 128000:
1364                 ucontrol->value.enumerated.item[0] = 6;
1365                 break;
1366         case 176400:
1367                 ucontrol->value.enumerated.item[0] = 7;
1368                 break;
1369         case 192000:
1370                 ucontrol->value.enumerated.item[0] = 8;
1371                 break;
1372
1373         default:
1374                 ucontrol->value.enumerated.item[0] = 9;
1375         }
1376         return 0;
1377 }
1378
1379 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
1380 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1381   .name = xname, \
1382   .index = xindex, \
1383   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1384   .info = snd_hdspm_info_system_clock_mode, \
1385   .get = snd_hdspm_get_system_clock_mode, \
1386 }
1387
1388
1389
1390 static int hdspm_system_clock_mode(struct hdspm * hdspm)
1391 {
1392         /* Always reflect the hardware info, rme is never wrong !!!! */
1393
1394         if (hdspm->control_register & HDSPM_ClockModeMaster)
1395                 return 0;
1396         return 1;
1397 }
1398
1399 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
1400                                             struct snd_ctl_elem_info *uinfo)
1401 {
1402         static char *texts[] = { "Master", "Slave" };
1403
1404         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1405         uinfo->count = 1;
1406         uinfo->value.enumerated.items = 2;
1407         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1408                 uinfo->value.enumerated.item =
1409                     uinfo->value.enumerated.items - 1;
1410         strcpy(uinfo->value.enumerated.name,
1411                texts[uinfo->value.enumerated.item]);
1412         return 0;
1413 }
1414
1415 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
1416                                            struct snd_ctl_elem_value *ucontrol)
1417 {
1418         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1419
1420         ucontrol->value.enumerated.item[0] =
1421             hdspm_system_clock_mode(hdspm);
1422         return 0;
1423 }
1424
1425 #define HDSPM_CLOCK_SOURCE(xname, xindex) \
1426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1427   .name = xname, \
1428   .index = xindex, \
1429   .info = snd_hdspm_info_clock_source, \
1430   .get = snd_hdspm_get_clock_source, \
1431   .put = snd_hdspm_put_clock_source \
1432 }
1433
1434 static int hdspm_clock_source(struct hdspm * hdspm)
1435 {
1436         if (hdspm->control_register & HDSPM_ClockModeMaster) {
1437                 switch (hdspm->system_sample_rate) {
1438                 case 32000:
1439                         return 1;
1440                 case 44100:
1441                         return 2;
1442                 case 48000:
1443                         return 3;
1444                 case 64000:
1445                         return 4;
1446                 case 88200:
1447                         return 5;
1448                 case 96000:
1449                         return 6;
1450                 case 128000:
1451                         return 7;
1452                 case 176400:
1453                         return 8;
1454                 case 192000:
1455                         return 9;
1456                 default:
1457                         return 3;
1458                 }
1459         } else {
1460                 return 0;
1461         }
1462 }
1463
1464 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
1465 {
1466         int rate;
1467         switch (mode) {
1468
1469         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
1470                 if (hdspm_external_sample_rate(hdspm) != 0) {
1471                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
1472                         hdspm_write(hdspm, HDSPM_controlRegister,
1473                                     hdspm->control_register);
1474                         return 0;
1475                 }
1476                 return -1;
1477         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
1478                 rate = 32000;
1479                 break;
1480         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1481                 rate = 44100;
1482                 break;
1483         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
1484                 rate = 48000;
1485                 break;
1486         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
1487                 rate = 64000;
1488                 break;
1489         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1490                 rate = 88200;
1491                 break;
1492         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
1493                 rate = 96000;
1494                 break;
1495         case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
1496                 rate = 128000;
1497                 break;
1498         case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1499                 rate = 176400;
1500                 break;
1501         case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
1502                 rate = 192000;
1503                 break;
1504
1505         default:
1506                 rate = 44100;
1507         }
1508         hdspm->control_register |= HDSPM_ClockModeMaster;
1509         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1510         hdspm_set_rate(hdspm, rate, 1);
1511         return 0;
1512 }
1513
1514 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
1515                                        struct snd_ctl_elem_info *uinfo)
1516 {
1517         static char *texts[] = { "AutoSync",
1518                 "Internal 32.0 kHz", "Internal 44.1 kHz",
1519                     "Internal 48.0 kHz",
1520                 "Internal 64.0 kHz", "Internal 88.2 kHz",
1521                     "Internal 96.0 kHz",
1522                 "Internal 128.0 kHz", "Internal 176.4 kHz",
1523                     "Internal 192.0 kHz"
1524         };
1525
1526         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1527         uinfo->count = 1;
1528         uinfo->value.enumerated.items = 10;
1529
1530         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1531                 uinfo->value.enumerated.item =
1532                     uinfo->value.enumerated.items - 1;
1533
1534         strcpy(uinfo->value.enumerated.name,
1535                texts[uinfo->value.enumerated.item]);
1536
1537         return 0;
1538 }
1539
1540 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
1541                                       struct snd_ctl_elem_value *ucontrol)
1542 {
1543         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1544
1545         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
1546         return 0;
1547 }
1548
1549 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
1550                                       struct snd_ctl_elem_value *ucontrol)
1551 {
1552         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1553         int change;
1554         int val;
1555
1556         if (!snd_hdspm_use_is_exclusive(hdspm))
1557                 return -EBUSY;
1558         val = ucontrol->value.enumerated.item[0];
1559         if (val < 0)
1560                 val = 0;
1561         if (val > 6)
1562                 val = 6;
1563         spin_lock_irq(&hdspm->lock);
1564         if (val != hdspm_clock_source(hdspm))
1565                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
1566         else
1567                 change = 0;
1568         spin_unlock_irq(&hdspm->lock);
1569         return change;
1570 }
1571
1572 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
1573 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1574   .name = xname, \
1575   .index = xindex, \
1576   .info = snd_hdspm_info_pref_sync_ref, \
1577   .get = snd_hdspm_get_pref_sync_ref, \
1578   .put = snd_hdspm_put_pref_sync_ref \
1579 }
1580
1581 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
1582 {
1583         /* Notice that this looks at the requested sync source,
1584            not the one actually in use.
1585          */
1586         if (hdspm->is_aes32) {
1587                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1588                 /* number gives AES index, except for 0 which
1589                    corresponds to WordClock */
1590                 case 0: return 0;
1591                 case HDSPM_SyncRef0: return 1;
1592                 case HDSPM_SyncRef1: return 2;
1593                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3;
1594                 case HDSPM_SyncRef2: return 4;
1595                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5;
1596                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6;
1597                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: return 7;
1598                 case HDSPM_SyncRef3: return 8;
1599                 }
1600         } else {
1601                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1602                 case HDSPM_SyncRef_Word:
1603                         return HDSPM_SYNC_FROM_WORD;
1604                 case HDSPM_SyncRef_MADI:
1605                         return HDSPM_SYNC_FROM_MADI;
1606                 }
1607         }
1608
1609         return HDSPM_SYNC_FROM_WORD;
1610 }
1611
1612 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
1613 {
1614         hdspm->control_register &= ~HDSPM_SyncRefMask;
1615
1616         if (hdspm->is_aes32) {
1617                 switch (pref) {
1618                 case 0:
1619                        hdspm->control_register |= 0;
1620                        break;
1621                 case 1:
1622                        hdspm->control_register |= HDSPM_SyncRef0;
1623                        break;
1624                 case 2:
1625                        hdspm->control_register |= HDSPM_SyncRef1;
1626                        break;
1627                 case 3:
1628                        hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0;
1629                        break;
1630                 case 4:
1631                        hdspm->control_register |= HDSPM_SyncRef2;
1632                        break;
1633                 case 5:
1634                        hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0;
1635                        break;
1636                 case 6:
1637                        hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1;
1638                        break;
1639                 case 7:
1640                        hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
1641                        break;
1642                 case 8:
1643                        hdspm->control_register |= HDSPM_SyncRef3;
1644                        break;
1645                 default:
1646                        return -1;
1647                 }
1648         } else {
1649                 switch (pref) {
1650                 case HDSPM_SYNC_FROM_MADI:
1651                         hdspm->control_register |= HDSPM_SyncRef_MADI;
1652                         break;
1653                 case HDSPM_SYNC_FROM_WORD:
1654                         hdspm->control_register |= HDSPM_SyncRef_Word;
1655                         break;
1656                 default:
1657                         return -1;
1658                 }
1659         }
1660         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1661         return 0;
1662 }
1663
1664 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
1665                                         struct snd_ctl_elem_info *uinfo)
1666 {
1667         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1668
1669         if (hdspm->is_aes32) {
1670                 static char *texts[] = { "Word", "AES1", "AES2", "AES3",
1671                         "AES4", "AES5", "AES6", "AES7", "AES8" };
1672
1673                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1674                 uinfo->count = 1;
1675
1676                 uinfo->value.enumerated.items = 9;
1677
1678                 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1679                         uinfo->value.enumerated.item =
1680                                 uinfo->value.enumerated.items - 1;
1681                 strcpy(uinfo->value.enumerated.name,
1682                                 texts[uinfo->value.enumerated.item]);
1683         } else {
1684                 static char *texts[] = { "Word", "MADI" };
1685
1686                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1687                 uinfo->count = 1;
1688
1689                 uinfo->value.enumerated.items = 2;
1690
1691                 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1692                         uinfo->value.enumerated.item =
1693                                 uinfo->value.enumerated.items - 1;
1694                 strcpy(uinfo->value.enumerated.name,
1695                                 texts[uinfo->value.enumerated.item]);
1696         }
1697         return 0;
1698 }
1699
1700 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
1701                                        struct snd_ctl_elem_value *ucontrol)
1702 {
1703         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1704
1705         ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1706         return 0;
1707 }
1708
1709 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
1710                                        struct snd_ctl_elem_value *ucontrol)
1711 {
1712         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1713         int change, max;
1714         unsigned int val;
1715
1716         max = hdspm->is_aes32 ? 9 : 2;
1717
1718         if (!snd_hdspm_use_is_exclusive(hdspm))
1719                 return -EBUSY;
1720
1721         val = ucontrol->value.enumerated.item[0] % max;
1722
1723         spin_lock_irq(&hdspm->lock);
1724         change = (int) val != hdspm_pref_sync_ref(hdspm);
1725         hdspm_set_pref_sync_ref(hdspm, val);
1726         spin_unlock_irq(&hdspm->lock);
1727         return change;
1728 }
1729
1730 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
1731 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1732   .name = xname, \
1733   .index = xindex, \
1734   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1735   .info = snd_hdspm_info_autosync_ref, \
1736   .get = snd_hdspm_get_autosync_ref, \
1737 }
1738
1739 static int hdspm_autosync_ref(struct hdspm * hdspm)
1740 {
1741         if (hdspm->is_aes32) {
1742                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
1743                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
1744                 if (syncref == 0)
1745                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
1746                 if (syncref <= 8)
1747                         return syncref;
1748                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
1749         } else {
1750                 /* This looks at the autosync selected sync reference */
1751                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1752
1753                 switch (status2 & HDSPM_SelSyncRefMask) {
1754                 case HDSPM_SelSyncRef_WORD:
1755                         return HDSPM_AUTOSYNC_FROM_WORD;
1756                 case HDSPM_SelSyncRef_MADI:
1757                         return HDSPM_AUTOSYNC_FROM_MADI;
1758                 case HDSPM_SelSyncRef_NVALID:
1759                         return HDSPM_AUTOSYNC_FROM_NONE;
1760                 default:
1761                         return 0;
1762                 }
1763
1764                 return 0;
1765         }
1766 }
1767
1768 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
1769                                        struct snd_ctl_elem_info *uinfo)
1770 {
1771         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1772
1773         if (hdspm->is_aes32) {
1774                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
1775                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
1776
1777                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1778                 uinfo->count = 1;
1779                 uinfo->value.enumerated.items = 10;
1780                 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1781                         uinfo->value.enumerated.item =
1782                                 uinfo->value.enumerated.items - 1;
1783                 strcpy(uinfo->value.enumerated.name,
1784                                 texts[uinfo->value.enumerated.item]);
1785         }
1786         else
1787         {
1788                 static char *texts[] = { "WordClock", "MADI", "None" };
1789
1790                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1791                 uinfo->count = 1;
1792                 uinfo->value.enumerated.items = 3;
1793                 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1794                         uinfo->value.enumerated.item =
1795                                 uinfo->value.enumerated.items - 1;
1796                 strcpy(uinfo->value.enumerated.name,
1797                                 texts[uinfo->value.enumerated.item]);
1798         }
1799         return 0;
1800 }
1801
1802 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
1803                                       struct snd_ctl_elem_value *ucontrol)
1804 {
1805         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1806
1807         ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1808         return 0;
1809 }
1810
1811 #define HDSPM_LINE_OUT(xname, xindex) \
1812 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1813   .name = xname, \
1814   .index = xindex, \
1815   .info = snd_hdspm_info_line_out, \
1816   .get = snd_hdspm_get_line_out, \
1817   .put = snd_hdspm_put_line_out \
1818 }
1819
1820 static int hdspm_line_out(struct hdspm * hdspm)
1821 {
1822         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
1823 }
1824
1825
1826 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
1827 {
1828         if (out)
1829                 hdspm->control_register |= HDSPM_LineOut;
1830         else
1831                 hdspm->control_register &= ~HDSPM_LineOut;
1832         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1833
1834         return 0;
1835 }
1836
1837 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
1838
1839 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
1840                                   struct snd_ctl_elem_value *ucontrol)
1841 {
1842         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1843
1844         spin_lock_irq(&hdspm->lock);
1845         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
1846         spin_unlock_irq(&hdspm->lock);
1847         return 0;
1848 }
1849
1850 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
1851                                   struct snd_ctl_elem_value *ucontrol)
1852 {
1853         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1854         int change;
1855         unsigned int val;
1856
1857         if (!snd_hdspm_use_is_exclusive(hdspm))
1858                 return -EBUSY;
1859         val = ucontrol->value.integer.value[0] & 1;
1860         spin_lock_irq(&hdspm->lock);
1861         change = (int) val != hdspm_line_out(hdspm);
1862         hdspm_set_line_output(hdspm, val);
1863         spin_unlock_irq(&hdspm->lock);
1864         return change;
1865 }
1866
1867 #define HDSPM_TX_64(xname, xindex) \
1868 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1869   .name = xname, \
1870   .index = xindex, \
1871   .info = snd_hdspm_info_tx_64, \
1872   .get = snd_hdspm_get_tx_64, \
1873   .put = snd_hdspm_put_tx_64 \
1874 }
1875
1876 static int hdspm_tx_64(struct hdspm * hdspm)
1877 {
1878         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
1879 }
1880
1881 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
1882 {
1883         if (out)
1884                 hdspm->control_register |= HDSPM_TX_64ch;
1885         else
1886                 hdspm->control_register &= ~HDSPM_TX_64ch;
1887         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1888
1889         return 0;
1890 }
1891
1892 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
1893
1894 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
1895                                struct snd_ctl_elem_value *ucontrol)
1896 {
1897         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1898
1899         spin_lock_irq(&hdspm->lock);
1900         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
1901         spin_unlock_irq(&hdspm->lock);
1902         return 0;
1903 }
1904
1905 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
1906                                struct snd_ctl_elem_value *ucontrol)
1907 {
1908         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1909         int change;
1910         unsigned int val;
1911
1912         if (!snd_hdspm_use_is_exclusive(hdspm))
1913                 return -EBUSY;
1914         val = ucontrol->value.integer.value[0] & 1;
1915         spin_lock_irq(&hdspm->lock);
1916         change = (int) val != hdspm_tx_64(hdspm);
1917         hdspm_set_tx_64(hdspm, val);
1918         spin_unlock_irq(&hdspm->lock);
1919         return change;
1920 }
1921
1922 #define HDSPM_C_TMS(xname, xindex) \
1923 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1924   .name = xname, \
1925   .index = xindex, \
1926   .info = snd_hdspm_info_c_tms, \
1927   .get = snd_hdspm_get_c_tms, \
1928   .put = snd_hdspm_put_c_tms \
1929 }
1930
1931 static int hdspm_c_tms(struct hdspm * hdspm)
1932 {
1933         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
1934 }
1935
1936 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
1937 {
1938         if (out)
1939                 hdspm->control_register |= HDSPM_clr_tms;
1940         else
1941                 hdspm->control_register &= ~HDSPM_clr_tms;
1942         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1943
1944         return 0;
1945 }
1946
1947 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
1948
1949 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
1950                                struct snd_ctl_elem_value *ucontrol)
1951 {
1952         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1953
1954         spin_lock_irq(&hdspm->lock);
1955         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
1956         spin_unlock_irq(&hdspm->lock);
1957         return 0;
1958 }
1959
1960 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
1961                                struct snd_ctl_elem_value *ucontrol)
1962 {
1963         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1964         int change;
1965         unsigned int val;
1966
1967         if (!snd_hdspm_use_is_exclusive(hdspm))
1968                 return -EBUSY;
1969         val = ucontrol->value.integer.value[0] & 1;
1970         spin_lock_irq(&hdspm->lock);
1971         change = (int) val != hdspm_c_tms(hdspm);
1972         hdspm_set_c_tms(hdspm, val);
1973         spin_unlock_irq(&hdspm->lock);
1974         return change;
1975 }
1976
1977 #define HDSPM_SAFE_MODE(xname, xindex) \
1978 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1979   .name = xname, \
1980   .index = xindex, \
1981   .info = snd_hdspm_info_safe_mode, \
1982   .get = snd_hdspm_get_safe_mode, \
1983   .put = snd_hdspm_put_safe_mode \
1984 }
1985
1986 static int hdspm_safe_mode(struct hdspm * hdspm)
1987 {
1988         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
1989 }
1990
1991 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
1992 {
1993         if (out)
1994                 hdspm->control_register |= HDSPM_AutoInp;
1995         else
1996                 hdspm->control_register &= ~HDSPM_AutoInp;
1997         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1998
1999         return 0;
2000 }
2001
2002 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
2003
2004 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2005                                    struct snd_ctl_elem_value *ucontrol)
2006 {
2007         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2008
2009         spin_lock_irq(&hdspm->lock);
2010         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2011         spin_unlock_irq(&hdspm->lock);
2012         return 0;
2013 }
2014
2015 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
2016                                    struct snd_ctl_elem_value *ucontrol)
2017 {
2018         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2019         int change;
2020         unsigned int val;
2021
2022         if (!snd_hdspm_use_is_exclusive(hdspm))
2023                 return -EBUSY;
2024         val = ucontrol->value.integer.value[0] & 1;
2025         spin_lock_irq(&hdspm->lock);
2026         change = (int) val != hdspm_safe_mode(hdspm);
2027         hdspm_set_safe_mode(hdspm, val);
2028         spin_unlock_irq(&hdspm->lock);
2029         return change;
2030 }
2031
2032 #define HDSPM_EMPHASIS(xname, xindex) \
2033 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2034   .name = xname, \
2035   .index = xindex, \
2036   .info = snd_hdspm_info_emphasis, \
2037   .get = snd_hdspm_get_emphasis, \
2038   .put = snd_hdspm_put_emphasis \
2039 }
2040
2041 static int hdspm_emphasis(struct hdspm * hdspm)
2042 {
2043         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
2044 }
2045
2046 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
2047 {
2048         if (emp)
2049                 hdspm->control_register |= HDSPM_Emphasis;
2050         else
2051                 hdspm->control_register &= ~HDSPM_Emphasis;
2052         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2053
2054         return 0;
2055 }
2056
2057 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
2058
2059 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
2060                                   struct snd_ctl_elem_value *ucontrol)
2061 {
2062         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2063
2064         spin_lock_irq(&hdspm->lock);
2065         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
2066         spin_unlock_irq(&hdspm->lock);
2067         return 0;
2068 }
2069
2070 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
2071                                   struct snd_ctl_elem_value *ucontrol)
2072 {
2073         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2074         int change;
2075         unsigned int val;
2076
2077         if (!snd_hdspm_use_is_exclusive(hdspm))
2078                 return -EBUSY;
2079         val = ucontrol->value.integer.value[0] & 1;
2080         spin_lock_irq(&hdspm->lock);
2081         change = (int) val != hdspm_emphasis(hdspm);
2082         hdspm_set_emphasis(hdspm, val);
2083         spin_unlock_irq(&hdspm->lock);
2084         return change;
2085 }
2086
2087 #define HDSPM_DOLBY(xname, xindex) \
2088 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2089   .name = xname, \
2090   .index = xindex, \
2091   .info = snd_hdspm_info_dolby, \
2092   .get = snd_hdspm_get_dolby, \
2093   .put = snd_hdspm_put_dolby \
2094 }
2095
2096 static int hdspm_dolby(struct hdspm * hdspm)
2097 {
2098         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
2099 }
2100
2101 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
2102 {
2103         if (dol)
2104                 hdspm->control_register |= HDSPM_Dolby;
2105         else
2106                 hdspm->control_register &= ~HDSPM_Dolby;
2107         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2108
2109         return 0;
2110 }
2111
2112 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
2113
2114 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
2115                                struct snd_ctl_elem_value *ucontrol)
2116 {
2117         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2118
2119         spin_lock_irq(&hdspm->lock);
2120         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
2121         spin_unlock_irq(&hdspm->lock);
2122         return 0;
2123 }
2124
2125 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
2126                                struct snd_ctl_elem_value *ucontrol)
2127 {
2128         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2129         int change;
2130         unsigned int val;
2131
2132         if (!snd_hdspm_use_is_exclusive(hdspm))
2133                 return -EBUSY;
2134         val = ucontrol->value.integer.value[0] & 1;
2135         spin_lock_irq(&hdspm->lock);
2136         change = (int) val != hdspm_dolby(hdspm);
2137         hdspm_set_dolby(hdspm, val);
2138         spin_unlock_irq(&hdspm->lock);
2139         return change;
2140 }
2141
2142 #define HDSPM_PROFESSIONAL(xname, xindex) \
2143 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2144   .name = xname, \
2145   .index = xindex, \
2146   .info = snd_hdspm_info_professional, \
2147   .get = snd_hdspm_get_professional, \
2148   .put = snd_hdspm_put_professional \
2149 }
2150
2151 static int hdspm_professional(struct hdspm * hdspm)
2152 {
2153         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
2154 }
2155
2156 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
2157 {
2158         if (dol)
2159                 hdspm->control_register |= HDSPM_Professional;
2160         else
2161                 hdspm->control_register &= ~HDSPM_Professional;
2162         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2163
2164         return 0;
2165 }
2166
2167 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
2168
2169 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
2170                                       struct snd_ctl_elem_value *ucontrol)
2171 {
2172         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2173
2174         spin_lock_irq(&hdspm->lock);
2175         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
2176         spin_unlock_irq(&hdspm->lock);
2177         return 0;
2178 }
2179
2180 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
2181                                       struct snd_ctl_elem_value *ucontrol)
2182 {
2183         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2184         int change;
2185         unsigned int val;
2186
2187         if (!snd_hdspm_use_is_exclusive(hdspm))
2188                 return -EBUSY;
2189         val = ucontrol->value.integer.value[0] & 1;
2190         spin_lock_irq(&hdspm->lock);
2191         change = (int) val != hdspm_professional(hdspm);
2192         hdspm_set_professional(hdspm, val);
2193         spin_unlock_irq(&hdspm->lock);
2194         return change;
2195 }
2196
2197 #define HDSPM_INPUT_SELECT(xname, xindex) \
2198 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2199   .name = xname, \
2200   .index = xindex, \
2201   .info = snd_hdspm_info_input_select, \
2202   .get = snd_hdspm_get_input_select, \
2203   .put = snd_hdspm_put_input_select \
2204 }
2205
2206 static int hdspm_input_select(struct hdspm * hdspm)
2207 {
2208         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
2209 }
2210
2211 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
2212 {
2213         if (out)
2214                 hdspm->control_register |= HDSPM_InputSelect0;
2215         else
2216                 hdspm->control_register &= ~HDSPM_InputSelect0;
2217         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2218
2219         return 0;
2220 }
2221
2222 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
2223                                        struct snd_ctl_elem_info *uinfo)
2224 {
2225         static char *texts[] = { "optical", "coaxial" };
2226
2227         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2228         uinfo->count = 1;
2229         uinfo->value.enumerated.items = 2;
2230
2231         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2232                 uinfo->value.enumerated.item =
2233                     uinfo->value.enumerated.items - 1;
2234         strcpy(uinfo->value.enumerated.name,
2235                texts[uinfo->value.enumerated.item]);
2236
2237         return 0;
2238 }
2239
2240 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
2241                                       struct snd_ctl_elem_value *ucontrol)
2242 {
2243         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2244
2245         spin_lock_irq(&hdspm->lock);
2246         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
2247         spin_unlock_irq(&hdspm->lock);
2248         return 0;
2249 }
2250
2251 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
2252                                       struct snd_ctl_elem_value *ucontrol)
2253 {
2254         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2255         int change;
2256         unsigned int val;
2257
2258         if (!snd_hdspm_use_is_exclusive(hdspm))
2259                 return -EBUSY;
2260         val = ucontrol->value.integer.value[0] & 1;
2261         spin_lock_irq(&hdspm->lock);
2262         change = (int) val != hdspm_input_select(hdspm);
2263         hdspm_set_input_select(hdspm, val);
2264         spin_unlock_irq(&hdspm->lock);
2265         return change;
2266 }
2267
2268 #define HDSPM_DS_WIRE(xname, xindex) \
2269 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2270   .name = xname, \
2271   .index = xindex, \
2272   .info = snd_hdspm_info_ds_wire, \
2273   .get = snd_hdspm_get_ds_wire, \
2274   .put = snd_hdspm_put_ds_wire \
2275 }
2276
2277 static int hdspm_ds_wire(struct hdspm * hdspm)
2278 {
2279         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
2280 }
2281
2282 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
2283 {
2284         if (ds)
2285                 hdspm->control_register |= HDSPM_DS_DoubleWire;
2286         else
2287                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
2288         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2289
2290         return 0;
2291 }
2292
2293 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
2294                                   struct snd_ctl_elem_info *uinfo)
2295 {
2296         static char *texts[] = { "Single", "Double" };
2297
2298         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2299         uinfo->count = 1;
2300         uinfo->value.enumerated.items = 2;
2301
2302         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2303                 uinfo->value.enumerated.item =
2304                     uinfo->value.enumerated.items - 1;
2305         strcpy(uinfo->value.enumerated.name,
2306                texts[uinfo->value.enumerated.item]);
2307
2308         return 0;
2309 }
2310
2311 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
2312                                  struct snd_ctl_elem_value *ucontrol)
2313 {
2314         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2315
2316         spin_lock_irq(&hdspm->lock);
2317         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
2318         spin_unlock_irq(&hdspm->lock);
2319         return 0;
2320 }
2321
2322 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
2323                                  struct snd_ctl_elem_value *ucontrol)
2324 {
2325         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2326         int change;
2327         unsigned int val;
2328
2329         if (!snd_hdspm_use_is_exclusive(hdspm))
2330                 return -EBUSY;
2331         val = ucontrol->value.integer.value[0] & 1;
2332         spin_lock_irq(&hdspm->lock);
2333         change = (int) val != hdspm_ds_wire(hdspm);
2334         hdspm_set_ds_wire(hdspm, val);
2335         spin_unlock_irq(&hdspm->lock);
2336         return change;
2337 }
2338
2339 #define HDSPM_QS_WIRE(xname, xindex) \
2340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2341   .name = xname, \
2342   .index = xindex, \
2343   .info = snd_hdspm_info_qs_wire, \
2344   .get = snd_hdspm_get_qs_wire, \
2345   .put = snd_hdspm_put_qs_wire \
2346 }
2347
2348 static int hdspm_qs_wire(struct hdspm * hdspm)
2349 {
2350         if (hdspm->control_register & HDSPM_QS_DoubleWire)
2351                 return 1;
2352         if (hdspm->control_register & HDSPM_QS_QuadWire)
2353                 return 2;
2354         return 0;
2355 }
2356
2357 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
2358 {
2359         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
2360         switch (mode) {
2361         case 0:
2362                 break;
2363         case 1:
2364                 hdspm->control_register |= HDSPM_QS_DoubleWire;
2365                 break;
2366         case 2:
2367                 hdspm->control_register |= HDSPM_QS_QuadWire;
2368                 break;
2369         }
2370         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2371
2372         return 0;
2373 }
2374
2375 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
2376                                        struct snd_ctl_elem_info *uinfo)
2377 {
2378         static char *texts[] = { "Single", "Double", "Quad" };
2379
2380         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2381         uinfo->count = 1;
2382         uinfo->value.enumerated.items = 3;
2383
2384         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2385                 uinfo->value.enumerated.item =
2386                     uinfo->value.enumerated.items - 1;
2387         strcpy(uinfo->value.enumerated.name,
2388                texts[uinfo->value.enumerated.item]);
2389
2390         return 0;
2391 }
2392
2393 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
2394                                       struct snd_ctl_elem_value *ucontrol)
2395 {
2396         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2397
2398         spin_lock_irq(&hdspm->lock);
2399         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
2400         spin_unlock_irq(&hdspm->lock);
2401         return 0;
2402 }
2403
2404 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
2405                                       struct snd_ctl_elem_value *ucontrol)
2406 {
2407         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2408         int change;
2409         int val;
2410
2411         if (!snd_hdspm_use_is_exclusive(hdspm))
2412                 return -EBUSY;
2413         val = ucontrol->value.integer.value[0];
2414         if (val < 0)
2415                 val = 0;
2416         if (val > 2)
2417                 val = 2;
2418         spin_lock_irq(&hdspm->lock);
2419         change = (int) val != hdspm_qs_wire(hdspm);
2420         hdspm_set_qs_wire(hdspm, val);
2421         spin_unlock_irq(&hdspm->lock);
2422         return change;
2423 }
2424
2425 /*           Simple Mixer
2426   deprecated since to much faders ???
2427   MIXER interface says output (source, destination, value)
2428    where source > MAX_channels are playback channels 
2429    on MADICARD 
2430   - playback mixer matrix: [channelout+64] [output] [value]
2431   - input(thru) mixer matrix: [channelin] [output] [value]
2432   (better do 2 kontrols for seperation ?)
2433 */
2434
2435 #define HDSPM_MIXER(xname, xindex) \
2436 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2437   .name = xname, \
2438   .index = xindex, \
2439   .device = 0, \
2440   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2441                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2442   .info = snd_hdspm_info_mixer, \
2443   .get = snd_hdspm_get_mixer, \
2444   .put = snd_hdspm_put_mixer \
2445 }
2446
2447 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
2448                                 struct snd_ctl_elem_info *uinfo)
2449 {
2450         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2451         uinfo->count = 3;
2452         uinfo->value.integer.min = 0;
2453         uinfo->value.integer.max = 65535;
2454         uinfo->value.integer.step = 1;
2455         return 0;
2456 }
2457
2458 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
2459                                struct snd_ctl_elem_value *ucontrol)
2460 {
2461         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2462         int source;
2463         int destination;
2464
2465         source = ucontrol->value.integer.value[0];
2466         if (source < 0)
2467                 source = 0;
2468         else if (source >= 2 * HDSPM_MAX_CHANNELS)
2469                 source = 2 * HDSPM_MAX_CHANNELS - 1;
2470
2471         destination = ucontrol->value.integer.value[1];
2472         if (destination < 0)
2473                 destination = 0;
2474         else if (destination >= HDSPM_MAX_CHANNELS)
2475                 destination = HDSPM_MAX_CHANNELS - 1;
2476
2477         spin_lock_irq(&hdspm->lock);
2478         if (source >= HDSPM_MAX_CHANNELS)
2479                 ucontrol->value.integer.value[2] =
2480                     hdspm_read_pb_gain(hdspm, destination,
2481                                        source - HDSPM_MAX_CHANNELS);
2482         else
2483                 ucontrol->value.integer.value[2] =
2484                     hdspm_read_in_gain(hdspm, destination, source);
2485
2486         spin_unlock_irq(&hdspm->lock);
2487
2488         return 0;
2489 }
2490
2491 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
2492                                struct snd_ctl_elem_value *ucontrol)
2493 {
2494         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2495         int change;
2496         int source;
2497         int destination;
2498         int gain;
2499
2500         if (!snd_hdspm_use_is_exclusive(hdspm))
2501                 return -EBUSY;
2502
2503         source = ucontrol->value.integer.value[0];
2504         destination = ucontrol->value.integer.value[1];
2505
2506         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
2507                 return -1;
2508         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
2509                 return -1;
2510
2511         gain = ucontrol->value.integer.value[2];
2512
2513         spin_lock_irq(&hdspm->lock);
2514
2515         if (source >= HDSPM_MAX_CHANNELS)
2516                 change = gain != hdspm_read_pb_gain(hdspm, destination,
2517                                                     source -
2518                                                     HDSPM_MAX_CHANNELS);
2519         else
2520                 change =
2521                     gain != hdspm_read_in_gain(hdspm, destination, source);
2522
2523         if (change) {
2524                 if (source >= HDSPM_MAX_CHANNELS)
2525                         hdspm_write_pb_gain(hdspm, destination,
2526                                             source - HDSPM_MAX_CHANNELS,
2527                                             gain);
2528                 else
2529                         hdspm_write_in_gain(hdspm, destination, source,
2530                                             gain);
2531         }
2532         spin_unlock_irq(&hdspm->lock);
2533
2534         return change;
2535 }
2536
2537 /* The simple mixer control(s) provide gain control for the
2538    basic 1:1 mappings of playback streams to output
2539    streams. 
2540 */
2541
2542 #define HDSPM_PLAYBACK_MIXER \
2543 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2544   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
2545                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2546   .info = snd_hdspm_info_playback_mixer, \
2547   .get = snd_hdspm_get_playback_mixer, \
2548   .put = snd_hdspm_put_playback_mixer \
2549 }
2550
2551 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
2552                                          struct snd_ctl_elem_info *uinfo)
2553 {
2554         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2555         uinfo->count = 1;
2556         uinfo->value.integer.min = 0;
2557         uinfo->value.integer.max = 65536;
2558         uinfo->value.integer.step = 1;
2559         return 0;
2560 }
2561
2562 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
2563                                         struct snd_ctl_elem_value *ucontrol)
2564 {
2565         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2566         int channel;
2567         int mapped_channel;
2568
2569         channel = ucontrol->id.index - 1;
2570
2571         snd_assert(channel >= 0
2572                    || channel < HDSPM_MAX_CHANNELS, return -EINVAL);
2573
2574         if ((mapped_channel = hdspm->channel_map[channel]) < 0)
2575                 return -EINVAL;
2576
2577         spin_lock_irq(&hdspm->lock);
2578         ucontrol->value.integer.value[0] =
2579             hdspm_read_pb_gain(hdspm, mapped_channel, mapped_channel);
2580         spin_unlock_irq(&hdspm->lock);
2581
2582         /*    snd_printdd("get pb mixer index %d, channel %d, mapped_channel %d, value %d\n",
2583            ucontrol->id.index,        channel, mapped_channel,  ucontrol->value.integer.value[0]); 
2584          */
2585
2586         return 0;
2587 }
2588
2589 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
2590                                         struct snd_ctl_elem_value *ucontrol)
2591 {
2592         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2593         int change;
2594         int channel;
2595         int mapped_channel;
2596         int gain;
2597
2598         if (!snd_hdspm_use_is_exclusive(hdspm))
2599                 return -EBUSY;
2600
2601         channel = ucontrol->id.index - 1;
2602
2603         snd_assert(channel >= 0
2604                    || channel < HDSPM_MAX_CHANNELS, return -EINVAL);
2605
2606         if ((mapped_channel = hdspm->channel_map[channel]) < 0)
2607                 return -EINVAL;
2608
2609         gain = ucontrol->value.integer.value[0];
2610
2611         spin_lock_irq(&hdspm->lock);
2612         change =
2613             gain != hdspm_read_pb_gain(hdspm, mapped_channel,
2614                                        mapped_channel);
2615         if (change)
2616                 hdspm_write_pb_gain(hdspm, mapped_channel, mapped_channel,
2617                                     gain);
2618         spin_unlock_irq(&hdspm->lock);
2619         return change;
2620 }
2621
2622 #define HDSPM_WC_SYNC_CHECK(xname, xindex) \
2623 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2624   .name = xname, \
2625   .index = xindex, \
2626   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2627   .info = snd_hdspm_info_sync_check, \
2628   .get = snd_hdspm_get_wc_sync_check \
2629 }
2630
2631 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
2632                                      struct snd_ctl_elem_info *uinfo)
2633 {
2634         static char *texts[] = { "No Lock", "Lock", "Sync" };
2635         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2636         uinfo->count = 1;
2637         uinfo->value.enumerated.items = 3;
2638         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2639                 uinfo->value.enumerated.item =
2640                     uinfo->value.enumerated.items - 1;
2641         strcpy(uinfo->value.enumerated.name,
2642                texts[uinfo->value.enumerated.item]);
2643         return 0;
2644 }
2645
2646 static int hdspm_wc_sync_check(struct hdspm * hdspm)
2647 {
2648         if (hdspm->is_aes32) {
2649                 int status = hdspm_read(hdspm, HDSPM_statusRegister);
2650                 if (status & HDSPM_AES32_wcLock) {
2651                         /* I don't know how to differenciate sync from lock.
2652                            Doing as if sync for now */
2653                         return 2;
2654                 }
2655                 return 0;
2656         } else {
2657                 int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2658                 if (status2 & HDSPM_wcLock) {
2659                         if (status2 & HDSPM_wcSync)
2660                                 return 2;
2661                         else
2662                                 return 1;
2663                 }
2664                 return 0;
2665         }
2666 }
2667
2668 static int snd_hdspm_get_wc_sync_check(struct snd_kcontrol *kcontrol,
2669                                        struct snd_ctl_elem_value *ucontrol)
2670 {
2671         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2672
2673         ucontrol->value.enumerated.item[0] = hdspm_wc_sync_check(hdspm);
2674         return 0;
2675 }
2676
2677
2678 #define HDSPM_MADI_SYNC_CHECK(xname, xindex) \
2679 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2680   .name = xname, \
2681   .index = xindex, \
2682   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2683   .info = snd_hdspm_info_sync_check, \
2684   .get = snd_hdspm_get_madisync_sync_check \
2685 }
2686
2687 static int hdspm_madisync_sync_check(struct hdspm * hdspm)
2688 {
2689         int status = hdspm_read(hdspm, HDSPM_statusRegister);
2690         if (status & HDSPM_madiLock) {
2691                 if (status & HDSPM_madiSync)
2692                         return 2;
2693                 else
2694                         return 1;
2695         }
2696         return 0;
2697 }
2698
2699 static int snd_hdspm_get_madisync_sync_check(struct snd_kcontrol *kcontrol,
2700                                              struct snd_ctl_elem_value *
2701                                              ucontrol)
2702 {
2703         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2704
2705         ucontrol->value.enumerated.item[0] =
2706             hdspm_madisync_sync_check(hdspm);
2707         return 0;
2708 }
2709
2710
2711 #define HDSPM_AES_SYNC_CHECK(xname, xindex) \
2712 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2713   .name = xname, \
2714   .index = xindex, \
2715   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2716   .info = snd_hdspm_info_sync_check, \
2717   .get = snd_hdspm_get_aes_sync_check \
2718 }
2719
2720 static int hdspm_aes_sync_check(struct hdspm * hdspm, int idx)
2721 {
2722         int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2723         if (status2 & (HDSPM_LockAES >> idx)) {
2724                 /* I don't know how to differenciate sync from lock.
2725                    Doing as if sync for now */
2726                 return 2;
2727         }
2728         return 0;
2729 }
2730
2731 static int snd_hdspm_get_aes_sync_check(struct snd_kcontrol *kcontrol,
2732                                         struct snd_ctl_elem_value *ucontrol)
2733 {
2734         int offset;
2735         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2736
2737         offset = ucontrol->id.index - 1;
2738         if (offset < 0 || offset >= 8)
2739                 return -EINVAL;
2740
2741         ucontrol->value.enumerated.item[0] =
2742                 hdspm_aes_sync_check(hdspm, offset);
2743         return 0;
2744 }
2745
2746
2747 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
2748
2749         HDSPM_MIXER("Mixer", 0),
2750 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2751         HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2752
2753         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2754         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2755         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2756         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2757 /* 'External Rate' complies with the alsa control naming scheme */
2758         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2759         HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2760         HDSPM_MADI_SYNC_CHECK("MADI Sync Lock Status", 0),
2761         HDSPM_LINE_OUT("Line Out", 0),
2762         HDSPM_TX_64("TX 64 channels mode", 0),
2763         HDSPM_C_TMS("Clear Track Marker", 0),
2764         HDSPM_SAFE_MODE("Safe Mode", 0),
2765         HDSPM_INPUT_SELECT("Input Select", 0),
2766 };
2767
2768 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
2769
2770         HDSPM_MIXER("Mixer", 0),
2771 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2772         HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2773
2774         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2775         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2776         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2777         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2778 /* 'External Rate' complies with the alsa control naming scheme */
2779         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2780         HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2781 /*      HDSPM_AES_SYNC_CHECK("AES Lock Status", 0),*/ /* created in snd_hdspm_create_controls() */
2782         HDSPM_LINE_OUT("Line Out", 0),
2783         HDSPM_EMPHASIS("Emphasis", 0),
2784         HDSPM_DOLBY("Non Audio", 0),
2785         HDSPM_PROFESSIONAL("Professional", 0),
2786         HDSPM_C_TMS("Clear Track Marker", 0),
2787         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
2788         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
2789 };
2790
2791 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
2792
2793
2794 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
2795 {
2796         int i;
2797
2798         for (i = hdspm->ds_channels; i < hdspm->ss_channels; ++i) {
2799                 if (hdspm->system_sample_rate > 48000) {
2800                         hdspm->playback_mixer_ctls[i]->vd[0].access =
2801                             SNDRV_CTL_ELEM_ACCESS_INACTIVE |
2802                             SNDRV_CTL_ELEM_ACCESS_READ |
2803                             SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2804                 } else {
2805                         hdspm->playback_mixer_ctls[i]->vd[0].access =
2806                             SNDRV_CTL_ELEM_ACCESS_READWRITE |
2807                             SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2808                 }
2809                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
2810                                SNDRV_CTL_EVENT_MASK_INFO,
2811                                &hdspm->playback_mixer_ctls[i]->id);
2812         }
2813
2814         return 0;
2815 }
2816
2817
2818 static int snd_hdspm_create_controls(struct snd_card *card, struct hdspm * hdspm)
2819 {
2820         unsigned int idx, limit;
2821         int err;
2822         struct snd_kcontrol *kctl;
2823
2824         /* add control list first */
2825         if (hdspm->is_aes32) {
2826                 struct snd_kcontrol_new aes_sync_ctl =
2827                         HDSPM_AES_SYNC_CHECK("AES Lock Status", 0);
2828
2829                 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_aes32);
2830                      idx++) {
2831                         err = snd_ctl_add(card,
2832                                           snd_ctl_new1(&snd_hdspm_controls_aes32[idx],
2833                                                        hdspm));
2834                         if (err < 0)
2835                                 return err;
2836                 }
2837                 for (idx = 1; idx <= 8; idx++) {
2838                         aes_sync_ctl.index = idx;
2839                         err = snd_ctl_add(card,
2840                                           snd_ctl_new1(&aes_sync_ctl, hdspm));
2841                         if (err < 0)
2842                                 return err;
2843                 }
2844         } else {
2845                 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_madi);
2846                      idx++) {
2847                         err = snd_ctl_add(card,
2848                                           snd_ctl_new1(&snd_hdspm_controls_madi[idx],
2849                                                        hdspm));
2850                         if (err < 0)
2851                                 return err;
2852                 }
2853         }
2854
2855         /* Channel playback mixer as default control 
2856 Note: the whole matrix would be 128*HDSPM_MIXER_CHANNELS Faders, thats too big for any alsamixer
2857 they are accesible via special IOCTL on hwdep
2858 and the mixer 2dimensional mixer control */
2859
2860         snd_hdspm_playback_mixer.name = "Chn";
2861         limit = HDSPM_MAX_CHANNELS;
2862
2863         /* The index values are one greater than the channel ID so that alsamixer
2864            will display them correctly. We want to use the index for fast lookup
2865            of the relevant channel, but if we use it at all, most ALSA software
2866            does the wrong thing with it ...
2867          */
2868
2869         for (idx = 0; idx < limit; ++idx) {
2870                 snd_hdspm_playback_mixer.index = idx + 1;
2871                 if ((err = snd_ctl_add(card,
2872                                        kctl =
2873                                        snd_ctl_new1
2874                                        (&snd_hdspm_playback_mixer,
2875                                         hdspm)))) {
2876                         return err;
2877                 }
2878                 hdspm->playback_mixer_ctls[idx] = kctl;
2879         }
2880
2881         return 0;
2882 }
2883
2884 /*------------------------------------------------------------
2885    /proc interface 
2886  ------------------------------------------------------------*/
2887
2888 static void
2889 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
2890                          struct snd_info_buffer *buffer)
2891 {
2892         struct hdspm *hdspm = (struct hdspm *) entry->private_data;
2893         unsigned int status;
2894         unsigned int status2;
2895         char *pref_sync_ref;
2896         char *autosync_ref;
2897         char *system_clock_mode;
2898         char *clock_source;
2899         char *insel;
2900         char *syncref;
2901         int x, x2;
2902
2903         status = hdspm_read(hdspm, HDSPM_statusRegister);
2904         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2905
2906         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
2907                     hdspm->card_name, hdspm->card->number + 1,
2908                     hdspm->firmware_rev,
2909                     (status2 & HDSPM_version0) |
2910                     (status2 & HDSPM_version1) | (status2 &
2911                                                   HDSPM_version2));
2912
2913         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
2914                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
2915
2916         snd_iprintf(buffer, "--- System ---\n");
2917
2918         snd_iprintf(buffer,
2919                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
2920                     status & HDSPM_audioIRQPending,
2921                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
2922                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
2923                     hdspm->irq_count);
2924         snd_iprintf(buffer,
2925                     "HW pointer: id = %d, rawptr = %d (%d->%d) estimated= %ld (bytes)\n",
2926                     ((status & HDSPM_BufferID) ? 1 : 0),
2927                     (status & HDSPM_BufferPositionMask),
2928                     (status & HDSPM_BufferPositionMask) % (2 *
2929                                                            (int)hdspm->
2930                                                            period_bytes),
2931                     ((status & HDSPM_BufferPositionMask) -
2932                      64) % (2 * (int)hdspm->period_bytes),
2933                     (long) hdspm_hw_pointer(hdspm) * 4);
2934
2935         snd_iprintf(buffer,
2936                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
2937                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
2938                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
2939                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
2940                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
2941         snd_iprintf(buffer,
2942                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, status2=0x%x\n",
2943                     hdspm->control_register, hdspm->control2_register,
2944                     status, status2);
2945
2946         snd_iprintf(buffer, "--- Settings ---\n");
2947
2948         x = 1 << (6 +
2949                   hdspm_decode_latency(hdspm->
2950                                        control_register &
2951                                        HDSPM_LatencyMask));
2952
2953         snd_iprintf(buffer,
2954                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
2955                     x, (unsigned long) hdspm->period_bytes);
2956
2957         snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
2958                     (hdspm->
2959                      control_register & HDSPM_LineOut) ? "on " : "off",
2960                     (hdspm->precise_ptr) ? "on" : "off");
2961
2962         switch (hdspm->control_register & HDSPM_InputMask) {
2963         case HDSPM_InputOptical:
2964                 insel = "Optical";
2965                 break;
2966         case HDSPM_InputCoaxial:
2967                 insel = "Coaxial";
2968                 break;
2969         default:
2970                 insel = "Unkown";
2971         }
2972
2973         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2974         case HDSPM_SyncRef_Word:
2975                 syncref = "WordClock";
2976                 break;
2977         case HDSPM_SyncRef_MADI:
2978                 syncref = "MADI";
2979                 break;
2980         default:
2981                 syncref = "Unkown";
2982         }
2983         snd_iprintf(buffer, "Inputsel = %s, SyncRef = %s\n", insel,
2984                     syncref);
2985
2986         snd_iprintf(buffer,
2987                     "ClearTrackMarker = %s, Transmit in %s Channel Mode, Auto Input %s\n",
2988                     (hdspm->
2989                      control_register & HDSPM_clr_tms) ? "on" : "off",
2990                     (hdspm->
2991                      control_register & HDSPM_TX_64ch) ? "64" : "56",
2992                     (hdspm->
2993                      control_register & HDSPM_AutoInp) ? "on" : "off");
2994
2995         switch (hdspm_clock_source(hdspm)) {
2996         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
2997                 clock_source = "AutoSync";
2998                 break;
2999         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3000                 clock_source = "Internal 32 kHz";
3001                 break;
3002         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3003                 clock_source = "Internal 44.1 kHz";
3004                 break;
3005         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3006                 clock_source = "Internal 48 kHz";
3007                 break;
3008         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3009                 clock_source = "Internal 64 kHz";
3010                 break;
3011         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3012                 clock_source = "Internal 88.2 kHz";
3013                 break;
3014         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3015                 clock_source = "Internal 96 kHz";
3016                 break;
3017         default:
3018                 clock_source = "Error";
3019         }
3020         snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3021         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3022                 system_clock_mode = "Slave";
3023         else
3024                 system_clock_mode = "Master";
3025         snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3026
3027         switch (hdspm_pref_sync_ref(hdspm)) {
3028         case HDSPM_SYNC_FROM_WORD:
3029                 pref_sync_ref = "Word Clock";
3030                 break;
3031         case HDSPM_SYNC_FROM_MADI:
3032                 pref_sync_ref = "MADI Sync";
3033                 break;
3034         default:
3035                 pref_sync_ref = "XXXX Clock";
3036                 break;
3037         }
3038         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
3039                     pref_sync_ref);
3040
3041         snd_iprintf(buffer, "System Clock Frequency: %d\n",
3042                     hdspm->system_sample_rate);
3043
3044
3045         snd_iprintf(buffer, "--- Status:\n");
3046
3047         x = status & HDSPM_madiSync;
3048         x2 = status2 & HDSPM_wcSync;
3049
3050         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
3051                     (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
3052                     "NoLock",
3053                     (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
3054                     "NoLock");
3055
3056         switch (hdspm_autosync_ref(hdspm)) {
3057         case HDSPM_AUTOSYNC_FROM_WORD:
3058                 autosync_ref = "Word Clock";
3059                 break;
3060         case HDSPM_AUTOSYNC_FROM_MADI:
3061                 autosync_ref = "MADI Sync";
3062                 break;
3063         case HDSPM_AUTOSYNC_FROM_NONE:
3064                 autosync_ref = "Input not valid";
3065                 break;
3066         default:
3067                 autosync_ref = "---";
3068                 break;
3069         }
3070         snd_iprintf(buffer,
3071                     "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
3072                     autosync_ref, hdspm_external_sample_rate(hdspm),
3073                     (status & HDSPM_madiFreqMask) >> 22,
3074                     (status2 & HDSPM_wcFreqMask) >> 5);
3075
3076         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
3077                     (status & HDSPM_AB_int) ? "Coax" : "Optical",
3078                     (status & HDSPM_RX_64ch) ? "64 channels" :
3079                     "56 channels");
3080
3081         snd_iprintf(buffer, "\n");
3082 }
3083
3084 static void
3085 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
3086                           struct snd_info_buffer *buffer)
3087 {
3088         struct hdspm *hdspm = (struct hdspm *) entry->private_data;
3089         unsigned int status;
3090         unsigned int status2;
3091         unsigned int timecode;
3092         int pref_syncref;
3093         char *autosync_ref;
3094         char *system_clock_mode;
3095         char *clock_source;
3096         int x;
3097
3098         status = hdspm_read(hdspm, HDSPM_statusRegister);
3099         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3100         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
3101
3102         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
3103                     hdspm->card_name, hdspm->card->number + 1,
3104                     hdspm->firmware_rev);
3105
3106         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3107                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
3108
3109         snd_iprintf(buffer, "--- System ---\n");
3110
3111         snd_iprintf(buffer,
3112                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
3113                     status & HDSPM_audioIRQPending,
3114                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
3115                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
3116                     hdspm->irq_count);
3117         snd_iprintf(buffer,
3118                     "HW pointer: id = %d, rawptr = %d (%d->%d) estimated= %ld (bytes)\n",
3119                     ((status & HDSPM_BufferID) ? 1 : 0),
3120                     (status & HDSPM_BufferPositionMask),
3121                     (status & HDSPM_BufferPositionMask) % (2 *
3122                                                            (int)hdspm->
3123                                                            period_bytes),
3124                     ((status & HDSPM_BufferPositionMask) -
3125                      64) % (2 * (int)hdspm->period_bytes),
3126                     (long) hdspm_hw_pointer(hdspm) * 4);
3127
3128         snd_iprintf(buffer,
3129                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
3130                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
3131                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
3132                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
3133                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
3134         snd_iprintf(buffer,
3135                     "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, timecode=0x%x\n",
3136                     hdspm->control_register,
3137                     status, status2, timecode);
3138
3139         snd_iprintf(buffer, "--- Settings ---\n");
3140
3141         x = 1 << (6 +
3142                   hdspm_decode_latency(hdspm->
3143                                        control_register &
3144                                        HDSPM_LatencyMask));
3145
3146         snd_iprintf(buffer,
3147                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3148                     x, (unsigned long) hdspm->period_bytes);
3149
3150         snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
3151                     (hdspm->
3152                      control_register & HDSPM_LineOut) ? "on " : "off",
3153                     (hdspm->precise_ptr) ? "on" : "off");
3154
3155         snd_iprintf(buffer,
3156                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
3157                     (hdspm->
3158                      control_register & HDSPM_clr_tms) ? "on" : "off",
3159                     (hdspm->
3160                      control_register & HDSPM_Emphasis) ? "on" : "off",
3161                     (hdspm->
3162                      control_register & HDSPM_Dolby) ? "on" : "off");
3163
3164         switch (hdspm_clock_source(hdspm)) {
3165         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3166                 clock_source = "AutoSync";
3167                 break;
3168         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3169                 clock_source = "Internal 32 kHz";
3170                 break;
3171         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3172                 clock_source = "Internal 44.1 kHz";
3173                 break;
3174         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3175                 clock_source = "Internal 48 kHz";
3176                 break;
3177         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3178                 clock_source = "Internal 64 kHz";
3179                 break;
3180         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3181                 clock_source = "Internal 88.2 kHz";
3182                 break;
3183         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3184                 clock_source = "Internal 96 kHz";
3185                 break;
3186         case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
3187                 clock_source = "Internal 128 kHz";
3188                 break;
3189         case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3190                 clock_source = "Internal 176.4 kHz";
3191                 break;
3192         case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
3193                 clock_source = "Internal 192 kHz";
3194                 break;
3195         default:
3196                 clock_source = "Error";
3197         }
3198         snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3199         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3200                 system_clock_mode = "Slave";
3201         else
3202                 system_clock_mode = "Master";
3203         snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3204
3205         pref_syncref = hdspm_pref_sync_ref(hdspm);
3206         if (pref_syncref == 0)
3207                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
3208         else
3209                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
3210                                 pref_syncref);
3211
3212         snd_iprintf(buffer, "System Clock Frequency: %d\n",
3213                     hdspm->system_sample_rate);
3214
3215         snd_iprintf(buffer, "Double speed: %s\n",
3216                         hdspm->control_register & HDSPM_DS_DoubleWire?
3217                         "Double wire" : "Single wire");
3218         snd_iprintf(buffer, "Quad speed: %s\n",
3219                         hdspm->control_register & HDSPM_QS_DoubleWire?
3220                         "Double wire" :
3221                         hdspm->control_register & HDSPM_QS_QuadWire?
3222                         "Quad wire" : "Single wire");
3223
3224         snd_iprintf(buffer, "--- Status:\n");
3225
3226         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
3227                         (status & HDSPM_AES32_wcLock)? "Sync   " : "No Lock",
3228                         HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
3229
3230         for (x = 0; x < 8; x++) {
3231                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
3232                                 x+1,
3233                                 (status2 & (HDSPM_LockAES >> x))? "Sync   ": "No Lock",
3234                                 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
3235         }
3236
<