sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,ESB2},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  68 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  69 static int ac97_clock;
  70 static char *ac97_quirk;
  71 static int buggy_semaphore;
  72 static int buggy_irq = -1; /* auto-check */
  73 static int xbox;
  74 static int spdif_aclink = -1;
  75
  76 module_param(index, int, 0444);
  77 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  78 module_param(id, charp, 0444);
  79 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  80 module_param(ac97_clock, int, 0444);
  81 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  82 module_param(ac97_quirk, charp, 0444);
  83 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  84 module_param(buggy_semaphore, bool, 0444);
  85 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  86 module_param(buggy_irq, bool, 0444);
  87 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  88 module_param(xbox, bool, 0444);
  89 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  90 module_param(spdif_aclink, int, 0444);
  91 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  92
  93 /* just for backward compatibility */
  94 static int enable;
  95 module_param(enable, bool, 0444);
  96 static int joystick;
  97 module_param(joystick, int, 0444);
  98
  99 /*
 100  *  Direct registers
 101  */
 102 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 103
 104 #define ICHREG(x) ICH_REG_##x
 105
 106 #define DEFINE_REGSET(name,base) \
 107 enum { \
 108         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 109         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 110         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 111         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 112         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 113         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 114         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 115 };
 116
 117 /* busmaster blocks */
 118 DEFINE_REGSET(OFF, 0);          /* offset */
 119 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 120 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 121 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 122
 123 /* ICH4 busmaster blocks */
 124 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 125 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 126 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 127
 128 /* values for each busmaster block */
 129
 130 /* LVI */
 131 #define ICH_REG_LVI_MASK                0x1f
 132
 133 /* SR */
 134 #define ICH_FIFOE                       0x10    /* FIFO error */
 135 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 136 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 137 #define ICH_CELV                        0x02    /* current equals last valid */
 138 #define ICH_DCH                         0x01    /* DMA controller halted */
 139
 140 /* PIV */
 141 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 142
 143 /* CR */
 144 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 145 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 146 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 147 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 148 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 149
 150
 151 /* global block */
 152 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 153 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 154 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 155 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 156 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 157 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 158 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 159 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 160 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 161 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 162 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 163 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 164 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 165 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 166 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 167 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 168 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 169 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 170 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 171 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 172 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 173 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 174 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 175 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 176 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 177 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 178 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 179 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 180 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 181 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 182 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 183 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 184 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 185 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 186 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 187 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 188 #define   ICH_RCS               0x00008000      /* read completion status */
 189 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 190 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 191 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 192 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 193 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 194 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 195 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 196 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 197 #define   ICH_POINT             0x00000040      /* playback interrupt */
 198 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 199 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 200 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 201 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 202 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 203 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 204 #define   ICH_CAS               0x01            /* codec access semaphore */
 205 #define ICH_REG_SDM             0x80
 206 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 207 #define   ICH_DI2L_SHIFT        6
 208 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 209 #define   ICH_DI1L_SHIFT        4
 210 #define   ICH_SE                0x00000008      /* steer enable */
 211 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 212
 213 #define ICH_MAX_FRAGS           32              /* max hw frags */
 214
 215
 216 /*
 217  * registers for Ali5455
 218  */
 219
 220 /* ALi 5455 busmaster blocks */
 221 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 222 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 223 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 224 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 225 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 226 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 227 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 228 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 229 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 230 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 231 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 232
 233 enum {
 234         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 235         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 236         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 237         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 238         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 239         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 240         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 241         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 242         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 243         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 244         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 245         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 246         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 247         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 248         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 249         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 250         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 251         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 252         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 253         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 254         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 255 };
 256
 257 #define ALI_CAS_SEM_BUSY        0x80000000
 258 #define ALI_CPR_ADDR_SECONDARY  0x100
 259 #define ALI_CPR_ADDR_READ       0x80
 260 #define ALI_CSPSR_CODEC_READY   0x08
 261 #define ALI_CSPSR_READ_OK       0x02
 262 #define ALI_CSPSR_WRITE_OK      0x01
 263
 264 /* interrupts for the whole chip by interrupt status register finish */
 265
 266 #define ALI_INT_MICIN2          (1<<26)
 267 #define ALI_INT_PCMIN2          (1<<25)
 268 #define ALI_INT_I2SIN           (1<<24)
 269 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 270 #define ALI_INT_SPDIFIN         (1<<22)
 271 #define ALI_INT_LFEOUT          (1<<21)
 272 #define ALI_INT_CENTEROUT       (1<<20)
 273 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 274 #define ALI_INT_MICIN           (1<<18)
 275 #define ALI_INT_PCMOUT          (1<<17)
 276 #define ALI_INT_PCMIN           (1<<16)
 277 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 278 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 279 #define ALI_INT_GPIO            (1<<1)
 280 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 281                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 282
 283 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 284 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 285 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 286 #define ICH_ALI_SC_IN_BITS      (3<<18)
 287 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 288 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 289 #define ICH_ALI_SC_PCM_4        (1<<8)
 290 #define ICH_ALI_SC_PCM_6        (2<<8)
 291 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 292
 293 #define ICH_ALI_SS_SEC_ID       (3<<5)
 294 #define ICH_ALI_SS_PRI_ID       (3<<3)
 295
 296 #define ICH_ALI_IF_AC97SP       (1<<21)
 297 #define ICH_ALI_IF_MC           (1<<20)
 298 #define ICH_ALI_IF_PI           (1<<19)
 299 #define ICH_ALI_IF_MC2          (1<<18)
 300 #define ICH_ALI_IF_PI2          (1<<17)
 301 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 302 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 303 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 304 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 305 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 306 #define ICH_ALI_IF_PO           (1<<1)
 307
 308 /*
 309  *
 310  */
 311
 312 enum {
 313         ICHD_PCMIN,
 314         ICHD_PCMOUT,
 315         ICHD_MIC,
 316         ICHD_MIC2,
 317         ICHD_PCM2IN,
 318         ICHD_SPBAR,
 319         ICHD_LAST = ICHD_SPBAR
 320 };
 321 enum {
 322         NVD_PCMIN,
 323         NVD_PCMOUT,
 324         NVD_MIC,
 325         NVD_SPBAR,
 326         NVD_LAST = NVD_SPBAR
 327 };
 328 enum {
 329         ALID_PCMIN,
 330         ALID_PCMOUT,
 331         ALID_MIC,
 332         ALID_AC97SPDIFOUT,
 333         ALID_SPDIFIN,
 334         ALID_SPDIFOUT,
 335         ALID_LAST = ALID_SPDIFOUT
 336 };
 337
 338 #define get_ichdev(substream) (substream->runtime->private_data)
 339
 340 struct ichdev {
 341         unsigned int ichd;                      /* ich device number */
 342         unsigned long reg_offset;               /* offset to bmaddr */
 343         u32 *bdbar;                             /* CPU address (32bit) */
 344         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 345         struct snd_pcm_substream *substream;
 346         unsigned int physbuf;                   /* physical address (32bit) */
 347         unsigned int size;
 348         unsigned int fragsize;
 349         unsigned int fragsize1;
 350         unsigned int position;
 351         unsigned int pos_shift;
 352         int frags;
 353         int lvi;
 354         int lvi_frag;
 355         int civ;
 356         int ack;
 357         int ack_reload;
 358         unsigned int ack_bit;
 359         unsigned int roff_sr;
 360         unsigned int roff_picb;
 361         unsigned int int_sta_mask;              /* interrupt status mask */
 362         unsigned int ali_slot;                  /* ALI DMA slot */
 363         struct ac97_pcm *pcm;
 364         int pcm_open_flag;
 365         unsigned int page_attr_changed: 1;
 366         unsigned int suspended: 1;
 367 };
 368
 369 struct intel8x0 {
 370         unsigned int device_type;
 371
 372         int irq;
 373
 374         void __iomem *addr;
 375         void __iomem *bmaddr;
 376
 377         struct pci_dev *pci;
 378         struct snd_card *card;
 379
 380         int pcm_devs;
 381         struct snd_pcm *pcm[6];
 382         struct ichdev ichd[6];
 383
 384         unsigned multi4: 1,
 385                  multi6: 1,
 386                  dra: 1,
 387                  smp20bit: 1;
 388         unsigned in_ac97_init: 1,
 389                  in_sdin_init: 1;
 390         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 391         unsigned fix_nocache: 1;        /* workaround for 440MX */
 392         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 393         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 394         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 395
 396         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 397         unsigned int sdm_saved; /* SDM reg value */
 398
 399         struct snd_ac97_bus *ac97_bus;
 400         struct snd_ac97 *ac97[3];
 401         unsigned int ac97_sdin[3];
 402         unsigned int max_codecs, ncodecs;
 403         unsigned int *codec_bit;
 404         unsigned int codec_isr_bits;
 405         unsigned int codec_ready_bits;
 406
 407         spinlock_t reg_lock;
 408
 409         u32 bdbars_count;
 410         struct snd_dma_buffer bdbars;
 411         u32 int_sta_reg;                /* interrupt status register */
 412         u32 int_sta_mask;               /* interrupt status mask */
 413 };
 414
 415 static struct pci_device_id snd_intel8x0_ids[] = {
 416         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 417         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 418         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 419         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 420         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 421         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 422         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 423         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 424         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 425         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 426         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 427         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 428         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 429         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 430         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 431         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 432         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 433         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 434         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 435         { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
 436         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 437         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 438         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 439         { 0, }
 440 };
 441
 442 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 443
 444 /*
 445  *  Lowlevel I/O - busmaster
 446  */
 447
 448 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 449 {
 450         return ioread8(chip->bmaddr + offset);
 451 }
 452
 453 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 454 {
 455         return ioread16(chip->bmaddr + offset);
 456 }
 457
 458 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 459 {
 460         return ioread32(chip->bmaddr + offset);
 461 }
 462
 463 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 464 {
 465         iowrite8(val, chip->bmaddr + offset);
 466 }
 467
 468 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 469 {
 470         iowrite16(val, chip->bmaddr + offset);
 471 }
 472
 473 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 474 {
 475         iowrite32(val, chip->bmaddr + offset);
 476 }
 477
 478 /*
 479  *  Lowlevel I/O - AC'97 registers
 480  */
 481
 482 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 483 {
 484         return ioread16(chip->addr + offset);
 485 }
 486
 487 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 488 {
 489         iowrite16(val, chip->addr + offset);
 490 }
 491
 492 /*
 493  *  Basic I/O
 494  */
 495
 496 /*
 497  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 498  */
 499
 500 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 501 {
 502         int time;
 503
 504         if (codec > 2)
 505                 return -EIO;
 506         if (chip->in_sdin_init) {
 507                 /* we don't know the ready bit assignment at the moment */
 508                 /* so we check any */
 509                 codec = chip->codec_isr_bits;
 510         } else {
 511                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 512         }
 513
 514         /* codec ready ? */
 515         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 516                 return -EIO;
 517
 518         if (chip->buggy_semaphore)
 519                 return 0; /* just ignore ... */
 520
 521         /* Anyone holding a semaphore for 1 msec should be shot... */
 522         time = 100;
 523         do {
 524                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 525                         return 0;
 526                 udelay(10);
 527         } while (time--);
 528
 529         /* access to some forbidden (non existant) ac97 registers will not
 530          * reset the semaphore. So even if you don't get the semaphore, still
 531          * continue the access. We don't need the semaphore anyway. */
 532         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 533                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 534         iagetword(chip, 0);     /* clear semaphore flag */
 535         /* I don't care about the semaphore */
 536         return -EBUSY;
 537 }
 538
 539 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 540                                      unsigned short reg,
 541                                      unsigned short val)
 542 {
 543         struct intel8x0 *chip = ac97->private_data;
 544
 545         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 546                 if (! chip->in_ac97_init)
 547                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 548         }
 549         iaputword(chip, reg + ac97->num * 0x80, val);
 550 }
 551
 552 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 553                                               unsigned short reg)
 554 {
 555         struct intel8x0 *chip = ac97->private_data;
 556         unsigned short res;
 557         unsigned int tmp;
 558
 559         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 560                 if (! chip->in_ac97_init)
 561                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 562                 res = 0xffff;
 563         } else {
 564                 res = iagetword(chip, reg + ac97->num * 0x80);
 565                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 566                         /* reset RCS and preserve other R/WC bits */
 567                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 568                                   ~(chip->codec_ready_bits | ICH_GSCI));
 569                         if (! chip->in_ac97_init)
 570                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 571                         res = 0xffff;
 572                 }
 573         }
 574         return res;
 575 }
 576
 577 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 578                                                    unsigned int codec)
 579 {
 580         unsigned int tmp;
 581
 582         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 583                 iagetword(chip, codec * 0x80);
 584                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 585                         /* reset RCS and preserve other R/WC bits */
 586                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 587                                   ~(chip->codec_ready_bits | ICH_GSCI));
 588                 }
 589         }
 590 }
 591
 592 /*
 593  * access to AC97 for Ali5455
 594  */
 595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 596 {
 597         int count = 0;
 598         for (count = 0; count < 0x7f; count++) {
 599                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 600                 if (val & mask)
 601                         return 0;
 602         }
 603         if (! chip->in_ac97_init)
 604                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 605         return -EBUSY;
 606 }
 607
 608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 609 {
 610         int time = 100;
 611         if (chip->buggy_semaphore)
 612                 return 0; /* just ignore ... */
 613         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 614                 udelay(1);
 615         if (! time && ! chip->in_ac97_init)
 616                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 617         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 618 }
 619
 620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 621 {
 622         struct intel8x0 *chip = ac97->private_data;
 623         unsigned short data = 0xffff;
 624
 625         if (snd_intel8x0_ali_codec_semaphore(chip))
 626                 goto __err;
 627         reg |= ALI_CPR_ADDR_READ;
 628         if (ac97->num)
 629                 reg |= ALI_CPR_ADDR_SECONDARY;
 630         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 631         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 632                 goto __err;
 633         data = igetword(chip, ICHREG(ALI_SPR));
 634  __err:
 635         return data;
 636 }
 637
 638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 639                                          unsigned short val)
 640 {
 641         struct intel8x0 *chip = ac97->private_data;
 642
 643         if (snd_intel8x0_ali_codec_semaphore(chip))
 644                 return;
 645         iputword(chip, ICHREG(ALI_CPR), val);
 646         if (ac97->num)
 647                 reg |= ALI_CPR_ADDR_SECONDARY;
 648         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 649         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 650 }
 651
 652
 653 /*
 654  * DMA I/O
 655  */
 656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 657 {
 658         int idx;
 659         u32 *bdbar = ichdev->bdbar;
 660         unsigned long port = ichdev->reg_offset;
 661
 662         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 663         if (ichdev->size == ichdev->fragsize) {
 664                 ichdev->ack_reload = ichdev->ack = 2;
 665                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 666                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 667                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 668                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 669                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 670                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 671                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 672                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 673                 }
 674                 ichdev->frags = 2;
 675         } else {
 676                 ichdev->ack_reload = ichdev->ack = 1;
 677                 ichdev->fragsize1 = ichdev->fragsize;
 678                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 679                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 680                                                      (((idx >> 1) * ichdev->fragsize) %
 681                                                       ichdev->size));
 682                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 683                                                      ichdev->fragsize >> ichdev->pos_shift);
 684 #if 0
 685                         printk("bdbar[%i] = 0x%x [0x%x]\n",
 686                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 687 #endif
 688                 }
 689                 ichdev->frags = ichdev->size / ichdev->fragsize;
 690         }
 691         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 692         ichdev->civ = 0;
 693         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 694         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 695         ichdev->position = 0;
 696 #if 0
 697         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 698                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 699 #endif
 700         /* clear interrupts */
 701         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 702 }
 703
 704 #ifdef __i386__
 705 /*
 706  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 707  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 708  * the pages as non-cached.  For details, see the errata in
 709  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 710  */
 711 static void fill_nocache(void *buf, int size, int nocache)
 712 {
 713         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 714         if (nocache)
 715                 set_pages_uc(virt_to_page(buf), size);
 716         else
 717                 set_pages_wb(virt_to_page(buf), size);
 718 }
 719 #else
 720 #define fill_nocache(buf, size, nocache) do { ; } while (0)
 721 #endif
 722
 723 /*
 724  *  Interrupt handler
 725  */
 726
 727 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 728 {
 729         unsigned long port = ichdev->reg_offset;
 730         unsigned long flags;
 731         int status, civ, i, step;
 732         int ack = 0;
 733
 734         spin_lock_irqsave(&chip->reg_lock, flags);
 735         status = igetbyte(chip, port + ichdev->roff_sr);
 736         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 737         if (!(status & ICH_BCIS)) {
 738                 step = 0;
 739         } else if (civ == ichdev->civ) {
 740                 // snd_printd("civ same %d\n", civ);
 741                 step = 1;
 742                 ichdev->civ++;
 743                 ichdev->civ &= ICH_REG_LVI_MASK;
 744         } else {
 745                 step = civ - ichdev->civ;
 746                 if (step < 0)
 747                         step += ICH_REG_LVI_MASK + 1;
 748                 // if (step != 1)
 749                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 750                 ichdev->civ = civ;
 751         }
 752
 753         ichdev->position += step * ichdev->fragsize1;
 754         if (! chip->in_measurement)
 755                 ichdev->position %= ichdev->size;
 756         ichdev->lvi += step;
 757         ichdev->lvi &= ICH_REG_LVI_MASK;
 758         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 759         for (i = 0; i < step; i++) {
 760                 ichdev->lvi_frag++;
 761                 ichdev->lvi_frag %= ichdev->frags;
 762                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 763 #if 0
 764         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 765                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 766                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 767                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 768 #endif
 769                 if (--ichdev->ack == 0) {
 770                         ichdev->ack = ichdev->ack_reload;
 771                         ack = 1;
 772                 }
 773         }
 774         spin_unlock_irqrestore(&chip->reg_lock, flags);
 775         if (ack && ichdev->substream) {
 776                 snd_pcm_period_elapsed(ichdev->substream);
 777         }
 778         iputbyte(chip, port + ichdev->roff_sr,
 779                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 780 }
 781
 782 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 783 {
 784         struct intel8x0 *chip = dev_id;
 785         struct ichdev *ichdev;
 786         unsigned int status;
 787         unsigned int i;
 788
 789         status = igetdword(chip, chip->int_sta_reg);
 790         if (status == 0xffffffff)       /* we are not yet resumed */
 791                 return IRQ_NONE;
 792
 793         if ((status & chip->int_sta_mask) == 0) {
 794                 if (status) {
 795                         /* ack */
 796                         iputdword(chip, chip->int_sta_reg, status);
 797                         if (! chip->buggy_irq)
 798                                 status = 0;
 799                 }
 800                 return IRQ_RETVAL(status);
 801         }
 802
 803         for (i = 0; i < chip->bdbars_count; i++) {
 804                 ichdev = &chip->ichd[i];
 805                 if (status & ichdev->int_sta_mask)
 806                         snd_intel8x0_update(chip, ichdev);
 807         }
 808
 809         /* ack them */
 810         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 811
 812         return IRQ_HANDLED;
 813 }
 814
 815 /*
 816  *  PCM part
 817  */
 818
 819 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 820 {
 821         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 822         struct ichdev *ichdev = get_ichdev(substream);
 823         unsigned char val = 0;
 824         unsigned long port = ichdev->reg_offset;
 825
 826         switch (cmd) {
 827         case SNDRV_PCM_TRIGGER_RESUME:
 828                 ichdev->suspended = 0;
 829                 /* fallthru */
 830         case SNDRV_PCM_TRIGGER_START:
 831                 val = ICH_IOCE | ICH_STARTBM;
 832                 break;
 833         case SNDRV_PCM_TRIGGER_SUSPEND:
 834                 ichdev->suspended = 1;
 835                 /* fallthru */
 836         case SNDRV_PCM_TRIGGER_STOP:
 837                 val = 0;
 838                 break;
 839         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 840                 val = ICH_IOCE;
 841                 break;
 842         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 843                 val = ICH_IOCE | ICH_STARTBM;
 844                 break;
 845         default:
 846                 return -EINVAL;
 847         }
 848         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 849         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 850                 /* wait until DMA stopped */
 851                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 852                 /* reset whole DMA things */
 853                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 854         }
 855         return 0;
 856 }
 857
 858 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 859 {
 860         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 861         struct ichdev *ichdev = get_ichdev(substream);
 862         unsigned long port = ichdev->reg_offset;
 863         static int fiforeg[] = {
 864                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 865         };
 866         unsigned int val, fifo;
 867
 868         val = igetdword(chip, ICHREG(ALI_DMACR));
 869         switch (cmd) {
 870         case SNDRV_PCM_TRIGGER_RESUME:
 871                 ichdev->suspended = 0;
 872                 /* fallthru */
 873         case SNDRV_PCM_TRIGGER_START:
 874         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 875                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 876                         /* clear FIFO for synchronization of channels */
 877                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 878                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 879                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 880                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 881                 }
 882                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 883                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 884                 /* start DMA */
 885                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 886                 break;
 887         case SNDRV_PCM_TRIGGER_SUSPEND:
 888                 ichdev->suspended = 1;
 889                 /* fallthru */
 890         case SNDRV_PCM_TRIGGER_STOP:
 891         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 892                 /* pause */
 893                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 894                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 895                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 896                         ;
 897                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 898                         break;
 899                 /* reset whole DMA things */
 900                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 901                 /* clear interrupts */
 902                 iputbyte(chip, port + ICH_REG_OFF_SR,
 903                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 904                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 905                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 906                 break;
 907         default:
 908                 return -EINVAL;
 909         }
 910         return 0;
 911 }
 912
 913 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 914                                   struct snd_pcm_hw_params *hw_params)
 915 {
 916         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 917         struct ichdev *ichdev = get_ichdev(substream);
 918         struct snd_pcm_runtime *runtime = substream->runtime;
 919         int dbl = params_rate(hw_params) > 48000;
 920         int err;
 921
 922         if (chip->fix_nocache && ichdev->page_attr_changed) {
 923                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 924                 ichdev->page_attr_changed = 0;
 925         }
 926         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 927         if (err < 0)
 928                 return err;
 929         if (chip->fix_nocache) {
 930                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 931                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 932                         ichdev->page_attr_changed = 1;
 933                 }
 934         }
 935         if (ichdev->pcm_open_flag) {
 936                 snd_ac97_pcm_close(ichdev->pcm);
 937                 ichdev->pcm_open_flag = 0;
 938         }
 939         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 940                                 params_channels(hw_params),
 941                                 ichdev->pcm->r[dbl].slots);
 942         if (err >= 0) {
 943                 ichdev->pcm_open_flag = 1;
 944                 /* Force SPDIF setting */
 945                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 946                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 947                                           params_rate(hw_params));
 948         }
 949         return err;
 950 }
 951
 952 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 953 {
 954         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 955         struct ichdev *ichdev = get_ichdev(substream);
 956
 957         if (ichdev->pcm_open_flag) {
 958                 snd_ac97_pcm_close(ichdev->pcm);
 959                 ichdev->pcm_open_flag = 0;
 960         }
 961         if (chip->fix_nocache && ichdev->page_attr_changed) {
 962                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 963                 ichdev->page_attr_changed = 0;
 964         }
 965         return snd_pcm_lib_free_pages(substream);
 966 }
 967
 968 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 969                                        struct snd_pcm_runtime *runtime)
 970 {
 971         unsigned int cnt;
 972         int dbl = runtime->rate > 48000;
 973
 974         spin_lock_irq(&chip->reg_lock);
 975         switch (chip->device_type) {
 976         case DEVICE_ALI:
 977                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 978                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 979                 if (runtime->channels == 4 || dbl)
 980                         cnt |= ICH_ALI_SC_PCM_4;
 981                 else if (runtime->channels == 6)
 982                         cnt |= ICH_ALI_SC_PCM_6;
 983                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 984                 break;
 985         case DEVICE_SIS:
 986                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 987                 cnt &= ~ICH_SIS_PCM_246_MASK;
 988                 if (runtime->channels == 4 || dbl)
 989                         cnt |= ICH_SIS_PCM_4;
 990                 else if (runtime->channels == 6)
 991                         cnt |= ICH_SIS_PCM_6;
 992                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 993                 break;
 994         default:
 995                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 996                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 997                 if (runtime->channels == 4 || dbl)
 998                         cnt |= ICH_PCM_4;
 999                 else if (runtime->channels == 6)
1000                         cnt |= ICH_PCM_6;
1001                 if (chip->device_type == DEVICE_NFORCE) {
1002                         /* reset to 2ch once to keep the 6 channel data in alignment,
1003                          * to start from Front Left always
1004                          */
1005                         if (cnt & ICH_PCM_246_MASK) {
1006                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1007                                 spin_unlock_irq(&chip->reg_lock);
1008                                 msleep(50); /* grrr... */
1009                                 spin_lock_irq(&chip->reg_lock);
1010                         }
1011                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1012                         if (runtime->sample_bits > 16)
1013                                 cnt |= ICH_PCM_20BIT;
1014                 }
1015                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1016                 break;
1017         }
1018         spin_unlock_irq(&chip->reg_lock);
1019 }
1020
1021 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1022 {
1023         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1024         struct snd_pcm_runtime *runtime = substream->runtime;
1025         struct ichdev *ichdev = get_ichdev(substream);
1026
1027         ichdev->physbuf = runtime->dma_addr;
1028         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1029         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1030         if (ichdev->ichd == ICHD_PCMOUT) {
1031                 snd_intel8x0_setup_pcm_out(chip, runtime);
1032                 if (chip->device_type == DEVICE_INTEL_ICH4)
1033                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1034         }
1035         snd_intel8x0_setup_periods(chip, ichdev);
1036         return 0;
1037 }
1038
1039 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1040 {
1041         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1042         struct ichdev *ichdev = get_ichdev(substream);
1043         size_t ptr1, ptr;
1044         int civ, timeout = 100;
1045         unsigned int position;
1046
1047         spin_lock(&chip->reg_lock);
1048         do {
1049                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1050                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1051                 position = ichdev->position;
1052                 if (ptr1 == 0) {
1053                         udelay(10);
1054                         continue;
1055                 }
1056                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1057                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1058                         break;
1059         } while (timeout--);
1060         ptr1 <<= ichdev->pos_shift;
1061         ptr = ichdev->fragsize1 - ptr1;
1062         ptr += position;
1063         spin_unlock(&chip->reg_lock);
1064         if (ptr >= ichdev->size)
1065                 return 0;
1066         return bytes_to_frames(substream->runtime, ptr);
1067 }
1068
1069 static struct snd_pcm_hardware snd_intel8x0_stream =
1070 {
1071         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1072                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1073                                  SNDRV_PCM_INFO_MMAP_VALID |
1074                                  SNDRV_PCM_INFO_PAUSE |
1075                                  SNDRV_PCM_INFO_RESUME),
1076         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1077         .rates =                SNDRV_PCM_RATE_48000,
1078         .rate_min =             48000,
1079         .rate_max =             48000,
1080         .channels_min =         2,
1081         .channels_max =         2,
1082         .buffer_bytes_max =     128 * 1024,
1083         .period_bytes_min =     32,
1084         .period_bytes_max =     128 * 1024,
1085         .periods_min =          1,
1086         .periods_max =          1024,
1087         .fifo_size =            0,
1088 };
1089
1090 static unsigned int channels4[] = {
1091         2, 4,
1092 };
1093
1094 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1095         .count = ARRAY_SIZE(channels4),
1096         .list = channels4,
1097         .mask = 0,
1098 };
1099
1100 static unsigned int channels6[] = {
1101         2, 4, 6,
1102 };
1103
1104 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1105         .count = ARRAY_SIZE(channels6),
1106         .list = channels6,
1107         .mask = 0,
1108 };
1109
1110 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1111 {
1112         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1113         struct snd_pcm_runtime *runtime = substream->runtime;
1114         int err;
1115
1116         ichdev->substream = substream;
1117         runtime->hw = snd_intel8x0_stream;
1118         runtime->hw.rates = ichdev->pcm->rates;
1119         snd_pcm_limit_hw_rates(runtime);
1120         if (chip->device_type == DEVICE_SIS) {
1121                 runtime->hw.buffer_bytes_max = 64*1024;
1122                 runtime->hw.period_bytes_max = 64*1024;
1123         }
1124         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1125                 return err;
1126         runtime->private_data = ichdev;
1127         return 0;
1128 }
1129
1130 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1131 {
1132         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1133         struct snd_pcm_runtime *runtime = substream->runtime;
1134         int err;
1135
1136         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1137         if (err < 0)
1138                 return err;
1139
1140         if (chip->multi6) {
1141                 runtime->hw.channels_max = 6;
1142                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1143                                            &hw_constraints_channels6);
1144         } else if (chip->multi4) {
1145                 runtime->hw.channels_max = 4;
1146                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1147                                            &hw_constraints_channels4);
1148         }
1149         if (chip->dra) {
1150                 snd_ac97_pcm_double_rate_rules(runtime);
1151         }
1152         if (chip->smp20bit) {
1153                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1154                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1155         }
1156         return 0;
1157 }
1158
1159 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1160 {
1161         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1162
1163         chip->ichd[ICHD_PCMOUT].substream = NULL;
1164         return 0;
1165 }
1166
1167 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1168 {
1169         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1170
1171         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1172 }
1173
1174 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1175 {
1176         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1177
1178         chip->ichd[ICHD_PCMIN].substream = NULL;
1179         return 0;
1180 }
1181
1182 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1183 {
1184         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1185
1186         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1187 }
1188
1189 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1190 {
1191         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1192
1193         chip->ichd[ICHD_MIC].substream = NULL;
1194         return 0;
1195 }
1196
1197 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1198 {
1199         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1200
1201         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1202 }
1203
1204 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1205 {
1206         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1207
1208         chip->ichd[ICHD_MIC2].substream = NULL;
1209         return 0;
1210 }
1211
1212 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1213 {
1214         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1215
1216         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1217 }
1218
1219 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1220 {
1221         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1222
1223         chip->ichd[ICHD_PCM2IN].substream = NULL;
1224         return 0;
1225 }
1226
1227 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1228 {
1229         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1230         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1231
1232         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1233 }
1234
1235 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1236 {
1237         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1239
1240         chip->ichd[idx].substream = NULL;
1241         return 0;
1242 }
1243
1244 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1245 {
1246         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1247         unsigned int val;
1248
1249         spin_lock_irq(&chip->reg_lock);
1250         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1251         val |= ICH_ALI_IF_AC97SP;
1252         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1253         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1254         spin_unlock_irq(&chip->reg_lock);
1255
1256         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1257 }
1258
1259 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1260 {
1261         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1262         unsigned int val;
1263
1264         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1265         spin_lock_irq(&chip->reg_lock);
1266         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1267         val &= ~ICH_ALI_IF_AC97SP;
1268         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1269         spin_unlock_irq(&chip->reg_lock);
1270
1271         return 0;
1272 }
1273
1274 #if 0 // NYI
1275 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1276 {
1277         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1278
1279         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1280 }
1281
1282 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1283 {
1284         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1285
1286         chip->ichd[ALID_SPDIFIN].substream = NULL;
1287         return 0;
1288 }
1289
1290 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1291 {
1292         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1293
1294         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1295 }
1296
1297 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1298 {
1299         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1300
1301         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1302         return 0;
1303 }
1304 #endif
1305
1306 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1307         .open =         snd_intel8x0_playback_open,
1308         .close =        snd_intel8x0_playback_close,
1309         .ioctl =        snd_pcm_lib_ioctl,
1310         .hw_params =    snd_intel8x0_hw_params,
1311         .hw_free =      snd_intel8x0_hw_free,
1312         .prepare =      snd_intel8x0_pcm_prepare,
1313         .trigger =      snd_intel8x0_pcm_trigger,
1314         .pointer =      snd_intel8x0_pcm_pointer,
1315 };
1316
1317 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1318         .open =         snd_intel8x0_capture_open,
1319         .close =        snd_intel8x0_capture_close,
1320         .ioctl =        snd_pcm_lib_ioctl,
1321         .hw_params =    snd_intel8x0_hw_params,
1322         .hw_free =      snd_intel8x0_hw_free,
1323         .prepare =      snd_intel8x0_pcm_prepare,
1324         .trigger =      snd_intel8x0_pcm_trigger,
1325         .pointer =      snd_intel8x0_pcm_pointer,
1326 };
1327
1328 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1329         .open =         snd_intel8x0_mic_open,
1330         .close =        snd_intel8x0_mic_close,
1331         .ioctl =        snd_pcm_lib_ioctl,
1332         .hw_params =    snd_intel8x0_hw_params,
1333         .hw_free =      snd_intel8x0_hw_free,
1334         .prepare =      snd_intel8x0_pcm_prepare,
1335         .trigger =      snd_intel8x0_pcm_trigger,
1336         .pointer =      snd_intel8x0_pcm_pointer,
1337 };
1338
1339 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1340         .open =         snd_intel8x0_mic2_open,
1341         .close =        snd_intel8x0_mic2_close,
1342         .ioctl =        snd_pcm_lib_ioctl,
1343         .hw_params =    snd_intel8x0_hw_params,
1344         .hw_free =      snd_intel8x0_hw_free,
1345         .prepare =      snd_intel8x0_pcm_prepare,
1346         .trigger =      snd_intel8x0_pcm_trigger,
1347         .pointer =      snd_intel8x0_pcm_pointer,
1348 };
1349
1350 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1351         .open =         snd_intel8x0_capture2_open,
1352         .close =        snd_intel8x0_capture2_close,
1353         .ioctl =        snd_pcm_lib_ioctl,
1354         .hw_params =    snd_intel8x0_hw_params,
1355         .hw_free =      snd_intel8x0_hw_free,
1356         .prepare =      snd_intel8x0_pcm_prepare,
1357         .trigger =      snd_intel8x0_pcm_trigger,
1358         .pointer =      snd_intel8x0_pcm_pointer,
1359 };
1360
1361 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1362         .open =         snd_intel8x0_spdif_open,
1363         .close =        snd_intel8x0_spdif_close,
1364         .ioctl =        snd_pcm_lib_ioctl,
1365         .hw_params =    snd_intel8x0_hw_params,
1366         .hw_free =      snd_intel8x0_hw_free,
1367         .prepare =      snd_intel8x0_pcm_prepare,
1368         .trigger =      snd_intel8x0_pcm_trigger,
1369         .pointer =      snd_intel8x0_pcm_pointer,
1370 };
1371
1372 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1373         .open =         snd_intel8x0_playback_open,
1374         .close =        snd_intel8x0_playback_close,
1375         .ioctl =        snd_pcm_lib_ioctl,
1376         .hw_params =    snd_intel8x0_hw_params,
1377         .hw_free =      snd_intel8x0_hw_free,
1378         .prepare =      snd_intel8x0_pcm_prepare,
1379         .trigger =      snd_intel8x0_ali_trigger,
1380         .pointer =      snd_intel8x0_pcm_pointer,
1381 };
1382
1383 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1384         .open =         snd_intel8x0_capture_open,
1385         .close =        snd_intel8x0_capture_close,
1386         .ioctl =        snd_pcm_lib_ioctl,
1387         .hw_params =    snd_intel8x0_hw_params,
1388         .hw_free =      snd_intel8x0_hw_free,
1389         .prepare =      snd_intel8x0_pcm_prepare,
1390         .trigger =      snd_intel8x0_ali_trigger,
1391         .pointer =      snd_intel8x0_pcm_pointer,
1392 };
1393
1394 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1395         .open =         snd_intel8x0_mic_open,
1396         .close =        snd_intel8x0_mic_close,
1397         .ioctl =        snd_pcm_lib_ioctl,
1398         .hw_params =    snd_intel8x0_hw_params,
1399         .hw_free =      snd_intel8x0_hw_free,
1400         .prepare =      snd_intel8x0_pcm_prepare,
1401         .trigger =      snd_intel8x0_ali_trigger,
1402         .pointer =      snd_intel8x0_pcm_pointer,
1403 };
1404
1405 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1406         .open =         snd_intel8x0_ali_ac97spdifout_open,
1407         .close =        snd_intel8x0_ali_ac97spdifout_close,
1408         .ioctl =        snd_pcm_lib_ioctl,
1409         .hw_params =    snd_intel8x0_hw_params,
1410         .hw_free =      snd_intel8x0_hw_free,
1411         .prepare =      snd_intel8x0_pcm_prepare,
1412         .trigger =      snd_intel8x0_ali_trigger,
1413         .pointer =      snd_intel8x0_pcm_pointer,
1414 };
1415
1416 #if 0 // NYI
1417 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1418         .open =         snd_intel8x0_ali_spdifin_open,
1419         .close =        snd_intel8x0_ali_spdifin_close,
1420         .ioctl =        snd_pcm_lib_ioctl,
1421         .hw_params =    snd_intel8x0_hw_params,
1422         .hw_free =      snd_intel8x0_hw_free,
1423         .prepare =      snd_intel8x0_pcm_prepare,
1424         .trigger =      snd_intel8x0_pcm_trigger,
1425         .pointer =      snd_intel8x0_pcm_pointer,
1426 };
1427
1428 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1429         .open =         snd_intel8x0_ali_spdifout_open,
1430         .close =        snd_intel8x0_ali_spdifout_close,
1431         .ioctl =        snd_pcm_lib_ioctl,
1432         .hw_params =    snd_intel8x0_hw_params,
1433         .hw_free =      snd_intel8x0_hw_free,
1434         .prepare =      snd_intel8x0_pcm_prepare,
1435         .trigger =      snd_intel8x0_pcm_trigger,
1436         .pointer =      snd_intel8x0_pcm_pointer,
1437 };
1438 #endif // NYI
1439
1440 struct ich_pcm_table {
1441         char *suffix;
1442         struct snd_pcm_ops *playback_ops;
1443         struct snd_pcm_ops *capture_ops;
1444         size_t prealloc_size;
1445         size_t prealloc_max_size;
1446         int ac97_idx;
1447 };
1448
1449 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1450                                        struct ich_pcm_table *rec)
1451 {
1452         struct snd_pcm *pcm;
1453         int err;
1454         char name[32];
1455
1456         if (rec->suffix)
1457                 sprintf(name, "Intel ICH - %s", rec->suffix);
1458         else
1459                 strcpy(name, "Intel ICH");
1460         err = snd_pcm_new(chip->card, name, device,
1461                           rec->playback_ops ? 1 : 0,
1462                           rec->capture_ops ? 1 : 0, &pcm);
1463         if (err < 0)
1464                 return err;
1465
1466         if (rec->playback_ops)
1467                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1468         if (rec->capture_ops)
1469                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1470
1471         pcm->private_data = chip;
1472         pcm->info_flags = 0;
1473         if (rec->suffix)
1474                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1475         else
1476                 strcpy(pcm->name, chip->card->shortname);
1477         chip->pcm[device] = pcm;
1478
1479         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1480                                               snd_dma_pci_data(chip->pci),
1481                                               rec->prealloc_size, rec->prealloc_max_size);
1482
1483         return 0;
1484 }
1485
1486 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1487         {
1488                 .playback_ops = &snd_intel8x0_playback_ops,
1489                 .capture_ops = &snd_intel8x0_capture_ops,
1490                 .prealloc_size = 64 * 1024,
1491                 .prealloc_max_size = 128 * 1024,
1492         },
1493         {
1494                 .suffix = "MIC ADC",
1495                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1496                 .prealloc_size = 0,
1497                 .prealloc_max_size = 128 * 1024,
1498                 .ac97_idx = ICHD_MIC,
1499         },
1500         {
1501                 .suffix = "MIC2 ADC",
1502                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1503                 .prealloc_size = 0,
1504                 .prealloc_max_size = 128 * 1024,
1505                 .ac97_idx = ICHD_MIC2,
1506         },
1507         {
1508                 .suffix = "ADC2",
1509                 .capture_ops = &snd_intel8x0_capture2_ops,
1510                 .prealloc_size = 0,
1511                 .prealloc_max_size = 128 * 1024,
1512                 .ac97_idx = ICHD_PCM2IN,
1513         },
1514         {
1515                 .suffix = "IEC958",
1516                 .playback_ops = &snd_intel8x0_spdif_ops,
1517                 .prealloc_size = 64 * 1024,
1518                 .prealloc_max_size = 128 * 1024,
1519                 .ac97_idx = ICHD_SPBAR,
1520         },
1521 };
1522
1523 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1524         {
1525                 .playback_ops = &snd_intel8x0_playback_ops,
1526                 .capture_ops = &snd_intel8x0_capture_ops,
1527                 .prealloc_size = 64 * 1024,
1528                 .prealloc_max_size = 128 * 1024,
1529         },
1530         {
1531                 .suffix = "MIC ADC",
1532                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1533                 .prealloc_size = 0,
1534                 .prealloc_max_size = 128 * 1024,
1535                 .ac97_idx = NVD_MIC,
1536         },
1537         {
1538                 .suffix = "IEC958",
1539                 .playback_ops = &snd_intel8x0_spdif_ops,
1540                 .prealloc_size = 64 * 1024,
1541                 .prealloc_max_size = 128 * 1024,
1542                 .ac97_idx = NVD_SPBAR,
1543         },
1544 };
1545
1546 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1547         {
1548                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1549                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1550                 .prealloc_size = 64 * 1024,
1551                 .prealloc_max_size = 128 * 1024,
1552         },
1553         {
1554                 .suffix = "MIC ADC",
1555                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1556                 .prealloc_size = 0,
1557                 .prealloc_max_size = 128 * 1024,
1558                 .ac97_idx = ALID_MIC,
1559         },
1560         {
1561                 .suffix = "IEC958",
1562                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1563                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1564                 .prealloc_size = 64 * 1024,
1565                 .prealloc_max_size = 128 * 1024,
1566                 .ac97_idx = ALID_AC97SPDIFOUT,
1567         },
1568 #if 0 // NYI
1569         {
1570                 .suffix = "HW IEC958",
1571                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1572                 .prealloc_size = 64 * 1024,
1573                 .prealloc_max_size = 128 * 1024,
1574         },
1575 #endif
1576 };
1577
1578 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1579 {
1580         int i, tblsize, device, err;
1581         struct ich_pcm_table *tbl, *rec;
1582
1583         switch (chip->device_type) {
1584         case DEVICE_INTEL_ICH4:
1585                 tbl = intel_pcms;
1586                 tblsize = ARRAY_SIZE(intel_pcms);
1587                 if (spdif_aclink)
1588                         tblsize--;
1589                 break;
1590         case DEVICE_NFORCE:
1591                 tbl = nforce_pcms;
1592                 tblsize = ARRAY_SIZE(nforce_pcms);
1593                 if (spdif_aclink)
1594                         tblsize--;
1595                 break;
1596         case DEVICE_ALI:
1597                 tbl = ali_pcms;
1598                 tblsize = ARRAY_SIZE(ali_pcms);
1599                 break;
1600         default:
1601                 tbl = intel_pcms;
1602                 tblsize = 2;
1603                 break;
1604         }
1605
1606         device = 0;
1607         for (i = 0; i < tblsize; i++) {
1608                 rec = tbl + i;
1609                 if (i > 0 && rec->ac97_idx) {
1610                         /* activate PCM only when associated AC'97 codec */
1611                         if (! chip->ichd[rec->ac97_idx].pcm)
1612                                 continue;
1613                 }
1614                 err = snd_intel8x0_pcm1(chip, device, rec);
1615                 if (err < 0)
1616                         return err;
1617                 device++;
1618         }
1619
1620         chip->pcm_devs = device;
1621         return 0;
1622 }
1623
1624
1625 /*
1626  *  Mixer part
1627  */
1628
1629 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1630 {
1631         struct intel8x0 *chip = bus->private_data;
1632         chip->ac97_bus = NULL;
1633 }
1634
1635 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1636 {
1637         struct intel8x0 *chip = ac97->private_data;
1638         chip->ac97[ac97->num] = NULL;
1639 }
1640
1641 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1642         /* front PCM */
1643         {
1644                 .exclusive = 1,
1645                 .r = {  {
1646                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1647                                          (1 << AC97_SLOT_PCM_RIGHT) |
1648                                          (1 << AC97_SLOT_PCM_CENTER) |
1649                                          (1 << AC97_SLOT_PCM_SLEFT) |
1650                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1651                                          (1 << AC97_SLOT_LFE)
1652                         },
1653                         {
1654                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1655                                          (1 << AC97_SLOT_PCM_RIGHT) |
1656                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1657                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1658                         }
1659                 }
1660         },
1661         /* PCM IN #1 */
1662         {
1663                 .stream = 1,
1664                 .exclusive = 1,
1665                 .r = {  {
1666                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1667                                          (1 << AC97_SLOT_PCM_RIGHT)
1668                         }
1669                 }
1670         },
1671         /* MIC IN #1 */
1672         {
1673                 .stream = 1,
1674                 .exclusive = 1,
1675                 .r = {  {
1676                                 .slots = (1 << AC97_SLOT_MIC)
1677                         }
1678                 }
1679         },
1680         /* S/PDIF PCM */
1681         {
1682                 .exclusive = 1,
1683                 .spdif = 1,
1684                 .r = {  {
1685                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1686                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1687                         }
1688                 }
1689         },
1690         /* PCM IN #2 */
1691         {
1692                 .stream = 1,
1693                 .exclusive = 1,
1694                 .r = {  {
1695                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1696                                          (1 << AC97_SLOT_PCM_RIGHT)
1697                         }
1698                 }
1699         },
1700         /* MIC IN #2 */
1701         {
1702                 .stream = 1,
1703                 .exclusive = 1,
1704                 .r = {  {
1705                                 .slots = (1 << AC97_SLOT_MIC)
1706                         }
1707                 }
1708         },
1709 };
1710
1711 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1712         {
1713                 .subvendor = 0x0e11,
1714                 .subdevice = 0x008a,
1715                 .name = "Compaq Evo W4000",     /* AD1885 */
1716                 .type = AC97_TUNE_HP_ONLY
1717         },
1718         {
1719                 .subvendor = 0x0e11,
1720                 .subdevice = 0x00b8,
1721                 .name = "Compaq Evo D510C",
1722                 .type = AC97_TUNE_HP_ONLY
1723         },
1724         {
1725                 .subvendor = 0x0e11,
1726                 .subdevice = 0x0860,
1727                 .name = "HP/Compaq nx7010",
1728                 .type = AC97_TUNE_MUTE_LED
1729         },
1730         {
1731                 .subvendor = 0x1014,
1732                 .subdevice = 0x1f00,
1733                 .name = "MS-9128",
1734                 .type = AC97_TUNE_ALC_JACK
1735         },
1736         {
1737                 .subvendor = 0x1014,
1738                 .subdevice = 0x0267,
1739                 .name = "IBM NetVista A30p",    /* AD1981B */
1740                 .type = AC97_TUNE_HP_ONLY
1741         },
1742         {
1743                 .subvendor = 0x1025,
1744                 .subdevice = 0x0083,
1745                 .name = "Acer Aspire 3003LCi",
1746                 .type = AC97_TUNE_HP_ONLY
1747         },
1748         {
1749                 .subvendor = 0x1028,
1750                 .subdevice = 0x00d8,
1751                 .name = "Dell Precision 530",   /* AD1885 */
1752                 .type = AC97_TUNE_HP_ONLY
1753         },
1754         {
1755                 .subvendor = 0x1028,
1756                 .subdevice = 0x010d,
1757                 .name = "Dell", /* which model?  AD1885 */
1758                 .type = AC97_TUNE_HP_ONLY
1759         },
1760         {
1761                 .subvendor = 0x1028,
1762                 .subdevice = 0x0126,
1763                 .name = "Dell Optiplex GX260",  /* AD1981A */
1764                 .type = AC97_TUNE_HP_ONLY
1765         },
1766         {
1767                 .subvendor = 0x1028,
1768                 .subdevice = 0x012c,
1769                 .name = "Dell Precision 650",   /* AD1981A */
1770                 .type = AC97_TUNE_HP_ONLY
1771         },
1772         {
1773                 .subvendor = 0x1028,
1774                 .subdevice = 0x012d,
1775                 .name = "Dell Precision 450",   /* AD1981B*/
1776                 .type = AC97_TUNE_HP_ONLY
1777         },
1778         {
1779                 .subvendor = 0x1028,
1780                 .subdevice = 0x0147,
1781                 .name = "Dell", /* which model?  AD1981B*/
1782                 .type = AC97_TUNE_HP_ONLY
1783         },
1784         {
1785                 .subvendor = 0x1028,
1786                 .subdevice = 0x0151,
1787                 .name = "Dell Optiplex GX270",  /* AD1981B */
1788                 .type = AC97_TUNE_HP_ONLY
1789         },
1790         {
1791                 .subvendor = 0x1028,
1792                 .subdevice = 0x014e,
1793                 .name = "Dell D800", /* STAC9750/51 */
1794                 .type = AC97_TUNE_HP_ONLY
1795         },
1796         {
1797                 .subvendor = 0x1028,
1798                 .subdevice = 0x0163,
1799                 .name = "Dell Unknown", /* STAC9750/51 */
1800                 .type = AC97_TUNE_HP_ONLY
1801         },
1802         {
1803                 .subvendor = 0x1028,
1804                 .subdevice = 0x0186,
1805                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1806                 .type = AC97_TUNE_HP_MUTE_LED
1807         },
1808         {
1809                 .subvendor = 0x1028,
1810                 .subdevice = 0x0188,
1811                 .name = "Dell Inspiron 6000",
1812                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1813         },
1814         {
1815                 .subvendor = 0x1028,
1816                 .subdevice = 0x0191,
1817                 .name = "Dell Inspiron 8600",
1818                 .type = AC97_TUNE_HP_ONLY
1819         },
1820         {
1821                 .subvendor = 0x103c,
1822                 .subdevice = 0x006d,
1823                 .name = "HP zv5000",
1824                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1825         },
1826         {       /* FIXME: which codec? */
1827                 .subvendor = 0x103c,
1828                 .subdevice = 0x00c3,
1829                 .name = "HP xw6000",
1830                 .type = AC97_TUNE_HP_ONLY
1831         },
1832         {
1833                 .subvendor = 0x103c,
1834                 .subdevice = 0x088c,
1835                 .name = "HP nc8000",
1836                 .type = AC97_TUNE_HP_MUTE_LED
1837         },
1838         {
1839                 .subvendor = 0x103c,
1840                 .subdevice = 0x0890,
1841                 .name = "HP nc6000",
1842                 .type = AC97_TUNE_MUTE_LED
1843         },
1844         {
1845                 .subvendor = 0x103c,
1846                 .subdevice = 0x0934,
1847                 .name = "HP nx8220",
1848                 .type = AC97_TUNE_MUTE_LED
1849         },
1850         {
1851                 .subvendor = 0x103c,
1852                 .subdevice = 0x129d,
1853                 .name = "HP xw8000",
1854                 .type = AC97_TUNE_HP_ONLY
1855         },
1856         {
1857                 .subvendor = 0x103c,
1858                 .subdevice = 0x0938,
1859                 .name = "HP nc4200",
1860                 .type = AC97_TUNE_HP_MUTE_LED
1861         },
1862         {
1863                 .subvendor = 0x103c,
1864                 .subdevice = 0x099c,
1865                 .name = "HP nx6110/nc6120",
1866                 .type = AC97_TUNE_HP_MUTE_LED
1867         },
1868         {
1869                 .subvendor = 0x103c,
1870                 .subdevice = 0x0944,
1871                 .name = "HP nc6220",
1872                 .type = AC97_TUNE_HP_MUTE_LED
1873         },
1874         {
1875                 .subvendor = 0x103c,
1876                 .subdevice = 0x0934,
1877                 .name = "HP nc8220",
1878                 .type = AC97_TUNE_HP_MUTE_LED
1879         },
1880         {
1881                 .subvendor = 0x103c,
1882                 .subdevice = 0x12f1,
1883                 .name = "HP xw8200",    /* AD1981B*/
1884                 .type = AC97_TUNE_HP_ONLY
1885         },
1886         {
1887                 .subvendor = 0x103c,
1888                 .subdevice = 0x12f2,
1889                 .name = "HP xw6200",
1890                 .type = AC97_TUNE_HP_ONLY
1891         },
1892         {
1893                 .subvendor = 0x103c,
1894                 .subdevice = 0x3008,
1895                 .name = "HP xw4200",    /* AD1981B*/
1896                 .type = AC97_TUNE_HP_ONLY
1897         },
1898         {
1899                 .subvendor = 0x104d,
1900                 .subdevice = 0x8197,
1901                 .name = "Sony S1XP",
1902                 .type = AC97_TUNE_INV_EAPD
1903         },
1904         {
1905                 .subvendor = 0x1043,
1906                 .subdevice = 0x80f3,
1907                 .name = "ASUS ICH5/AD1985",
1908                 .type = AC97_TUNE_AD_SHARING
1909         },
1910         {
1911                 .subvendor = 0x10cf,
1912                 .subdevice = 0x11c3,
1913                 .name = "Fujitsu-Siemens E4010",
1914                 .type = AC97_TUNE_HP_ONLY
1915         },
1916         {
1917                 .subvendor = 0x10cf,
1918                 .subdevice = 0x1225,
1919                 .name = "Fujitsu-Siemens T3010",
1920                 .type = AC97_TUNE_HP_ONLY
1921         },
1922         {
1923                 .subvendor = 0x10cf,
1924                 .subdevice = 0x1253,
1925                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1926                 .type = AC97_TUNE_HP_ONLY
1927         },
1928         {
1929                 .subvendor = 0x10cf,
1930                 .subdevice = 0x127e,
1931                 .name = "Fujitsu Lifebook C1211D",
1932                 .type = AC97_TUNE_HP_ONLY
1933         },
1934         {
1935                 .subvendor = 0x10cf,
1936                 .subdevice = 0x12ec,
1937                 .name = "Fujitsu-Siemens 4010",
1938                 .type = AC97_TUNE_HP_ONLY
1939         },
1940         {
1941                 .subvendor = 0x10cf,
1942                 .subdevice = 0x12f2,
1943                 .name = "Fujitsu-Siemens Celsius H320",
1944                 .type = AC97_TUNE_SWAP_HP
1945         },
1946         {
1947                 .subvendor = 0x10f1,
1948                 .subdevice = 0x2665,
1949                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1950                 .type = AC97_TUNE_HP_ONLY
1951         },
1952         {
1953                 .subvendor = 0x10f1,
1954                 .subdevice = 0x2885,
1955                 .name = "AMD64 Mobo",   /* ALC650 */
1956                 .type = AC97_TUNE_HP_ONLY
1957         },
1958         {
1959                 .subvendor = 0x10f1,
1960                 .subdevice = 0x2895,
1961                 .name = "Tyan Thunder K8WE",
1962                 .type = AC97_TUNE_HP_ONLY
1963         },
1964         {
1965                 .subvendor = 0x10f7,
1966                 .subdevice = 0x834c,
1967                 .name = "Panasonic CF-R4",
1968                 .type = AC97_TUNE_HP_ONLY,
1969         },
1970         {
1971                 .subvendor = 0x110a,
1972                 .subdevice = 0x0056,
1973                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1974                 .type = AC97_TUNE_HP_ONLY
1975         },
1976         {
1977                 .subvendor = 0x11d4,
1978                 .subdevice = 0x5375,
1979                 .name = "ADI AD1985 (discrete)",
1980                 .type = AC97_TUNE_HP_ONLY
1981         },
1982         {
1983                 .subvendor = 0x1462,
1984                 .subdevice = 0x5470,
1985                 .name = "MSI P4 ATX 645 Ultra",
1986                 .type = AC97_TUNE_HP_ONLY
1987         },
1988         {
1989                 .subvendor = 0x1734,
1990                 .subdevice = 0x0088,
1991                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1992                 .type = AC97_TUNE_HP_ONLY
1993         },
1994         {
1995                 .subvendor = 0x8086,
1996                 .subdevice = 0x2000,
1997                 .mask = 0xfff0,
1998                 .name = "Intel ICH5/AD1985",
1999                 .type = AC97_TUNE_AD_SHARING
2000         },
2001         {
2002                 .subvendor = 0x8086,
2003                 .subdevice = 0x4000,
2004                 .mask = 0xfff0,
2005                 .name = "Intel ICH5/AD1985",
2006                 .type = AC97_TUNE_AD_SHARING
2007         },
2008         {
2009                 .subvendor = 0x8086,
2010                 .subdevice = 0x4856,
2011                 .name = "Intel D845WN (82801BA)",
2012                 .type = AC97_TUNE_SWAP_HP
2013         },
2014         {
2015                 .subvendor = 0x8086,
2016                 .subdevice = 0x4d44,
2017                 .name = "Intel D850EMV2",       /* AD1885 */
2018                 .type = AC97_TUNE_HP_ONLY
2019         },
2020         {
2021                 .subvendor = 0x8086,
2022                 .subdevice = 0x4d56,
2023                 .name = "Intel ICH/AD1885",
2024                 .type = AC97_TUNE_HP_ONLY
2025         },
2026         {
2027                 .subvendor = 0x8086,
2028                 .subdevice = 0x6000,
2029                 .mask = 0xfff0,
2030                 .name = "Intel ICH5/AD1985",
2031                 .type = AC97_TUNE_AD_SHARING
2032         },
2033         {
2034                 .subvendor = 0x8086,
2035                 .subdevice = 0xe000,
2036                 .mask = 0xfff0,
2037                 .name = "Intel ICH5/AD1985",
2038                 .type = AC97_TUNE_AD_SHARING
2039         },
2040 #if 0 /* FIXME: this seems wrong on most boards */
2041         {
2042                 .subvendor = 0x8086,
2043                 .subdevice = 0xa000,
2044                 .mask = 0xfff0,
2045                 .name = "Intel ICH5/AD1985",
2046                 .type = AC97_TUNE_HP_ONLY
2047         },
2048 #endif
2049         { } /* terminator */
2050 };
2051
2052 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2053                                         const char *quirk_override)
2054 {
2055         struct snd_ac97_bus *pbus;
2056         struct snd_ac97_template ac97;
2057         int err;
2058         unsigned int i, codecs;
2059         unsigned int glob_sta = 0;
2060         struct snd_ac97_bus_ops *ops;
2061         static struct snd_ac97_bus_ops standard_bus_ops = {
2062                 .write = snd_intel8x0_codec_write,
2063                 .read = snd_intel8x0_codec_read,
2064         };
2065         static struct snd_ac97_bus_ops ali_bus_ops = {
2066                 .write = snd_intel8x0_ali_codec_write,
2067                 .read = snd_intel8x0_ali_codec_read,
2068         };
2069
2070         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2071         if (!spdif_aclink) {
2072                 switch (chip->device_type) {
2073                 case DEVICE_NFORCE:
2074                         chip->spdif_idx = NVD_SPBAR;
2075                         break;
2076                 case DEVICE_ALI:
2077                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2078                         break;
2079                 case DEVICE_INTEL_ICH4:
2080                         chip->spdif_idx = ICHD_SPBAR;
2081                         break;
2082                 };
2083         }
2084
2085         chip->in_ac97_init = 1;
2086
2087         memset(&ac97, 0, sizeof(ac97));
2088         ac97.private_data = chip;
2089         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2090         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2091         if (chip->xbox)
2092                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2093         if (chip->device_type != DEVICE_ALI) {
2094                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2095                 ops = &standard_bus_ops;
2096                 chip->in_sdin_init = 1;
2097                 codecs = 0;
2098                 for (i = 0; i < chip->max_codecs; i++) {
2099                         if (! (glob_sta & chip->codec_bit[i]))
2100                                 continue;
2101                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2102                                 snd_intel8x0_codec_read_test(chip, codecs);
2103                                 chip->ac97_sdin[codecs] =
2104                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2105                                 snd_assert(chip->ac97_sdin[codecs] < 3,
2106                                            chip->ac97_sdin[codecs] = 0);
2107                         } else
2108                                 chip->ac97_sdin[codecs] = i;
2109                         codecs++;
2110                 }
2111                 chip->in_sdin_init = 0;
2112                 if (! codecs)
2113                         codecs = 1;
2114         } else {
2115                 ops = &ali_bus_ops;
2116                 codecs = 1;
2117                 /* detect the secondary codec */
2118                 for (i = 0; i < 100; i++) {
2119                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2120                         if (reg & 0x40) {
2121                                 codecs = 2;
2122                                 break;
2123                         }
2124                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2125                         udelay(1);
2126                 }
2127         }
2128         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2129                 goto __err;
2130         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2131         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2132                 pbus->clock = ac97_clock;
2133         /* FIXME: my test board doesn't work well with VRA... */
2134         if (chip->device_type == DEVICE_ALI)
2135                 pbus->no_vra = 1;
2136         else
2137                 pbus->dra = 1;
2138         chip->ac97_bus = pbus;
2139         chip->ncodecs = codecs;
2140
2141         ac97.pci = chip->pci;
2142         for (i = 0; i < codecs; i++) {
2143                 ac97.num = i;
2144                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2145                         if (err != -EACCES)
2146                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2147                         if (i == 0)
2148                                 goto __err;
2149                 }
2150         }
2151         /* tune up the primary codec */
2152         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2153         /* enable separate SDINs for ICH4 */
2154         if (chip->device_type == DEVICE_INTEL_ICH4)
2155                 pbus->isdin = 1;
2156         /* find the available PCM streams */
2157         i = ARRAY_SIZE(ac97_pcm_defs);
2158         if (chip->device_type != DEVICE_INTEL_ICH4)
2159                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2160         if (chip->spdif_idx < 0)
2161                 i--;            /* do not allocate S/PDIF */
2162         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2163         if (err < 0)
2164                 goto __err;
2165         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2166         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2167         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2168         if (chip->spdif_idx >= 0)
2169                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2170         if (chip->device_type == DEVICE_INTEL_ICH4) {
2171                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2172                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2173         }
2174         /* enable separate SDINs for ICH4 */
2175         if (chip->device_type == DEVICE_INTEL_ICH4) {
2176                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2177                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2178                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2179                 if (pcm) {
2180                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2181                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2182                         for (i = 1; i < 4; i++) {
2183                                 if (pcm->r[0].codec[i]) {
2184                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2185                                         break;
2186                                 }
2187                         }
2188                 } else {
2189                         tmp &= ~ICH_SE; /* steer disable */
2190                 }
2191                 iputbyte(chip, ICHREG(SDM), tmp);
2192         }
2193         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2194                 chip->multi4 = 1;
2195                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2196                         chip->multi6 = 1;
2197         }
2198         if (pbus->pcms[0].r[1].rslots[0]) {
2199                 chip->dra = 1;
2200         }
2201         if (chip->device_type == DEVICE_INTEL_ICH4) {
2202                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2203                         chip->smp20bit = 1;
2204         }
2205         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2206                 /* 48kHz only */
2207                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2208         }
2209         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2210                 /* use slot 10/11 for SPDIF */
2211                 u32 val;
2212                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2213                 val |= ICH_PCM_SPDIF_1011;
2214                 iputdword(chip, ICHREG(GLOB_CNT), val);
2215                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2216         }
2217         chip->in_ac97_init = 0;
2218         return 0;
2219
2220  __err:
2221         /* clear the cold-reset bit for the next chance */
2222         if (chip->device_type != DEVICE_ALI)
2223                 iputdword(chip, ICHREG(GLOB_CNT),
2224                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2225         return err;
2226 }
2227
2228
2229 /*
2230  *
2231  */
2232
2233 static void do_ali_reset(struct intel8x0 *chip)
2234 {
2235         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2236         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2237         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2238         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2239         iputdword(chip, ICHREG(ALI_INTERFACECR),
2240                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2241         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2242         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2243 }
2244
2245 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2246 {
2247         unsigned long end_time;
2248         unsigned int cnt, status, nstatus;
2249
2250         /* put logic to right state */
2251         /* first clear status bits */
2252         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2253         if (chip->device_type == DEVICE_NFORCE)
2254                 status |= ICH_NVSPINT;
2255         cnt = igetdword(chip, ICHREG(GLOB_STA));
2256         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2257
2258         /* ACLink on, 2 channels */
2259         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2260         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2261 #ifdef CONFIG_SND_AC97_POWER_SAVE
2262         /* do cold reset - the full ac97 powerdown may leave the controller
2263          * in a warm state but actually it cannot communicate with the codec.
2264          */
2265         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2266         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2267         udelay(10);
2268         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2269         msleep(1);
2270 #else
2271         /* finish cold or do warm reset */
2272         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2273         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2274         end_time = (jiffies + (HZ / 4)) + 1;
2275         do {
2276                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2277                         goto __ok;
2278                 schedule_timeout_uninterruptible(1);
2279         } while (time_after_eq(end_time, jiffies));
2280         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2281                    igetdword(chip, ICHREG(GLOB_CNT)));
2282         return -EIO;
2283
2284       __ok:
2285 #endif
2286         if (probing) {
2287                 /* wait for any codec ready status.
2288                  * Once it becomes ready it should remain ready
2289                  * as long as we do not disable the ac97 link.
2290                  */
2291                 end_time = jiffies + HZ;
2292                 do {
2293                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2294                                 chip->codec_isr_bits;
2295                         if (status)
2296                                 break;
2297                         schedule_timeout_uninterruptible(1);
2298                 } while (time_after_eq(end_time, jiffies));
2299                 if (! status) {
2300                         /* no codec is found */
2301                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2302                                    igetdword(chip, ICHREG(GLOB_STA)));
2303                         return -EIO;
2304                 }
2305
2306                 /* wait for other codecs ready status. */
2307                 end_time = jiffies + HZ / 4;
2308                 while (status != chip->codec_isr_bits &&
2309                        time_after_eq(end_time, jiffies)) {
2310                         schedule_timeout_uninterruptible(1);
2311                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2312                                 chip->codec_isr_bits;
2313                 }
2314
2315         } else {
2316                 /* resume phase */
2317                 int i;
2318                 status = 0;
2319                 for (i = 0; i < chip->ncodecs; i++)
2320                         if (chip->ac97[i])
2321                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2322                 /* wait until all the probed codecs are ready */
2323                 end_time = jiffies + HZ;
2324                 do {
2325                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2326                                 chip->codec_isr_bits;
2327                         if (status == nstatus)
2328                                 break;
2329                         schedule_timeout_uninterruptible(1);
2330                 } while (time_after_eq(end_time, jiffies));
2331         }
2332
2333         if (chip->device_type == DEVICE_SIS) {
2334                 /* unmute the output on SIS7012 */
2335                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2336         }
2337         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2338                 /* enable SPDIF interrupt */
2339                 unsigned int val;
2340                 pci_read_config_dword(chip->pci, 0x4c, &val);
2341                 val |= 0x1000000;
2342                 pci_write_config_dword(chip->pci, 0x4c, val);
2343         }
2344         return 0;
2345 }
2346
2347 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2348 {
2349         u32 reg;
2350         int i = 0;
2351
2352         reg = igetdword(chip, ICHREG(ALI_SCR));
2353         if ((reg & 2) == 0)     /* Cold required */
2354                 reg |= 2;
2355         else
2356                 reg |= 1;       /* Warm */
2357         reg &= ~0x80000000;     /* ACLink on */
2358         iputdword(chip, ICHREG(ALI_SCR), reg);
2359
2360         for (i = 0; i < HZ / 2; i++) {
2361                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2362                         goto __ok;
2363                 schedule_timeout_uninterruptible(1);
2364         }
2365         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2366         if (probing)
2367                 return -EIO;
2368
2369  __ok:
2370         for (i = 0; i < HZ / 2; i++) {
2371                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2372                 if (reg & 0x80) /* primary codec */
2373                         break;
2374                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2375                 schedule_timeout_uninterruptible(1);
2376         }
2377
2378         do_ali_reset(chip);
2379         return 0;
2380 }
2381
2382 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2383 {
2384         unsigned int i, timeout;
2385         int err;
2386
2387         if (chip->device_type != DEVICE_ALI) {
2388                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2389                         return err;
2390                 iagetword(chip, 0);     /* clear semaphore flag */
2391         } else {
2392                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2393                         return err;
2394         }
2395
2396         /* disable interrupts */
2397         for (i = 0; i < chip->bdbars_count; i++)
2398                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2399         /* reset channels */
2400         for (i = 0; i < chip->bdbars_count; i++)
2401                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2402         for (i = 0; i < chip->bdbars_count; i++) {
2403                 timeout = 100000;
2404                 while (--timeout != 0) {
2405                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2406                                 break;
2407                 }
2408                 if (timeout == 0)
2409                         printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2410         }
2411         /* initialize Buffer Descriptor Lists */
2412         for (i = 0; i < chip->bdbars_count; i++)
2413                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2414                           chip->ichd[i].bdbar_addr);
2415         return 0;
2416 }
2417
2418 static int snd_intel8x0_free(struct intel8x0 *chip)
2419 {
2420         unsigned int i;
2421
2422         if (chip->irq < 0)
2423                 goto __hw_end;
2424         /* disable interrupts */
2425         for (i = 0; i < chip->bdbars_count; i++)
2426                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2427         /* reset channels */
2428         for (i = 0; i < chip->bdbars_count; i++)
2429                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2430         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2431                 /* stop the spdif interrupt */
2432                 unsigned int val;
2433                 pci_read_config_dword(chip->pci, 0x4c, &val);
2434                 val &= ~0x1000000;
2435                 pci_write_config_dword(chip->pci, 0x4c, val);
2436         }
2437         /* --- */
2438         synchronize_irq(chip->irq);
2439       __hw_end:
2440         if (chip->irq >= 0)
2441                 free_irq(chip->irq, chip);
2442         if (chip->bdbars.area) {
2443                 if (chip->fix_nocache)
2444                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2445                 snd_dma_free_pages(&chip->bdbars);
2446         }
2447         if (chip->addr)
2448                 pci_iounmap(chip->pci, chip->addr);
2449         if (chip->bmaddr)
2450                 pci_iounmap(chip->pci, chip->bmaddr);
2451         pci_release_regions(chip->pci);
2452         pci_disable_device(chip->pci);
2453         kfree(chip);
2454         return 0;
2455 }
2456
2457 #ifdef CONFIG_PM
2458 /*
2459  * power management
2460  */
2461 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2462 {
2463         struct snd_card *card = pci_get_drvdata(pci);
2464         struct intel8x0 *chip = card->private_data;
2465         int i;
2466
2467         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2468         for (i = 0; i < chip->pcm_devs; i++)
2469                 snd_pcm_suspend_all(chip->pcm[i]);
2470         /* clear nocache */
2471         if (chip->fix_nocache) {
2472                 for (i = 0; i < chip->bdbars_count; i++) {
2473                         struct ichdev *ichdev = &chip->ichd[i];
2474                         if (ichdev->substream && ichdev->page_attr_changed) {
2475                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2476                                 if (runtime->dma_area)
2477                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2478                         }
2479                 }
2480         }
2481         for (i = 0; i < chip->ncodecs; i++)
2482                 snd_ac97_suspend(chip->ac97[i]);
2483         if (chip->device_type == DEVICE_INTEL_ICH4)
2484                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2485
2486         if (chip->irq >= 0) {
2487                 synchronize_irq(chip->irq);
2488                 free_irq(chip->irq, chip);
2489                 chip->irq = -1;
2490         }
2491         pci_disable_device(pci);
2492         pci_save_state(pci);
2493         /* The call below may disable built-in speaker on some laptops
2494          * after S2RAM.  So, don't touch it.
2495          */
2496         /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2497         return 0;
2498 }
2499
2500 static int intel8x0_resume(struct pci_dev *pci)
2501 {
2502         struct snd_card *card = pci_get_drvdata(pci);
2503         struct intel8x0 *chip = card->private_data;
2504         int i;
2505
2506         pci_set_power_state(pci, PCI_D0);
2507         pci_restore_state(pci);
2508         if (pci_enable_device(pci) < 0) {
2509                 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2510                        "disabling device\n");
2511                 snd_card_disconnect(card);
2512                 return -EIO;
2513         }
2514         pci_set_master(pci);
2515         snd_intel8x0_chip_init(chip, 0);
2516         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2517                         IRQF_SHARED, card->shortname, chip)) {
2518                 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2519                        "disabling device\n", pci->irq);
2520                 snd_card_disconnect(card);
2521                 return -EIO;
2522         }
2523         chip->irq = pci->irq;
2524         synchronize_irq(chip->irq);
2525
2526         /* re-initialize mixer stuff */
2527         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2528                 /* enable separate SDINs for ICH4 */
2529                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2530                 /* use slot 10/11 for SPDIF */
2531                 iputdword(chip, ICHREG(GLOB_CNT),
2532                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2533                           ICH_PCM_SPDIF_1011);
2534         }
2535
2536         /* refill nocache */
2537         if (chip->fix_nocache)
2538                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2539
2540         for (i = 0; i < chip->ncodecs; i++)
2541                 snd_ac97_resume(chip->ac97[i]);
2542
2543         /* refill nocache */
2544         if (chip->fix_nocache) {
2545                 for (i = 0; i < chip->bdbars_count; i++) {
2546                         struct ichdev *ichdev = &chip->ichd[i];
2547                         if (ichdev->substream && ichdev->page_attr_changed) {
2548                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2549                                 if (runtime->dma_area)
2550                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2551                         }
2552                 }
2553         }
2554
2555         /* resume status */
2556         for (i = 0; i < chip->bdbars_count; i++) {
2557                 struct ichdev *ichdev = &chip->ichd[i];
2558                 unsigned long port = ichdev->reg_offset;
2559                 if (! ichdev->substream || ! ichdev->suspended)
2560                         continue;
2561                 if (ichdev->ichd == ICHD_PCMOUT)
2562                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2563                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2564                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2565                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2566                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2567         }
2568
2569         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2570         return 0;
2571 }
2572 #endif /* CONFIG_PM */
2573
2574 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2575
2576 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2577 {
2578         struct snd_pcm_substream *subs;
2579         struct ichdev *ichdev;
2580         unsigned long port;
2581         unsigned long pos, t;
2582         struct timeval start_time, stop_time;
2583
2584         if (chip->ac97_bus->clock != 48000)
2585                 return; /* specified in module option */
2586
2587         subs = chip->pcm[0]->streams[0].substream;
2588         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2589                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2590                 return;
2591         }
2592         ichdev = &chip->ichd[ICHD_PCMOUT];
2593         ichdev->physbuf = subs->dma_buffer.addr;
2594         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2595         ichdev->substream = NULL; /* don't process interrupts */
2596
2597         /* set rate */
2598         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2599                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2600                 return;
2601         }
2602         snd_intel8x0_setup_periods(chip, ichdev);
2603         port = ichdev->reg_offset;
2604         spin_lock_irq(&chip->reg_lock);
2605         chip->in_measurement = 1;
2606         /* trigger */
2607         if (chip->device_type != DEVICE_ALI)
2608                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2609         else {
2610                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2611                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2612         }
2613         do_gettimeofday(&start_time);
2614         spin_unlock_irq(&chip->reg_lock);
2615         msleep(50);
2616         spin_lock_irq(&chip->reg_lock);
2617         /* check the position */
2618         pos = ichdev->fragsize1;
2619         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2620         pos += ichdev->position;
2621         chip->in_measurement = 0;
2622         do_gettimeofday(&stop_time);
2623         /* stop */
2624         if (chip->device_type == DEVICE_ALI) {
2625                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2626                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2627                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2628                         ;
2629         } else {
2630                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2631                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2632                         ;
2633         }
2634         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2635         spin_unlock_irq(&chip->reg_lock);
2636
2637         t = stop_time.tv_sec - start_time.tv_sec;
2638         t *= 1000000;
2639         t += stop_time.tv_usec - start_time.tv_usec;
2640         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2641         if (t == 0) {
2642                 snd_printk(KERN_ERR "?? calculation error..\n");
2643                 return;
2644         }
2645         pos = (pos / 4) * 1000;
2646         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2647         if (pos < 40000 || pos >= 60000)
2648                 /* abnormal value. hw problem? */
2649                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2650         else if (pos < 47500 || pos > 48500)
2651                 /* not 48000Hz, tuning the clock.. */
2652                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2653         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2654         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2655 }
2656
2657 #ifdef CONFIG_PROC_FS
2658 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2659                                    struct snd_info_buffer *buffer)
2660 {
2661         struct intel8x0 *chip = entry->private_data;
2662         unsigned int tmp;
2663
2664         snd_iprintf(buffer, "Intel8x0\n\n");
2665         if (chip->device_type == DEVICE_ALI)
2666                 return;
2667         tmp = igetdword(chip, ICHREG(GLOB_STA));
2668         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2669         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2670         if (chip->device_type == DEVICE_INTEL_ICH4)
2671                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2672         snd_iprintf(buffer, "AC'97 codecs ready    :");
2673         if (tmp & chip->codec_isr_bits) {
2674                 int i;
2675                 static const char *codecs[3] = {
2676                         "primary", "secondary", "tertiary"
2677                 };
2678                 for (i = 0; i < chip->max_codecs; i++)
2679                         if (tmp & chip->codec_bit[i])
2680                                 snd_iprintf(buffer, " %s", codecs[i]);
2681         } else
2682                 snd_iprintf(buffer, " none");
2683         snd_iprintf(buffer, "\n");
2684         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2685             chip->device_type == DEVICE_SIS)
2686                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2687                         chip->ac97_sdin[0],
2688                         chip->ac97_sdin[1],
2689                         chip->ac97_sdin[2]);
2690 }
2691
2692 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2693 {
2694         struct snd_info_entry *entry;
2695
2696         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2697                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2698 }
2699 #else
2700 #define snd_intel8x0_proc_init(x)
2701 #endif
2702
2703 static int snd_intel8x0_dev_free(struct snd_device *device)
2704 {
2705         struct intel8x0 *chip = device->device_data;
2706         return snd_intel8x0_free(chip);
2707 }
2708
2709 struct ich_reg_info {
2710         unsigned int int_sta_mask;
2711         unsigned int offset;
2712 };
2713
2714 static unsigned int ich_codec_bits[3] = {
2715         ICH_PCR, ICH_SCR, ICH_TCR
2716 };
2717 static unsigned int sis_codec_bits[3] = {
2718         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2719 };
2720
2721 static int __devinit snd_intel8x0_create(struct snd_card *card,
2722                                          struct pci_dev *pci,
2723                                          unsigned long device_type,
2724                                          struct intel8x0 ** r_intel8x0)
2725 {
2726         struct intel8x0 *chip;
2727         int err;
2728         unsigned int i;
2729         unsigned int int_sta_masks;
2730         struct ichdev *ichdev;
2731         static struct snd_device_ops ops = {
2732                 .dev_free =     snd_intel8x0_dev_free,
2733         };
2734
2735         static unsigned int bdbars[] = {
2736                 3, /* DEVICE_INTEL */
2737                 6, /* DEVICE_INTEL_ICH4 */
2738                 3, /* DEVICE_SIS */
2739                 6, /* DEVICE_ALI */
2740                 4, /* DEVICE_NFORCE */
2741         };
2742         static struct ich_reg_info intel_regs[6] = {
2743                 { ICH_PIINT, 0 },
2744                 { ICH_POINT, 0x10 },
2745                 { ICH_MCINT, 0x20 },
2746                 { ICH_M2INT, 0x40 },
2747                 { ICH_P2INT, 0x50 },
2748                 { ICH_SPINT, 0x60 },
2749         };
2750         static struct ich_reg_info nforce_regs[4] = {
2751                 { ICH_PIINT, 0 },
2752                 { ICH_POINT, 0x10 },
2753                 { ICH_MCINT, 0x20 },
2754                 { ICH_NVSPINT, 0x70 },
2755         };
2756         static struct ich_reg_info ali_regs[6] = {
2757                 { ALI_INT_PCMIN, 0x40 },
2758                 { ALI_INT_PCMOUT, 0x50 },
2759                 { ALI_INT_MICIN, 0x60 },
2760                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2761                 { ALI_INT_SPDIFIN, 0xa0 },
2762                 { ALI_INT_SPDIFOUT, 0xb0 },
2763         };
2764         struct ich_reg_info *tbl;
2765
2766         *r_intel8x0 = NULL;
2767
2768         if ((err = pci_enable_device(pci)) < 0)
2769                 return err;
2770
2771         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2772         if (chip == NULL) {
2773                 pci_disable_device(pci);
2774                 return -ENOMEM;
2775         }
2776         spin_lock_init(&chip->reg_lock);
2777         chip->device_type = device_type;
2778         chip->card = card;
2779         chip->pci = pci;
2780         chip->irq = -1;
2781
2782         /* module parameters */
2783         chip->buggy_irq = buggy_irq;
2784         chip->buggy_semaphore = buggy_semaphore;
2785         if (xbox)
2786                 chip->xbox = 1;
2787
2788         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2789             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2790                 chip->fix_nocache = 1; /* enable workaround */
2791
2792         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2793                 kfree(chip);
2794                 pci_disable_device(pci);
2795                 return err;
2796         }
2797
2798         if (device_type == DEVICE_ALI) {
2799                 /* ALI5455 has no ac97 region */
2800                 chip->bmaddr = pci_iomap(pci, 0, 0);
2801                 goto port_inited;
2802         }
2803
2804         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2805                 chip->addr = pci_iomap(pci, 2, 0);
2806         else
2807                 chip->addr = pci_iomap(pci, 0, 0);
2808         if (!chip->addr) {
2809                 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2810                 snd_intel8x0_free(chip);
2811                 return -EIO;
2812         }
2813         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2814                 chip->bmaddr = pci_iomap(pci, 3, 0);
2815         else
2816                 chip->bmaddr = pci_iomap(pci, 1, 0);
2817         if (!chip->bmaddr) {
2818                 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2819                 snd_intel8x0_free(chip);
2820                 return -EIO;
2821         }
2822
2823  port_inited:
2824         chip->bdbars_count = bdbars[device_type];
2825
2826         /* initialize offsets */
2827         switch (device_type) {
2828         case DEVICE_NFORCE:
2829                 tbl = nforce_regs;
2830                 break;
2831         case DEVICE_ALI:
2832                 tbl = ali_regs;
2833                 break;
2834         default:
2835                 tbl = intel_regs;
2836                 break;
2837         }
2838         for (i = 0; i < chip->bdbars_count; i++) {
2839                 ichdev = &chip->ichd[i];
2840                 ichdev->ichd = i;
2841                 ichdev->reg_offset = tbl[i].offset;
2842                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2843                 if (device_type == DEVICE_SIS) {
2844                         /* SiS 7012 swaps the registers */
2845                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2846                         ichdev->roff_picb = ICH_REG_OFF_SR;
2847                 } else {
2848                         ichdev->roff_sr = ICH_REG_OFF_SR;
2849                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2850                 }
2851                 if (device_type == DEVICE_ALI)
2852                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2853                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2854                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2855         }
2856
2857         /* allocate buffer descriptor lists */
2858         /* the start of each lists must be aligned to 8 bytes */
2859         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2860                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2861                                 &chip->bdbars) < 0) {
2862                 snd_intel8x0_free(chip);
2863                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2864                 return -ENOMEM;
2865         }
2866         /* tables must be aligned to 8 bytes here, but the kernel pages
2867            are much bigger, so we don't care (on i386) */
2868         /* workaround for 440MX */
2869         if (chip->fix_nocache)
2870                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2871         int_sta_masks = 0;
2872         for (i = 0; i < chip->bdbars_count; i++) {
2873                 ichdev = &chip->ichd[i];
2874                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2875                         (i * ICH_MAX_FRAGS * 2);
2876                 ichdev->bdbar_addr = chip->bdbars.addr +
2877                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2878                 int_sta_masks |= ichdev->int_sta_mask;
2879         }
2880         chip->int_sta_reg = device_type == DEVICE_ALI ?
2881                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2882         chip->int_sta_mask = int_sta_masks;
2883
2884         pci_set_master(pci);
2885
2886         switch(chip->device_type) {
2887         case DEVICE_INTEL_ICH4:
2888                 /* ICH4 can have three codecs */
2889                 chip->max_codecs = 3;
2890                 chip->codec_bit = ich_codec_bits;
2891                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2892                 break;
2893         case DEVICE_SIS:
2894                 /* recent SIS7012 can have three codecs */
2895                 chip->max_codecs = 3;
2896                 chip->codec_bit = sis_codec_bits;
2897                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2898                 break;
2899         default:
2900                 /* others up to two codecs */
2901                 chip->max_codecs = 2;
2902                 chip->codec_bit = ich_codec_bits;
2903                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2904                 break;
2905         }
2906         for (i = 0; i < chip->max_codecs; i++)
2907                 chip->codec_isr_bits |= chip->codec_bit[i];
2908
2909         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2910                 snd_intel8x0_free(chip);
2911                 return err;
2912         }
2913
2914         /* request irq after initializaing int_sta_mask, etc */
2915         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2916                         IRQF_SHARED, card->shortname, chip)) {
2917                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2918                 snd_intel8x0_free(chip);
2919                 return -EBUSY;
2920         }
2921         chip->irq = pci->irq;
2922
2923         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2924                 snd_intel8x0_free(chip);
2925                 return err;
2926         }
2927
2928         snd_card_set_dev(card, &pci->dev);
2929
2930         *r_intel8x0 = chip;
2931         return 0;
2932 }
2933
2934 static struct shortname_table {
2935         unsigned int id;
2936         const char *s;
2937 } shortnames[] __devinitdata = {
2938         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2939         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2940         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2941         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2942         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2943         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2944         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2945         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2946         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2947         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2948         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2949         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2950         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2951         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2952         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2953         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2954         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2955         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2956         { 0x003a, "NVidia MCP04" },
2957         { 0x746d, "AMD AMD8111" },
2958         { 0x7445, "AMD AMD768" },
2959         { 0x5455, "ALi M5455" },
2960         { 0, NULL },
2961 };
2962
2963 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
2964         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
2965         { } /* end */
2966 };
2967
2968 /* look up white/black list for SPDIF over ac-link */
2969 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
2970 {
2971         const struct snd_pci_quirk *w;
2972
2973         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
2974         if (w) {
2975                 if (w->value)
2976                         snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
2977                                     "AC-Link for %s\n", w->name);
2978                 else
2979                         snd_printdd(KERN_INFO "intel8x0: Using integrated "
2980                                     "SPDIF DMA for %s\n", w->name);
2981                 return w->value;
2982         }
2983         return 0;
2984 }
2985
2986 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2987                                         const struct pci_device_id *pci_id)
2988 {
2989         struct snd_card *card;
2990         struct intel8x0 *chip;
2991         int err;
2992         struct shortname_table *name;
2993
2994         card = snd_card_new(index, id, THIS_MODULE, 0);
2995         if (card == NULL)
2996                 return -ENOMEM;
2997
2998         if (spdif_aclink < 0)
2999                 spdif_aclink = check_default_spdif_aclink(pci);
3000
3001         strcpy(card->driver, "ICH");
3002         if (!spdif_aclink) {
3003                 switch (pci_id->driver_data) {
3004                 case DEVICE_NFORCE:
3005                         strcpy(card->driver, "NFORCE");
3006                         break;
3007                 case DEVICE_INTEL_ICH4:
3008                         strcpy(card->driver, "ICH4");
3009                 }
3010         }
3011
3012         strcpy(card->shortname, "Intel ICH");
3013         for (name = shortnames; name->id; name++) {
3014                 if (pci->device == name->id) {
3015                         strcpy(card->shortname, name->s);
3016                         break;
3017                 }
3018         }
3019
3020         if (buggy_irq < 0) {
3021                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3022                  * Needs to return IRQ_HANDLED for unknown irqs.
3023                  */
3024                 if (pci_id->driver_data == DEVICE_NFORCE)
3025                         buggy_irq = 1;
3026                 else
3027                         buggy_irq = 0;
3028         }
3029
3030         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3031                                        &chip)) < 0) {
3032                 snd_card_free(card);
3033                 return err;
3034         }
3035         card->private_data = chip;
3036
3037         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3038                 snd_card_free(card);
3039                 return err;
3040         }
3041         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3042                 snd_card_free(card);
3043                 return err;
3044         }
3045
3046         snd_intel8x0_proc_init(chip);
3047
3048         snprintf(card->longname, sizeof(card->longname),
3049                  "%s with %s at irq %i", card->shortname,
3050                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3051
3052         if (! ac97_clock)
3053                 intel8x0_measure_ac97_clock(chip);
3054
3055         if ((err = snd_card_register(card)) < 0) {
3056                 snd_card_free(card);
3057                 return err;
3058         }
3059         pci_set_drvdata(pci, card);
3060         return 0;
3061 }
3062
3063 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3064 {
3065         snd_card_free(pci_get_drvdata(pci));
3066         pci_set_drvdata(pci, NULL);
3067 }
3068
3069 static struct pci_driver driver = {
3070         .name = "Intel ICH",
3071         .id_table = snd_intel8x0_ids,
3072         .probe = snd_intel8x0_probe,
3073         .remove = __devexit_p(snd_intel8x0_remove),
3074 #ifdef CONFIG_PM
3075         .suspend = intel8x0_suspend,
3076         .resume = intel8x0_resume,
3077 #endif
3078 };
3079
3080
3081 static int __init alsa_card_intel8x0_init(void)
3082 {
3083         return pci_register_driver(&driver);
3084 }
3085
3086 static void __exit alsa_card_intel8x0_exit(void)
3087 {
3088         pci_unregister_driver(&driver);
3089 }
3090
3091 module_init(alsa_card_intel8x0_init)
3092 module_exit(alsa_card_intel8x0_exit)