ALSA: hda - Drop bus->avoid_link_reset flag
[sfrench/cifs-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66
67
68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
71 static char *model[SNDRV_CARDS];
72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_only[SNDRV_CARDS];
76 static int jackpoll_ms[SNDRV_CARDS];
77 static bool single_cmd;
78 static int enable_msi = -1;
79 #ifdef CONFIG_SND_HDA_PATCH_LOADER
80 static char *patch[SNDRV_CARDS];
81 #endif
82 #ifdef CONFIG_SND_HDA_INPUT_BEEP
83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
84                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
85 #endif
86
87 module_param_array(index, int, NULL, 0444);
88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
89 module_param_array(id, charp, NULL, 0444);
90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
91 module_param_array(enable, bool, NULL, 0444);
92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93 module_param_array(model, charp, NULL, 0444);
94 MODULE_PARM_DESC(model, "Use the given board model.");
95 module_param_array(position_fix, int, NULL, 0444);
96 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
97                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
98 module_param_array(bdl_pos_adj, int, NULL, 0644);
99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
100 module_param_array(probe_mask, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
102 module_param_array(probe_only, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
104 module_param_array(jackpoll_ms, int, NULL, 0444);
105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
106 module_param(single_cmd, bool, 0444);
107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108                  "(for debugging only).");
109 module_param(enable_msi, bint, 0444);
110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
112 module_param_array(patch, charp, NULL, 0444);
113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114 #endif
115 #ifdef CONFIG_SND_HDA_INPUT_BEEP
116 module_param_array(beep_mode, bool, NULL, 0444);
117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
118                             "(0=off, 1=on) (default=1).");
119 #endif
120
121 #ifdef CONFIG_PM
122 static int param_set_xint(const char *val, const struct kernel_param *kp);
123 static struct kernel_param_ops param_ops_xint = {
124         .set = param_set_xint,
125         .get = param_get_int,
126 };
127 #define param_check_xint param_check_int
128
129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
130 module_param(power_save, xint, 0644);
131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132                  "(in second, 0 = disable).");
133
134 /* reset the HD-audio controller in power save mode.
135  * this may give more power-saving, but will take longer time to
136  * wake up.
137  */
138 static bool power_save_controller = 1;
139 module_param(power_save_controller, bool, 0644);
140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
141 #endif /* CONFIG_PM */
142
143 static int align_buffer_size = -1;
144 module_param(align_buffer_size, bint, 0644);
145 MODULE_PARM_DESC(align_buffer_size,
146                 "Force buffer and period sizes to be multiple of 128 bytes.");
147
148 #ifdef CONFIG_X86
149 static bool hda_snoop = true;
150 module_param_named(snoop, hda_snoop, bool, 0444);
151 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152 #define azx_snoop(chip)         (chip)->snoop
153 #else
154 #define hda_snoop               true
155 #define azx_snoop(chip)         true
156 #endif
157
158
159 MODULE_LICENSE("GPL");
160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161                          "{Intel, ICH6M},"
162                          "{Intel, ICH7},"
163                          "{Intel, ESB2},"
164                          "{Intel, ICH8},"
165                          "{Intel, ICH9},"
166                          "{Intel, ICH10},"
167                          "{Intel, PCH},"
168                          "{Intel, CPT},"
169                          "{Intel, PPT},"
170                          "{Intel, LPT},"
171                          "{Intel, LPT_LP},"
172                          "{Intel, WPT_LP},"
173                          "{Intel, HPT},"
174                          "{Intel, PBG},"
175                          "{Intel, SCH},"
176                          "{ATI, SB450},"
177                          "{ATI, SB600},"
178                          "{ATI, RS600},"
179                          "{ATI, RS690},"
180                          "{ATI, RS780},"
181                          "{ATI, R600},"
182                          "{ATI, RV630},"
183                          "{ATI, RV610},"
184                          "{ATI, RV670},"
185                          "{ATI, RV635},"
186                          "{ATI, RV620},"
187                          "{ATI, RV770},"
188                          "{VIA, VT8251},"
189                          "{VIA, VT8237A},"
190                          "{SiS, SIS966},"
191                          "{ULI, M5461}}");
192 MODULE_DESCRIPTION("Intel HDA driver");
193
194 #ifdef CONFIG_SND_VERBOSE_PRINTK
195 #define SFX     /* nop */
196 #else
197 #define SFX     "hda-intel "
198 #endif
199
200 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
201 #ifdef CONFIG_SND_HDA_CODEC_HDMI
202 #define SUPPORT_VGA_SWITCHEROO
203 #endif
204 #endif
205
206
207 /*
208  * registers
209  */
210 #define ICH6_REG_GCAP                   0x00
211 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
212 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
213 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
214 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
215 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
216 #define ICH6_REG_VMIN                   0x02
217 #define ICH6_REG_VMAJ                   0x03
218 #define ICH6_REG_OUTPAY                 0x04
219 #define ICH6_REG_INPAY                  0x06
220 #define ICH6_REG_GCTL                   0x08
221 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
222 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
223 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
224 #define ICH6_REG_WAKEEN                 0x0c
225 #define ICH6_REG_STATESTS               0x0e
226 #define ICH6_REG_GSTS                   0x10
227 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
228 #define ICH6_REG_INTCTL                 0x20
229 #define ICH6_REG_INTSTS                 0x24
230 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
231 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
232 #define ICH6_REG_SSYNC                  0x38
233 #define ICH6_REG_CORBLBASE              0x40
234 #define ICH6_REG_CORBUBASE              0x44
235 #define ICH6_REG_CORBWP                 0x48
236 #define ICH6_REG_CORBRP                 0x4a
237 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
238 #define ICH6_REG_CORBCTL                0x4c
239 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
240 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
241 #define ICH6_REG_CORBSTS                0x4d
242 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
243 #define ICH6_REG_CORBSIZE               0x4e
244
245 #define ICH6_REG_RIRBLBASE              0x50
246 #define ICH6_REG_RIRBUBASE              0x54
247 #define ICH6_REG_RIRBWP                 0x58
248 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
249 #define ICH6_REG_RINTCNT                0x5a
250 #define ICH6_REG_RIRBCTL                0x5c
251 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
252 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
253 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
254 #define ICH6_REG_RIRBSTS                0x5d
255 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
256 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
257 #define ICH6_REG_RIRBSIZE               0x5e
258
259 #define ICH6_REG_IC                     0x60
260 #define ICH6_REG_IR                     0x64
261 #define ICH6_REG_IRS                    0x68
262 #define   ICH6_IRS_VALID        (1<<1)
263 #define   ICH6_IRS_BUSY         (1<<0)
264
265 #define ICH6_REG_DPLBASE                0x70
266 #define ICH6_REG_DPUBASE                0x74
267 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
268
269 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
271
272 /* stream register offsets from stream base */
273 #define ICH6_REG_SD_CTL                 0x00
274 #define ICH6_REG_SD_STS                 0x03
275 #define ICH6_REG_SD_LPIB                0x04
276 #define ICH6_REG_SD_CBL                 0x08
277 #define ICH6_REG_SD_LVI                 0x0c
278 #define ICH6_REG_SD_FIFOW               0x0e
279 #define ICH6_REG_SD_FIFOSIZE            0x10
280 #define ICH6_REG_SD_FORMAT              0x12
281 #define ICH6_REG_SD_BDLPL               0x18
282 #define ICH6_REG_SD_BDLPU               0x1c
283
284 /* PCI space */
285 #define ICH6_PCIREG_TCSEL       0x44
286
287 /*
288  * other constants
289  */
290
291 /* max number of SDs */
292 /* ICH, ATI and VIA have 4 playback and 4 capture */
293 #define ICH6_NUM_CAPTURE        4
294 #define ICH6_NUM_PLAYBACK       4
295
296 /* ULI has 6 playback and 5 capture */
297 #define ULI_NUM_CAPTURE         5
298 #define ULI_NUM_PLAYBACK        6
299
300 /* ATI HDMI has 1 playback and 0 capture */
301 #define ATIHDMI_NUM_CAPTURE     0
302 #define ATIHDMI_NUM_PLAYBACK    1
303
304 /* TERA has 4 playback and 3 capture */
305 #define TERA_NUM_CAPTURE        3
306 #define TERA_NUM_PLAYBACK       4
307
308 /* this number is statically defined for simplicity */
309 #define MAX_AZX_DEV             16
310
311 /* max number of fragments - we may use more if allocating more pages for BDL */
312 #define BDL_SIZE                4096
313 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
314 #define AZX_MAX_FRAG            32
315 /* max buffer size - no h/w limit, you can increase as you like */
316 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
317
318 /* RIRB int mask: overrun[2], response[0] */
319 #define RIRB_INT_RESPONSE       0x01
320 #define RIRB_INT_OVERRUN        0x04
321 #define RIRB_INT_MASK           0x05
322
323 /* STATESTS int mask: S3,SD2,SD1,SD0 */
324 #define AZX_MAX_CODECS          8
325 #define AZX_DEFAULT_CODECS      4
326 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
327
328 /* SD_CTL bits */
329 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
330 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
331 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
332 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
333 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
334 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
335 #define SD_CTL_STREAM_TAG_SHIFT 20
336
337 /* SD_CTL and SD_STS */
338 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
339 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
340 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
341 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342                                  SD_INT_COMPLETE)
343
344 /* SD_STS */
345 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
346
347 /* INTCTL and INTSTS */
348 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
349 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
350 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
351
352 /* below are so far hardcoded - should read registers in future */
353 #define ICH6_MAX_CORB_ENTRIES   256
354 #define ICH6_MAX_RIRB_ENTRIES   256
355
356 /* position fix mode */
357 enum {
358         POS_FIX_AUTO,
359         POS_FIX_LPIB,
360         POS_FIX_POSBUF,
361         POS_FIX_VIACOMBO,
362         POS_FIX_COMBO,
363 };
364
365 /* Defines for ATI HD Audio support in SB450 south bridge */
366 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
367 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
368
369 /* Defines for Nvidia HDA support */
370 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
371 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
372 #define NVIDIA_HDA_ISTRM_COH          0x4d
373 #define NVIDIA_HDA_OSTRM_COH          0x4c
374 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
375
376 /* Defines for Intel SCH HDA snoop control */
377 #define INTEL_SCH_HDA_DEVC      0x78
378 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
379
380 /* Define IN stream 0 FIFO size offset in VIA controller */
381 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382 /* Define VIA HD Audio Device ID*/
383 #define VIA_HDAC_DEVICE_ID              0x3288
384
385 /* HD Audio class code */
386 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
387
388 /*
389  */
390
391 struct azx_dev {
392         struct snd_dma_buffer bdl; /* BDL buffer */
393         u32 *posbuf;            /* position buffer pointer */
394
395         unsigned int bufsize;   /* size of the play buffer in bytes */
396         unsigned int period_bytes; /* size of the period in bytes */
397         unsigned int frags;     /* number for period in the play buffer */
398         unsigned int fifo_size; /* FIFO size */
399         unsigned long start_wallclk;    /* start + minimum wallclk */
400         unsigned long period_wallclk;   /* wallclk for period */
401
402         void __iomem *sd_addr;  /* stream descriptor pointer */
403
404         u32 sd_int_sta_mask;    /* stream int status mask */
405
406         /* pcm support */
407         struct snd_pcm_substream *substream;    /* assigned substream,
408                                                  * set in PCM open
409                                                  */
410         unsigned int format_val;        /* format value to be set in the
411                                          * controller and the codec
412                                          */
413         unsigned char stream_tag;       /* assigned stream */
414         unsigned char index;            /* stream index */
415         int assigned_key;               /* last device# key assigned to */
416
417         unsigned int opened :1;
418         unsigned int running :1;
419         unsigned int irq_pending :1;
420         unsigned int prepared:1;
421         unsigned int locked:1;
422         /*
423          * For VIA:
424          *  A flag to ensure DMA position is 0
425          *  when link position is not greater than FIFO size
426          */
427         unsigned int insufficient :1;
428         unsigned int wc_marked:1;
429         unsigned int no_period_wakeup:1;
430
431         struct timecounter  azx_tc;
432         struct cyclecounter azx_cc;
433
434 #ifdef CONFIG_SND_HDA_DSP_LOADER
435         struct mutex dsp_mutex;
436 #endif
437 };
438
439 /* DSP lock helpers */
440 #ifdef CONFIG_SND_HDA_DSP_LOADER
441 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
442 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
443 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
444 #define dsp_is_locked(dev)      ((dev)->locked)
445 #else
446 #define dsp_lock_init(dev)      do {} while (0)
447 #define dsp_lock(dev)           do {} while (0)
448 #define dsp_unlock(dev)         do {} while (0)
449 #define dsp_is_locked(dev)      0
450 #endif
451
452 /* CORB/RIRB */
453 struct azx_rb {
454         u32 *buf;               /* CORB/RIRB buffer
455                                  * Each CORB entry is 4byte, RIRB is 8byte
456                                  */
457         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
458         /* for RIRB */
459         unsigned short rp, wp;  /* read/write pointers */
460         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
461         u32 res[AZX_MAX_CODECS];        /* last read value */
462 };
463
464 struct azx_pcm {
465         struct azx *chip;
466         struct snd_pcm *pcm;
467         struct hda_codec *codec;
468         struct hda_pcm_stream *hinfo[2];
469         struct list_head list;
470 };
471
472 struct azx {
473         struct snd_card *card;
474         struct pci_dev *pci;
475         int dev_index;
476
477         /* chip type specific */
478         int driver_type;
479         unsigned int driver_caps;
480         int playback_streams;
481         int playback_index_offset;
482         int capture_streams;
483         int capture_index_offset;
484         int num_streams;
485
486         /* pci resources */
487         unsigned long addr;
488         void __iomem *remap_addr;
489         int irq;
490
491         /* locks */
492         spinlock_t reg_lock;
493         struct mutex open_mutex;
494         struct completion probe_wait;
495
496         /* streams (x num_streams) */
497         struct azx_dev *azx_dev;
498
499         /* PCM */
500         struct list_head pcm_list; /* azx_pcm list */
501
502         /* HD codec */
503         unsigned short codec_mask;
504         int  codec_probe_mask; /* copied from probe_mask option */
505         struct hda_bus *bus;
506         unsigned int beep_mode;
507
508         /* CORB/RIRB */
509         struct azx_rb corb;
510         struct azx_rb rirb;
511
512         /* CORB/RIRB and position buffers */
513         struct snd_dma_buffer rb;
514         struct snd_dma_buffer posbuf;
515
516 #ifdef CONFIG_SND_HDA_PATCH_LOADER
517         const struct firmware *fw;
518 #endif
519
520         /* flags */
521         int position_fix[2]; /* for both playback/capture streams */
522         int poll_count;
523         unsigned int running :1;
524         unsigned int initialized :1;
525         unsigned int single_cmd :1;
526         unsigned int polling_mode :1;
527         unsigned int msi :1;
528         unsigned int irq_pending_warned :1;
529         unsigned int probing :1; /* codec probing phase */
530         unsigned int snoop:1;
531         unsigned int align_buffer_size:1;
532         unsigned int region_requested:1;
533
534         /* VGA-switcheroo setup */
535         unsigned int use_vga_switcheroo:1;
536         unsigned int vga_switcheroo_registered:1;
537         unsigned int init_failed:1; /* delayed init failed */
538         unsigned int disabled:1; /* disabled by VGA-switcher */
539
540         /* for debugging */
541         unsigned int last_cmd[AZX_MAX_CODECS];
542
543         /* for pending irqs */
544         struct work_struct irq_pending_work;
545
546 #ifdef CONFIG_SND_HDA_I915
547         struct work_struct probe_work;
548 #endif
549
550         /* reboot notifier (for mysterious hangup problem at power-down) */
551         struct notifier_block reboot_notifier;
552
553         /* card list (for power_save trigger) */
554         struct list_head list;
555
556 #ifdef CONFIG_SND_HDA_DSP_LOADER
557         struct azx_dev saved_azx_dev;
558 #endif
559
560         /* secondary power domain for hdmi audio under vga device */
561         struct dev_pm_domain hdmi_pm_domain;
562 };
563
564 #define CREATE_TRACE_POINTS
565 #include "hda_intel_trace.h"
566
567 /* driver types */
568 enum {
569         AZX_DRIVER_ICH,
570         AZX_DRIVER_PCH,
571         AZX_DRIVER_SCH,
572         AZX_DRIVER_HDMI,
573         AZX_DRIVER_ATI,
574         AZX_DRIVER_ATIHDMI,
575         AZX_DRIVER_ATIHDMI_NS,
576         AZX_DRIVER_VIA,
577         AZX_DRIVER_SIS,
578         AZX_DRIVER_ULI,
579         AZX_DRIVER_NVIDIA,
580         AZX_DRIVER_TERA,
581         AZX_DRIVER_CTX,
582         AZX_DRIVER_CTHDA,
583         AZX_DRIVER_GENERIC,
584         AZX_NUM_DRIVERS, /* keep this as last entry */
585 };
586
587 /* driver quirks (capabilities) */
588 /* bits 0-7 are used for indicating driver type */
589 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
590 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
591 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
592 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
593 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
594 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
595 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
596 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
597 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
598 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
599 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
600 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
601 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
602 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
603 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
604 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
605 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
606 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
607 #define AZX_DCAPS_I915_POWERWELL (1 << 27)      /* HSW i915 power well support */
608
609 /* quirks for Intel PCH */
610 #define AZX_DCAPS_INTEL_PCH_NOPM \
611         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
612          AZX_DCAPS_COUNT_LPIB_DELAY)
613
614 #define AZX_DCAPS_INTEL_PCH \
615         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
616
617 #define AZX_DCAPS_INTEL_HASWELL \
618         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
619          AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
620          AZX_DCAPS_I915_POWERWELL)
621
622 /* quirks for ATI SB / AMD Hudson */
623 #define AZX_DCAPS_PRESET_ATI_SB \
624         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
625          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
626
627 /* quirks for ATI/AMD HDMI */
628 #define AZX_DCAPS_PRESET_ATI_HDMI \
629         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
630
631 /* quirks for Nvidia */
632 #define AZX_DCAPS_PRESET_NVIDIA \
633         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
634          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
635
636 #define AZX_DCAPS_PRESET_CTHDA \
637         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
638
639 /*
640  * VGA-switcher support
641  */
642 #ifdef SUPPORT_VGA_SWITCHEROO
643 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
644 #else
645 #define use_vga_switcheroo(chip)        0
646 #endif
647
648 static char *driver_short_names[] = {
649         [AZX_DRIVER_ICH] = "HDA Intel",
650         [AZX_DRIVER_PCH] = "HDA Intel PCH",
651         [AZX_DRIVER_SCH] = "HDA Intel MID",
652         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
653         [AZX_DRIVER_ATI] = "HDA ATI SB",
654         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
655         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
656         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
657         [AZX_DRIVER_SIS] = "HDA SIS966",
658         [AZX_DRIVER_ULI] = "HDA ULI M5461",
659         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
660         [AZX_DRIVER_TERA] = "HDA Teradici", 
661         [AZX_DRIVER_CTX] = "HDA Creative", 
662         [AZX_DRIVER_CTHDA] = "HDA Creative",
663         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
664 };
665
666 /*
667  * macros for easy use
668  */
669 #define azx_writel(chip,reg,value) \
670         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
671 #define azx_readl(chip,reg) \
672         readl((chip)->remap_addr + ICH6_REG_##reg)
673 #define azx_writew(chip,reg,value) \
674         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
675 #define azx_readw(chip,reg) \
676         readw((chip)->remap_addr + ICH6_REG_##reg)
677 #define azx_writeb(chip,reg,value) \
678         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
679 #define azx_readb(chip,reg) \
680         readb((chip)->remap_addr + ICH6_REG_##reg)
681
682 #define azx_sd_writel(dev,reg,value) \
683         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
684 #define azx_sd_readl(dev,reg) \
685         readl((dev)->sd_addr + ICH6_REG_##reg)
686 #define azx_sd_writew(dev,reg,value) \
687         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
688 #define azx_sd_readw(dev,reg) \
689         readw((dev)->sd_addr + ICH6_REG_##reg)
690 #define azx_sd_writeb(dev,reg,value) \
691         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
692 #define azx_sd_readb(dev,reg) \
693         readb((dev)->sd_addr + ICH6_REG_##reg)
694
695 /* for pcm support */
696 #define get_azx_dev(substream) (substream->runtime->private_data)
697
698 #ifdef CONFIG_X86
699 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
700 {
701         int pages;
702
703         if (azx_snoop(chip))
704                 return;
705         if (!dmab || !dmab->area || !dmab->bytes)
706                 return;
707
708 #ifdef CONFIG_SND_DMA_SGBUF
709         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
710                 struct snd_sg_buf *sgbuf = dmab->private_data;
711                 if (on)
712                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
713                 else
714                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
715                 return;
716         }
717 #endif
718
719         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
720         if (on)
721                 set_memory_wc((unsigned long)dmab->area, pages);
722         else
723                 set_memory_wb((unsigned long)dmab->area, pages);
724 }
725
726 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
727                                  bool on)
728 {
729         __mark_pages_wc(chip, buf, on);
730 }
731 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
732                                    struct snd_pcm_substream *substream, bool on)
733 {
734         if (azx_dev->wc_marked != on) {
735                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
736                 azx_dev->wc_marked = on;
737         }
738 }
739 #else
740 /* NOP for other archs */
741 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
742                                  bool on)
743 {
744 }
745 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
746                                    struct snd_pcm_substream *substream, bool on)
747 {
748 }
749 #endif
750
751 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
752 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
753 /*
754  * Interface for HD codec
755  */
756
757 /*
758  * CORB / RIRB interface
759  */
760 static int azx_alloc_cmd_io(struct azx *chip)
761 {
762         int err;
763
764         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
765         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
766                                   snd_dma_pci_data(chip->pci),
767                                   PAGE_SIZE, &chip->rb);
768         if (err < 0) {
769                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
770                 return err;
771         }
772         mark_pages_wc(chip, &chip->rb, true);
773         return 0;
774 }
775
776 static void azx_init_cmd_io(struct azx *chip)
777 {
778         spin_lock_irq(&chip->reg_lock);
779         /* CORB set up */
780         chip->corb.addr = chip->rb.addr;
781         chip->corb.buf = (u32 *)chip->rb.area;
782         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
783         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
784
785         /* set the corb size to 256 entries (ULI requires explicitly) */
786         azx_writeb(chip, CORBSIZE, 0x02);
787         /* set the corb write pointer to 0 */
788         azx_writew(chip, CORBWP, 0);
789         /* reset the corb hw read pointer */
790         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
791         /* enable corb dma */
792         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
793
794         /* RIRB set up */
795         chip->rirb.addr = chip->rb.addr + 2048;
796         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
797         chip->rirb.wp = chip->rirb.rp = 0;
798         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
799         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
800         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
801
802         /* set the rirb size to 256 entries (ULI requires explicitly) */
803         azx_writeb(chip, RIRBSIZE, 0x02);
804         /* reset the rirb hw write pointer */
805         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
806         /* set N=1, get RIRB response interrupt for new entry */
807         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
808                 azx_writew(chip, RINTCNT, 0xc0);
809         else
810                 azx_writew(chip, RINTCNT, 1);
811         /* enable rirb dma and response irq */
812         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
813         spin_unlock_irq(&chip->reg_lock);
814 }
815
816 static void azx_free_cmd_io(struct azx *chip)
817 {
818         spin_lock_irq(&chip->reg_lock);
819         /* disable ringbuffer DMAs */
820         azx_writeb(chip, RIRBCTL, 0);
821         azx_writeb(chip, CORBCTL, 0);
822         spin_unlock_irq(&chip->reg_lock);
823 }
824
825 static unsigned int azx_command_addr(u32 cmd)
826 {
827         unsigned int addr = cmd >> 28;
828
829         if (addr >= AZX_MAX_CODECS) {
830                 snd_BUG();
831                 addr = 0;
832         }
833
834         return addr;
835 }
836
837 static unsigned int azx_response_addr(u32 res)
838 {
839         unsigned int addr = res & 0xf;
840
841         if (addr >= AZX_MAX_CODECS) {
842                 snd_BUG();
843                 addr = 0;
844         }
845
846         return addr;
847 }
848
849 /* send a command */
850 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
851 {
852         struct azx *chip = bus->private_data;
853         unsigned int addr = azx_command_addr(val);
854         unsigned int wp, rp;
855
856         spin_lock_irq(&chip->reg_lock);
857
858         /* add command to corb */
859         wp = azx_readw(chip, CORBWP);
860         if (wp == 0xffff) {
861                 /* something wrong, controller likely turned to D3 */
862                 spin_unlock_irq(&chip->reg_lock);
863                 return -EIO;
864         }
865         wp++;
866         wp %= ICH6_MAX_CORB_ENTRIES;
867
868         rp = azx_readw(chip, CORBRP);
869         if (wp == rp) {
870                 /* oops, it's full */
871                 spin_unlock_irq(&chip->reg_lock);
872                 return -EAGAIN;
873         }
874
875         chip->rirb.cmds[addr]++;
876         chip->corb.buf[wp] = cpu_to_le32(val);
877         azx_writel(chip, CORBWP, wp);
878
879         spin_unlock_irq(&chip->reg_lock);
880
881         return 0;
882 }
883
884 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
885
886 /* retrieve RIRB entry - called from interrupt handler */
887 static void azx_update_rirb(struct azx *chip)
888 {
889         unsigned int rp, wp;
890         unsigned int addr;
891         u32 res, res_ex;
892
893         wp = azx_readw(chip, RIRBWP);
894         if (wp == 0xffff) {
895                 /* something wrong, controller likely turned to D3 */
896                 return;
897         }
898
899         if (wp == chip->rirb.wp)
900                 return;
901         chip->rirb.wp = wp;
902
903         while (chip->rirb.rp != wp) {
904                 chip->rirb.rp++;
905                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
906
907                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
908                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
909                 res = le32_to_cpu(chip->rirb.buf[rp]);
910                 addr = azx_response_addr(res_ex);
911                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
912                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
913                 else if (chip->rirb.cmds[addr]) {
914                         chip->rirb.res[addr] = res;
915                         smp_wmb();
916                         chip->rirb.cmds[addr]--;
917                 } else if (printk_ratelimit()) {
918                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, last cmd=%#08x\n",
919                                    pci_name(chip->pci),
920                                    res, res_ex,
921                                    chip->last_cmd[addr]);
922                 }
923         }
924 }
925
926 /* receive a response */
927 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
928                                           unsigned int addr)
929 {
930         struct azx *chip = bus->private_data;
931         unsigned long timeout;
932         unsigned long loopcounter;
933         int do_poll = 0;
934
935  again:
936         timeout = jiffies + msecs_to_jiffies(1000);
937
938         for (loopcounter = 0;; loopcounter++) {
939                 if (chip->polling_mode || do_poll) {
940                         spin_lock_irq(&chip->reg_lock);
941                         azx_update_rirb(chip);
942                         spin_unlock_irq(&chip->reg_lock);
943                 }
944                 if (!chip->rirb.cmds[addr]) {
945                         smp_rmb();
946                         bus->rirb_error = 0;
947
948                         if (!do_poll)
949                                 chip->poll_count = 0;
950                         return chip->rirb.res[addr]; /* the last value */
951                 }
952                 if (time_after(jiffies, timeout))
953                         break;
954                 if (bus->needs_damn_long_delay || loopcounter > 3000)
955                         msleep(2); /* temporary workaround */
956                 else {
957                         udelay(10);
958                         cond_resched();
959                 }
960         }
961
962         if (!bus->no_response_fallback)
963                 return -1;
964
965         if (!chip->polling_mode && chip->poll_count < 2) {
966                 snd_printdd(SFX "%s: azx_get_response timeout, "
967                            "polling the codec once: last cmd=0x%08x\n",
968                            pci_name(chip->pci), chip->last_cmd[addr]);
969                 do_poll = 1;
970                 chip->poll_count++;
971                 goto again;
972         }
973
974
975         if (!chip->polling_mode) {
976                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
977                            "switching to polling mode: last cmd=0x%08x\n",
978                            pci_name(chip->pci), chip->last_cmd[addr]);
979                 chip->polling_mode = 1;
980                 goto again;
981         }
982
983         if (chip->msi) {
984                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
985                            "disabling MSI: last cmd=0x%08x\n",
986                            pci_name(chip->pci), chip->last_cmd[addr]);
987                 free_irq(chip->irq, chip);
988                 chip->irq = -1;
989                 pci_disable_msi(chip->pci);
990                 chip->msi = 0;
991                 if (azx_acquire_irq(chip, 1) < 0) {
992                         bus->rirb_error = 1;
993                         return -1;
994                 }
995                 goto again;
996         }
997
998         if (chip->probing) {
999                 /* If this critical timeout happens during the codec probing
1000                  * phase, this is likely an access to a non-existing codec
1001                  * slot.  Better to return an error and reset the system.
1002                  */
1003                 return -1;
1004         }
1005
1006         /* a fatal communication error; need either to reset or to fallback
1007          * to the single_cmd mode
1008          */
1009         bus->rirb_error = 1;
1010         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1011                 bus->response_reset = 1;
1012                 return -1; /* give a chance to retry */
1013         }
1014
1015         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1016                    "switching to single_cmd mode: last cmd=0x%08x\n",
1017                    chip->last_cmd[addr]);
1018         chip->single_cmd = 1;
1019         bus->response_reset = 0;
1020         /* release CORB/RIRB */
1021         azx_free_cmd_io(chip);
1022         /* disable unsolicited responses */
1023         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1024         return -1;
1025 }
1026
1027 /*
1028  * Use the single immediate command instead of CORB/RIRB for simplicity
1029  *
1030  * Note: according to Intel, this is not preferred use.  The command was
1031  *       intended for the BIOS only, and may get confused with unsolicited
1032  *       responses.  So, we shouldn't use it for normal operation from the
1033  *       driver.
1034  *       I left the codes, however, for debugging/testing purposes.
1035  */
1036
1037 /* receive a response */
1038 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1039 {
1040         int timeout = 50;
1041
1042         while (timeout--) {
1043                 /* check IRV busy bit */
1044                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1045                         /* reuse rirb.res as the response return value */
1046                         chip->rirb.res[addr] = azx_readl(chip, IR);
1047                         return 0;
1048                 }
1049                 udelay(1);
1050         }
1051         if (printk_ratelimit())
1052                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1053                            pci_name(chip->pci), azx_readw(chip, IRS));
1054         chip->rirb.res[addr] = -1;
1055         return -EIO;
1056 }
1057
1058 /* send a command */
1059 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1060 {
1061         struct azx *chip = bus->private_data;
1062         unsigned int addr = azx_command_addr(val);
1063         int timeout = 50;
1064
1065         bus->rirb_error = 0;
1066         while (timeout--) {
1067                 /* check ICB busy bit */
1068                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1069                         /* Clear IRV valid bit */
1070                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1071                                    ICH6_IRS_VALID);
1072                         azx_writel(chip, IC, val);
1073                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1074                                    ICH6_IRS_BUSY);
1075                         return azx_single_wait_for_response(chip, addr);
1076                 }
1077                 udelay(1);
1078         }
1079         if (printk_ratelimit())
1080                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1081                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1082         return -EIO;
1083 }
1084
1085 /* receive a response */
1086 static unsigned int azx_single_get_response(struct hda_bus *bus,
1087                                             unsigned int addr)
1088 {
1089         struct azx *chip = bus->private_data;
1090         return chip->rirb.res[addr];
1091 }
1092
1093 /*
1094  * The below are the main callbacks from hda_codec.
1095  *
1096  * They are just the skeleton to call sub-callbacks according to the
1097  * current setting of chip->single_cmd.
1098  */
1099
1100 /* send a command */
1101 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1102 {
1103         struct azx *chip = bus->private_data;
1104
1105         if (chip->disabled)
1106                 return 0;
1107         chip->last_cmd[azx_command_addr(val)] = val;
1108         if (chip->single_cmd)
1109                 return azx_single_send_cmd(bus, val);
1110         else
1111                 return azx_corb_send_cmd(bus, val);
1112 }
1113
1114 /* get a response */
1115 static unsigned int azx_get_response(struct hda_bus *bus,
1116                                      unsigned int addr)
1117 {
1118         struct azx *chip = bus->private_data;
1119         if (chip->disabled)
1120                 return 0;
1121         if (chip->single_cmd)
1122                 return azx_single_get_response(bus, addr);
1123         else
1124                 return azx_rirb_get_response(bus, addr);
1125 }
1126
1127 #ifdef CONFIG_PM
1128 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1129 #endif
1130
1131 #ifdef CONFIG_SND_HDA_DSP_LOADER
1132 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1133                                 unsigned int byte_size,
1134                                 struct snd_dma_buffer *bufp);
1135 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1136 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1137                                  struct snd_dma_buffer *dmab);
1138 #endif
1139
1140 /* enter link reset */
1141 static void azx_enter_link_reset(struct azx *chip)
1142 {
1143         unsigned long timeout;
1144
1145         /* reset controller */
1146         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1147
1148         timeout = jiffies + msecs_to_jiffies(100);
1149         while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1150                         time_before(jiffies, timeout))
1151                 usleep_range(500, 1000);
1152 }
1153
1154 /* exit link reset */
1155 static void azx_exit_link_reset(struct azx *chip)
1156 {
1157         unsigned long timeout;
1158
1159         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1160
1161         timeout = jiffies + msecs_to_jiffies(100);
1162         while (!azx_readb(chip, GCTL) &&
1163                         time_before(jiffies, timeout))
1164                 usleep_range(500, 1000);
1165 }
1166
1167 /* reset codec link */
1168 static int azx_reset(struct azx *chip, int full_reset)
1169 {
1170         if (!full_reset)
1171                 goto __skip;
1172
1173         /* clear STATESTS */
1174         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1175
1176         /* reset controller */
1177         azx_enter_link_reset(chip);
1178
1179         /* delay for >= 100us for codec PLL to settle per spec
1180          * Rev 0.9 section 5.5.1
1181          */
1182         usleep_range(500, 1000);
1183
1184         /* Bring controller out of reset */
1185         azx_exit_link_reset(chip);
1186
1187         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1188         usleep_range(1000, 1200);
1189
1190       __skip:
1191         /* check to see if controller is ready */
1192         if (!azx_readb(chip, GCTL)) {
1193                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1194                 return -EBUSY;
1195         }
1196
1197         /* Accept unsolicited responses */
1198         if (!chip->single_cmd)
1199                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1200                            ICH6_GCTL_UNSOL);
1201
1202         /* detect codecs */
1203         if (!chip->codec_mask) {
1204                 chip->codec_mask = azx_readw(chip, STATESTS);
1205                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1206         }
1207
1208         return 0;
1209 }
1210
1211
1212 /*
1213  * Lowlevel interface
1214  */  
1215
1216 /* enable interrupts */
1217 static void azx_int_enable(struct azx *chip)
1218 {
1219         /* enable controller CIE and GIE */
1220         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1221                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1222 }
1223
1224 /* disable interrupts */
1225 static void azx_int_disable(struct azx *chip)
1226 {
1227         int i;
1228
1229         /* disable interrupts in stream descriptor */
1230         for (i = 0; i < chip->num_streams; i++) {
1231                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1232                 azx_sd_writeb(azx_dev, SD_CTL,
1233                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1234         }
1235
1236         /* disable SIE for all streams */
1237         azx_writeb(chip, INTCTL, 0);
1238
1239         /* disable controller CIE and GIE */
1240         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1241                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1242 }
1243
1244 /* clear interrupts */
1245 static void azx_int_clear(struct azx *chip)
1246 {
1247         int i;
1248
1249         /* clear stream status */
1250         for (i = 0; i < chip->num_streams; i++) {
1251                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1252                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1253         }
1254
1255         /* clear STATESTS */
1256         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1257
1258         /* clear rirb status */
1259         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1260
1261         /* clear int status */
1262         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1263 }
1264
1265 /* start a stream */
1266 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1267 {
1268         /*
1269          * Before stream start, initialize parameter
1270          */
1271         azx_dev->insufficient = 1;
1272
1273         /* enable SIE */
1274         azx_writel(chip, INTCTL,
1275                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1276         /* set DMA start and interrupt mask */
1277         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1278                       SD_CTL_DMA_START | SD_INT_MASK);
1279 }
1280
1281 /* stop DMA */
1282 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1283 {
1284         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1285                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1286         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1287 }
1288
1289 /* stop a stream */
1290 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1291 {
1292         azx_stream_clear(chip, azx_dev);
1293         /* disable SIE */
1294         azx_writel(chip, INTCTL,
1295                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1296 }
1297
1298
1299 /*
1300  * reset and start the controller registers
1301  */
1302 static void azx_init_chip(struct azx *chip, int full_reset)
1303 {
1304         if (chip->initialized)
1305                 return;
1306
1307         /* reset controller */
1308         azx_reset(chip, full_reset);
1309
1310         /* initialize interrupts */
1311         azx_int_clear(chip);
1312         azx_int_enable(chip);
1313
1314         /* initialize the codec command I/O */
1315         if (!chip->single_cmd)
1316                 azx_init_cmd_io(chip);
1317
1318         /* program the position buffer */
1319         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1320         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1321
1322         chip->initialized = 1;
1323 }
1324
1325 /*
1326  * initialize the PCI registers
1327  */
1328 /* update bits in a PCI register byte */
1329 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1330                             unsigned char mask, unsigned char val)
1331 {
1332         unsigned char data;
1333
1334         pci_read_config_byte(pci, reg, &data);
1335         data &= ~mask;
1336         data |= (val & mask);
1337         pci_write_config_byte(pci, reg, data);
1338 }
1339
1340 static void azx_init_pci(struct azx *chip)
1341 {
1342         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1343          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1344          * Ensuring these bits are 0 clears playback static on some HD Audio
1345          * codecs.
1346          * The PCI register TCSEL is defined in the Intel manuals.
1347          */
1348         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1349                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1350                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1351         }
1352
1353         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1354          * we need to enable snoop.
1355          */
1356         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1357                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1358                 update_pci_byte(chip->pci,
1359                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1360                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1361         }
1362
1363         /* For NVIDIA HDA, enable snoop */
1364         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1365                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1366                 update_pci_byte(chip->pci,
1367                                 NVIDIA_HDA_TRANSREG_ADDR,
1368                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1369                 update_pci_byte(chip->pci,
1370                                 NVIDIA_HDA_ISTRM_COH,
1371                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1372                 update_pci_byte(chip->pci,
1373                                 NVIDIA_HDA_OSTRM_COH,
1374                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1375         }
1376
1377         /* Enable SCH/PCH snoop if needed */
1378         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1379                 unsigned short snoop;
1380                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1381                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1382                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1383                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1384                         if (!azx_snoop(chip))
1385                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1386                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1387                         pci_read_config_word(chip->pci,
1388                                 INTEL_SCH_HDA_DEVC, &snoop);
1389                 }
1390                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1391                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1392                                 ? "Disabled" : "Enabled");
1393         }
1394 }
1395
1396
1397 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1398
1399 /*
1400  * interrupt handler
1401  */
1402 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1403 {
1404         struct azx *chip = dev_id;
1405         struct azx_dev *azx_dev;
1406         u32 status;
1407         u8 sd_status;
1408         int i, ok;
1409
1410 #ifdef CONFIG_PM_RUNTIME
1411         if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1412                 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1413                         return IRQ_NONE;
1414 #endif
1415
1416         spin_lock(&chip->reg_lock);
1417
1418         if (chip->disabled) {
1419                 spin_unlock(&chip->reg_lock);
1420                 return IRQ_NONE;
1421         }
1422
1423         status = azx_readl(chip, INTSTS);
1424         if (status == 0 || status == 0xffffffff) {
1425                 spin_unlock(&chip->reg_lock);
1426                 return IRQ_NONE;
1427         }
1428         
1429         for (i = 0; i < chip->num_streams; i++) {
1430                 azx_dev = &chip->azx_dev[i];
1431                 if (status & azx_dev->sd_int_sta_mask) {
1432                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1433                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1434                         if (!azx_dev->substream || !azx_dev->running ||
1435                             !(sd_status & SD_INT_COMPLETE))
1436                                 continue;
1437                         /* check whether this IRQ is really acceptable */
1438                         ok = azx_position_ok(chip, azx_dev);
1439                         if (ok == 1) {
1440                                 azx_dev->irq_pending = 0;
1441                                 spin_unlock(&chip->reg_lock);
1442                                 snd_pcm_period_elapsed(azx_dev->substream);
1443                                 spin_lock(&chip->reg_lock);
1444                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1445                                 /* bogus IRQ, process it later */
1446                                 azx_dev->irq_pending = 1;
1447                                 queue_work(chip->bus->workq,
1448                                            &chip->irq_pending_work);
1449                         }
1450                 }
1451         }
1452
1453         /* clear rirb int */
1454         status = azx_readb(chip, RIRBSTS);
1455         if (status & RIRB_INT_MASK) {
1456                 if (status & RIRB_INT_RESPONSE) {
1457                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1458                                 udelay(80);
1459                         azx_update_rirb(chip);
1460                 }
1461                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1462         }
1463
1464 #if 0
1465         /* clear state status int */
1466         if (azx_readw(chip, STATESTS) & 0x04)
1467                 azx_writew(chip, STATESTS, 0x04);
1468 #endif
1469         spin_unlock(&chip->reg_lock);
1470         
1471         return IRQ_HANDLED;
1472 }
1473
1474
1475 /*
1476  * set up a BDL entry
1477  */
1478 static int setup_bdle(struct azx *chip,
1479                       struct snd_dma_buffer *dmab,
1480                       struct azx_dev *azx_dev, u32 **bdlp,
1481                       int ofs, int size, int with_ioc)
1482 {
1483         u32 *bdl = *bdlp;
1484
1485         while (size > 0) {
1486                 dma_addr_t addr;
1487                 int chunk;
1488
1489                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1490                         return -EINVAL;
1491
1492                 addr = snd_sgbuf_get_addr(dmab, ofs);
1493                 /* program the address field of the BDL entry */
1494                 bdl[0] = cpu_to_le32((u32)addr);
1495                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1496                 /* program the size field of the BDL entry */
1497                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1498                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1499                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1500                         u32 remain = 0x1000 - (ofs & 0xfff);
1501                         if (chunk > remain)
1502                                 chunk = remain;
1503                 }
1504                 bdl[2] = cpu_to_le32(chunk);
1505                 /* program the IOC to enable interrupt
1506                  * only when the whole fragment is processed
1507                  */
1508                 size -= chunk;
1509                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1510                 bdl += 4;
1511                 azx_dev->frags++;
1512                 ofs += chunk;
1513         }
1514         *bdlp = bdl;
1515         return ofs;
1516 }
1517
1518 /*
1519  * set up BDL entries
1520  */
1521 static int azx_setup_periods(struct azx *chip,
1522                              struct snd_pcm_substream *substream,
1523                              struct azx_dev *azx_dev)
1524 {
1525         u32 *bdl;
1526         int i, ofs, periods, period_bytes;
1527         int pos_adj;
1528
1529         /* reset BDL address */
1530         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1531         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1532
1533         period_bytes = azx_dev->period_bytes;
1534         periods = azx_dev->bufsize / period_bytes;
1535
1536         /* program the initial BDL entries */
1537         bdl = (u32 *)azx_dev->bdl.area;
1538         ofs = 0;
1539         azx_dev->frags = 0;
1540         pos_adj = bdl_pos_adj[chip->dev_index];
1541         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1542                 struct snd_pcm_runtime *runtime = substream->runtime;
1543                 int pos_align = pos_adj;
1544                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1545                 if (!pos_adj)
1546                         pos_adj = pos_align;
1547                 else
1548                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1549                                 pos_align;
1550                 pos_adj = frames_to_bytes(runtime, pos_adj);
1551                 if (pos_adj >= period_bytes) {
1552                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1553                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1554                         pos_adj = 0;
1555                 } else {
1556                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1557                                          azx_dev,
1558                                          &bdl, ofs, pos_adj, true);
1559                         if (ofs < 0)
1560                                 goto error;
1561                 }
1562         } else
1563                 pos_adj = 0;
1564         for (i = 0; i < periods; i++) {
1565                 if (i == periods - 1 && pos_adj)
1566                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1567                                          azx_dev, &bdl, ofs,
1568                                          period_bytes - pos_adj, 0);
1569                 else
1570                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1571                                          azx_dev, &bdl, ofs,
1572                                          period_bytes,
1573                                          !azx_dev->no_period_wakeup);
1574                 if (ofs < 0)
1575                         goto error;
1576         }
1577         return 0;
1578
1579  error:
1580         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1581                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1582         return -EINVAL;
1583 }
1584
1585 /* reset stream */
1586 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1587 {
1588         unsigned char val;
1589         int timeout;
1590
1591         azx_stream_clear(chip, azx_dev);
1592
1593         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1594                       SD_CTL_STREAM_RESET);
1595         udelay(3);
1596         timeout = 300;
1597         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1598                --timeout)
1599                 ;
1600         val &= ~SD_CTL_STREAM_RESET;
1601         azx_sd_writeb(azx_dev, SD_CTL, val);
1602         udelay(3);
1603
1604         timeout = 300;
1605         /* waiting for hardware to report that the stream is out of reset */
1606         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1607                --timeout)
1608                 ;
1609
1610         /* reset first position - may not be synced with hw at this time */
1611         *azx_dev->posbuf = 0;
1612 }
1613
1614 /*
1615  * set up the SD for streaming
1616  */
1617 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1618 {
1619         unsigned int val;
1620         /* make sure the run bit is zero for SD */
1621         azx_stream_clear(chip, azx_dev);
1622         /* program the stream_tag */
1623         val = azx_sd_readl(azx_dev, SD_CTL);
1624         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1625                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1626         if (!azx_snoop(chip))
1627                 val |= SD_CTL_TRAFFIC_PRIO;
1628         azx_sd_writel(azx_dev, SD_CTL, val);
1629
1630         /* program the length of samples in cyclic buffer */
1631         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1632
1633         /* program the stream format */
1634         /* this value needs to be the same as the one programmed */
1635         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1636
1637         /* program the stream LVI (last valid index) of the BDL */
1638         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1639
1640         /* program the BDL address */
1641         /* lower BDL address */
1642         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1643         /* upper BDL address */
1644         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1645
1646         /* enable the position buffer */
1647         if (chip->position_fix[0] != POS_FIX_LPIB ||
1648             chip->position_fix[1] != POS_FIX_LPIB) {
1649                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1650                         azx_writel(chip, DPLBASE,
1651                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1652         }
1653
1654         /* set the interrupt enable bits in the descriptor control register */
1655         azx_sd_writel(azx_dev, SD_CTL,
1656                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1657
1658         return 0;
1659 }
1660
1661 /*
1662  * Probe the given codec address
1663  */
1664 static int probe_codec(struct azx *chip, int addr)
1665 {
1666         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1667                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1668         unsigned int res;
1669
1670         mutex_lock(&chip->bus->cmd_mutex);
1671         chip->probing = 1;
1672         azx_send_cmd(chip->bus, cmd);
1673         res = azx_get_response(chip->bus, addr);
1674         chip->probing = 0;
1675         mutex_unlock(&chip->bus->cmd_mutex);
1676         if (res == -1)
1677                 return -EIO;
1678         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1679         return 0;
1680 }
1681
1682 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1683                                  struct hda_pcm *cpcm);
1684 static void azx_stop_chip(struct azx *chip);
1685
1686 static void azx_bus_reset(struct hda_bus *bus)
1687 {
1688         struct azx *chip = bus->private_data;
1689
1690         bus->in_reset = 1;
1691         azx_stop_chip(chip);
1692         azx_init_chip(chip, 1);
1693 #ifdef CONFIG_PM
1694         if (chip->initialized) {
1695                 struct azx_pcm *p;
1696                 list_for_each_entry(p, &chip->pcm_list, list)
1697                         snd_pcm_suspend_all(p->pcm);
1698                 snd_hda_suspend(chip->bus);
1699                 snd_hda_resume(chip->bus);
1700         }
1701 #endif
1702         bus->in_reset = 0;
1703 }
1704
1705 static int get_jackpoll_interval(struct azx *chip)
1706 {
1707         int i = jackpoll_ms[chip->dev_index];
1708         unsigned int j;
1709         if (i == 0)
1710                 return 0;
1711         if (i < 50 || i > 60000)
1712                 j = 0;
1713         else
1714                 j = msecs_to_jiffies(i);
1715         if (j == 0)
1716                 snd_printk(KERN_WARNING SFX
1717                            "jackpoll_ms value out of range: %d\n", i);
1718         return j;
1719 }
1720
1721 /*
1722  * Codec initialization
1723  */
1724
1725 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1726 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1727         [AZX_DRIVER_NVIDIA] = 8,
1728         [AZX_DRIVER_TERA] = 1,
1729 };
1730
1731 static int azx_codec_create(struct azx *chip, const char *model)
1732 {
1733         struct hda_bus_template bus_temp;
1734         int c, codecs, err;
1735         int max_slots;
1736
1737         memset(&bus_temp, 0, sizeof(bus_temp));
1738         bus_temp.private_data = chip;
1739         bus_temp.modelname = model;
1740         bus_temp.pci = chip->pci;
1741         bus_temp.ops.command = azx_send_cmd;
1742         bus_temp.ops.get_response = azx_get_response;
1743         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1744         bus_temp.ops.bus_reset = azx_bus_reset;
1745 #ifdef CONFIG_PM
1746         bus_temp.power_save = &power_save;
1747         bus_temp.ops.pm_notify = azx_power_notify;
1748 #endif
1749 #ifdef CONFIG_SND_HDA_DSP_LOADER
1750         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1751         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1752         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1753 #endif
1754
1755         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1756         if (err < 0)
1757                 return err;
1758
1759         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1760                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1761                 chip->bus->needs_damn_long_delay = 1;
1762         }
1763
1764         codecs = 0;
1765         max_slots = azx_max_codecs[chip->driver_type];
1766         if (!max_slots)
1767                 max_slots = AZX_DEFAULT_CODECS;
1768
1769         /* First try to probe all given codec slots */
1770         for (c = 0; c < max_slots; c++) {
1771                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1772                         if (probe_codec(chip, c) < 0) {
1773                                 /* Some BIOSen give you wrong codec addresses
1774                                  * that don't exist
1775                                  */
1776                                 snd_printk(KERN_WARNING SFX
1777                                            "%s: Codec #%d probe error; "
1778                                            "disabling it...\n", pci_name(chip->pci), c);
1779                                 chip->codec_mask &= ~(1 << c);
1780                                 /* More badly, accessing to a non-existing
1781                                  * codec often screws up the controller chip,
1782                                  * and disturbs the further communications.
1783                                  * Thus if an error occurs during probing,
1784                                  * better to reset the controller chip to
1785                                  * get back to the sanity state.
1786                                  */
1787                                 azx_stop_chip(chip);
1788                                 azx_init_chip(chip, 1);
1789                         }
1790                 }
1791         }
1792
1793         /* AMD chipsets often cause the communication stalls upon certain
1794          * sequence like the pin-detection.  It seems that forcing the synced
1795          * access works around the stall.  Grrr...
1796          */
1797         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1798                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1799                         pci_name(chip->pci));
1800                 chip->bus->sync_write = 1;
1801                 chip->bus->allow_bus_reset = 1;
1802         }
1803
1804         /* Then create codec instances */
1805         for (c = 0; c < max_slots; c++) {
1806                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1807                         struct hda_codec *codec;
1808                         err = snd_hda_codec_new(chip->bus, c, &codec);
1809                         if (err < 0)
1810                                 continue;
1811                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1812                         codec->beep_mode = chip->beep_mode;
1813                         codecs++;
1814                 }
1815         }
1816         if (!codecs) {
1817                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1818                 return -ENXIO;
1819         }
1820         return 0;
1821 }
1822
1823 /* configure each codec instance */
1824 static int azx_codec_configure(struct azx *chip)
1825 {
1826         struct hda_codec *codec;
1827         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1828                 snd_hda_codec_configure(codec);
1829         }
1830         return 0;
1831 }
1832
1833
1834 /*
1835  * PCM support
1836  */
1837
1838 /* assign a stream for the PCM */
1839 static inline struct azx_dev *
1840 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1841 {
1842         int dev, i, nums;
1843         struct azx_dev *res = NULL;
1844         /* make a non-zero unique key for the substream */
1845         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1846                 (substream->stream + 1);
1847
1848         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1849                 dev = chip->playback_index_offset;
1850                 nums = chip->playback_streams;
1851         } else {
1852                 dev = chip->capture_index_offset;
1853                 nums = chip->capture_streams;
1854         }
1855         for (i = 0; i < nums; i++, dev++) {
1856                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1857                 dsp_lock(azx_dev);
1858                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1859                         res = azx_dev;
1860                         if (res->assigned_key == key) {
1861                                 res->opened = 1;
1862                                 res->assigned_key = key;
1863                                 dsp_unlock(azx_dev);
1864                                 return azx_dev;
1865                         }
1866                 }
1867                 dsp_unlock(azx_dev);
1868         }
1869         if (res) {
1870                 dsp_lock(res);
1871                 res->opened = 1;
1872                 res->assigned_key = key;
1873                 dsp_unlock(res);
1874         }
1875         return res;
1876 }
1877
1878 /* release the assigned stream */
1879 static inline void azx_release_device(struct azx_dev *azx_dev)
1880 {
1881         azx_dev->opened = 0;
1882 }
1883
1884 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1885 {
1886         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1887         struct snd_pcm_substream *substream = azx_dev->substream;
1888         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1889         struct azx *chip = apcm->chip;
1890
1891         return azx_readl(chip, WALLCLK);
1892 }
1893
1894 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1895                                 bool force, cycle_t last)
1896 {
1897         struct azx_dev *azx_dev = get_azx_dev(substream);
1898         struct timecounter *tc = &azx_dev->azx_tc;
1899         struct cyclecounter *cc = &azx_dev->azx_cc;
1900         u64 nsec;
1901
1902         cc->read = azx_cc_read;
1903         cc->mask = CLOCKSOURCE_MASK(32);
1904
1905         /*
1906          * Converting from 24 MHz to ns means applying a 125/3 factor.
1907          * To avoid any saturation issues in intermediate operations,
1908          * the 125 factor is applied first. The division is applied
1909          * last after reading the timecounter value.
1910          * Applying the 1/3 factor as part of the multiplication
1911          * requires at least 20 bits for a decent precision, however
1912          * overflows occur after about 4 hours or less, not a option.
1913          */
1914
1915         cc->mult = 125; /* saturation after 195 years */
1916         cc->shift = 0;
1917
1918         nsec = 0; /* audio time is elapsed time since trigger */
1919         timecounter_init(tc, cc, nsec);
1920         if (force)
1921                 /*
1922                  * force timecounter to use predefined value,
1923                  * used for synchronized starts
1924                  */
1925                 tc->cycle_last = last;
1926 }
1927
1928 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1929                                 u64 nsec)
1930 {
1931         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1932         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1933         u64 codec_frames, codec_nsecs;
1934
1935         if (!hinfo->ops.get_delay)
1936                 return nsec;
1937
1938         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1939         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1940                               substream->runtime->rate);
1941
1942         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1943                 return nsec + codec_nsecs;
1944
1945         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1946 }
1947
1948 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1949                                 struct timespec *ts)
1950 {
1951         struct azx_dev *azx_dev = get_azx_dev(substream);
1952         u64 nsec;
1953
1954         nsec = timecounter_read(&azx_dev->azx_tc);
1955         nsec = div_u64(nsec, 3); /* can be optimized */
1956         nsec = azx_adjust_codec_delay(substream, nsec);
1957
1958         *ts = ns_to_timespec(nsec);
1959
1960         return 0;
1961 }
1962
1963 static struct snd_pcm_hardware azx_pcm_hw = {
1964         .info =                 (SNDRV_PCM_INFO_MMAP |
1965                                  SNDRV_PCM_INFO_INTERLEAVED |
1966                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1967                                  SNDRV_PCM_INFO_MMAP_VALID |
1968                                  /* No full-resume yet implemented */
1969                                  /* SNDRV_PCM_INFO_RESUME |*/
1970                                  SNDRV_PCM_INFO_PAUSE |
1971                                  SNDRV_PCM_INFO_SYNC_START |
1972                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1973                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1974         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1975         .rates =                SNDRV_PCM_RATE_48000,
1976         .rate_min =             48000,
1977         .rate_max =             48000,
1978         .channels_min =         2,
1979         .channels_max =         2,
1980         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1981         .period_bytes_min =     128,
1982         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1983         .periods_min =          2,
1984         .periods_max =          AZX_MAX_FRAG,
1985         .fifo_size =            0,
1986 };
1987
1988 static int azx_pcm_open(struct snd_pcm_substream *substream)
1989 {
1990         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1991         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1992         struct azx *chip = apcm->chip;
1993         struct azx_dev *azx_dev;
1994         struct snd_pcm_runtime *runtime = substream->runtime;
1995         unsigned long flags;
1996         int err;
1997         int buff_step;
1998
1999         mutex_lock(&chip->open_mutex);
2000         azx_dev = azx_assign_device(chip, substream);
2001         if (azx_dev == NULL) {
2002                 mutex_unlock(&chip->open_mutex);
2003                 return -EBUSY;
2004         }
2005         runtime->hw = azx_pcm_hw;
2006         runtime->hw.channels_min = hinfo->channels_min;
2007         runtime->hw.channels_max = hinfo->channels_max;
2008         runtime->hw.formats = hinfo->formats;
2009         runtime->hw.rates = hinfo->rates;
2010         snd_pcm_limit_hw_rates(runtime);
2011         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2012
2013         /* avoid wrap-around with wall-clock */
2014         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2015                                 20,
2016                                 178000000);
2017
2018         if (chip->align_buffer_size)
2019                 /* constrain buffer sizes to be multiple of 128
2020                    bytes. This is more efficient in terms of memory
2021                    access but isn't required by the HDA spec and
2022                    prevents users from specifying exact period/buffer
2023                    sizes. For example for 44.1kHz, a period size set
2024                    to 20ms will be rounded to 19.59ms. */
2025                 buff_step = 128;
2026         else
2027                 /* Don't enforce steps on buffer sizes, still need to
2028                    be multiple of 4 bytes (HDA spec). Tested on Intel
2029                    HDA controllers, may not work on all devices where
2030                    option needs to be disabled */
2031                 buff_step = 4;
2032
2033         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2034                                    buff_step);
2035         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2036                                    buff_step);
2037         snd_hda_power_up_d3wait(apcm->codec);
2038         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2039         if (err < 0) {
2040                 azx_release_device(azx_dev);
2041                 snd_hda_power_down(apcm->codec);
2042                 mutex_unlock(&chip->open_mutex);
2043                 return err;
2044         }
2045         snd_pcm_limit_hw_rates(runtime);
2046         /* sanity check */
2047         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2048             snd_BUG_ON(!runtime->hw.channels_max) ||
2049             snd_BUG_ON(!runtime->hw.formats) ||
2050             snd_BUG_ON(!runtime->hw.rates)) {
2051                 azx_release_device(azx_dev);
2052                 hinfo->ops.close(hinfo, apcm->codec, substream);
2053                 snd_hda_power_down(apcm->codec);
2054                 mutex_unlock(&chip->open_mutex);
2055                 return -EINVAL;
2056         }
2057
2058         /* disable WALLCLOCK timestamps for capture streams
2059            until we figure out how to handle digital inputs */
2060         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2061                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2062
2063         spin_lock_irqsave(&chip->reg_lock, flags);
2064         azx_dev->substream = substream;
2065         azx_dev->running = 0;
2066         spin_unlock_irqrestore(&chip->reg_lock, flags);
2067
2068         runtime->private_data = azx_dev;
2069         snd_pcm_set_sync(substream);
2070         mutex_unlock(&chip->open_mutex);
2071         return 0;
2072 }
2073
2074 static int azx_pcm_close(struct snd_pcm_substream *substream)
2075 {
2076         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2077         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2078         struct azx *chip = apcm->chip;
2079         struct azx_dev *azx_dev = get_azx_dev(substream);
2080         unsigned long flags;
2081
2082         mutex_lock(&chip->open_mutex);
2083         spin_lock_irqsave(&chip->reg_lock, flags);
2084         azx_dev->substream = NULL;
2085         azx_dev->running = 0;
2086         spin_unlock_irqrestore(&chip->reg_lock, flags);
2087         azx_release_device(azx_dev);
2088         hinfo->ops.close(hinfo, apcm->codec, substream);
2089         snd_hda_power_down(apcm->codec);
2090         mutex_unlock(&chip->open_mutex);
2091         return 0;
2092 }
2093
2094 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2095                              struct snd_pcm_hw_params *hw_params)
2096 {
2097         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2098         struct azx *chip = apcm->chip;
2099         struct azx_dev *azx_dev = get_azx_dev(substream);
2100         int ret;
2101
2102         dsp_lock(azx_dev);
2103         if (dsp_is_locked(azx_dev)) {
2104                 ret = -EBUSY;
2105                 goto unlock;
2106         }
2107
2108         mark_runtime_wc(chip, azx_dev, substream, false);
2109         azx_dev->bufsize = 0;
2110         azx_dev->period_bytes = 0;
2111         azx_dev->format_val = 0;
2112         ret = snd_pcm_lib_malloc_pages(substream,
2113                                         params_buffer_bytes(hw_params));
2114         if (ret < 0)
2115                 goto unlock;
2116         mark_runtime_wc(chip, azx_dev, substream, true);
2117  unlock:
2118         dsp_unlock(azx_dev);
2119         return ret;
2120 }
2121
2122 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2123 {
2124         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2125         struct azx_dev *azx_dev = get_azx_dev(substream);
2126         struct azx *chip = apcm->chip;
2127         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2128
2129         /* reset BDL address */
2130         dsp_lock(azx_dev);
2131         if (!dsp_is_locked(azx_dev)) {
2132                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2133                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2134                 azx_sd_writel(azx_dev, SD_CTL, 0);
2135                 azx_dev->bufsize = 0;
2136                 azx_dev->period_bytes = 0;
2137                 azx_dev->format_val = 0;
2138         }
2139
2140         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2141
2142         mark_runtime_wc(chip, azx_dev, substream, false);
2143         azx_dev->prepared = 0;
2144         dsp_unlock(azx_dev);
2145         return snd_pcm_lib_free_pages(substream);
2146 }
2147
2148 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2149 {
2150         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2151         struct azx *chip = apcm->chip;
2152         struct azx_dev *azx_dev = get_azx_dev(substream);
2153         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2154         struct snd_pcm_runtime *runtime = substream->runtime;
2155         unsigned int bufsize, period_bytes, format_val, stream_tag;
2156         int err;
2157         struct hda_spdif_out *spdif =
2158                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2159         unsigned short ctls = spdif ? spdif->ctls : 0;
2160
2161         dsp_lock(azx_dev);
2162         if (dsp_is_locked(azx_dev)) {
2163                 err = -EBUSY;
2164                 goto unlock;
2165         }
2166
2167         azx_stream_reset(chip, azx_dev);
2168         format_val = snd_hda_calc_stream_format(runtime->rate,
2169                                                 runtime->channels,
2170                                                 runtime->format,
2171                                                 hinfo->maxbps,
2172                                                 ctls);
2173         if (!format_val) {
2174                 snd_printk(KERN_ERR SFX
2175                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2176                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2177                 err = -EINVAL;
2178                 goto unlock;
2179         }
2180
2181         bufsize = snd_pcm_lib_buffer_bytes(substream);
2182         period_bytes = snd_pcm_lib_period_bytes(substream);
2183
2184         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2185                     pci_name(chip->pci), bufsize, format_val);
2186
2187         if (bufsize != azx_dev->bufsize ||
2188             period_bytes != azx_dev->period_bytes ||
2189             format_val != azx_dev->format_val ||
2190             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2191                 azx_dev->bufsize = bufsize;
2192                 azx_dev->period_bytes = period_bytes;
2193                 azx_dev->format_val = format_val;
2194                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2195                 err = azx_setup_periods(chip, substream, azx_dev);
2196                 if (err < 0)
2197                         goto unlock;
2198         }
2199
2200         /* wallclk has 24Mhz clock source */
2201         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2202                                                 runtime->rate) * 1000);
2203         azx_setup_controller(chip, azx_dev);
2204         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2205                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2206         else
2207                 azx_dev->fifo_size = 0;
2208
2209         stream_tag = azx_dev->stream_tag;
2210         /* CA-IBG chips need the playback stream starting from 1 */
2211         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2212             stream_tag > chip->capture_streams)
2213                 stream_tag -= chip->capture_streams;
2214         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2215                                      azx_dev->format_val, substream);
2216
2217  unlock:
2218         if (!err)
2219                 azx_dev->prepared = 1;
2220         dsp_unlock(azx_dev);
2221         return err;
2222 }
2223
2224 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2225 {
2226         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2227         struct azx *chip = apcm->chip;
2228         struct azx_dev *azx_dev;
2229         struct snd_pcm_substream *s;
2230         int rstart = 0, start, nsync = 0, sbits = 0;
2231         int nwait, timeout;
2232
2233         azx_dev = get_azx_dev(substream);
2234         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2235
2236         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2237                 return -EPIPE;
2238
2239         switch (cmd) {
2240         case SNDRV_PCM_TRIGGER_START:
2241                 rstart = 1;
2242         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2243         case SNDRV_PCM_TRIGGER_RESUME:
2244                 start = 1;
2245                 break;
2246         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2247         case SNDRV_PCM_TRIGGER_SUSPEND:
2248         case SNDRV_PCM_TRIGGER_STOP:
2249                 start = 0;
2250                 break;
2251         default:
2252                 return -EINVAL;
2253         }
2254
2255         snd_pcm_group_for_each_entry(s, substream) {
2256                 if (s->pcm->card != substream->pcm->card)
2257                         continue;
2258                 azx_dev = get_azx_dev(s);
2259                 sbits |= 1 << azx_dev->index;
2260                 nsync++;
2261                 snd_pcm_trigger_done(s, substream);
2262         }
2263
2264         spin_lock(&chip->reg_lock);
2265
2266         /* first, set SYNC bits of corresponding streams */
2267         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2268                 azx_writel(chip, OLD_SSYNC,
2269                         azx_readl(chip, OLD_SSYNC) | sbits);
2270         else
2271                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2272
2273         snd_pcm_group_for_each_entry(s, substream) {
2274                 if (s->pcm->card != substream->pcm->card)
2275                         continue;
2276                 azx_dev = get_azx_dev(s);
2277                 if (start) {
2278                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2279                         if (!rstart)
2280                                 azx_dev->start_wallclk -=
2281                                                 azx_dev->period_wallclk;
2282                         azx_stream_start(chip, azx_dev);
2283                 } else {
2284                         azx_stream_stop(chip, azx_dev);
2285                 }
2286                 azx_dev->running = start;
2287         }
2288         spin_unlock(&chip->reg_lock);
2289         if (start) {
2290                 /* wait until all FIFOs get ready */
2291                 for (timeout = 5000; timeout; timeout--) {
2292                         nwait = 0;
2293                         snd_pcm_group_for_each_entry(s, substream) {
2294                                 if (s->pcm->card != substream->pcm->card)
2295                                         continue;
2296                                 azx_dev = get_azx_dev(s);
2297                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2298                                       SD_STS_FIFO_READY))
2299                                         nwait++;
2300                         }
2301                         if (!nwait)
2302                                 break;
2303                         cpu_relax();
2304                 }
2305         } else {
2306                 /* wait until all RUN bits are cleared */
2307                 for (timeout = 5000; timeout; timeout--) {
2308                         nwait = 0;
2309                         snd_pcm_group_for_each_entry(s, substream) {
2310                                 if (s->pcm->card != substream->pcm->card)
2311                                         continue;
2312                                 azx_dev = get_azx_dev(s);
2313                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2314                                     SD_CTL_DMA_START)
2315                                         nwait++;
2316                         }
2317                         if (!nwait)
2318                                 break;
2319                         cpu_relax();
2320                 }
2321         }
2322         spin_lock(&chip->reg_lock);
2323         /* reset SYNC bits */
2324         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2325                 azx_writel(chip, OLD_SSYNC,
2326                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2327         else
2328                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2329         if (start) {
2330                 azx_timecounter_init(substream, 0, 0);
2331                 if (nsync > 1) {
2332                         cycle_t cycle_last;
2333
2334                         /* same start cycle for master and group */
2335                         azx_dev = get_azx_dev(substream);
2336                         cycle_last = azx_dev->azx_tc.cycle_last;
2337
2338                         snd_pcm_group_for_each_entry(s, substream) {
2339                                 if (s->pcm->card != substream->pcm->card)
2340                                         continue;
2341                                 azx_timecounter_init(s, 1, cycle_last);
2342                         }
2343                 }
2344         }
2345         spin_unlock(&chip->reg_lock);
2346         return 0;
2347 }
2348
2349 /* get the current DMA position with correction on VIA chips */
2350 static unsigned int azx_via_get_position(struct azx *chip,
2351                                          struct azx_dev *azx_dev)
2352 {
2353         unsigned int link_pos, mini_pos, bound_pos;
2354         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2355         unsigned int fifo_size;
2356
2357         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2358         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2359                 /* Playback, no problem using link position */
2360                 return link_pos;
2361         }
2362
2363         /* Capture */
2364         /* For new chipset,
2365          * use mod to get the DMA position just like old chipset
2366          */
2367         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2368         mod_dma_pos %= azx_dev->period_bytes;
2369
2370         /* azx_dev->fifo_size can't get FIFO size of in stream.
2371          * Get from base address + offset.
2372          */
2373         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2374
2375         if (azx_dev->insufficient) {
2376                 /* Link position never gather than FIFO size */
2377                 if (link_pos <= fifo_size)
2378                         return 0;
2379
2380                 azx_dev->insufficient = 0;
2381         }
2382
2383         if (link_pos <= fifo_size)
2384                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2385         else
2386                 mini_pos = link_pos - fifo_size;
2387
2388         /* Find nearest previous boudary */
2389         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2390         mod_link_pos = link_pos % azx_dev->period_bytes;
2391         if (mod_link_pos >= fifo_size)
2392                 bound_pos = link_pos - mod_link_pos;
2393         else if (mod_dma_pos >= mod_mini_pos)
2394                 bound_pos = mini_pos - mod_mini_pos;
2395         else {
2396                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2397                 if (bound_pos >= azx_dev->bufsize)
2398                         bound_pos = 0;
2399         }
2400
2401         /* Calculate real DMA position we want */
2402         return bound_pos + mod_dma_pos;
2403 }
2404
2405 static unsigned int azx_get_position(struct azx *chip,
2406                                      struct azx_dev *azx_dev,
2407                                      bool with_check)
2408 {
2409         struct snd_pcm_substream *substream = azx_dev->substream;
2410         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2411         unsigned int pos;
2412         int stream = substream->stream;
2413         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2414         int delay = 0;
2415
2416         switch (chip->position_fix[stream]) {
2417         case POS_FIX_LPIB:
2418                 /* read LPIB */
2419                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2420                 break;
2421         case POS_FIX_VIACOMBO:
2422                 pos = azx_via_get_position(chip, azx_dev);
2423                 break;
2424         default:
2425                 /* use the position buffer */
2426                 pos = le32_to_cpu(*azx_dev->posbuf);
2427                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2428                         if (!pos || pos == (u32)-1) {
2429                                 printk(KERN_WARNING
2430                                        "hda-intel: Invalid position buffer, "
2431                                        "using LPIB read method instead.\n");
2432                                 chip->position_fix[stream] = POS_FIX_LPIB;
2433                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2434                         } else
2435                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2436                 }
2437                 break;
2438         }
2439
2440         if (pos >= azx_dev->bufsize)
2441                 pos = 0;
2442
2443         /* calculate runtime delay from LPIB */
2444         if (substream->runtime &&
2445             chip->position_fix[stream] == POS_FIX_POSBUF &&
2446             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2447                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2448                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2449                         delay = pos - lpib_pos;
2450                 else
2451                         delay = lpib_pos - pos;
2452                 if (delay < 0)
2453                         delay += azx_dev->bufsize;
2454                 if (delay >= azx_dev->period_bytes) {
2455                         snd_printk(KERN_WARNING SFX
2456                                    "%s: Unstable LPIB (%d >= %d); "
2457                                    "disabling LPIB delay counting\n",
2458                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2459                         delay = 0;
2460                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2461                 }
2462                 delay = bytes_to_frames(substream->runtime, delay);
2463         }
2464
2465         if (substream->runtime) {
2466                 if (hinfo->ops.get_delay)
2467                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2468                                                       substream);
2469                 substream->runtime->delay = delay;
2470         }
2471
2472         trace_azx_get_position(chip, azx_dev, pos, delay);
2473         return pos;
2474 }
2475
2476 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2477 {
2478         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2479         struct azx *chip = apcm->chip;
2480         struct azx_dev *azx_dev = get_azx_dev(substream);
2481         return bytes_to_frames(substream->runtime,
2482                                azx_get_position(chip, azx_dev, false));
2483 }
2484
2485 /*
2486  * Check whether the current DMA position is acceptable for updating
2487  * periods.  Returns non-zero if it's OK.
2488  *
2489  * Many HD-audio controllers appear pretty inaccurate about
2490  * the update-IRQ timing.  The IRQ is issued before actually the
2491  * data is processed.  So, we need to process it afterwords in a
2492  * workqueue.
2493  */
2494 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2495 {
2496         u32 wallclk;
2497         unsigned int pos;
2498
2499         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2500         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2501                 return -1;      /* bogus (too early) interrupt */
2502
2503         pos = azx_get_position(chip, azx_dev, true);
2504
2505         if (WARN_ONCE(!azx_dev->period_bytes,
2506                       "hda-intel: zero azx_dev->period_bytes"))
2507                 return -1; /* this shouldn't happen! */
2508         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2509             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2510                 /* NG - it's below the first next period boundary */
2511                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2512         azx_dev->start_wallclk += wallclk;
2513         return 1; /* OK, it's fine */
2514 }
2515
2516 /*
2517  * The work for pending PCM period updates.
2518  */
2519 static void azx_irq_pending_work(struct work_struct *work)
2520 {
2521         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2522         int i, pending, ok;
2523
2524         if (!chip->irq_pending_warned) {
2525                 printk(KERN_WARNING
2526                        "hda-intel: IRQ timing workaround is activated "
2527                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2528                        chip->card->number);
2529                 chip->irq_pending_warned = 1;
2530         }
2531
2532         for (;;) {
2533                 pending = 0;
2534                 spin_lock_irq(&chip->reg_lock);
2535                 for (i = 0; i < chip->num_streams; i++) {
2536                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2537                         if (!azx_dev->irq_pending ||
2538                             !azx_dev->substream ||
2539                             !azx_dev->running)
2540                                 continue;
2541                         ok = azx_position_ok(chip, azx_dev);
2542                         if (ok > 0) {
2543                                 azx_dev->irq_pending = 0;
2544                                 spin_unlock(&chip->reg_lock);
2545                                 snd_pcm_period_elapsed(azx_dev->substream);
2546                                 spin_lock(&chip->reg_lock);
2547                         } else if (ok < 0) {
2548                                 pending = 0;    /* too early */
2549                         } else
2550                                 pending++;
2551                 }
2552                 spin_unlock_irq(&chip->reg_lock);
2553                 if (!pending)
2554                         return;
2555                 msleep(1);
2556         }
2557 }
2558
2559 /* clear irq_pending flags and assure no on-going workq */
2560 static void azx_clear_irq_pending(struct azx *chip)
2561 {
2562         int i;
2563
2564         spin_lock_irq(&chip->reg_lock);
2565         for (i = 0; i < chip->num_streams; i++)
2566                 chip->azx_dev[i].irq_pending = 0;
2567         spin_unlock_irq(&chip->reg_lock);
2568 }
2569
2570 #ifdef CONFIG_X86
2571 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2572                         struct vm_area_struct *area)
2573 {
2574         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2575         struct azx *chip = apcm->chip;
2576         if (!azx_snoop(chip))
2577                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2578         return snd_pcm_lib_default_mmap(substream, area);
2579 }
2580 #else
2581 #define azx_pcm_mmap    NULL
2582 #endif
2583
2584 static struct snd_pcm_ops azx_pcm_ops = {
2585         .open = azx_pcm_open,
2586         .close = azx_pcm_close,
2587         .ioctl = snd_pcm_lib_ioctl,
2588         .hw_params = azx_pcm_hw_params,
2589         .hw_free = azx_pcm_hw_free,
2590         .prepare = azx_pcm_prepare,
2591         .trigger = azx_pcm_trigger,
2592         .pointer = azx_pcm_pointer,
2593         .wall_clock =  azx_get_wallclock_tstamp,
2594         .mmap = azx_pcm_mmap,
2595         .page = snd_pcm_sgbuf_ops_page,
2596 };
2597
2598 static void azx_pcm_free(struct snd_pcm *pcm)
2599 {
2600         struct azx_pcm *apcm = pcm->private_data;
2601         if (apcm) {
2602                 list_del(&apcm->list);
2603                 kfree(apcm);
2604         }
2605 }
2606
2607 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2608
2609 static int
2610 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2611                       struct hda_pcm *cpcm)
2612 {
2613         struct azx *chip = bus->private_data;
2614         struct snd_pcm *pcm;
2615         struct azx_pcm *apcm;
2616         int pcm_dev = cpcm->device;
2617         unsigned int size;
2618         int s, err;
2619
2620         list_for_each_entry(apcm, &chip->pcm_list, list) {
2621                 if (apcm->pcm->device == pcm_dev) {
2622                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2623                                    pci_name(chip->pci), pcm_dev);
2624                         return -EBUSY;
2625                 }
2626         }
2627         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2628                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2629                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2630                           &pcm);
2631         if (err < 0)
2632                 return err;
2633         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2634         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2635         if (apcm == NULL)
2636                 return -ENOMEM;
2637         apcm->chip = chip;
2638         apcm->pcm = pcm;
2639         apcm->codec = codec;
2640         pcm->private_data = apcm;
2641         pcm->private_free = azx_pcm_free;
2642         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2643                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2644         list_add_tail(&apcm->list, &chip->pcm_list);
2645         cpcm->pcm = pcm;
2646         for (s = 0; s < 2; s++) {
2647                 apcm->hinfo[s] = &cpcm->stream[s];
2648                 if (cpcm->stream[s].substreams)
2649                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2650         }
2651         /* buffer pre-allocation */
2652         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2653         if (size > MAX_PREALLOC_SIZE)
2654                 size = MAX_PREALLOC_SIZE;
2655         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2656                                               snd_dma_pci_data(chip->pci),
2657                                               size, MAX_PREALLOC_SIZE);
2658         return 0;
2659 }
2660
2661 /*
2662  * mixer creation - all stuff is implemented in hda module
2663  */
2664 static int azx_mixer_create(struct azx *chip)
2665 {
2666         return snd_hda_build_controls(chip->bus);
2667 }
2668
2669
2670 /*
2671  * initialize SD streams
2672  */
2673 static int azx_init_stream(struct azx *chip)
2674 {
2675         int i;
2676
2677         /* initialize each stream (aka device)
2678          * assign the starting bdl address to each stream (device)
2679          * and initialize
2680          */
2681         for (i = 0; i < chip->num_streams; i++) {
2682                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2683                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2684                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2685                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2686                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2687                 azx_dev->sd_int_sta_mask = 1 << i;
2688                 /* stream tag: must be non-zero and unique */
2689                 azx_dev->index = i;
2690                 azx_dev->stream_tag = i + 1;
2691         }
2692
2693         return 0;
2694 }
2695
2696 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2697 {
2698         if (request_irq(chip->pci->irq, azx_interrupt,
2699                         chip->msi ? 0 : IRQF_SHARED,
2700                         KBUILD_MODNAME, chip)) {
2701                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2702                        "disabling device\n", chip->pci->irq);
2703                 if (do_disconnect)
2704                         snd_card_disconnect(chip->card);
2705                 return -1;
2706         }
2707         chip->irq = chip->pci->irq;
2708         pci_intx(chip->pci, !chip->msi);
2709         return 0;
2710 }
2711
2712
2713 static void azx_stop_chip(struct azx *chip)
2714 {
2715         if (!chip->initialized)
2716                 return;
2717
2718         /* disable interrupts */
2719         azx_int_disable(chip);
2720         azx_int_clear(chip);
2721
2722         /* disable CORB/RIRB */
2723         azx_free_cmd_io(chip);
2724
2725         /* disable position buffer */
2726         azx_writel(chip, DPLBASE, 0);
2727         azx_writel(chip, DPUBASE, 0);
2728
2729         chip->initialized = 0;
2730 }
2731
2732 #ifdef CONFIG_SND_HDA_DSP_LOADER
2733 /*
2734  * DSP loading code (e.g. for CA0132)
2735  */
2736
2737 /* use the first stream for loading DSP */
2738 static struct azx_dev *
2739 azx_get_dsp_loader_dev(struct azx *chip)
2740 {
2741         return &chip->azx_dev[chip->playback_index_offset];
2742 }
2743
2744 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2745                                 unsigned int byte_size,
2746                                 struct snd_dma_buffer *bufp)
2747 {
2748         u32 *bdl;
2749         struct azx *chip = bus->private_data;
2750         struct azx_dev *azx_dev;
2751         int err;
2752
2753         azx_dev = azx_get_dsp_loader_dev(chip);
2754
2755         dsp_lock(azx_dev);
2756         spin_lock_irq(&chip->reg_lock);
2757         if (azx_dev->running || azx_dev->locked) {
2758                 spin_unlock_irq(&chip->reg_lock);
2759                 err = -EBUSY;
2760                 goto unlock;
2761         }
2762         azx_dev->prepared = 0;
2763         chip->saved_azx_dev = *azx_dev;
2764         azx_dev->locked = 1;
2765         spin_unlock_irq(&chip->reg_lock);
2766
2767         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2768                                   snd_dma_pci_data(chip->pci),
2769                                   byte_size, bufp);
2770         if (err < 0)
2771                 goto err_alloc;
2772
2773         mark_pages_wc(chip, bufp, true);
2774         azx_dev->bufsize = byte_size;
2775         azx_dev->period_bytes = byte_size;
2776         azx_dev->format_val = format;
2777
2778         azx_stream_reset(chip, azx_dev);
2779
2780         /* reset BDL address */
2781         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2782         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2783
2784         azx_dev->frags = 0;
2785         bdl = (u32 *)azx_dev->bdl.area;
2786         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2787         if (err < 0)
2788                 goto error;
2789
2790         azx_setup_controller(chip, azx_dev);
2791         dsp_unlock(azx_dev);
2792         return azx_dev->stream_tag;
2793
2794  error:
2795         mark_pages_wc(chip, bufp, false);
2796         snd_dma_free_pages(bufp);
2797  err_alloc:
2798         spin_lock_irq(&chip->reg_lock);
2799         if (azx_dev->opened)
2800                 *azx_dev = chip->saved_azx_dev;
2801         azx_dev->locked = 0;
2802         spin_unlock_irq(&chip->reg_lock);
2803  unlock:
2804         dsp_unlock(azx_dev);
2805         return err;
2806 }
2807
2808 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2809 {
2810         struct azx *chip = bus->private_data;
2811         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2812
2813         if (start)
2814                 azx_stream_start(chip, azx_dev);
2815         else
2816                 azx_stream_stop(chip, azx_dev);
2817         azx_dev->running = start;
2818 }
2819
2820 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2821                                  struct snd_dma_buffer *dmab)
2822 {
2823         struct azx *chip = bus->private_data;
2824         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2825
2826         if (!dmab->area || !azx_dev->locked)
2827                 return;
2828
2829         dsp_lock(azx_dev);
2830         /* reset BDL address */
2831         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2832         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2833         azx_sd_writel(azx_dev, SD_CTL, 0);
2834         azx_dev->bufsize = 0;
2835         azx_dev->period_bytes = 0;
2836         azx_dev->format_val = 0;
2837
2838         mark_pages_wc(chip, dmab, false);
2839         snd_dma_free_pages(dmab);
2840         dmab->area = NULL;
2841
2842         spin_lock_irq(&chip->reg_lock);
2843         if (azx_dev->opened)
2844                 *azx_dev = chip->saved_azx_dev;
2845         azx_dev->locked = 0;
2846         spin_unlock_irq(&chip->reg_lock);
2847         dsp_unlock(azx_dev);
2848 }
2849 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2850
2851 #ifdef CONFIG_PM
2852 /* power-up/down the controller */
2853 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2854 {
2855         struct azx *chip = bus->private_data;
2856
2857         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2858                 return;
2859
2860         if (power_up)
2861                 pm_runtime_get_sync(&chip->pci->dev);
2862         else
2863                 pm_runtime_put_sync(&chip->pci->dev);
2864 }
2865
2866 static DEFINE_MUTEX(card_list_lock);
2867 static LIST_HEAD(card_list);
2868
2869 static void azx_add_card_list(struct azx *chip)
2870 {
2871         mutex_lock(&card_list_lock);
2872         list_add(&chip->list, &card_list);
2873         mutex_unlock(&card_list_lock);
2874 }
2875
2876 static void azx_del_card_list(struct azx *chip)
2877 {
2878         mutex_lock(&card_list_lock);
2879         list_del_init(&chip->list);
2880         mutex_unlock(&card_list_lock);
2881 }
2882
2883 /* trigger power-save check at writing parameter */
2884 static int param_set_xint(const char *val, const struct kernel_param *kp)
2885 {
2886         struct azx *chip;
2887         struct hda_codec *c;
2888         int prev = power_save;
2889         int ret = param_set_int(val, kp);
2890
2891         if (ret || prev == power_save)
2892                 return ret;
2893
2894         mutex_lock(&card_list_lock);
2895         list_for_each_entry(chip, &card_list, list) {
2896                 if (!chip->bus || chip->disabled)
2897                         continue;
2898                 list_for_each_entry(c, &chip->bus->codec_list, list)
2899                         snd_hda_power_sync(c);
2900         }
2901         mutex_unlock(&card_list_lock);
2902         return 0;
2903 }
2904 #else
2905 #define azx_add_card_list(chip) /* NOP */
2906 #define azx_del_card_list(chip) /* NOP */
2907 #endif /* CONFIG_PM */
2908
2909 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2910 /*
2911  * power management
2912  */
2913 static int azx_suspend(struct device *dev)
2914 {
2915         struct pci_dev *pci = to_pci_dev(dev);
2916         struct snd_card *card = dev_get_drvdata(dev);
2917         struct azx *chip = card->private_data;
2918         struct azx_pcm *p;
2919
2920         if (chip->disabled)
2921                 return 0;
2922
2923         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2924         azx_clear_irq_pending(chip);
2925         list_for_each_entry(p, &chip->pcm_list, list)
2926                 snd_pcm_suspend_all(p->pcm);
2927         if (chip->initialized)
2928                 snd_hda_suspend(chip->bus);
2929         azx_stop_chip(chip);
2930         azx_enter_link_reset(chip);
2931         if (chip->irq >= 0) {
2932                 free_irq(chip->irq, chip);
2933                 chip->irq = -1;
2934         }
2935         if (chip->msi)
2936                 pci_disable_msi(chip->pci);
2937         pci_disable_device(pci);
2938         pci_save_state(pci);
2939         pci_set_power_state(pci, PCI_D3hot);
2940         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2941                 hda_display_power(false);
2942         return 0;
2943 }
2944
2945 static int azx_resume(struct device *dev)
2946 {
2947         struct pci_dev *pci = to_pci_dev(dev);
2948         struct snd_card *card = dev_get_drvdata(dev);
2949         struct azx *chip = card->private_data;
2950
2951         if (chip->disabled)
2952                 return 0;
2953
2954         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2955                 hda_display_power(true);
2956         pci_set_power_state(pci, PCI_D0);
2957         pci_restore_state(pci);
2958         if (pci_enable_device(pci) < 0) {
2959                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2960                        "disabling device\n");
2961                 snd_card_disconnect(card);
2962                 return -EIO;
2963         }
2964         pci_set_master(pci);
2965         if (chip->msi)
2966                 if (pci_enable_msi(pci) < 0)
2967                         chip->msi = 0;
2968         if (azx_acquire_irq(chip, 1) < 0)
2969                 return -EIO;
2970         azx_init_pci(chip);
2971
2972         azx_init_chip(chip, 1);
2973
2974         snd_hda_resume(chip->bus);
2975         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2976         return 0;
2977 }
2978 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2979
2980 #ifdef CONFIG_PM_RUNTIME
2981 static int azx_runtime_suspend(struct device *dev)
2982 {
2983         struct snd_card *card = dev_get_drvdata(dev);
2984         struct azx *chip = card->private_data;
2985
2986         if (chip->disabled)
2987                 return 0;
2988
2989         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2990                 return 0;
2991
2992         /* enable controller wake up event */
2993         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2994                   STATESTS_INT_MASK);
2995
2996         azx_stop_chip(chip);
2997         azx_enter_link_reset(chip);
2998         azx_clear_irq_pending(chip);
2999         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3000                 hda_display_power(false);
3001         return 0;
3002 }
3003
3004 static int azx_runtime_resume(struct device *dev)
3005 {
3006         struct snd_card *card = dev_get_drvdata(dev);
3007         struct azx *chip = card->private_data;
3008         struct hda_bus *bus;
3009         struct hda_codec *codec;
3010         int status;
3011
3012         if (chip->disabled)
3013                 return 0;
3014
3015         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3016                 return 0;
3017
3018         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3019                 hda_display_power(true);
3020
3021         /* Read STATESTS before controller reset */
3022         status = azx_readw(chip, STATESTS);
3023
3024         azx_init_pci(chip);
3025         azx_init_chip(chip, 1);
3026
3027         bus = chip->bus;
3028         if (status && bus) {
3029                 list_for_each_entry(codec, &bus->codec_list, list)
3030                         if (status & (1 << codec->addr))
3031                                 queue_delayed_work(codec->bus->workq,
3032                                                    &codec->jackpoll_work, codec->jackpoll_interval);
3033         }
3034
3035         /* disable controller Wake Up event*/
3036         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3037                         ~STATESTS_INT_MASK);
3038
3039         return 0;
3040 }
3041
3042 static int azx_runtime_idle(struct device *dev)
3043 {
3044         struct snd_card *card = dev_get_drvdata(dev);
3045         struct azx *chip = card->private_data;
3046
3047         if (chip->disabled)
3048                 return 0;
3049
3050         if (!power_save_controller ||
3051             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3052                 return -EBUSY;
3053
3054         return 0;
3055 }
3056
3057 #endif /* CONFIG_PM_RUNTIME */
3058
3059 #ifdef CONFIG_PM
3060 static const struct dev_pm_ops azx_pm = {
3061         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3062         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3063 };
3064
3065 #define AZX_PM_OPS      &azx_pm
3066 #else
3067 #define AZX_PM_OPS      NULL
3068 #endif /* CONFIG_PM */
3069
3070
3071 /*
3072  * reboot notifier for hang-up problem at power-down
3073  */
3074 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3075 {
3076         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3077         snd_hda_bus_reboot_notify(chip->bus);
3078         azx_stop_chip(chip);
3079         return NOTIFY_OK;
3080 }
3081
3082 static void azx_notifier_register(struct azx *chip)
3083 {
3084         chip->reboot_notifier.notifier_call = azx_halt;
3085         register_reboot_notifier(&chip->reboot_notifier);
3086 }
3087
3088 static void azx_notifier_unregister(struct azx *chip)
3089 {
3090         if (chip->reboot_notifier.notifier_call)
3091                 unregister_reboot_notifier(&chip->reboot_notifier);
3092 }
3093
3094 static int azx_probe_continue(struct azx *chip);
3095
3096 #ifdef SUPPORT_VGA_SWITCHEROO
3097 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3098
3099 static void azx_vs_set_state(struct pci_dev *pci,
3100                              enum vga_switcheroo_state state)
3101 {
3102         struct snd_card *card = pci_get_drvdata(pci);
3103         struct azx *chip = card->private_data;
3104         bool disabled;
3105
3106         wait_for_completion(&chip->probe_wait);
3107         if (chip->init_failed)
3108                 return;
3109
3110         disabled = (state == VGA_SWITCHEROO_OFF);
3111         if (chip->disabled == disabled)
3112                 return;
3113
3114         if (!chip->bus) {
3115                 chip->disabled = disabled;
3116                 if (!disabled) {
3117                         snd_printk(KERN_INFO SFX
3118                                    "%s: Start delayed initialization\n",
3119                                    pci_name(chip->pci));
3120                         if (azx_probe_continue(chip) < 0) {
3121                                 snd_printk(KERN_ERR SFX
3122                                            "%s: initialization error\n",
3123                                            pci_name(chip->pci));
3124                                 chip->init_failed = true;
3125                         }
3126                 }
3127         } else {
3128                 snd_printk(KERN_INFO SFX
3129                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3130                            disabled ? "Disabling" : "Enabling");
3131                 if (disabled) {
3132                         pm_runtime_put_sync_suspend(&pci->dev);
3133                         azx_suspend(&pci->dev);
3134                         /* when we get suspended by vga switcheroo we end up in D3cold,
3135                          * however we have no ACPI handle, so pci/acpi can't put us there,
3136                          * put ourselves there */
3137                         pci->current_state = PCI_D3cold;
3138                         chip->disabled = true;
3139                         if (snd_hda_lock_devices(chip->bus))
3140                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3141                                            pci_name(chip->pci));
3142                 } else {
3143                         snd_hda_unlock_devices(chip->bus);
3144                         pm_runtime_get_noresume(&pci->dev);
3145                         chip->disabled = false;
3146                         azx_resume(&pci->dev);
3147                 }
3148         }
3149 }
3150
3151 static bool azx_vs_can_switch(struct pci_dev *pci)
3152 {
3153         struct snd_card *card = pci_get_drvdata(pci);
3154         struct azx *chip = card->private_data;
3155
3156         wait_for_completion(&chip->probe_wait);
3157         if (chip->init_failed)
3158                 return false;
3159         if (chip->disabled || !chip->bus)
3160                 return true;
3161         if (snd_hda_lock_devices(chip->bus))
3162                 return false;
3163         snd_hda_unlock_devices(chip->bus);
3164         return true;
3165 }
3166
3167 static void init_vga_switcheroo(struct azx *chip)
3168 {
3169         struct pci_dev *p = get_bound_vga(chip->pci);
3170         if (p) {
3171                 snd_printk(KERN_INFO SFX
3172                            "%s: Handle VGA-switcheroo audio client\n",
3173                            pci_name(chip->pci));
3174                 chip->use_vga_switcheroo = 1;
3175                 pci_dev_put(p);
3176         }
3177 }
3178
3179 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3180         .set_gpu_state = azx_vs_set_state,
3181         .can_switch = azx_vs_can_switch,
3182 };
3183
3184 static int register_vga_switcheroo(struct azx *chip)
3185 {
3186         int err;
3187
3188         if (!chip->use_vga_switcheroo)
3189                 return 0;
3190         /* FIXME: currently only handling DIS controller
3191          * is there any machine with two switchable HDMI audio controllers?
3192          */
3193         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3194                                                     VGA_SWITCHEROO_DIS,
3195                                                     chip->bus != NULL);
3196         if (err < 0)
3197                 return err;
3198         chip->vga_switcheroo_registered = 1;
3199
3200         /* register as an optimus hdmi audio power domain */
3201         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
3202         return 0;
3203 }
3204 #else
3205 #define init_vga_switcheroo(chip)               /* NOP */
3206 #define register_vga_switcheroo(chip)           0
3207 #define check_hdmi_disabled(pci)        false
3208 #endif /* SUPPORT_VGA_SWITCHER */
3209
3210 /*
3211  * destructor
3212  */
3213 static int azx_free(struct azx *chip)
3214 {
3215         struct pci_dev *pci = chip->pci;
3216         int i;
3217
3218         if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3219                         && chip->running)
3220                 pm_runtime_get_noresume(&pci->dev);