sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 /* Power-Management-Code ( CONFIG_PM )
  23  * for ens1371 only ( FIXME )
  24  * derived from cs4281.c, atiixp.c and via82xx.c
  25  * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
  26  * by Kurt J. Bosch
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/gameport.h>
  37 #include <linux/moduleparam.h>
  38 #include <linux/mutex.h>
  39
  40 #include <sound/core.h>
  41 #include <sound/control.h>
  42 #include <sound/pcm.h>
  43 #include <sound/rawmidi.h>
  44 #ifdef CHIP1371
  45 #include <sound/ac97_codec.h>
  46 #else
  47 #include <sound/ak4531_codec.h>
  48 #endif
  49 #include <sound/initval.h>
  50 #include <sound/asoundef.h>
  51
  52 #ifndef CHIP1371
  53 #undef CHIP1370
  54 #define CHIP1370
  55 #endif
  56
  57 #ifdef CHIP1370
  58 #define DRIVER_NAME "ENS1370"
  59 #else
  60 #define DRIVER_NAME "ENS1371"
  61 #endif
  62
  63
  64 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  65 MODULE_LICENSE("GPL");
  66 #ifdef CHIP1370
  67 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  68 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  69                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  70 #endif
  71 #ifdef CHIP1371
  72 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  73 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  74                 "{Ensoniq,AudioPCI ES1373},"
  75                 "{Creative Labs,Ectiva EV1938},"
  76                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  77                 "{Creative Labs,Vibra PCI128},"
  78                 "{Ectiva,EV1938}}");
  79 #endif
  80
  81 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  82 #define SUPPORT_JOYSTICK
  83 #endif
  84
  85 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  86 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  87 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  88 #ifdef SUPPORT_JOYSTICK
  89 #ifdef CHIP1371
  90 static int joystick_port[SNDRV_CARDS];
  91 #else
  92 static int joystick[SNDRV_CARDS];
  93 #endif
  94 #endif
  95 #ifdef CHIP1371
  96 static int spdif[SNDRV_CARDS];
  97 static int lineio[SNDRV_CARDS];
  98 #endif
  99
 100 module_param_array(index, int, NULL, 0444);
 101 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
 102 module_param_array(id, charp, NULL, 0444);
 103 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
 104 module_param_array(enable, bool, NULL, 0444);
 105 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
 106 #ifdef SUPPORT_JOYSTICK
 107 #ifdef CHIP1371
 108 module_param_array(joystick_port, int, NULL, 0444);
 109 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 110 #else
 111 module_param_array(joystick, bool, NULL, 0444);
 112 MODULE_PARM_DESC(joystick, "Enable joystick.");
 113 #endif
 114 #endif /* SUPPORT_JOYSTICK */
 115 #ifdef CHIP1371
 116 module_param_array(spdif, int, NULL, 0444);
 117 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
 118 module_param_array(lineio, int, NULL, 0444);
 119 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
 120 #endif
 121
 122 /* ES1371 chip ID */
 123 /* This is a little confusing because all ES1371 compatible chips have the
 124    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 125    This is only significant if you want to enable features on the later parts.
 126    Yes, I know it's stupid and why didn't we use the sub IDs?
 127 */
 128 #define ES1371REV_ES1373_A  0x04
 129 #define ES1371REV_ES1373_B  0x06
 130 #define ES1371REV_CT5880_A  0x07
 131 #define CT5880REV_CT5880_C  0x02
 132 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 133 #define CT5880REV_CT5880_E  0x04        /* mw */
 134 #define ES1371REV_ES1371_B  0x09
 135 #define EV1938REV_EV1938_A  0x00
 136 #define ES1371REV_ES1373_8  0x08
 137
 138 /*
 139  * Direct registers
 140  */
 141
 142 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 143
 144 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 145 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 146 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 147 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 148 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 149 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 150 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 151 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 152 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 153 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 154 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 155 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 156 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 157 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 158 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 159 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 160 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 161 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 162 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 163 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 164 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 165 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 166 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 167 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 168 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 169 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 170 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 171 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 172 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 173 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 174 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 175 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 176 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 177 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 178 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 179 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 180 #define   ES_UART_EN            (1<<3)          /* UART enable */
 181 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 182 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 183 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 184 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 185 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 186 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 187 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 188 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 189 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 190 #define   ES_1373_REAR_BIT26    (1<<26)
 191 #define   ES_1373_REAR_BIT24    (1<<24)
 192 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 193 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 194 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 195 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 196 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 197 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 198 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 199 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 200 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 201 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 202 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 203 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 204 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 205 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 206 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 207 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 208 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 209 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 210 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 211 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 212 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 213 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 214 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 215 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 216 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 217 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 218 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 219 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 220 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 221 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 222 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 223 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 224 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 225 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 226 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 227 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 228 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 229 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 230 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 231 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 232 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 233 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 234 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 235 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 236 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 237
 238 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 239 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 240 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 241 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 242 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 243 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 244 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 245 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 246 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 247 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 248 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 249 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 250 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 251
 252 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 253 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 254 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 255 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 256 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 257 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 258 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 259 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 260 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 261 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 262 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 263 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 264 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 265 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 266 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 267 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 268 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 269 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 270 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 271 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 272 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 273 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 274 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 275
 276 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 277
 278 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 279 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 280 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 281 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 282 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 283 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 284 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 285 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 286 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 287 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 288 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 289 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 290 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 291 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 292 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 293 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 294 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 295 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 296 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 297 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 298 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 299 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 300 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 301 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 302 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 303 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 304 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 305
 306 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 307 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 308 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 309 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 310 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 311 #define   ES_REG_COUNTM         (0xffff<<0)
 312 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 313
 314 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 315 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 316 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 317 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 318 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 319 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 320 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 321 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 322 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 323 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 324 #define   ES_REG_FSIZEM          (0xffff<<0)
 325 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 326 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 327 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 328
 329 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 330 #define   ES_REG_UF_VALID        (1<<8)
 331 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 332 #define   ES_REG_UF_BYTEM        (0xff<<0)
 333 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 334
 335
 336 /*
 337  *  Pages
 338  */
 339
 340 #define ES_PAGE_DAC     0x0c
 341 #define ES_PAGE_ADC     0x0d
 342 #define ES_PAGE_UART    0x0e
 343 #define ES_PAGE_UART1   0x0f
 344
 345 /*
 346  *  Sample rate converter addresses
 347  */
 348
 349 #define ES_SMPREG_DAC1          0x70
 350 #define ES_SMPREG_DAC2          0x74
 351 #define ES_SMPREG_ADC           0x78
 352 #define ES_SMPREG_VOL_ADC       0x6c
 353 #define ES_SMPREG_VOL_DAC1      0x7c
 354 #define ES_SMPREG_VOL_DAC2      0x7e
 355 #define ES_SMPREG_TRUNC_N       0x00
 356 #define ES_SMPREG_INT_REGS      0x01
 357 #define ES_SMPREG_ACCUM_FRAC    0x02
 358 #define ES_SMPREG_VFREQ_FRAC    0x03
 359
 360 /*
 361  *  Some contants
 362  */
 363
 364 #define ES_1370_SRCLOCK    1411200
 365 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 366
 367 /*
 368  *  Open modes
 369  */
 370
 371 #define ES_MODE_PLAY1   0x0001
 372 #define ES_MODE_PLAY2   0x0002
 373 #define ES_MODE_CAPTURE 0x0004
 374
 375 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 376 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 377
 378 /*
 379
 380  */
 381
 382 struct ensoniq {
 383         spinlock_t reg_lock;
 384         struct mutex src_mutex;
 385
 386         int irq;
 387
 388         unsigned long playback1size;
 389         unsigned long playback2size;
 390         unsigned long capture3size;
 391
 392         unsigned long port;
 393         unsigned int mode;
 394         unsigned int uartm;     /* UART mode */
 395
 396         unsigned int ctrl;      /* control register */
 397         unsigned int sctrl;     /* serial control register */
 398         unsigned int cssr;      /* control status register */
 399         unsigned int uartc;     /* uart control register */
 400         unsigned int rev;       /* chip revision */
 401
 402         union {
 403 #ifdef CHIP1371
 404                 struct {
 405                         struct snd_ac97 *ac97;
 406                 } es1371;
 407 #else
 408                 struct {
 409                         int pclkdiv_lock;
 410                         struct snd_ak4531 *ak4531;
 411                 } es1370;
 412 #endif
 413         } u;
 414
 415         struct pci_dev *pci;
 416         struct snd_card *card;
 417         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
 418         struct snd_pcm *pcm2;   /* DAC2 PCM */
 419         struct snd_pcm_substream *playback1_substream;
 420         struct snd_pcm_substream *playback2_substream;
 421         struct snd_pcm_substream *capture_substream;
 422         unsigned int p1_dma_size;
 423         unsigned int p2_dma_size;
 424         unsigned int c_dma_size;
 425         unsigned int p1_period_size;
 426         unsigned int p2_period_size;
 427         unsigned int c_period_size;
 428         struct snd_rawmidi *rmidi;
 429         struct snd_rawmidi_substream *midi_input;
 430         struct snd_rawmidi_substream *midi_output;
 431
 432         unsigned int spdif;
 433         unsigned int spdif_default;
 434         unsigned int spdif_stream;
 435
 436 #ifdef CHIP1370
 437         struct snd_dma_buffer dma_bug;
 438 #endif
 439
 440 #ifdef SUPPORT_JOYSTICK
 441         struct gameport *gameport;
 442 #endif
 443 };
 444
 445 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
 446
 447 static struct pci_device_id snd_audiopci_ids[] = {
 448 #ifdef CHIP1370
 449         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 450 #endif
 451 #ifdef CHIP1371
 452         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 453         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 454         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 455 #endif
 456         { 0, }
 457 };
 458
 459 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 460
 461 /*
 462  *  constants
 463  */
 464
 465 #define POLL_COUNT      0xa000
 466
 467 #ifdef CHIP1370
 468 static unsigned int snd_es1370_fixed_rates[] =
 469         {5512, 11025, 22050, 44100};
 470 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
 471         .count = 4,
 472         .list = snd_es1370_fixed_rates,
 473         .mask = 0,
 474 };
 475 static struct snd_ratnum es1370_clock = {
 476         .num = ES_1370_SRCLOCK,
 477         .den_min = 29,
 478         .den_max = 353,
 479         .den_step = 1,
 480 };
 481 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
 482         .nrats = 1,
 483         .rats = &es1370_clock,
 484 };
 485 #else
 486 static struct snd_ratden es1371_dac_clock = {
 487         .num_min = 3000 * (1 << 15),
 488         .num_max = 48000 * (1 << 15),
 489         .num_step = 3000,
 490         .den = 1 << 15,
 491 };
 492 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
 493         .nrats = 1,
 494         .rats = &es1371_dac_clock,
 495 };
 496 static struct snd_ratnum es1371_adc_clock = {
 497         .num = 48000 << 15,
 498         .den_min = 32768,
 499         .den_max = 393216,
 500         .den_step = 1,
 501 };
 502 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
 503         .nrats = 1,
 504         .rats = &es1371_adc_clock,
 505 };
 506 #endif
 507 static const unsigned int snd_ensoniq_sample_shift[] =
 508         {0, 1, 1, 2};
 509
 510 /*
 511  *  common I/O routines
 512  */
 513
 514 #ifdef CHIP1371
 515
 516 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
 517 {
 518         unsigned int t, r = 0;
 519
 520         for (t = 0; t < POLL_COUNT; t++) {
 521                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 522                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 523                         return r;
 524                 cond_resched();
 525         }
 526         snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
 527                    ES_REG(ensoniq, 1371_SMPRATE), r);
 528         return 0;
 529 }
 530
 531 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
 532 {
 533         unsigned int temp, i, orig, r;
 534
 535         /* wait for ready */
 536         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 537
 538         /* expose the SRC state bits */
 539         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 540                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 541         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 542         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 543
 544         /* now, wait for busy and the correct time to read */
 545         temp = snd_es1371_wait_src_ready(ensoniq);
 546
 547         if ((temp & 0x00870000) != 0x00010000) {
 548                 /* wait for the right state */
 549                 for (i = 0; i < POLL_COUNT; i++) {
 550                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 551                         if ((temp & 0x00870000) == 0x00010000)
 552                                 break;
 553                 }
 554         }
 555
 556         /* hide the state bits */
 557         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 558                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 559         r |= ES_1371_SRC_RAM_ADDRO(reg);
 560         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 561
 562         return temp;
 563 }
 564
 565 static void snd_es1371_src_write(struct ensoniq * ensoniq,
 566                                  unsigned short reg, unsigned short data)
 567 {
 568         unsigned int r;
 569
 570         r = snd_es1371_wait_src_ready(ensoniq) &
 571             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 572              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 573         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 574         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 575 }
 576
 577 #endif /* CHIP1371 */
 578
 579 #ifdef CHIP1370
 580
 581 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
 582                                    unsigned short reg, unsigned short val)
 583 {
 584         struct ensoniq *ensoniq = ak4531->private_data;
 585         unsigned long end_time = jiffies + HZ / 10;
 586
 587 #if 0
 588         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
 589                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 590 #endif
 591         do {
 592                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 593                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 594                         return;
 595                 }
 596                 schedule_timeout_uninterruptible(1);
 597         } while (time_after(end_time, jiffies));
 598         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
 599                    inl(ES_REG(ensoniq, STATUS)));
 600 }
 601
 602 #endif /* CHIP1370 */
 603
 604 #ifdef CHIP1371
 605
 606 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
 607                                    unsigned short reg, unsigned short val)
 608 {
 609         struct ensoniq *ensoniq = ac97->private_data;
 610         unsigned int t, x;
 611
 612         mutex_lock(&ensoniq->src_mutex);
 613         for (t = 0; t < POLL_COUNT; t++) {
 614                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 615                         /* save the current state for latter */
 616                         x = snd_es1371_wait_src_ready(ensoniq);
 617                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 618                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 619                              ES_REG(ensoniq, 1371_SMPRATE));
 620                         /* wait for not busy (state 0) first to avoid
 621                            transition states */
 622                         for (t = 0; t < POLL_COUNT; t++) {
 623                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 624                                     0x00000000)
 625                                         break;
 626                         }
 627                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 628                         for (t = 0; t < POLL_COUNT; t++) {
 629                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 630                                     0x00010000)
 631                                         break;
 632                         }
 633                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 634                         /* restore SRC reg */
 635                         snd_es1371_wait_src_ready(ensoniq);
 636                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 637                         mutex_unlock(&ensoniq->src_mutex);
 638                         return;
 639                 }
 640         }
 641         mutex_unlock(&ensoniq->src_mutex);
 642         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
 643                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 644 }
 645
 646 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
 647                                             unsigned short reg)
 648 {
 649         struct ensoniq *ensoniq = ac97->private_data;
 650         unsigned int t, x, fail = 0;
 651
 652       __again:
 653         mutex_lock(&ensoniq->src_mutex);
 654         for (t = 0; t < POLL_COUNT; t++) {
 655                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 656                         /* save the current state for latter */
 657                         x = snd_es1371_wait_src_ready(ensoniq);
 658                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 659                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 660                              ES_REG(ensoniq, 1371_SMPRATE));
 661                         /* wait for not busy (state 0) first to avoid
 662                            transition states */
 663                         for (t = 0; t < POLL_COUNT; t++) {
 664                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 665                                     0x00000000)
 666                                         break;
 667                         }
 668                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 669                         for (t = 0; t < POLL_COUNT; t++) {
 670                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 671                                     0x00010000)
 672                                         break;
 673                         }
 674                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 675                         /* restore SRC reg */
 676                         snd_es1371_wait_src_ready(ensoniq);
 677                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 678                         /* wait for WIP again */
 679                         for (t = 0; t < POLL_COUNT; t++) {
 680                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 681                                         break;
 682                         }
 683                         /* now wait for the stinkin' data (RDY) */
 684                         for (t = 0; t < POLL_COUNT; t++) {
 685                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 686                                         mutex_unlock(&ensoniq->src_mutex);
 687                                         return ES_1371_CODEC_READ(x);
 688                                 }
 689                         }
 690                         mutex_unlock(&ensoniq->src_mutex);
 691                         if (++fail > 10) {
 692                                 snd_printk(KERN_ERR "codec read timeout (final) "
 693                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
 694                                            ES_REG(ensoniq, 1371_CODEC), reg,
 695                                            inl(ES_REG(ensoniq, 1371_CODEC)));
 696                                 return 0;
 697                         }
 698                         goto __again;
 699                 }
 700         }
 701         mutex_unlock(&ensoniq->src_mutex);
 702         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
 703                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 704         return 0;
 705 }
 706
 707 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
 708 {
 709         msleep(750);
 710         snd_es1371_codec_read(ac97, AC97_RESET);
 711         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 712         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 713         msleep(50);
 714 }
 715
 716 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
 717 {
 718         unsigned int n, truncm, freq, result;
 719
 720         mutex_lock(&ensoniq->src_mutex);
 721         n = rate / 3000;
 722         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 723                 n--;
 724         truncm = (21 * n - 1) | 1;
 725         freq = ((48000UL << 15) / rate) * n;
 726         result = (48000UL << 15) / (freq / n);
 727         if (rate >= 24000) {
 728                 if (truncm > 239)
 729                         truncm = 239;
 730                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 731                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 732         } else {
 733                 if (truncm > 119)
 734                         truncm = 119;
 735                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 736                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 737         }
 738         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 739                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
 740                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 741                              ((freq >> 5) & 0xfc00));
 742         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 743         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 744         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 745         mutex_unlock(&ensoniq->src_mutex);
 746 }
 747
 748 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
 749 {
 750         unsigned int freq, r;
 751
 752         mutex_lock(&ensoniq->src_mutex);
 753         freq = ((rate << 15) + 1500) / 3000;
 754         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 755                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
 756                 ES_1371_DIS_P1;
 757         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 758         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 759                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
 760                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 761                              ((freq >> 5) & 0xfc00));
 762         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 763         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 764                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
 765         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 766         mutex_unlock(&ensoniq->src_mutex);
 767 }
 768
 769 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
 770 {
 771         unsigned int freq, r;
 772
 773         mutex_lock(&ensoniq->src_mutex);
 774         freq = ((rate << 15) + 1500) / 3000;
 775         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 776                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
 777                 ES_1371_DIS_P2;
 778         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 779         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 780                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
 781                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 782                              ((freq >> 5) & 0xfc00));
 783         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
 784                              freq & 0x7fff);
 785         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 786                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
 787         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 788         mutex_unlock(&ensoniq->src_mutex);
 789 }
 790
 791 #endif /* CHIP1371 */
 792
 793 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
 794 {
 795         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 796         switch (cmd) {
 797         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 798         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 799         {
 800                 unsigned int what = 0;
 801                 struct snd_pcm_substream *s;
 802                 snd_pcm_group_for_each_entry(s, substream) {
 803                         if (s == ensoniq->playback1_substream) {
 804                                 what |= ES_P1_PAUSE;
 805                                 snd_pcm_trigger_done(s, substream);
 806                         } else if (s == ensoniq->playback2_substream) {
 807                                 what |= ES_P2_PAUSE;
 808                                 snd_pcm_trigger_done(s, substream);
 809                         } else if (s == ensoniq->capture_substream)
 810                                 return -EINVAL;
 811                 }
 812                 spin_lock(&ensoniq->reg_lock);
 813                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 814                         ensoniq->sctrl |= what;
 815                 else
 816                         ensoniq->sctrl &= ~what;
 817                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 818                 spin_unlock(&ensoniq->reg_lock);
 819                 break;
 820         }
 821         case SNDRV_PCM_TRIGGER_START:
 822         case SNDRV_PCM_TRIGGER_STOP:
 823         {
 824                 unsigned int what = 0;
 825                 struct snd_pcm_substream *s;
 826                 snd_pcm_group_for_each_entry(s, substream) {
 827                         if (s == ensoniq->playback1_substream) {
 828                                 what |= ES_DAC1_EN;
 829                                 snd_pcm_trigger_done(s, substream);
 830                         } else if (s == ensoniq->playback2_substream) {
 831                                 what |= ES_DAC2_EN;
 832                                 snd_pcm_trigger_done(s, substream);
 833                         } else if (s == ensoniq->capture_substream) {
 834                                 what |= ES_ADC_EN;
 835                                 snd_pcm_trigger_done(s, substream);
 836                         }
 837                 }
 838                 spin_lock(&ensoniq->reg_lock);
 839                 if (cmd == SNDRV_PCM_TRIGGER_START)
 840                         ensoniq->ctrl |= what;
 841                 else
 842                         ensoniq->ctrl &= ~what;
 843                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 844                 spin_unlock(&ensoniq->reg_lock);
 845                 break;
 846         }
 847         default:
 848                 return -EINVAL;
 849         }
 850         return 0;
 851 }
 852
 853 /*
 854  *  PCM part
 855  */
 856
 857 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
 858                                  struct snd_pcm_hw_params *hw_params)
 859 {
 860         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 861 }
 862
 863 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
 864 {
 865         return snd_pcm_lib_free_pages(substream);
 866 }
 867
 868 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
 869 {
 870         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 871         struct snd_pcm_runtime *runtime = substream->runtime;
 872         unsigned int mode = 0;
 873
 874         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 875         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 876         if (snd_pcm_format_width(runtime->format) == 16)
 877                 mode |= 0x02;
 878         if (runtime->channels > 1)
 879                 mode |= 0x01;
 880         spin_lock_irq(&ensoniq->reg_lock);
 881         ensoniq->ctrl &= ~ES_DAC1_EN;
 882 #ifdef CHIP1371
 883         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 884         if (runtime->rate == 48000)
 885                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 886         else
 887                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 888 #endif
 889         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 890         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 891         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 892         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 893         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 894         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 895         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 896         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 897              ES_REG(ensoniq, DAC1_COUNT));
 898 #ifdef CHIP1370
 899         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 900         switch (runtime->rate) {
 901         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 902         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 903         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 904         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 905         default: snd_BUG();
 906         }
 907 #endif
 908         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 909         spin_unlock_irq(&ensoniq->reg_lock);
 910 #ifndef CHIP1370
 911         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 912 #endif
 913         return 0;
 914 }
 915
 916 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
 917 {
 918         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 919         struct snd_pcm_runtime *runtime = substream->runtime;
 920         unsigned int mode = 0;
 921
 922         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 923         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 924         if (snd_pcm_format_width(runtime->format) == 16)
 925                 mode |= 0x02;
 926         if (runtime->channels > 1)
 927                 mode |= 0x01;
 928         spin_lock_irq(&ensoniq->reg_lock);
 929         ensoniq->ctrl &= ~ES_DAC2_EN;
 930         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 931         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 932         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 933         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 934         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 935                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 936         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 937                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 938         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 939         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 940              ES_REG(ensoniq, DAC2_COUNT));
 941 #ifdef CHIP1370
 942         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 943                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 944                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 945                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 946         }
 947 #endif
 948         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 949         spin_unlock_irq(&ensoniq->reg_lock);
 950 #ifndef CHIP1370
 951         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 952 #endif
 953         return 0;
 954 }
 955
 956 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
 957 {
 958         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 959         struct snd_pcm_runtime *runtime = substream->runtime;
 960         unsigned int mode = 0;
 961
 962         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 963         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 964         if (snd_pcm_format_width(runtime->format) == 16)
 965                 mode |= 0x02;
 966         if (runtime->channels > 1)
 967                 mode |= 0x01;
 968         spin_lock_irq(&ensoniq->reg_lock);
 969         ensoniq->ctrl &= ~ES_ADC_EN;
 970         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 971         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 972         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 973         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 974         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 975         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 976         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 977         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 978              ES_REG(ensoniq, ADC_COUNT));
 979 #ifdef CHIP1370
 980         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 981                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 982                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 983                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 984         }
 985 #endif
 986         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 987         spin_unlock_irq(&ensoniq->reg_lock);
 988 #ifndef CHIP1370
 989         snd_es1371_adc_rate(ensoniq, runtime->rate);
 990 #endif
 991         return 0;
 992 }
 993
 994 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
 995 {
 996         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 997         size_t ptr;
 998
 999         spin_lock(&ensoniq->reg_lock);
1000         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1001                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1002                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1003                 ptr = bytes_to_frames(substream->runtime, ptr);
1004         } else {
1005                 ptr = 0;
1006         }
1007         spin_unlock(&ensoniq->reg_lock);
1008         return ptr;
1009 }
1010
1011 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1012 {
1013         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014         size_t ptr;
1015
1016         spin_lock(&ensoniq->reg_lock);
1017         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1018                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1019                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1020                 ptr = bytes_to_frames(substream->runtime, ptr);
1021         } else {
1022                 ptr = 0;
1023         }
1024         spin_unlock(&ensoniq->reg_lock);
1025         return ptr;
1026 }
1027
1028 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1029 {
1030         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1031         size_t ptr;
1032
1033         spin_lock(&ensoniq->reg_lock);
1034         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1035                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1036                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1037                 ptr = bytes_to_frames(substream->runtime, ptr);
1038         } else {
1039                 ptr = 0;
1040         }
1041         spin_unlock(&ensoniq->reg_lock);
1042         return ptr;
1043 }
1044
1045 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1046 {
1047         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1048                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1049                                  SNDRV_PCM_INFO_MMAP_VALID |
1050                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1051         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1052         .rates =
1053 #ifndef CHIP1370
1054                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1055 #else
1056                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1057                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1058                                  SNDRV_PCM_RATE_44100),
1059 #endif
1060         .rate_min =             4000,
1061         .rate_max =             48000,
1062         .channels_min =         1,
1063         .channels_max =         2,
1064         .buffer_bytes_max =     (128*1024),
1065         .period_bytes_min =     64,
1066         .period_bytes_max =     (128*1024),
1067         .periods_min =          1,
1068         .periods_max =          1024,
1069         .fifo_size =            0,
1070 };
1071
1072 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1073 {
1074         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1075                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1076                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1077                                  SNDRV_PCM_INFO_SYNC_START),
1078         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1079         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1080         .rate_min =             4000,
1081         .rate_max =             48000,
1082         .channels_min =         1,
1083         .channels_max =         2,
1084         .buffer_bytes_max =     (128*1024),
1085         .period_bytes_min =     64,
1086         .period_bytes_max =     (128*1024),
1087         .periods_min =          1,
1088         .periods_max =          1024,
1089         .fifo_size =            0,
1090 };
1091
1092 static struct snd_pcm_hardware snd_ensoniq_capture =
1093 {
1094         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1095                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1096                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1097         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1098         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1099         .rate_min =             4000,
1100         .rate_max =             48000,
1101         .channels_min =         1,
1102         .channels_max =         2,
1103         .buffer_bytes_max =     (128*1024),
1104         .period_bytes_min =     64,
1105         .period_bytes_max =     (128*1024),
1106         .periods_min =          1,
1107         .periods_max =          1024,
1108         .fifo_size =            0,
1109 };
1110
1111 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1112 {
1113         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1114         struct snd_pcm_runtime *runtime = substream->runtime;
1115
1116         ensoniq->mode |= ES_MODE_PLAY1;
1117         ensoniq->playback1_substream = substream;
1118         runtime->hw = snd_ensoniq_playback1;
1119         snd_pcm_set_sync(substream);
1120         spin_lock_irq(&ensoniq->reg_lock);
1121         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1122                 ensoniq->spdif_stream = ensoniq->spdif_default;
1123         spin_unlock_irq(&ensoniq->reg_lock);
1124 #ifdef CHIP1370
1125         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1126                                    &snd_es1370_hw_constraints_rates);
1127 #else
1128         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1129                                       &snd_es1371_hw_constraints_dac_clock);
1130 #endif
1131         return 0;
1132 }
1133
1134 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1135 {
1136         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1137         struct snd_pcm_runtime *runtime = substream->runtime;
1138
1139         ensoniq->mode |= ES_MODE_PLAY2;
1140         ensoniq->playback2_substream = substream;
1141         runtime->hw = snd_ensoniq_playback2;
1142         snd_pcm_set_sync(substream);
1143         spin_lock_irq(&ensoniq->reg_lock);
1144         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1145                 ensoniq->spdif_stream = ensoniq->spdif_default;
1146         spin_unlock_irq(&ensoniq->reg_lock);
1147 #ifdef CHIP1370
1148         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1149                                       &snd_es1370_hw_constraints_clock);
1150 #else
1151         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1152                                       &snd_es1371_hw_constraints_dac_clock);
1153 #endif
1154         return 0;
1155 }
1156
1157 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1158 {
1159         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1160         struct snd_pcm_runtime *runtime = substream->runtime;
1161
1162         ensoniq->mode |= ES_MODE_CAPTURE;
1163         ensoniq->capture_substream = substream;
1164         runtime->hw = snd_ensoniq_capture;
1165         snd_pcm_set_sync(substream);
1166 #ifdef CHIP1370
1167         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1168                                       &snd_es1370_hw_constraints_clock);
1169 #else
1170         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1171                                       &snd_es1371_hw_constraints_adc_clock);
1172 #endif
1173         return 0;
1174 }
1175
1176 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1177 {
1178         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1179
1180         ensoniq->playback1_substream = NULL;
1181         ensoniq->mode &= ~ES_MODE_PLAY1;
1182         return 0;
1183 }
1184
1185 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1186 {
1187         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1188
1189         ensoniq->playback2_substream = NULL;
1190         spin_lock_irq(&ensoniq->reg_lock);
1191 #ifdef CHIP1370
1192         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1193 #endif
1194         ensoniq->mode &= ~ES_MODE_PLAY2;
1195         spin_unlock_irq(&ensoniq->reg_lock);
1196         return 0;
1197 }
1198
1199 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1200 {
1201         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1202
1203         ensoniq->capture_substream = NULL;
1204         spin_lock_irq(&ensoniq->reg_lock);
1205 #ifdef CHIP1370
1206         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1207 #endif
1208         ensoniq->mode &= ~ES_MODE_CAPTURE;
1209         spin_unlock_irq(&ensoniq->reg_lock);
1210         return 0;
1211 }
1212
1213 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1214         .open =         snd_ensoniq_playback1_open,
1215         .close =        snd_ensoniq_playback1_close,
1216         .ioctl =        snd_pcm_lib_ioctl,
1217         .hw_params =    snd_ensoniq_hw_params,
1218         .hw_free =      snd_ensoniq_hw_free,
1219         .prepare =      snd_ensoniq_playback1_prepare,
1220         .trigger =      snd_ensoniq_trigger,
1221         .pointer =      snd_ensoniq_playback1_pointer,
1222 };
1223
1224 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1225         .open =         snd_ensoniq_playback2_open,
1226         .close =        snd_ensoniq_playback2_close,
1227         .ioctl =        snd_pcm_lib_ioctl,
1228         .hw_params =    snd_ensoniq_hw_params,
1229         .hw_free =      snd_ensoniq_hw_free,
1230         .prepare =      snd_ensoniq_playback2_prepare,
1231         .trigger =      snd_ensoniq_trigger,
1232         .pointer =      snd_ensoniq_playback2_pointer,
1233 };
1234
1235 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1236         .open =         snd_ensoniq_capture_open,
1237         .close =        snd_ensoniq_capture_close,
1238         .ioctl =        snd_pcm_lib_ioctl,
1239         .hw_params =    snd_ensoniq_hw_params,
1240         .hw_free =      snd_ensoniq_hw_free,
1241         .prepare =      snd_ensoniq_capture_prepare,
1242         .trigger =      snd_ensoniq_trigger,
1243         .pointer =      snd_ensoniq_capture_pointer,
1244 };
1245
1246 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1247                                      struct snd_pcm ** rpcm)
1248 {
1249         struct snd_pcm *pcm;
1250         int err;
1251
1252         if (rpcm)
1253                 *rpcm = NULL;
1254 #ifdef CHIP1370
1255         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1256 #else
1257         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1258 #endif
1259         if (err < 0)
1260                 return err;
1261
1262 #ifdef CHIP1370
1263         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1264 #else
1265         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1266 #endif
1267         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1268
1269         pcm->private_data = ensoniq;
1270         pcm->info_flags = 0;
1271 #ifdef CHIP1370
1272         strcpy(pcm->name, "ES1370 DAC2/ADC");
1273 #else
1274         strcpy(pcm->name, "ES1371 DAC2/ADC");
1275 #endif
1276         ensoniq->pcm1 = pcm;
1277
1278         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1279                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1280
1281         if (rpcm)
1282                 *rpcm = pcm;
1283         return 0;
1284 }
1285
1286 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1287                                       struct snd_pcm ** rpcm)
1288 {
1289         struct snd_pcm *pcm;
1290         int err;
1291
1292         if (rpcm)
1293                 *rpcm = NULL;
1294 #ifdef CHIP1370
1295         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1296 #else
1297         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1298 #endif
1299         if (err < 0)
1300                 return err;
1301
1302 #ifdef CHIP1370
1303         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1304 #else
1305         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1306 #endif
1307         pcm->private_data = ensoniq;
1308         pcm->info_flags = 0;
1309 #ifdef CHIP1370
1310         strcpy(pcm->name, "ES1370 DAC1");
1311 #else
1312         strcpy(pcm->name, "ES1371 DAC1");
1313 #endif
1314         ensoniq->pcm2 = pcm;
1315
1316         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1317                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1318
1319         if (rpcm)
1320                 *rpcm = pcm;
1321         return 0;
1322 }
1323
1324 /*
1325  *  Mixer section
1326  */
1327
1328 /*
1329  * ENS1371 mixer (including SPDIF interface)
1330  */
1331 #ifdef CHIP1371
1332 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1333                                   struct snd_ctl_elem_info *uinfo)
1334 {
1335         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1336         uinfo->count = 1;
1337         return 0;
1338 }
1339
1340 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1341                                          struct snd_ctl_elem_value *ucontrol)
1342 {
1343         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1344         spin_lock_irq(&ensoniq->reg_lock);
1345         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1346         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1347         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1348         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1349         spin_unlock_irq(&ensoniq->reg_lock);
1350         return 0;
1351 }
1352
1353 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1354                                          struct snd_ctl_elem_value *ucontrol)
1355 {
1356         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1357         unsigned int val;
1358         int change;
1359
1360         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1361               ((u32)ucontrol->value.iec958.status[1] << 8) |
1362               ((u32)ucontrol->value.iec958.status[2] << 16) |
1363               ((u32)ucontrol->value.iec958.status[3] << 24);
1364         spin_lock_irq(&ensoniq->reg_lock);
1365         change = ensoniq->spdif_default != val;
1366         ensoniq->spdif_default = val;
1367         if (change && ensoniq->playback1_substream == NULL &&
1368             ensoniq->playback2_substream == NULL)
1369                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1370         spin_unlock_irq(&ensoniq->reg_lock);
1371         return change;
1372 }
1373
1374 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1375                                       struct snd_ctl_elem_value *ucontrol)
1376 {
1377         ucontrol->value.iec958.status[0] = 0xff;
1378         ucontrol->value.iec958.status[1] = 0xff;
1379         ucontrol->value.iec958.status[2] = 0xff;
1380         ucontrol->value.iec958.status[3] = 0xff;
1381         return 0;
1382 }
1383
1384 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1385                                         struct snd_ctl_elem_value *ucontrol)
1386 {
1387         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1388         spin_lock_irq(&ensoniq->reg_lock);
1389         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1390         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1391         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1392         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1393         spin_unlock_irq(&ensoniq->reg_lock);
1394         return 0;
1395 }
1396
1397 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1398                                         struct snd_ctl_elem_value *ucontrol)
1399 {
1400         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1401         unsigned int val;
1402         int change;
1403
1404         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1405               ((u32)ucontrol->value.iec958.status[1] << 8) |
1406               ((u32)ucontrol->value.iec958.status[2] << 16) |
1407               ((u32)ucontrol->value.iec958.status[3] << 24);
1408         spin_lock_irq(&ensoniq->reg_lock);
1409         change = ensoniq->spdif_stream != val;
1410         ensoniq->spdif_stream = val;
1411         if (change && (ensoniq->playback1_substream != NULL ||
1412                        ensoniq->playback2_substream != NULL))
1413                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1414         spin_unlock_irq(&ensoniq->reg_lock);
1415         return change;
1416 }
1417
1418 #define ES1371_SPDIF(xname) \
1419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1420   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1421
1422 static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1423                                  struct snd_ctl_elem_info *uinfo)
1424 {
1425         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1426         uinfo->count = 1;
1427         uinfo->value.integer.min = 0;
1428         uinfo->value.integer.max = 1;
1429         return 0;
1430 }
1431
1432 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1433                                 struct snd_ctl_elem_value *ucontrol)
1434 {
1435         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1436
1437         spin_lock_irq(&ensoniq->reg_lock);
1438         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1439         spin_unlock_irq(&ensoniq->reg_lock);
1440         return 0;
1441 }
1442
1443 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1444                                 struct snd_ctl_elem_value *ucontrol)
1445 {
1446         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1447         unsigned int nval1, nval2;
1448         int change;
1449
1450         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1451         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1452         spin_lock_irq(&ensoniq->reg_lock);
1453         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1454         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1455         ensoniq->ctrl |= nval1;
1456         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1457         ensoniq->cssr |= nval2;
1458         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1459         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1460         spin_unlock_irq(&ensoniq->reg_lock);
1461         return change;
1462 }
1463
1464
1465 /* spdif controls */
1466 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1467         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1468         {
1469                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1470                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1471                 .info =         snd_ens1373_spdif_info,
1472                 .get =          snd_ens1373_spdif_default_get,
1473                 .put =          snd_ens1373_spdif_default_put,
1474         },
1475         {
1476                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1477                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1478                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1479                 .info =         snd_ens1373_spdif_info,
1480                 .get =          snd_ens1373_spdif_mask_get
1481         },
1482         {
1483                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1484                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1485                 .info =         snd_ens1373_spdif_info,
1486                 .get =          snd_ens1373_spdif_stream_get,
1487                 .put =          snd_ens1373_spdif_stream_put
1488         },
1489 };
1490
1491
1492 static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1493                                 struct snd_ctl_elem_info *uinfo)
1494 {
1495         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1496         uinfo->count = 1;
1497         uinfo->value.integer.min = 0;
1498         uinfo->value.integer.max = 1;
1499         return 0;
1500 }
1501
1502 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1503                                struct snd_ctl_elem_value *ucontrol)
1504 {
1505         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1506         int val = 0;
1507
1508         spin_lock_irq(&ensoniq->reg_lock);
1509         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1510                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1511                 val = 1;
1512         ucontrol->value.integer.value[0] = val;
1513         spin_unlock_irq(&ensoniq->reg_lock);
1514         return 0;
1515 }
1516
1517 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1518                                struct snd_ctl_elem_value *ucontrol)
1519 {
1520         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1521         unsigned int nval1;
1522         int change;
1523
1524         nval1 = ucontrol->value.integer.value[0] ?
1525                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1526         spin_lock_irq(&ensoniq->reg_lock);
1527         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1528                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1529         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1530         ensoniq->cssr |= nval1;
1531         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1532         spin_unlock_irq(&ensoniq->reg_lock);
1533         return change;
1534 }
1535
1536 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1537 {
1538         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1539         .name =         "AC97 2ch->4ch Copy Switch",
1540         .info =         snd_es1373_rear_info,
1541         .get =          snd_es1373_rear_get,
1542         .put =          snd_es1373_rear_put,
1543 };
1544
1545 static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1546                                 struct snd_ctl_elem_info *uinfo)
1547 {
1548         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1549         uinfo->count = 1;
1550         uinfo->value.integer.min = 0;
1551         uinfo->value.integer.max = 1;
1552         return 0;
1553 }
1554
1555 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1556                                struct snd_ctl_elem_value *ucontrol)
1557 {
1558         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1559         int val = 0;
1560
1561         spin_lock_irq(&ensoniq->reg_lock);
1562         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1563                 val = 1;
1564         ucontrol->value.integer.value[0] = val;
1565         spin_unlock_irq(&ensoniq->reg_lock);
1566         return 0;
1567 }
1568
1569 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1570                                struct snd_ctl_elem_value *ucontrol)
1571 {
1572         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1573         int changed;
1574         unsigned int ctrl;
1575
1576         spin_lock_irq(&ensoniq->reg_lock);
1577         ctrl = ensoniq->ctrl;
1578         if (ucontrol->value.integer.value[0])
1579                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1580         else
1581                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1582         changed = (ctrl != ensoniq->ctrl);
1583         if (changed)
1584                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1585         spin_unlock_irq(&ensoniq->reg_lock);
1586         return changed;
1587 }
1588
1589 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1590 {
1591         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1592         .name =         "Line In->Rear Out Switch",
1593         .info =         snd_es1373_line_info,
1594         .get =          snd_es1373_line_get,
1595         .put =          snd_es1373_line_put,
1596 };
1597
1598 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1599 {
1600         struct ensoniq *ensoniq = ac97->private_data;
1601         ensoniq->u.es1371.ac97 = NULL;
1602 }
1603
1604 struct es1371_quirk {
1605         unsigned short vid;             /* vendor ID */
1606         unsigned short did;             /* device ID */
1607         unsigned char rev;              /* revision */
1608 };
1609
1610 static int __devinit es1371_quirk_lookup(struct ensoniq *ensoniq,
1611                                          struct es1371_quirk *list)
1612 {
1613         while (list->vid != (unsigned short)PCI_ANY_ID) {
1614                 if (ensoniq->pci->vendor == list->vid &&
1615                     ensoniq->pci->device == list->did &&
1616                     ensoniq->rev == list->rev)
1617                         return 1;
1618                 list++;
1619         }
1620         return 0;
1621 }
1622
1623 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1624         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1625         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1626         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1627         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1628         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1629         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1630 };
1631
1632 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1633         SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1634         SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1635         { } /* end */
1636 };
1637
1638 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1639                                             int has_spdif, int has_line)
1640 {
1641         struct snd_card *card = ensoniq->card;
1642         struct snd_ac97_bus *pbus;
1643         struct snd_ac97_template ac97;
1644         int err;
1645         static struct snd_ac97_bus_ops ops = {
1646                 .write = snd_es1371_codec_write,
1647                 .read = snd_es1371_codec_read,
1648                 .wait = snd_es1371_codec_wait,
1649         };
1650
1651         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1652                 return err;
1653
1654         memset(&ac97, 0, sizeof(ac97));
1655         ac97.private_data = ensoniq;
1656         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1657         ac97.scaps = AC97_SCAP_AUDIO;
1658         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1659                 return err;
1660         if (has_spdif > 0 ||
1661             (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1662                 struct snd_kcontrol *kctl;
1663                 int i, index = 0;
1664
1665                 ensoniq->spdif_default = ensoniq->spdif_stream =
1666                         SNDRV_PCM_DEFAULT_CON_SPDIF;
1667                 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1668
1669                 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1670                         index++;
1671
1672                 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1673                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1674                         if (!kctl)
1675                                 return -ENOMEM;
1676                         kctl->id.index = index;
1677                         err = snd_ctl_add(card, kctl);
1678                         if (err < 0)
1679                                 return err;
1680                 }
1681         }
1682         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1683                 /* mirror rear to front speakers */
1684                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1685                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1686                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1687                 if (err < 0)
1688                         return err;
1689         }
1690         if (has_line > 0 ||
1691             snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1692                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1693                                                       ensoniq));
1694                  if (err < 0)
1695                          return err;
1696         }
1697
1698         return 0;
1699 }
1700
1701 #endif /* CHIP1371 */
1702
1703 /* generic control callbacks for ens1370 */
1704 #ifdef CHIP1370
1705 #define ENSONIQ_CONTROL(xname, mask) \
1706 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1707   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1708   .private_value = mask }
1709
1710 static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1711                                     struct snd_ctl_elem_info *uinfo)
1712 {
1713         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1714         uinfo->count = 1;
1715         uinfo->value.integer.min = 0;
1716         uinfo->value.integer.max = 1;
1717         return 0;
1718 }
1719
1720 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1721                                    struct snd_ctl_elem_value *ucontrol)
1722 {
1723         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1724         int mask = kcontrol->private_value;
1725
1726         spin_lock_irq(&ensoniq->reg_lock);
1727         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1728         spin_unlock_irq(&ensoniq->reg_lock);
1729         return 0;
1730 }
1731
1732 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1733                                    struct snd_ctl_elem_value *ucontrol)
1734 {
1735         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1736         int mask = kcontrol->private_value;
1737         unsigned int nval;
1738         int change;
1739
1740         nval = ucontrol->value.integer.value[0] ? mask : 0;
1741         spin_lock_irq(&ensoniq->reg_lock);
1742         change = (ensoniq->ctrl & mask) != nval;
1743         ensoniq->ctrl &= ~mask;
1744         ensoniq->ctrl |= nval;
1745         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1746         spin_unlock_irq(&ensoniq->reg_lock);
1747         return change;
1748 }
1749
1750 /*
1751  * ENS1370 mixer
1752  */
1753
1754 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1755 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1756 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1757 };
1758
1759 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1760
1761 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1762 {
1763         struct ensoniq *ensoniq = ak4531->private_data;
1764         ensoniq->u.es1370.ak4531 = NULL;
1765 }
1766
1767 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1768 {
1769         struct snd_card *card = ensoniq->card;
1770         struct snd_ak4531 ak4531;
1771         unsigned int idx;
1772         int err;
1773
1774         /* try reset AK4531 */
1775         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1776         inw(ES_REG(ensoniq, 1370_CODEC));
1777         udelay(100);
1778         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1779         inw(ES_REG(ensoniq, 1370_CODEC));
1780         udelay(100);
1781
1782         memset(&ak4531, 0, sizeof(ak4531));
1783         ak4531.write = snd_es1370_codec_write;
1784         ak4531.private_data = ensoniq;
1785         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1786         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1787                 return err;
1788         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1789                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1790                 if (err < 0)
1791                         return err;
1792         }
1793         return 0;
1794 }
1795
1796 #endif /* CHIP1370 */
1797
1798 #ifdef SUPPORT_JOYSTICK
1799
1800 #ifdef CHIP1371
1801 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1802 {
1803         switch (joystick_port[dev]) {
1804         case 0: /* disabled */
1805         case 1: /* auto-detect */
1806         case 0x200:
1807         case 0x208:
1808         case 0x210:
1809         case 0x218:
1810                 return joystick_port[dev];
1811
1812         default:
1813                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1814                 return 0;
1815         }
1816 }
1817 #else
1818 static inline int snd_ensoniq_get_joystick_port(int dev)
1819 {
1820         return joystick[dev] ? 0x200 : 0;
1821 }
1822 #endif
1823
1824 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1825 {
1826         struct gameport *gp;
1827         int io_port;
1828
1829         io_port = snd_ensoniq_get_joystick_port(dev);
1830
1831         switch (io_port) {
1832         case 0:
1833                 return -ENOSYS;
1834
1835         case 1: /* auto_detect */
1836                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1837                         if (request_region(io_port, 8, "ens137x: gameport"))
1838                                 break;
1839                 if (io_port > 0x218) {
1840                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1841                         return -EBUSY;
1842                 }
1843                 break;
1844
1845         default:
1846                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1847                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1848                                io_port);
1849                         return -EBUSY;
1850                 }
1851                 break;
1852         }
1853
1854         ensoniq->gameport = gp = gameport_allocate_port();
1855         if (!gp) {
1856                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1857                 release_region(io_port, 8);
1858                 return -ENOMEM;
1859         }
1860
1861         gameport_set_name(gp, "ES137x");
1862         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1863         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1864         gp->io = io_port;
1865
1866         ensoniq->ctrl |= ES_JYSTK_EN;
1867 #ifdef CHIP1371
1868         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1869         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1870 #endif
1871         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1872
1873         gameport_register_port(ensoniq->gameport);
1874
1875         return 0;
1876 }
1877
1878 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1879 {
1880         if (ensoniq->gameport) {
1881                 int port = ensoniq->gameport->io;
1882
1883                 gameport_unregister_port(ensoniq->gameport);
1884                 ensoniq->gameport = NULL;
1885                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1886                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1887                 release_region(port, 8);
1888         }
1889 }
1890 #else
1891 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1892 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1893 #endif /* SUPPORT_JOYSTICK */
1894
1895 /*
1896
1897  */
1898
1899 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1900                                   struct snd_info_buffer *buffer)
1901 {
1902         struct ensoniq *ensoniq = entry->private_data;
1903
1904 #ifdef CHIP1370
1905         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1906 #else
1907         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1908 #endif
1909         snd_iprintf(buffer, "Joystick enable  : %s\n",
1910                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1911 #ifdef CHIP1370
1912         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1913                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1914         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1915                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1916 #else
1917         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1918                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1919 #endif
1920 }
1921
1922 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1923 {
1924         struct snd_info_entry *entry;
1925
1926         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1927                 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1928 }
1929
1930 /*
1931
1932  */
1933
1934 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1935 {
1936         snd_ensoniq_free_gameport(ensoniq);
1937         if (ensoniq->irq < 0)
1938                 goto __hw_end;
1939 #ifdef CHIP1370
1940         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1941         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1942 #else
1943         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1944         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1945 #endif
1946         synchronize_irq(ensoniq->irq);
1947         pci_set_power_state(ensoniq->pci, 3);
1948       __hw_end:
1949 #ifdef CHIP1370
1950         if (ensoniq->dma_bug.area)
1951                 snd_dma_free_pages(&ensoniq->dma_bug);
1952 #endif
1953         if (ensoniq->irq >= 0)
1954                 free_irq(ensoniq->irq, ensoniq);
1955         pci_release_regions(ensoniq->pci);
1956         pci_disable_device(ensoniq->pci);
1957         kfree(ensoniq);
1958         return 0;
1959 }
1960
1961 static int snd_ensoniq_dev_free(struct snd_device *device)
1962 {
1963         struct ensoniq *ensoniq = device->device_data;
1964         return snd_ensoniq_free(ensoniq);
1965 }
1966
1967 #ifdef CHIP1371
1968 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1969         SND_PCI_QUIRK_ID(0x107b, 0x2150),       /* Gateway Solo 2150 */
1970         SND_PCI_QUIRK_ID(0x13bd, 0x100c),       /* EV1938 on Mebius PC-MJ100V */
1971         SND_PCI_QUIRK_ID(0x1102, 0x5938),       /* Targa Xtender300 */
1972         SND_PCI_QUIRK_ID(0x1102, 0x8938),       /* IPC Topnote G notebook */
1973         { } /* end */
1974 };
1975
1976 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1977         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1978         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1979         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1980         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1981         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1982         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1983 };
1984 #endif
1985
1986 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1987 {
1988 #ifdef CHIP1371
1989         int idx;
1990 #endif
1991         /* this code was part of snd_ensoniq_create before intruduction
1992           * of suspend/resume
1993           */
1994 #ifdef CHIP1370
1995         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1996         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1997         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1998         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1999         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
2000 #else
2001         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2002         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2003         outl(0, ES_REG(ensoniq, 1371_LEGACY));
2004         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
2005             outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2006             /* need to delay around 20ms(bleech) to give
2007                some CODECs enough time to wakeup */
2008             msleep(20);
2009         }
2010         /* AC'97 warm reset to start the bitclk */
2011         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2012         inl(ES_REG(ensoniq, CONTROL));
2013         udelay(20);
2014         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2015         /* Init the sample rate converter */
2016         snd_es1371_wait_src_ready(ensoniq);
2017         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2018         for (idx = 0; idx < 0x80; idx++)
2019                 snd_es1371_src_write(ensoniq, idx, 0);
2020         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2021         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2022         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2023         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2024         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2025         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2026         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2027         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2028         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2029         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2030         snd_es1371_adc_rate(ensoniq, 22050);
2031         snd_es1371_dac1_rate(ensoniq, 22050);
2032         snd_es1371_dac2_rate(ensoniq, 22050);
2033         /* WARNING:
2034          * enabling the sample rate converter without properly programming
2035          * its parameters causes the chip to lock up (the SRC busy bit will
2036          * be stuck high, and I've found no way to rectify this other than
2037          * power cycle) - Thomas Sailer
2038          */
2039         snd_es1371_wait_src_ready(ensoniq);
2040         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2041         /* try reset codec directly */
2042         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2043 #endif
2044         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2045         outb(0x00, ES_REG(ensoniq, UART_RES));
2046         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2047         synchronize_irq(ensoniq->irq);
2048 }
2049
2050 #ifdef CONFIG_PM
2051 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2052 {
2053         struct snd_card *card = pci_get_drvdata(pci);
2054         struct ensoniq *ensoniq = card->private_data;
2055
2056         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2057
2058         snd_pcm_suspend_all(ensoniq->pcm1);
2059         snd_pcm_suspend_all(ensoniq->pcm2);
2060
2061 #ifdef CHIP1371
2062         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2063 #else
2064         /* try to reset AK4531 */
2065         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2066         inw(ES_REG(ensoniq, 1370_CODEC));
2067         udelay(100);
2068         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2069         inw(ES_REG(ensoniq, 1370_CODEC));
2070         udelay(100);
2071         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2072 #endif
2073
2074         pci_disable_device(pci);
2075         pci_save_state(pci);
2076         pci_set_power_state(pci, pci_choose_state(pci, state));
2077         return 0;
2078 }
2079
2080 static int snd_ensoniq_resume(struct pci_dev *pci)
2081 {
2082         struct snd_card *card = pci_get_drvdata(pci);
2083         struct ensoniq *ensoniq = card->private_data;
2084
2085         pci_set_power_state(pci, PCI_D0);
2086         pci_restore_state(pci);
2087         if (pci_enable_device(pci) < 0) {
2088                 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2089                        "disabling device\n");
2090                 snd_card_disconnect(card);
2091                 return -EIO;
2092         }
2093         pci_set_master(pci);
2094
2095         snd_ensoniq_chip_init(ensoniq);
2096
2097 #ifdef CHIP1371
2098         snd_ac97_resume(ensoniq->u.es1371.ac97);
2099 #else
2100         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2101 #endif
2102         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2103         return 0;
2104 }
2105 #endif /* CONFIG_PM */
2106
2107
2108 static int __devinit snd_ensoniq_create(struct snd_card *card,
2109                                      struct pci_dev *pci,
2110                                      struct ensoniq ** rensoniq)
2111 {
2112         struct ensoniq *ensoniq;
2113         unsigned char cmdb;
2114         int err;
2115         static struct snd_device_ops ops = {
2116                 .dev_free =     snd_ensoniq_dev_free,
2117         };
2118
2119         *rensoniq = NULL;
2120         if ((err = pci_enable_device(pci)) < 0)
2121                 return err;
2122         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2123         if (ensoniq == NULL) {
2124                 pci_disable_device(pci);
2125                 return -ENOMEM;
2126         }
2127         spin_lock_init(&ensoniq->reg_lock);
2128         mutex_init(&ensoniq->src_mutex);
2129         ensoniq->card = card;
2130         ensoniq->pci = pci;
2131         ensoniq->irq = -1;
2132         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2133                 kfree(ensoniq);
2134                 pci_disable_device(pci);
2135                 return err;
2136         }
2137         ensoniq->port = pci_resource_start(pci, 0);
2138         if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2139                         "Ensoniq AudioPCI", ensoniq)) {
2140                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2141                 snd_ensoniq_free(ensoniq);
2142                 return -EBUSY;
2143         }
2144         ensoniq->irq = pci->irq;
2145 #ifdef CHIP1370
2146         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2147                                 16, &ensoniq->dma_bug) < 0) {
2148                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2149                 snd_ensoniq_free(ensoniq);
2150                 return -EBUSY;
2151         }
2152 #endif
2153         pci_set_master(pci);
2154         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2155         ensoniq->rev = cmdb;
2156 #ifdef CHIP1370
2157 #if 0
2158         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2159                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2160 #else   /* get microphone working */
2161         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2162 #endif
2163         ensoniq->sctrl = 0;
2164 #else
2165         ensoniq->ctrl = 0;
2166         ensoniq->sctrl = 0;
2167         ensoniq->cssr = 0;
2168         if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2169                 ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2170
2171         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2172                 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2173 #endif
2174
2175         snd_ensoniq_chip_init(ensoniq);
2176
2177         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2178                 snd_ensoniq_free(ensoniq);
2179                 return err;
2180         }
2181
2182         snd_ensoniq_proc_init(ensoniq);
2183
2184         snd_card_set_dev(card, &pci->dev);
2185
2186         *rensoniq = ensoniq;
2187         return 0;
2188 }
2189
2190 /*
2191  *  MIDI section
2192  */
2193
2194 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2195 {
2196         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2197         unsigned char status, mask, byte;
2198
2199         if (rmidi == NULL)
2200                 return;
2201         /* do Rx at first */
2202         spin_lock(&ensoniq->reg_lock);
2203         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2204         while (mask) {
2205                 status = inb(ES_REG(ensoniq, UART_STATUS));
2206                 if ((status & mask) == 0)
2207                         break;
2208                 byte = inb(ES_REG(ensoniq, UART_DATA));
2209                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2210         }
2211         spin_unlock(&ensoniq->reg_lock);
2212
2213         /* do Tx at second */
2214         spin_lock(&ensoniq->reg_lock);
2215         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2216         while (mask) {
2217                 status = inb(ES_REG(ensoniq, UART_STATUS));
2218                 if ((status & mask) == 0)
2219                         break;
2220                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2221                         ensoniq->uartc &= ~ES_TXINTENM;
2222                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2223                         mask &= ~ES_TXRDY;
2224                 } else {
2225                         outb(byte, ES_REG(ensoniq, UART_DATA));
2226                 }
2227         }
2228         spin_unlock(&ensoniq->reg_lock);
2229 }
2230
2231 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2232 {
2233         struct ensoniq *ensoniq = substream->rmidi->private_data;
2234
2235         spin_lock_irq(&ensoniq->reg_lock);
2236         ensoniq->uartm |= ES_MODE_INPUT;
2237         ensoniq->midi_input = substream;
2238         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2239                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2240                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2241                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2242         }
2243         spin_unlock_irq(&ensoniq->reg_lock);
2244         return 0;
2245 }
2246
2247 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2248 {
2249         struct ensoniq *ensoniq = substream->rmidi->private_data;
2250
2251         spin_lock_irq(&ensoniq->reg_lock);
2252         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2253                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2254                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2255         } else {
2256                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2257         }
2258         ensoniq->midi_input = NULL;
2259         ensoniq->uartm &= ~ES_MODE_INPUT;
2260         spin_unlock_irq(&ensoniq->reg_lock);
2261         return 0;
2262 }
2263
2264 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2265 {
2266         struct ensoniq *ensoniq = substream->rmidi->private_data;
2267
2268         spin_lock_irq(&ensoniq->reg_lock);
2269         ensoniq->uartm |= ES_MODE_OUTPUT;
2270         ensoniq->midi_output = substream;
2271         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2272                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2273                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2274                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2275         }
2276         spin_unlock_irq(&ensoniq->reg_lock);
2277         return 0;
2278 }
2279
2280 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2281 {
2282         struct ensoniq *ensoniq = substream->rmidi->private_data;
2283
2284         spin_lock_irq(&ensoniq->reg_lock);
2285         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2286                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2287                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2288         } else {
2289                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2290         }
2291         ensoniq->midi_output = NULL;
2292         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2293         spin_unlock_irq(&ensoniq->reg_lock);
2294         return 0;
2295 }
2296
2297 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2298 {
2299         unsigned long flags;
2300         struct ensoniq *ensoniq = substream->rmidi->private_data;
2301         int idx;
2302
2303         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2304         if (up) {
2305                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2306                         /* empty input FIFO */
2307                         for (idx = 0; idx < 32; idx++)
2308                                 inb(ES_REG(ensoniq, UART_DATA));
2309                         ensoniq->uartc |= ES_RXINTEN;
2310                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2311                 }
2312         } else {
2313                 if (ensoniq->uartc & ES_RXINTEN) {
2314                         ensoniq->uartc &= ~ES_RXINTEN;
2315                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2316                 }
2317         }
2318         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2319 }
2320
2321 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2322 {
2323         unsigned long flags;
2324         struct ensoniq *ensoniq = substream->rmidi->private_data;
2325         unsigned char byte;
2326
2327         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2328         if (up) {
2329                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2330                         ensoniq->uartc |= ES_TXINTENO(1);
2331                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2332                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2333                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2334                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2335                                         ensoniq->uartc &= ~ES_TXINTENM;
2336                                 } else {
2337                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2338                                 }
2339                         }
2340                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2341                 }
2342         } else {
2343                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2344                         ensoniq->uartc &= ~ES_TXINTENM;
2345                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2346                 }
2347         }
2348         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2349 }
2350
2351 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2352 {
2353         .open =         snd_ensoniq_midi_output_open,
2354         .close =        snd_ensoniq_midi_output_close,
2355         .trigger =      snd_ensoniq_midi_output_trigger,
2356 };
2357
2358 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2359 {
2360         .open =         snd_ensoniq_midi_input_open,
2361         .close =        snd_ensoniq_midi_input_close,
2362         .trigger =      snd_ensoniq_midi_input_trigger,
2363 };
2364
2365 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2366                                       struct snd_rawmidi **rrawmidi)
2367 {
2368         struct snd_rawmidi *rmidi;
2369         int err;
2370
2371         if (rrawmidi)
2372                 *rrawmidi = NULL;
2373         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2374                 return err;
2375 #ifdef CHIP1370
2376         strcpy(rmidi->name, "ES1370");
2377 #else
2378         strcpy(rmidi->name, "ES1371");
2379 #endif
2380         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2381         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2382         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2383                 SNDRV_RAWMIDI_INFO_DUPLEX;
2384         rmidi->private_data = ensoniq;
2385         ensoniq->rmidi = rmidi;
2386         if (rrawmidi)
2387                 *rrawmidi = rmidi;
2388         return 0;
2389 }
2390
2391 /*
2392  *  Interrupt handler
2393  */
2394
2395 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2396 {
2397         struct ensoniq *ensoniq = dev_id;
2398         unsigned int status, sctrl;
2399
2400         if (ensoniq == NULL)
2401                 return IRQ_NONE;
2402
2403         status = inl(ES_REG(ensoniq, STATUS));
2404         if (!(status & ES_INTR))
2405                 return IRQ_NONE;
2406
2407         spin_lock(&ensoniq->reg_lock);
2408         sctrl = ensoniq->sctrl;
2409         if (status & ES_DAC1)
2410                 sctrl &= ~ES_P1_INT_EN;
2411         if (status & ES_DAC2)
2412                 sctrl &= ~ES_P2_INT_EN;
2413         if (status & ES_ADC)
2414                 sctrl &= ~ES_R1_INT_EN;
2415         outl(sctrl, ES_REG(ensoniq, SERIAL));
2416         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2417         spin_unlock(&ensoniq->reg_lock);
2418
2419         if (status & ES_UART)
2420                 snd_ensoniq_midi_interrupt(ensoniq);
2421         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2422                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2423         if ((status & ES_ADC) && ensoniq->capture_substream)
2424                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2425         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2426                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2427         return IRQ_HANDLED;
2428 }
2429
2430 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2431                                         const struct pci_device_id *pci_id)
2432 {
2433         static int dev;
2434         struct snd_card *card;
2435         struct ensoniq *ensoniq;
2436         int err, pcm_devs[2];
2437
2438         if (dev >= SNDRV_CARDS)
2439                 return -ENODEV;
2440         if (!enable[dev]) {
2441                 dev++;
2442                 return -ENOENT;
2443         }
2444
2445         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2446         if (card == NULL)
2447                 return -ENOMEM;
2448
2449         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2450                 snd_card_free(card);
2451                 return err;
2452         }
2453         card->private_data = ensoniq;
2454
2455         pcm_devs[0] = 0; pcm_devs[1] = 1;
2456 #ifdef CHIP1370
2457         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2458                 snd_card_free(card);
2459                 return err;
2460         }
2461 #endif
2462 #ifdef CHIP1371
2463         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2464                 snd_card_free(card);
2465                 return err;
2466         }
2467 #endif
2468         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2469                 snd_card_free(card);
2470                 return err;
2471         }
2472         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2473                 snd_card_free(card);
2474                 return err;
2475         }
2476         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2477                 snd_card_free(card);
2478                 return err;
2479         }
2480
2481         snd_ensoniq_create_gameport(ensoniq, dev);
2482
2483         strcpy(card->driver, DRIVER_NAME);
2484
2485         strcpy(card->shortname, "Ensoniq AudioPCI");
2486         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2487                 card->shortname,
2488                 card->driver,
2489                 ensoniq->port,
2490                 ensoniq->irq);
2491
2492         if ((err = snd_card_register(card)) < 0) {
2493                 snd_card_free(card);
2494                 return err;
2495         }
2496
2497         pci_set_drvdata(pci, card);
2498         dev++;
2499         return 0;
2500 }
2501
2502 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2503 {
2504         snd_card_free(pci_get_drvdata(pci));
2505         pci_set_drvdata(pci, NULL);
2506 }
2507
2508 static struct pci_driver driver = {
2509         .name = DRIVER_NAME,
2510         .id_table = snd_audiopci_ids,
2511         .probe = snd_audiopci_probe,
2512         .remove = __devexit_p(snd_audiopci_remove),
2513 #ifdef CONFIG_PM
2514         .suspend = snd_ensoniq_suspend,
2515         .resume = snd_ensoniq_resume,
2516 #endif
2517 };
2518
2519 static int __init alsa_card_ens137x_init(void)
2520 {
2521         return pci_register_driver(&driver);
2522 }
2523
2524 static void __exit alsa_card_ens137x_exit(void)
2525 {
2526         pci_unregister_driver(&driver);
2527 }
2528
2529 module_init(alsa_card_ens137x_init)
2530 module_exit(alsa_card_ens137x_exit)