219795171c714796df5aaa51f740abd75fad7116
[sfrench/cifs-2.6.git] / sound / oss / au1550_ac97.c
1 /*
2  * au1550_ac97.c  --  Sound driver for Alchemy Au1550 MIPS Internet Edge
3  *                    Processor.
4  *
5  * Copyright 2004 Embedded Edge, LLC
6  *      dan@embeddededge.com
7  *
8  * Mostly copied from the au1000.c driver and some from the
9  * PowerMac dbdma driver.
10  * We assume the processor can do memory coherent DMA.
11  *
12  * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13  *
14  *  This program is free software; you can redistribute  it and/or modify it
15  *  under  the terms of  the GNU General  Public License as published by the
16  *  Free Software Foundation;  either version 2 of the  License, or (at your
17  *  option) any later version.
18  *
19  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
20  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
21  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
22  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
23  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
25  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
27  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  *  You should have received a copy of the  GNU General Public License along
31  *  with this program; if not, write  to the Free Software Foundation, Inc.,
32  *  675 Mass Ave, Cambridge, MA 02139, USA.
33  *
34  */
35
36 #undef DEBUG
37
38 #include <linux/module.h>
39 #include <linux/string.h>
40 #include <linux/ioport.h>
41 #include <linux/sched.h>
42 #include <linux/delay.h>
43 #include <linux/sound.h>
44 #include <linux/slab.h>
45 #include <linux/soundcard.h>
46 #include <linux/init.h>
47 #include <linux/interrupt.h>
48 #include <linux/kernel.h>
49 #include <linux/poll.h>
50 #include <linux/pci.h>
51 #include <linux/bitops.h>
52 #include <linux/spinlock.h>
53 #include <linux/smp_lock.h>
54 #include <linux/ac97_codec.h>
55 #include <linux/mutex.h>
56
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59 #include <asm/hardirq.h>
60 #include <asm/mach-au1x00/au1xxx_psc.h>
61 #include <asm/mach-au1x00/au1xxx_dbdma.h>
62 #include <asm/mach-au1x00/au1xxx.h>
63
64 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
65
66 /* misc stuff */
67 #define POLL_COUNT   0x50000
68 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
69
70 /* The number of DBDMA ring descriptors to allocate.  No sense making
71  * this too large....if you can't keep up with a few you aren't likely
72  * to be able to with lots of them, either.
73  */
74 #define NUM_DBDMA_DESCRIPTORS 4
75
76 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
77
78 /* Boot options
79  * 0 = no VRA, 1 = use VRA if codec supports it
80  */
81 static int      vra = 1;
82 module_param(vra, bool, 0);
83 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
84
85 static struct au1550_state {
86         /* soundcore stuff */
87         int             dev_audio;
88
89         struct ac97_codec *codec;
90         unsigned        codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
91         unsigned        codec_ext_caps;  /* AC'97 reg 28h, "Extended Audio ID" */
92         int             no_vra;         /* do not use VRA */
93
94         spinlock_t      lock;
95         struct mutex open_mutex;
96         struct mutex sem;
97         mode_t          open_mode;
98         wait_queue_head_t open_wait;
99
100         struct dmabuf {
101                 u32             dmanr;
102                 unsigned        sample_rate;
103                 unsigned        src_factor;
104                 unsigned        sample_size;
105                 int             num_channels;
106                 int             dma_bytes_per_sample;
107                 int             user_bytes_per_sample;
108                 int             cnt_factor;
109
110                 void            *rawbuf;
111                 unsigned        buforder;
112                 unsigned        numfrag;
113                 unsigned        fragshift;
114                 void            *nextIn;
115                 void            *nextOut;
116                 int             count;
117                 unsigned        total_bytes;
118                 unsigned        error;
119                 wait_queue_head_t wait;
120
121                 /* redundant, but makes calculations easier */
122                 unsigned        fragsize;
123                 unsigned        dma_fragsize;
124                 unsigned        dmasize;
125                 unsigned        dma_qcount;
126
127                 /* OSS stuff */
128                 unsigned        mapped:1;
129                 unsigned        ready:1;
130                 unsigned        stopped:1;
131                 unsigned        ossfragshift;
132                 int             ossmaxfrags;
133                 unsigned        subdivision;
134         } dma_dac, dma_adc;
135 } au1550_state;
136
137 static unsigned
138 ld2(unsigned int x)
139 {
140         unsigned        r = 0;
141
142         if (x >= 0x10000) {
143                 x >>= 16;
144                 r += 16;
145         }
146         if (x >= 0x100) {
147                 x >>= 8;
148                 r += 8;
149         }
150         if (x >= 0x10) {
151                 x >>= 4;
152                 r += 4;
153         }
154         if (x >= 4) {
155                 x >>= 2;
156                 r += 2;
157         }
158         if (x >= 2)
159                 r++;
160         return r;
161 }
162
163 static void
164 au1550_delay(int msec)
165 {
166         unsigned long   tmo;
167         signed long     tmo2;
168
169         if (in_interrupt())
170                 return;
171
172         tmo = jiffies + (msec * HZ) / 1000;
173         for (;;) {
174                 tmo2 = tmo - jiffies;
175                 if (tmo2 <= 0)
176                         break;
177                 schedule_timeout(tmo2);
178         }
179 }
180
181 static u16
182 rdcodec(struct ac97_codec *codec, u8 addr)
183 {
184         struct au1550_state *s = (struct au1550_state *)codec->private_data;
185         unsigned long   flags;
186         u32             cmd, val;
187         u16             data;
188         int             i;
189
190         spin_lock_irqsave(&s->lock, flags);
191
192         for (i = 0; i < POLL_COUNT; i++) {
193                 val = au_readl(PSC_AC97STAT);
194                 au_sync();
195                 if (!(val & PSC_AC97STAT_CP))
196                         break;
197         }
198         if (i == POLL_COUNT)
199                 err("rdcodec: codec cmd pending expired!");
200
201         cmd = (u32)PSC_AC97CDC_INDX(addr);
202         cmd |= PSC_AC97CDC_RD;  /* read command */
203         au_writel(cmd, PSC_AC97CDC);
204         au_sync();
205
206         /* now wait for the data
207         */
208         for (i = 0; i < POLL_COUNT; i++) {
209                 val = au_readl(PSC_AC97STAT);
210                 au_sync();
211                 if (!(val & PSC_AC97STAT_CP))
212                         break;
213         }
214         if (i == POLL_COUNT) {
215                 err("rdcodec: read poll expired!");
216                 data = 0;
217                 goto out;
218         }
219
220         /* wait for command done?
221         */
222         for (i = 0; i < POLL_COUNT; i++) {
223                 val = au_readl(PSC_AC97EVNT);
224                 au_sync();
225                 if (val & PSC_AC97EVNT_CD)
226                         break;
227         }
228         if (i == POLL_COUNT) {
229                 err("rdcodec: read cmdwait expired!");
230                 data = 0;
231                 goto out;
232         }
233
234         data = au_readl(PSC_AC97CDC) & 0xffff;
235         au_sync();
236
237         /* Clear command done event.
238         */
239         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
240         au_sync();
241
242  out:
243         spin_unlock_irqrestore(&s->lock, flags);
244
245         return data;
246 }
247
248
249 static void
250 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
251 {
252         struct au1550_state *s = (struct au1550_state *)codec->private_data;
253         unsigned long   flags;
254         u32             cmd, val;
255         int             i;
256
257         spin_lock_irqsave(&s->lock, flags);
258
259         for (i = 0; i < POLL_COUNT; i++) {
260                 val = au_readl(PSC_AC97STAT);
261                 au_sync();
262                 if (!(val & PSC_AC97STAT_CP))
263                         break;
264         }
265         if (i == POLL_COUNT)
266                 err("wrcodec: codec cmd pending expired!");
267
268         cmd = (u32)PSC_AC97CDC_INDX(addr);
269         cmd |= (u32)data;
270         au_writel(cmd, PSC_AC97CDC);
271         au_sync();
272
273         for (i = 0; i < POLL_COUNT; i++) {
274                 val = au_readl(PSC_AC97STAT);
275                 au_sync();
276                 if (!(val & PSC_AC97STAT_CP))
277                         break;
278         }
279         if (i == POLL_COUNT)
280                 err("wrcodec: codec cmd pending expired!");
281
282         for (i = 0; i < POLL_COUNT; i++) {
283                 val = au_readl(PSC_AC97EVNT);
284                 au_sync();
285                 if (val & PSC_AC97EVNT_CD)
286                         break;
287         }
288         if (i == POLL_COUNT)
289                 err("wrcodec: read cmdwait expired!");
290
291         /* Clear command done event.
292         */
293         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
294         au_sync();
295
296         spin_unlock_irqrestore(&s->lock, flags);
297 }
298
299 static void
300 waitcodec(struct ac97_codec *codec)
301 {
302         u16     temp;
303         u32     val;
304         int     i;
305
306         /* codec_wait is used to wait for a ready state after
307          * an AC97C_RESET.
308          */
309         au1550_delay(10);
310
311         /* first poll the CODEC_READY tag bit
312         */
313         for (i = 0; i < POLL_COUNT; i++) {
314                 val = au_readl(PSC_AC97STAT);
315                 au_sync();
316                 if (val & PSC_AC97STAT_CR)
317                         break;
318         }
319         if (i == POLL_COUNT) {
320                 err("waitcodec: CODEC_READY poll expired!");
321                 return;
322         }
323
324         /* get AC'97 powerdown control/status register
325         */
326         temp = rdcodec(codec, AC97_POWER_CONTROL);
327
328         /* If anything is powered down, power'em up
329         */
330         if (temp & 0x7f00) {
331                 /* Power on
332                 */
333                 wrcodec(codec, AC97_POWER_CONTROL, 0);
334                 au1550_delay(100);
335
336                 /* Reread
337                 */
338                 temp = rdcodec(codec, AC97_POWER_CONTROL);
339         }
340
341         /* Check if Codec REF,ANL,DAC,ADC ready
342         */
343         if ((temp & 0x7f0f) != 0x000f)
344                 err("codec reg 26 status (0x%x) not ready!!", temp);
345 }
346
347 /* stop the ADC before calling */
348 static void
349 set_adc_rate(struct au1550_state *s, unsigned rate)
350 {
351         struct dmabuf  *adc = &s->dma_adc;
352         struct dmabuf  *dac = &s->dma_dac;
353         unsigned        adc_rate, dac_rate;
354         u16             ac97_extstat;
355
356         if (s->no_vra) {
357                 /* calc SRC factor
358                 */
359                 adc->src_factor = ((96000 / rate) + 1) >> 1;
360                 adc->sample_rate = 48000 / adc->src_factor;
361                 return;
362         }
363
364         adc->src_factor = 1;
365
366         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
367
368         rate = rate > 48000 ? 48000 : rate;
369
370         /* enable VRA
371         */
372         wrcodec(s->codec, AC97_EXTENDED_STATUS,
373                 ac97_extstat | AC97_EXTSTAT_VRA);
374
375         /* now write the sample rate
376         */
377         wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
378
379         /* read it back for actual supported rate
380         */
381         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
382
383         pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
384
385         /* some codec's don't allow unequal DAC and ADC rates, in which case
386          * writing one rate reg actually changes both.
387          */
388         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
389         if (dac->num_channels > 2)
390                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
391         if (dac->num_channels > 4)
392                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
393
394         adc->sample_rate = adc_rate;
395         dac->sample_rate = dac_rate;
396 }
397
398 /* stop the DAC before calling */
399 static void
400 set_dac_rate(struct au1550_state *s, unsigned rate)
401 {
402         struct dmabuf  *dac = &s->dma_dac;
403         struct dmabuf  *adc = &s->dma_adc;
404         unsigned        adc_rate, dac_rate;
405         u16             ac97_extstat;
406
407         if (s->no_vra) {
408                 /* calc SRC factor
409                 */
410                 dac->src_factor = ((96000 / rate) + 1) >> 1;
411                 dac->sample_rate = 48000 / dac->src_factor;
412                 return;
413         }
414
415         dac->src_factor = 1;
416
417         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
418
419         rate = rate > 48000 ? 48000 : rate;
420
421         /* enable VRA
422         */
423         wrcodec(s->codec, AC97_EXTENDED_STATUS,
424                 ac97_extstat | AC97_EXTSTAT_VRA);
425
426         /* now write the sample rate
427         */
428         wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
429
430         /* I don't support different sample rates for multichannel,
431          * so make these channels the same.
432          */
433         if (dac->num_channels > 2)
434                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
435         if (dac->num_channels > 4)
436                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
437         /* read it back for actual supported rate
438         */
439         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
440
441         pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
442
443         /* some codec's don't allow unequal DAC and ADC rates, in which case
444          * writing one rate reg actually changes both.
445          */
446         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
447
448         dac->sample_rate = dac_rate;
449         adc->sample_rate = adc_rate;
450 }
451
452 static void
453 stop_dac(struct au1550_state *s)
454 {
455         struct dmabuf  *db = &s->dma_dac;
456         u32             stat;
457         unsigned long   flags;
458
459         if (db->stopped)
460                 return;
461
462         spin_lock_irqsave(&s->lock, flags);
463
464         au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
465         au_sync();
466
467         /* Wait for Transmit Busy to show disabled.
468         */
469         do {
470                 stat = au_readl(PSC_AC97STAT);
471                 au_sync();
472         } while ((stat & PSC_AC97STAT_TB) != 0);
473
474         au1xxx_dbdma_reset(db->dmanr);
475
476         db->stopped = 1;
477
478         spin_unlock_irqrestore(&s->lock, flags);
479 }
480
481 static void
482 stop_adc(struct au1550_state *s)
483 {
484         struct dmabuf  *db = &s->dma_adc;
485         unsigned long   flags;
486         u32             stat;
487
488         if (db->stopped)
489                 return;
490
491         spin_lock_irqsave(&s->lock, flags);
492
493         au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
494         au_sync();
495
496         /* Wait for Receive Busy to show disabled.
497         */
498         do {
499                 stat = au_readl(PSC_AC97STAT);
500                 au_sync();
501         } while ((stat & PSC_AC97STAT_RB) != 0);
502
503         au1xxx_dbdma_reset(db->dmanr);
504
505         db->stopped = 1;
506
507         spin_unlock_irqrestore(&s->lock, flags);
508 }
509
510
511 static void
512 set_xmit_slots(int num_channels)
513 {
514         u32     ac97_config, stat;
515
516         ac97_config = au_readl(PSC_AC97CFG);
517         au_sync();
518         ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
519         au_writel(ac97_config, PSC_AC97CFG);
520         au_sync();
521
522         switch (num_channels) {
523         case 6:         /* stereo with surround and center/LFE,
524                          * slots 3,4,6,7,8,9
525                          */
526                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
527                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
528
529         case 4:         /* stereo with surround, slots 3,4,7,8 */
530                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
531                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
532
533         case 2:         /* stereo, slots 3,4 */
534         case 1:         /* mono */
535                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
536                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
537         }
538
539         au_writel(ac97_config, PSC_AC97CFG);
540         au_sync();
541
542         ac97_config |= PSC_AC97CFG_DE_ENABLE;
543         au_writel(ac97_config, PSC_AC97CFG);
544         au_sync();
545
546         /* Wait for Device ready.
547         */
548         do {
549                 stat = au_readl(PSC_AC97STAT);
550                 au_sync();
551         } while ((stat & PSC_AC97STAT_DR) == 0);
552 }
553
554 static void
555 set_recv_slots(int num_channels)
556 {
557         u32     ac97_config, stat;
558
559         ac97_config = au_readl(PSC_AC97CFG);
560         au_sync();
561         ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
562         au_writel(ac97_config, PSC_AC97CFG);
563         au_sync();
564
565         /* Always enable slots 3 and 4 (stereo). Slot 6 is
566          * optional Mic ADC, which we don't support yet.
567          */
568         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
569         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
570
571         au_writel(ac97_config, PSC_AC97CFG);
572         au_sync();
573
574         ac97_config |= PSC_AC97CFG_DE_ENABLE;
575         au_writel(ac97_config, PSC_AC97CFG);
576         au_sync();
577
578         /* Wait for Device ready.
579         */
580         do {
581                 stat = au_readl(PSC_AC97STAT);
582                 au_sync();
583         } while ((stat & PSC_AC97STAT_DR) == 0);
584 }
585
586 /* Hold spinlock for both start_dac() and start_adc() calls */
587 static void
588 start_dac(struct au1550_state *s)
589 {
590         struct dmabuf  *db = &s->dma_dac;
591
592         if (!db->stopped)
593                 return;
594
595         set_xmit_slots(db->num_channels);
596         au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
597         au_sync();
598         au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
599         au_sync();
600
601         au1xxx_dbdma_start(db->dmanr);
602
603         db->stopped = 0;
604 }
605
606 static void
607 start_adc(struct au1550_state *s)
608 {
609         struct dmabuf  *db = &s->dma_adc;
610         int     i;
611
612         if (!db->stopped)
613                 return;
614
615         /* Put two buffers on the ring to get things started.
616         */
617         for (i=0; i<2; i++) {
618                 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
619
620                 db->nextIn += db->dma_fragsize;
621                 if (db->nextIn >= db->rawbuf + db->dmasize)
622                         db->nextIn -= db->dmasize;
623         }
624
625         set_recv_slots(db->num_channels);
626         au1xxx_dbdma_start(db->dmanr);
627         au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
628         au_sync();
629         au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
630         au_sync();
631
632         db->stopped = 0;
633 }
634
635 static int
636 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
637 {
638         unsigned user_bytes_per_sec;
639         unsigned        bufs;
640         unsigned        rate = db->sample_rate;
641
642         if (!db->rawbuf) {
643                 db->ready = db->mapped = 0;
644                 db->buforder = 5;       /* 32 * PAGE_SIZE */
645                 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
646                 if (!db->rawbuf)
647                         return -ENOMEM;
648         }
649
650         db->cnt_factor = 1;
651         if (db->sample_size == 8)
652                 db->cnt_factor *= 2;
653         if (db->num_channels == 1)
654                 db->cnt_factor *= 2;
655         db->cnt_factor *= db->src_factor;
656
657         db->count = 0;
658         db->dma_qcount = 0;
659         db->nextIn = db->nextOut = db->rawbuf;
660
661         db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
662         db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
663                                         2 : db->num_channels);
664
665         user_bytes_per_sec = rate * db->user_bytes_per_sample;
666         bufs = PAGE_SIZE << db->buforder;
667         if (db->ossfragshift) {
668                 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
669                         db->fragshift = ld2(user_bytes_per_sec/1000);
670                 else
671                         db->fragshift = db->ossfragshift;
672         } else {
673                 db->fragshift = ld2(user_bytes_per_sec / 100 /
674                                     (db->subdivision ? db->subdivision : 1));
675                 if (db->fragshift < 3)
676                         db->fragshift = 3;
677         }
678
679         db->fragsize = 1 << db->fragshift;
680         db->dma_fragsize = db->fragsize * db->cnt_factor;
681         db->numfrag = bufs / db->dma_fragsize;
682
683         while (db->numfrag < 4 && db->fragshift > 3) {
684                 db->fragshift--;
685                 db->fragsize = 1 << db->fragshift;
686                 db->dma_fragsize = db->fragsize * db->cnt_factor;
687                 db->numfrag = bufs / db->dma_fragsize;
688         }
689
690         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
691                 db->numfrag = db->ossmaxfrags;
692
693         db->dmasize = db->dma_fragsize * db->numfrag;
694         memset(db->rawbuf, 0, bufs);
695
696         pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
697             rate, db->sample_size, db->num_channels);
698         pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
699             db->fragsize, db->cnt_factor, db->dma_fragsize);
700         pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
701
702         db->ready = 1;
703         return 0;
704 }
705
706 static int
707 prog_dmabuf_adc(struct au1550_state *s)
708 {
709         stop_adc(s);
710         return prog_dmabuf(s, &s->dma_adc);
711
712 }
713
714 static int
715 prog_dmabuf_dac(struct au1550_state *s)
716 {
717         stop_dac(s);
718         return prog_dmabuf(s, &s->dma_dac);
719 }
720
721
722 static void dac_dma_interrupt(int irq, void *dev_id)
723 {
724         struct au1550_state *s = (struct au1550_state *) dev_id;
725         struct dmabuf  *db = &s->dma_dac;
726         u32     ac97c_stat;
727
728         spin_lock(&s->lock);
729
730         ac97c_stat = au_readl(PSC_AC97STAT);
731         if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
732                 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
733         db->dma_qcount--;
734
735         if (db->count >= db->fragsize) {
736                 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
737                                                         db->fragsize) == 0) {
738                         err("qcount < 2 and no ring room!");
739                 }
740                 db->nextOut += db->fragsize;
741                 if (db->nextOut >= db->rawbuf + db->dmasize)
742                         db->nextOut -= db->dmasize;
743                 db->count -= db->fragsize;
744                 db->total_bytes += db->dma_fragsize;
745                 db->dma_qcount++;
746         }
747
748         /* wake up anybody listening */
749         if (waitqueue_active(&db->wait))
750                 wake_up(&db->wait);
751
752         spin_unlock(&s->lock);
753 }
754
755
756 static void adc_dma_interrupt(int irq, void *dev_id)
757 {
758         struct  au1550_state *s = (struct au1550_state *)dev_id;
759         struct  dmabuf  *dp = &s->dma_adc;
760         u32     obytes;
761         char    *obuf;
762
763         spin_lock(&s->lock);
764
765         /* Pull the buffer from the dma queue.
766         */
767         au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
768
769         if ((dp->count + obytes) > dp->dmasize) {
770                 /* Overrun. Stop ADC and log the error
771                 */
772                 spin_unlock(&s->lock);
773                 stop_adc(s);
774                 dp->error++;
775                 err("adc overrun");
776                 return;
777         }
778
779         /* Put a new empty buffer on the destination DMA.
780         */
781         au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
782
783         dp->nextIn += dp->dma_fragsize;
784         if (dp->nextIn >= dp->rawbuf + dp->dmasize)
785                 dp->nextIn -= dp->dmasize;
786
787         dp->count += obytes;
788         dp->total_bytes += obytes;
789
790         /* wake up anybody listening
791         */
792         if (waitqueue_active(&dp->wait))
793                 wake_up(&dp->wait);
794
795         spin_unlock(&s->lock);
796 }
797
798 static loff_t
799 au1550_llseek(struct file *file, loff_t offset, int origin)
800 {
801         return -ESPIPE;
802 }
803
804
805 static int
806 au1550_open_mixdev(struct inode *inode, struct file *file)
807 {
808         file->private_data = &au1550_state;
809         return 0;
810 }
811
812 static int
813 au1550_release_mixdev(struct inode *inode, struct file *file)
814 {
815         return 0;
816 }
817
818 static int
819 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
820                         unsigned long arg)
821 {
822         return codec->mixer_ioctl(codec, cmd, arg);
823 }
824
825 static int
826 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
827                                unsigned int cmd, unsigned long arg)
828 {
829         struct au1550_state *s = (struct au1550_state *)file->private_data;
830         struct ac97_codec *codec = s->codec;
831
832         return mixdev_ioctl(codec, cmd, arg);
833 }
834
835 static /*const */ struct file_operations au1550_mixer_fops = {
836         owner:THIS_MODULE,
837         llseek:au1550_llseek,
838         ioctl:au1550_ioctl_mixdev,
839         open:au1550_open_mixdev,
840         release:au1550_release_mixdev,
841 };
842
843 static int
844 drain_dac(struct au1550_state *s, int nonblock)
845 {
846         unsigned long   flags;
847         int             count, tmo;
848
849         if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
850                 return 0;
851
852         for (;;) {
853                 spin_lock_irqsave(&s->lock, flags);
854                 count = s->dma_dac.count;
855                 spin_unlock_irqrestore(&s->lock, flags);
856                 if (count <= s->dma_dac.fragsize)
857                         break;
858                 if (signal_pending(current))
859                         break;
860                 if (nonblock)
861                         return -EBUSY;
862                 tmo = 1000 * count / (s->no_vra ?
863                                       48000 : s->dma_dac.sample_rate);
864                 tmo /= s->dma_dac.dma_bytes_per_sample;
865                 au1550_delay(tmo);
866         }
867         if (signal_pending(current))
868                 return -ERESTARTSYS;
869         return 0;
870 }
871
872 static inline u8 S16_TO_U8(s16 ch)
873 {
874         return (u8) (ch >> 8) + 0x80;
875 }
876 static inline s16 U8_TO_S16(u8 ch)
877 {
878         return (s16) (ch - 0x80) << 8;
879 }
880
881 /*
882  * Translates user samples to dma buffer suitable for AC'97 DAC data:
883  *     If mono, copy left channel to right channel in dma buffer.
884  *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
885  *     If interpolating (no VRA), duplicate every audio frame src_factor times.
886  */
887 static int
888 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
889                                                                int dmacount)
890 {
891         int             sample, i;
892         int             interp_bytes_per_sample;
893         int             num_samples;
894         int             mono = (db->num_channels == 1);
895         char            usersample[12];
896         s16             ch, dmasample[6];
897
898         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
899                 /* no translation necessary, just copy
900                 */
901                 if (copy_from_user(dmabuf, userbuf, dmacount))
902                         return -EFAULT;
903                 return dmacount;
904         }
905
906         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
907         num_samples = dmacount / interp_bytes_per_sample;
908
909         for (sample = 0; sample < num_samples; sample++) {
910                 if (copy_from_user(usersample, userbuf,
911                                    db->user_bytes_per_sample)) {
912                         return -EFAULT;
913                 }
914
915                 for (i = 0; i < db->num_channels; i++) {
916                         if (db->sample_size == 8)
917                                 ch = U8_TO_S16(usersample[i]);
918                         else
919                                 ch = *((s16 *) (&usersample[i * 2]));
920                         dmasample[i] = ch;
921                         if (mono)
922                                 dmasample[i + 1] = ch;  /* right channel */
923                 }
924
925                 /* duplicate every audio frame src_factor times
926                 */
927                 for (i = 0; i < db->src_factor; i++)
928                         memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
929
930                 userbuf += db->user_bytes_per_sample;
931                 dmabuf += interp_bytes_per_sample;
932         }
933
934         return num_samples * interp_bytes_per_sample;
935 }
936
937 /*
938  * Translates AC'97 ADC samples to user buffer:
939  *     If mono, send only left channel to user buffer.
940  *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
941  *     If decimating (no VRA), skip over src_factor audio frames.
942  */
943 static int
944 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
945                                                              int dmacount)
946 {
947         int             sample, i;
948         int             interp_bytes_per_sample;
949         int             num_samples;
950         int             mono = (db->num_channels == 1);
951         char            usersample[12];
952
953         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
954                 /* no translation necessary, just copy
955                 */
956                 if (copy_to_user(userbuf, dmabuf, dmacount))
957                         return -EFAULT;
958                 return dmacount;
959         }
960
961         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
962         num_samples = dmacount / interp_bytes_per_sample;
963
964         for (sample = 0; sample < num_samples; sample++) {
965                 for (i = 0; i < db->num_channels; i++) {
966                         if (db->sample_size == 8)
967                                 usersample[i] =
968                                         S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
969                         else
970                                 *((s16 *) (&usersample[i * 2])) =
971                                         *((s16 *) (&dmabuf[i * 2]));
972                 }
973
974                 if (copy_to_user(userbuf, usersample,
975                                  db->user_bytes_per_sample)) {
976                         return -EFAULT;
977                 }
978
979                 userbuf += db->user_bytes_per_sample;
980                 dmabuf += interp_bytes_per_sample;
981         }
982
983         return num_samples * interp_bytes_per_sample;
984 }
985
986 /*
987  * Copy audio data to/from user buffer from/to dma buffer, taking care
988  * that we wrap when reading/writing the dma buffer. Returns actual byte
989  * count written to or read from the dma buffer.
990  */
991 static int
992 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
993 {
994         char           *bufptr = to_user ? db->nextOut : db->nextIn;
995         char           *bufend = db->rawbuf + db->dmasize;
996         int             cnt, ret;
997
998         if (bufptr + count > bufend) {
999                 int             partial = (int) (bufend - bufptr);
1000                 if (to_user) {
1001                         if ((cnt = translate_to_user(db, userbuf,
1002                                                      bufptr, partial)) < 0)
1003                                 return cnt;
1004                         ret = cnt;
1005                         if ((cnt = translate_to_user(db, userbuf + partial,
1006                                                      db->rawbuf,
1007                                                      count - partial)) < 0)
1008                                 return cnt;
1009                         ret += cnt;
1010                 } else {
1011                         if ((cnt = translate_from_user(db, bufptr, userbuf,
1012                                                        partial)) < 0)
1013                                 return cnt;
1014                         ret = cnt;
1015                         if ((cnt = translate_from_user(db, db->rawbuf,
1016                                                        userbuf + partial,
1017                                                        count - partial)) < 0)
1018                                 return cnt;
1019                         ret += cnt;
1020                 }
1021         } else {
1022                 if (to_user)
1023                         ret = translate_to_user(db, userbuf, bufptr, count);
1024                 else
1025                         ret = translate_from_user(db, bufptr, userbuf, count);
1026         }
1027
1028         return ret;
1029 }
1030
1031
1032 static ssize_t
1033 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1034 {
1035         struct au1550_state *s = (struct au1550_state *)file->private_data;
1036         struct dmabuf  *db = &s->dma_adc;
1037         DECLARE_WAITQUEUE(wait, current);
1038         ssize_t         ret;
1039         unsigned long   flags;
1040         int             cnt, usercnt, avail;
1041
1042         if (db->mapped)
1043                 return -ENXIO;
1044         if (!access_ok(VERIFY_WRITE, buffer, count))
1045                 return -EFAULT;
1046         ret = 0;
1047
1048         count *= db->cnt_factor;
1049
1050         mutex_lock(&s->sem);
1051         add_wait_queue(&db->wait, &wait);
1052
1053         while (count > 0) {
1054                 /* wait for samples in ADC dma buffer
1055                 */
1056                 do {
1057                         spin_lock_irqsave(&s->lock, flags);
1058                         if (db->stopped)
1059                                 start_adc(s);
1060                         avail = db->count;
1061                         if (avail <= 0)
1062                                 __set_current_state(TASK_INTERRUPTIBLE);
1063                         spin_unlock_irqrestore(&s->lock, flags);
1064                         if (avail <= 0) {
1065                                 if (file->f_flags & O_NONBLOCK) {
1066                                         if (!ret)
1067                                                 ret = -EAGAIN;
1068                                         goto out;
1069                                 }
1070                                 mutex_unlock(&s->sem);
1071                                 schedule();
1072                                 if (signal_pending(current)) {
1073                                         if (!ret)
1074                                                 ret = -ERESTARTSYS;
1075                                         goto out2;
1076                                 }
1077                                 mutex_lock(&s->sem);
1078                         }
1079                 } while (avail <= 0);
1080
1081                 /* copy from nextOut to user
1082                 */
1083                 if ((cnt = copy_dmabuf_user(db, buffer,
1084                                             count > avail ?
1085                                             avail : count, 1)) < 0) {
1086                         if (!ret)
1087                                 ret = -EFAULT;
1088                         goto out;
1089                 }
1090
1091                 spin_lock_irqsave(&s->lock, flags);
1092                 db->count -= cnt;
1093                 db->nextOut += cnt;
1094                 if (db->nextOut >= db->rawbuf + db->dmasize)
1095                         db->nextOut -= db->dmasize;
1096                 spin_unlock_irqrestore(&s->lock, flags);
1097
1098                 count -= cnt;
1099                 usercnt = cnt / db->cnt_factor;
1100                 buffer += usercnt;
1101                 ret += usercnt;
1102         }                       /* while (count > 0) */
1103
1104 out:
1105         mutex_unlock(&s->sem);
1106 out2:
1107         remove_wait_queue(&db->wait, &wait);
1108         set_current_state(TASK_RUNNING);
1109         return ret;
1110 }
1111
1112 static ssize_t
1113 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1114 {
1115         struct au1550_state *s = (struct au1550_state *)file->private_data;
1116         struct dmabuf  *db = &s->dma_dac;
1117         DECLARE_WAITQUEUE(wait, current);
1118         ssize_t         ret = 0;
1119         unsigned long   flags;
1120         int             cnt, usercnt, avail;
1121
1122         pr_debug("write: count=%d\n", count);
1123
1124         if (db->mapped)
1125                 return -ENXIO;
1126         if (!access_ok(VERIFY_READ, buffer, count))
1127                 return -EFAULT;
1128
1129         count *= db->cnt_factor;
1130
1131         mutex_lock(&s->sem);
1132         add_wait_queue(&db->wait, &wait);
1133
1134         while (count > 0) {
1135                 /* wait for space in playback buffer
1136                 */
1137                 do {
1138                         spin_lock_irqsave(&s->lock, flags);
1139                         avail = (int) db->dmasize - db->count;
1140                         if (avail <= 0)
1141                                 __set_current_state(TASK_INTERRUPTIBLE);
1142                         spin_unlock_irqrestore(&s->lock, flags);
1143                         if (avail <= 0) {
1144                                 if (file->f_flags & O_NONBLOCK) {
1145                                         if (!ret)
1146                                                 ret = -EAGAIN;
1147                                         goto out;
1148                                 }
1149                                 mutex_unlock(&s->sem);
1150                                 schedule();
1151                                 if (signal_pending(current)) {
1152                                         if (!ret)
1153                                                 ret = -ERESTARTSYS;
1154                                         goto out2;
1155                                 }
1156                                 mutex_lock(&s->sem);
1157                         }
1158                 } while (avail <= 0);
1159
1160                 /* copy from user to nextIn
1161                 */
1162                 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1163                                             count > avail ?
1164                                             avail : count, 0)) < 0) {
1165                         if (!ret)
1166                                 ret = -EFAULT;
1167                         goto out;
1168                 }
1169
1170                 spin_lock_irqsave(&s->lock, flags);
1171                 db->count += cnt;
1172                 db->nextIn += cnt;
1173                 if (db->nextIn >= db->rawbuf + db->dmasize)
1174                         db->nextIn -= db->dmasize;
1175
1176                 /* If the data is available, we want to keep two buffers
1177                  * on the dma queue.  If the queue count reaches zero,
1178                  * we know the dma has stopped.
1179                  */
1180                 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1181                         if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1182                                                         db->fragsize) == 0) {
1183                                 err("qcount < 2 and no ring room!");
1184                         }
1185                         db->nextOut += db->fragsize;
1186                         if (db->nextOut >= db->rawbuf + db->dmasize)
1187                                 db->nextOut -= db->dmasize;
1188                         db->total_bytes += db->dma_fragsize;
1189                         if (db->dma_qcount == 0)
1190                                 start_dac(s);
1191                         db->dma_qcount++;
1192                 }
1193                 spin_unlock_irqrestore(&s->lock, flags);
1194
1195                 count -= cnt;
1196                 usercnt = cnt / db->cnt_factor;
1197                 buffer += usercnt;
1198                 ret += usercnt;
1199         }                       /* while (count > 0) */
1200
1201 out:
1202         mutex_unlock(&s->sem);
1203 out2:
1204         remove_wait_queue(&db->wait, &wait);
1205         set_current_state(TASK_RUNNING);
1206         return ret;
1207 }
1208
1209
1210 /* No kernel lock - we have our own spinlock */
1211 static unsigned int
1212 au1550_poll(struct file *file, struct poll_table_struct *wait)
1213 {
1214         struct au1550_state *s = (struct au1550_state *)file->private_data;
1215         unsigned long   flags;
1216         unsigned int    mask = 0;
1217
1218         if (file->f_mode & FMODE_WRITE) {
1219                 if (!s->dma_dac.ready)
1220                         return 0;
1221                 poll_wait(file, &s->dma_dac.wait, wait);
1222         }
1223         if (file->f_mode & FMODE_READ) {
1224                 if (!s->dma_adc.ready)
1225                         return 0;
1226                 poll_wait(file, &s->dma_adc.wait, wait);
1227         }
1228
1229         spin_lock_irqsave(&s->lock, flags);
1230
1231         if (file->f_mode & FMODE_READ) {
1232                 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1233                         mask |= POLLIN | POLLRDNORM;
1234         }
1235         if (file->f_mode & FMODE_WRITE) {
1236                 if (s->dma_dac.mapped) {
1237                         if (s->dma_dac.count >=
1238                             (signed)s->dma_dac.dma_fragsize)
1239                                 mask |= POLLOUT | POLLWRNORM;
1240                 } else {
1241                         if ((signed) s->dma_dac.dmasize >=
1242                             s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1243                                 mask |= POLLOUT | POLLWRNORM;
1244                 }
1245         }
1246         spin_unlock_irqrestore(&s->lock, flags);
1247         return mask;
1248 }
1249
1250 static int
1251 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1252 {
1253         struct au1550_state *s = (struct au1550_state *)file->private_data;
1254         struct dmabuf  *db;
1255         unsigned long   size;
1256         int ret = 0;
1257
1258         lock_kernel();
1259         mutex_lock(&s->sem);
1260         if (vma->vm_flags & VM_WRITE)
1261                 db = &s->dma_dac;
1262         else if (vma->vm_flags & VM_READ)
1263                 db = &s->dma_adc;
1264         else {
1265                 ret = -EINVAL;
1266                 goto out;
1267         }
1268         if (vma->vm_pgoff != 0) {
1269                 ret = -EINVAL;
1270                 goto out;
1271         }
1272         size = vma->vm_end - vma->vm_start;
1273         if (size > (PAGE_SIZE << db->buforder)) {
1274                 ret = -EINVAL;
1275                 goto out;
1276         }
1277         if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1278                              size, vma->vm_page_prot)) {
1279                 ret = -EAGAIN;
1280                 goto out;
1281         }
1282         vma->vm_flags &= ~VM_IO;
1283         db->mapped = 1;
1284 out:
1285         mutex_unlock(&s->sem);
1286         unlock_kernel();
1287         return ret;
1288 }
1289
1290 #ifdef DEBUG
1291 static struct ioctl_str_t {
1292         unsigned int    cmd;
1293         const char     *str;
1294 } ioctl_str[] = {
1295         {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1296         {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1297         {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1298         {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1299         {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1300         {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1301         {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1302         {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1303         {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1304         {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1305         {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1306         {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1307         {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1308         {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1309         {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1310         {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1311         {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1312         {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1313         {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1314         {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1315         {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1316         {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1317         {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1318         {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1319         {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1320         {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1321         {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1322         {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1323         {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1324         {OSS_GETVERSION, "OSS_GETVERSION"},
1325         {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1326         {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1327         {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1328         {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1329 };
1330 #endif
1331
1332 static int
1333 dma_count_done(struct dmabuf *db)
1334 {
1335         if (db->stopped)
1336                 return 0;
1337
1338         return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1339 }
1340
1341
1342 static int
1343 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1344                                                         unsigned long arg)
1345 {
1346         struct au1550_state *s = (struct au1550_state *)file->private_data;
1347         unsigned long   flags;
1348         audio_buf_info  abinfo;
1349         count_info      cinfo;
1350         int             count;
1351         int             val, mapped, ret, diff;
1352
1353         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1354                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1355
1356 #ifdef DEBUG
1357         for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1358                 if (ioctl_str[count].cmd == cmd)
1359                         break;
1360         }
1361         if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1362                 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1363         else
1364                 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1365 #endif
1366
1367         switch (cmd) {
1368         case OSS_GETVERSION:
1369                 return put_user(SOUND_VERSION, (int *) arg);
1370
1371         case SNDCTL_DSP_SYNC:
1372                 if (file->f_mode & FMODE_WRITE)
1373                         return drain_dac(s, file->f_flags & O_NONBLOCK);
1374                 return 0;
1375
1376         case SNDCTL_DSP_SETDUPLEX:
1377                 return 0;
1378
1379         case SNDCTL_DSP_GETCAPS:
1380                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1381                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1382
1383         case SNDCTL_DSP_RESET:
1384                 if (file->f_mode & FMODE_WRITE) {
1385                         stop_dac(s);
1386                         synchronize_irq();
1387                         s->dma_dac.count = s->dma_dac.total_bytes = 0;
1388                         s->dma_dac.nextIn = s->dma_dac.nextOut =
1389                                 s->dma_dac.rawbuf;
1390                 }
1391                 if (file->f_mode & FMODE_READ) {
1392                         stop_adc(s);
1393                         synchronize_irq();
1394                         s->dma_adc.count = s->dma_adc.total_bytes = 0;
1395                         s->dma_adc.nextIn = s->dma_adc.nextOut =
1396                                 s->dma_adc.rawbuf;
1397                 }
1398                 return 0;
1399
1400         case SNDCTL_DSP_SPEED:
1401                 if (get_user(val, (int *) arg))
1402                         return -EFAULT;
1403                 if (val >= 0) {
1404                         if (file->f_mode & FMODE_READ) {
1405                                 stop_adc(s);
1406                                 set_adc_rate(s, val);
1407                         }
1408                         if (file->f_mode & FMODE_WRITE) {
1409                                 stop_dac(s);
1410                                 set_dac_rate(s, val);
1411                         }
1412                         if (s->open_mode & FMODE_READ)
1413                                 if ((ret = prog_dmabuf_adc(s)))
1414                                         return ret;
1415                         if (s->open_mode & FMODE_WRITE)
1416                                 if ((ret = prog_dmabuf_dac(s)))
1417                                         return ret;
1418                 }
1419                 return put_user((file->f_mode & FMODE_READ) ?
1420                                 s->dma_adc.sample_rate :
1421                                 s->dma_dac.sample_rate,
1422                                 (int *)arg);
1423
1424         case SNDCTL_DSP_STEREO:
1425                 if (get_user(val, (int *) arg))
1426                         return -EFAULT;
1427                 if (file->f_mode & FMODE_READ) {
1428                         stop_adc(s);
1429                         s->dma_adc.num_channels = val ? 2 : 1;
1430                         if ((ret = prog_dmabuf_adc(s)))
1431                                 return ret;
1432                 }
1433                 if (file->f_mode & FMODE_WRITE) {
1434                         stop_dac(s);
1435                         s->dma_dac.num_channels = val ? 2 : 1;
1436                         if (s->codec_ext_caps & AC97_EXT_DACS) {
1437                                 /* disable surround and center/lfe in AC'97
1438                                 */
1439                                 u16 ext_stat = rdcodec(s->codec,
1440                                                        AC97_EXTENDED_STATUS);
1441                                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1442                                         ext_stat | (AC97_EXTSTAT_PRI |
1443                                                     AC97_EXTSTAT_PRJ |
1444                                                     AC97_EXTSTAT_PRK));
1445                         }
1446                         if ((ret = prog_dmabuf_dac(s)))
1447                                 return ret;
1448                 }
1449                 return 0;
1450
1451         case SNDCTL_DSP_CHANNELS:
1452                 if (get_user(val, (int *) arg))
1453                         return -EFAULT;
1454                 if (val != 0) {
1455                         if (file->f_mode & FMODE_READ) {
1456                                 if (val < 0 || val > 2)
1457                                         return -EINVAL;
1458                                 stop_adc(s);
1459                                 s->dma_adc.num_channels = val;
1460                                 if ((ret = prog_dmabuf_adc(s)))
1461                                         return ret;
1462                         }
1463                         if (file->f_mode & FMODE_WRITE) {
1464                                 switch (val) {
1465                                 case 1:
1466                                 case 2:
1467                                         break;
1468                                 case 3:
1469                                 case 5:
1470                                         return -EINVAL;
1471                                 case 4:
1472                                         if (!(s->codec_ext_caps &
1473                                               AC97_EXTID_SDAC))
1474                                                 return -EINVAL;
1475                                         break;
1476                                 case 6:
1477                                         if ((s->codec_ext_caps &
1478                                              AC97_EXT_DACS) != AC97_EXT_DACS)
1479                                                 return -EINVAL;
1480                                         break;
1481                                 default:
1482                                         return -EINVAL;
1483                                 }
1484
1485                                 stop_dac(s);
1486                                 if (val <= 2 &&
1487                                     (s->codec_ext_caps & AC97_EXT_DACS)) {
1488                                         /* disable surround and center/lfe
1489                                          * channels in AC'97
1490                                          */
1491                                         u16             ext_stat =
1492                                                 rdcodec(s->codec,
1493                                                         AC97_EXTENDED_STATUS);
1494                                         wrcodec(s->codec,
1495                                                 AC97_EXTENDED_STATUS,
1496                                                 ext_stat | (AC97_EXTSTAT_PRI |
1497                                                             AC97_EXTSTAT_PRJ |
1498                                                             AC97_EXTSTAT_PRK));
1499                                 } else if (val >= 4) {
1500                                         /* enable surround, center/lfe
1501                                          * channels in AC'97
1502                                          */
1503                                         u16             ext_stat =
1504                                                 rdcodec(s->codec,
1505                                                         AC97_EXTENDED_STATUS);
1506                                         ext_stat &= ~AC97_EXTSTAT_PRJ;
1507                                         if (val == 6)
1508                                                 ext_stat &=
1509                                                         ~(AC97_EXTSTAT_PRI |
1510                                                           AC97_EXTSTAT_PRK);
1511                                         wrcodec(s->codec,
1512                                                 AC97_EXTENDED_STATUS,
1513                                                 ext_stat);
1514                                 }
1515
1516                                 s->dma_dac.num_channels = val;
1517                                 if ((ret = prog_dmabuf_dac(s)))
1518                                         return ret;
1519                         }
1520                 }
1521                 return put_user(val, (int *) arg);
1522
1523         case SNDCTL_DSP_GETFMTS:        /* Returns a mask */
1524                 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1525
1526         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1527                 if (get_user(val, (int *) arg))
1528                         return -EFAULT;
1529                 if (val != AFMT_QUERY) {
1530                         if (file->f_mode & FMODE_READ) {
1531                                 stop_adc(s);
1532                                 if (val == AFMT_S16_LE)
1533                                         s->dma_adc.sample_size = 16;
1534                                 else {
1535                                         val = AFMT_U8;
1536                                         s->dma_adc.sample_size = 8;
1537                                 }
1538                                 if ((ret = prog_dmabuf_adc(s)))
1539                                         return ret;
1540                         }
1541                         if (file->f_mode & FMODE_WRITE) {
1542                                 stop_dac(s);
1543                                 if (val == AFMT_S16_LE)
1544                                         s->dma_dac.sample_size = 16;
1545                                 else {
1546                                         val = AFMT_U8;
1547                                         s->dma_dac.sample_size = 8;
1548                                 }
1549                                 if ((ret = prog_dmabuf_dac(s)))
1550                                         return ret;
1551                         }
1552                 } else {
1553                         if (file->f_mode & FMODE_READ)
1554                                 val = (s->dma_adc.sample_size == 16) ?
1555                                         AFMT_S16_LE : AFMT_U8;
1556                         else
1557                                 val = (s->dma_dac.sample_size == 16) ?
1558                                         AFMT_S16_LE : AFMT_U8;
1559                 }
1560                 return put_user(val, (int *) arg);
1561
1562         case SNDCTL_DSP_POST:
1563                 return 0;
1564
1565         case SNDCTL_DSP_GETTRIGGER:
1566                 val = 0;
1567                 spin_lock_irqsave(&s->lock, flags);
1568                 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1569                         val |= PCM_ENABLE_INPUT;
1570                 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1571                         val |= PCM_ENABLE_OUTPUT;
1572                 spin_unlock_irqrestore(&s->lock, flags);
1573                 return put_user(val, (int *) arg);
1574
1575         case SNDCTL_DSP_SETTRIGGER:
1576                 if (get_user(val, (int *) arg))
1577                         return -EFAULT;
1578                 if (file->f_mode & FMODE_READ) {
1579                         if (val & PCM_ENABLE_INPUT) {
1580                                 spin_lock_irqsave(&s->lock, flags);
1581                                 start_adc(s);
1582                                 spin_unlock_irqrestore(&s->lock, flags);
1583                         } else
1584                                 stop_adc(s);
1585                 }
1586                 if (file->f_mode & FMODE_WRITE) {
1587                         if (val & PCM_ENABLE_OUTPUT) {
1588                                 spin_lock_irqsave(&s->lock, flags);
1589                                 start_dac(s);
1590                                 spin_unlock_irqrestore(&s->lock, flags);
1591                         } else
1592                                 stop_dac(s);
1593                 }
1594                 return 0;
1595
1596         case SNDCTL_DSP_GETOSPACE:
1597                 if (!(file->f_mode & FMODE_WRITE))
1598                         return -EINVAL;
1599                 abinfo.fragsize = s->dma_dac.fragsize;
1600                 spin_lock_irqsave(&s->lock, flags);
1601                 count = s->dma_dac.count;
1602                 count -= dma_count_done(&s->dma_dac);
1603                 spin_unlock_irqrestore(&s->lock, flags);
1604                 if (count < 0)
1605                         count = 0;
1606                 abinfo.bytes = (s->dma_dac.dmasize - count) /
1607                         s->dma_dac.cnt_factor;
1608                 abinfo.fragstotal = s->dma_dac.numfrag;
1609                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1610                 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1611                 return copy_to_user((void *) arg, &abinfo,
1612                                     sizeof(abinfo)) ? -EFAULT : 0;
1613
1614         case SNDCTL_DSP_GETISPACE:
1615                 if (!(file->f_mode & FMODE_READ))
1616                         return -EINVAL;
1617                 abinfo.fragsize = s->dma_adc.fragsize;
1618                 spin_lock_irqsave(&s->lock, flags);
1619                 count = s->dma_adc.count;
1620                 count += dma_count_done(&s->dma_adc);
1621                 spin_unlock_irqrestore(&s->lock, flags);
1622                 if (count < 0)
1623                         count = 0;
1624                 abinfo.bytes = count / s->dma_adc.cnt_factor;
1625                 abinfo.fragstotal = s->dma_adc.numfrag;
1626                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1627                 return copy_to_user((void *) arg, &abinfo,
1628                                     sizeof(abinfo)) ? -EFAULT : 0;
1629
1630         case SNDCTL_DSP_NONBLOCK:
1631                 file->f_flags |= O_NONBLOCK;
1632                 return 0;
1633
1634         case SNDCTL_DSP_GETODELAY:
1635                 if (!(file->f_mode & FMODE_WRITE))
1636                         return -EINVAL;
1637                 spin_lock_irqsave(&s->lock, flags);
1638                 count = s->dma_dac.count;
1639                 count -= dma_count_done(&s->dma_dac);
1640                 spin_unlock_irqrestore(&s->lock, flags);
1641                 if (count < 0)
1642                         count = 0;
1643                 count /= s->dma_dac.cnt_factor;
1644                 return put_user(count, (int *) arg);
1645
1646         case SNDCTL_DSP_GETIPTR:
1647                 if (!(file->f_mode & FMODE_READ))
1648                         return -EINVAL;
1649                 spin_lock_irqsave(&s->lock, flags);
1650                 cinfo.bytes = s->dma_adc.total_bytes;
1651                 count = s->dma_adc.count;
1652                 if (!s->dma_adc.stopped) {
1653                         diff = dma_count_done(&s->dma_adc);
1654                         count += diff;
1655                         cinfo.bytes += diff;
1656                         cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
1657                                 virt_to_phys(s->dma_adc.rawbuf);
1658                 } else
1659                         cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1660                                 virt_to_phys(s->dma_adc.rawbuf);
1661                 if (s->dma_adc.mapped)
1662                         s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1663                 spin_unlock_irqrestore(&s->lock, flags);
1664                 if (count < 0)
1665                         count = 0;
1666                 cinfo.blocks = count >> s->dma_adc.fragshift;
1667                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1668
1669         case SNDCTL_DSP_GETOPTR:
1670                 if (!(file->f_mode & FMODE_READ))
1671                         return -EINVAL;
1672                 spin_lock_irqsave(&s->lock, flags);
1673                 cinfo.bytes = s->dma_dac.total_bytes;
1674                 count = s->dma_dac.count;
1675                 if (!s->dma_dac.stopped) {
1676                         diff = dma_count_done(&s->dma_dac);
1677                         count -= diff;
1678                         cinfo.bytes += diff;
1679                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1680                                 virt_to_phys(s->dma_dac.rawbuf);
1681                 } else
1682                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1683                                 virt_to_phys(s->dma_dac.rawbuf);
1684                 if (s->dma_dac.mapped)
1685                         s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1686                 spin_unlock_irqrestore(&s->lock, flags);
1687                 if (count < 0)
1688                         count = 0;
1689                 cinfo.blocks = count >> s->dma_dac.fragshift;
1690                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1691
1692         case SNDCTL_DSP_GETBLKSIZE:
1693                 if (file->f_mode & FMODE_WRITE)
1694                         return put_user(s->dma_dac.fragsize, (int *) arg);
1695                 else
1696                         return put_user(s->dma_adc.fragsize, (int *) arg);
1697
1698         case SNDCTL_DSP_SETFRAGMENT:
1699                 if (get_user(val, (int *) arg))
1700                         return -EFAULT;
1701                 if (file->f_mode & FMODE_READ) {
1702                         stop_adc(s);
1703                         s->dma_adc.ossfragshift = val & 0xffff;
1704                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1705                         if (s->dma_adc.ossfragshift < 4)
1706                                 s->dma_adc.ossfragshift = 4;
1707                         if (s->dma_adc.ossfragshift > 15)
1708                                 s->dma_adc.ossfragshift = 15;
1709                         if (s->dma_adc.ossmaxfrags < 4)
1710                                 s->dma_adc.ossmaxfrags = 4;
1711                         if ((ret = prog_dmabuf_adc(s)))
1712                                 return ret;
1713                 }
1714                 if (file->f_mode & FMODE_WRITE) {
1715                         stop_dac(s);
1716                         s->dma_dac.ossfragshift = val & 0xffff;
1717                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1718                         if (s->dma_dac.ossfragshift < 4)
1719                                 s->dma_dac.ossfragshift = 4;
1720                         if (s->dma_dac.ossfragshift > 15)
1721                                 s->dma_dac.ossfragshift = 15;
1722                         if (s->dma_dac.ossmaxfrags < 4)
1723                                 s->dma_dac.ossmaxfrags = 4;
1724                         if ((ret = prog_dmabuf_dac(s)))
1725                                 return ret;
1726                 }
1727                 return 0;
1728
1729         case SNDCTL_DSP_SUBDIVIDE:
1730                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1731                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1732                         return -EINVAL;
1733                 if (get_user(val, (int *) arg))
1734                         return -EFAULT;
1735                 if (val != 1 && val != 2 && val != 4)
1736                         return -EINVAL;
1737                 if (file->f_mode & FMODE_READ) {
1738                         stop_adc(s);
1739                         s->dma_adc.subdivision = val;
1740                         if ((ret = prog_dmabuf_adc(s)))
1741                                 return ret;
1742                 }
1743                 if (file->f_mode & FMODE_WRITE) {
1744                         stop_dac(s);
1745                         s->dma_dac.subdivision = val;
1746                         if ((ret = prog_dmabuf_dac(s)))
1747                                 return ret;
1748                 }
1749                 return 0;
1750
1751         case SOUND_PCM_READ_RATE:
1752                 return put_user((file->f_mode & FMODE_READ) ?
1753                                 s->dma_adc.sample_rate :
1754                                 s->dma_dac.sample_rate,
1755                                 (int *)arg);
1756
1757         case SOUND_PCM_READ_CHANNELS:
1758                 if (file->f_mode & FMODE_READ)
1759                         return put_user(s->dma_adc.num_channels, (int *)arg);
1760                 else
1761                         return put_user(s->dma_dac.num_channels, (int *)arg);
1762
1763         case SOUND_PCM_READ_BITS:
1764                 if (file->f_mode & FMODE_READ)
1765                         return put_user(s->dma_adc.sample_size, (int *)arg);
1766                 else
1767                         return put_user(s->dma_dac.sample_size, (int *)arg);
1768
1769         case SOUND_PCM_WRITE_FILTER:
1770         case SNDCTL_DSP_SETSYNCRO:
1771         case SOUND_PCM_READ_FILTER:
1772                 return -EINVAL;
1773         }
1774
1775         return mixdev_ioctl(s->codec, cmd, arg);
1776 }
1777
1778
1779 static int
1780 au1550_open(struct inode *inode, struct file *file)
1781 {
1782         int             minor = MINOR(inode->i_rdev);
1783         DECLARE_WAITQUEUE(wait, current);
1784         struct au1550_state *s = &au1550_state;
1785         int             ret;
1786
1787 #ifdef DEBUG
1788         if (file->f_flags & O_NONBLOCK)
1789                 pr_debug("open: non-blocking\n");
1790         else
1791                 pr_debug("open: blocking\n");
1792 #endif
1793
1794         file->private_data = s;
1795         /* wait for device to become free */
1796         mutex_lock(&s->open_mutex);
1797         while (s->open_mode & file->f_mode) {
1798                 if (file->f_flags & O_NONBLOCK) {
1799                         mutex_unlock(&s->open_mutex);
1800                         return -EBUSY;
1801                 }
1802                 add_wait_queue(&s->open_wait, &wait);
1803                 __set_current_state(TASK_INTERRUPTIBLE);
1804                 mutex_unlock(&s->open_mutex);
1805                 schedule();
1806                 remove_wait_queue(&s->open_wait, &wait);
1807                 set_current_state(TASK_RUNNING);
1808                 if (signal_pending(current))
1809                         return -ERESTARTSYS;
1810                 mutex_lock(&s->open_mutex);
1811         }
1812
1813         stop_dac(s);
1814         stop_adc(s);
1815
1816         if (file->f_mode & FMODE_READ) {
1817                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1818                         s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1819                 s->dma_adc.num_channels = 1;
1820                 s->dma_adc.sample_size = 8;
1821                 set_adc_rate(s, 8000);
1822                 if ((minor & 0xf) == SND_DEV_DSP16)
1823                         s->dma_adc.sample_size = 16;
1824         }
1825
1826         if (file->f_mode & FMODE_WRITE) {
1827                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1828                         s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1829                 s->dma_dac.num_channels = 1;
1830                 s->dma_dac.sample_size = 8;
1831                 set_dac_rate(s, 8000);
1832                 if ((minor & 0xf) == SND_DEV_DSP16)
1833                         s->dma_dac.sample_size = 16;
1834         }
1835
1836         if (file->f_mode & FMODE_READ) {
1837                 if ((ret = prog_dmabuf_adc(s)))
1838                         return ret;
1839         }
1840         if (file->f_mode & FMODE_WRITE) {
1841                 if ((ret = prog_dmabuf_dac(s)))
1842                         return ret;
1843         }
1844
1845         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1846         mutex_unlock(&s->open_mutex);
1847         mutex_init(&s->sem);
1848         return 0;
1849 }
1850
1851 static int
1852 au1550_release(struct inode *inode, struct file *file)
1853 {
1854         struct au1550_state *s = (struct au1550_state *)file->private_data;
1855
1856         lock_kernel();
1857
1858         if (file->f_mode & FMODE_WRITE) {
1859                 unlock_kernel();
1860                 drain_dac(s, file->f_flags & O_NONBLOCK);
1861                 lock_kernel();
1862         }
1863
1864         mutex_lock(&s->open_mutex);
1865         if (file->f_mode & FMODE_WRITE) {
1866                 stop_dac(s);
1867                 kfree(s->dma_dac.rawbuf);
1868                 s->dma_dac.rawbuf = NULL;
1869         }
1870         if (file->f_mode & FMODE_READ) {
1871                 stop_adc(s);
1872                 kfree(s->dma_adc.rawbuf);
1873                 s->dma_adc.rawbuf = NULL;
1874         }
1875         s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1876         mutex_unlock(&s->open_mutex);
1877         wake_up(&s->open_wait);
1878         unlock_kernel();
1879         return 0;
1880 }
1881
1882 static /*const */ struct file_operations au1550_audio_fops = {
1883         owner:          THIS_MODULE,
1884         llseek:         au1550_llseek,
1885         read:           au1550_read,
1886         write:          au1550_write,
1887         poll:           au1550_poll,
1888         ioctl:          au1550_ioctl,
1889         mmap:           au1550_mmap,
1890         open:           au1550_open,
1891         release:        au1550_release,
1892 };
1893
1894 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1895 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1896 MODULE_LICENSE("GPL");
1897
1898
1899 static int __devinit
1900 au1550_probe(void)
1901 {
1902         struct au1550_state *s = &au1550_state;
1903         int             val;
1904
1905         memset(s, 0, sizeof(struct au1550_state));
1906
1907         init_waitqueue_head(&s->dma_adc.wait);
1908         init_waitqueue_head(&s->dma_dac.wait);
1909         init_waitqueue_head(&s->open_wait);
1910         mutex_init(&s->open_mutex);
1911         spin_lock_init(&s->lock);
1912
1913         s->codec = ac97_alloc_codec();
1914         if(s->codec == NULL) {
1915                 err("Out of memory");
1916                 return -1;
1917         }
1918         s->codec->private_data = s;
1919         s->codec->id = 0;
1920         s->codec->codec_read = rdcodec;
1921         s->codec->codec_write = wrcodec;
1922         s->codec->codec_wait = waitcodec;
1923
1924         if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1925                             0x30, "Au1550 AC97")) {
1926                 err("AC'97 ports in use");
1927         }
1928
1929         /* Allocate the DMA Channels
1930         */
1931         if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1932             DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1933                 err("Can't get DAC DMA");
1934                 goto err_dma1;
1935         }
1936         au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1937         if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1938                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1939                 err("Can't get DAC DMA descriptors");
1940                 goto err_dma1;
1941         }
1942
1943         if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1944             DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1945                 err("Can't get ADC DMA");
1946                 goto err_dma2;
1947         }
1948         au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1949         if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1950                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1951                 err("Can't get ADC DMA descriptors");
1952                 goto err_dma2;
1953         }
1954
1955         pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1956
1957         /* register devices */
1958
1959         if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1960                 goto err_dev1;
1961         if ((s->codec->dev_mixer =
1962              register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1963                 goto err_dev2;
1964
1965         /* The GPIO for the appropriate PSC was configured by the
1966          * board specific start up.
1967          *
1968          * configure PSC for AC'97
1969          */
1970         au_writel(0, AC97_PSC_CTRL);    /* Disable PSC */
1971         au_sync();
1972         au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1973         au_sync();
1974
1975         /* cold reset the AC'97
1976         */
1977         au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1978         au_sync();
1979         au1550_delay(10);
1980         au_writel(0, PSC_AC97RST);
1981         au_sync();
1982
1983         /* need to delay around 500msec(bleech) to give
1984            some CODECs enough time to wakeup */
1985         au1550_delay(500);
1986
1987         /* warm reset the AC'97 to start the bitclk
1988         */
1989         au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1990         au_sync();
1991         udelay(100);
1992         au_writel(0, PSC_AC97RST);
1993         au_sync();
1994
1995         /* Enable PSC
1996         */
1997         au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
1998         au_sync();
1999
2000         /* Wait for PSC ready.
2001         */
2002         do {
2003                 val = au_readl(PSC_AC97STAT);
2004                 au_sync();
2005         } while ((val & PSC_AC97STAT_SR) == 0);
2006
2007         /* Configure AC97 controller.
2008          * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2009          */
2010         val = PSC_AC97CFG_SET_LEN(16);
2011         val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2012
2013         /* Enable device so we can at least
2014          * talk over the AC-link.
2015          */
2016         au_writel(val, PSC_AC97CFG);
2017         au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2018         au_sync();
2019         val |= PSC_AC97CFG_DE_ENABLE;
2020         au_writel(val, PSC_AC97CFG);
2021         au_sync();
2022
2023         /* Wait for Device ready.
2024         */
2025         do {
2026                 val = au_readl(PSC_AC97STAT);
2027                 au_sync();
2028         } while ((val & PSC_AC97STAT_DR) == 0);
2029
2030         /* codec init */
2031         if (!ac97_probe_codec(s->codec))
2032                 goto err_dev3;
2033
2034         s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2035         s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2036         pr_info("AC'97 Base/Extended ID = %04x/%04x",
2037              s->codec_base_caps, s->codec_ext_caps);
2038
2039         if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2040                 /* codec does not support VRA
2041                 */
2042                 s->no_vra = 1;
2043         } else if (!vra) {
2044                 /* Boot option says disable VRA
2045                 */
2046                 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2047                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2048                         ac97_extstat & ~AC97_EXTSTAT_VRA);
2049                 s->no_vra = 1;
2050         }
2051         if (s->no_vra)
2052                 pr_info("no VRA, interpolating and decimating");
2053
2054         /* set mic to be the recording source */
2055         val = SOUND_MASK_MIC;
2056         mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2057                      (unsigned long) &val);
2058
2059         return 0;
2060
2061  err_dev3:
2062         unregister_sound_mixer(s->codec->dev_mixer);
2063  err_dev2:
2064         unregister_sound_dsp(s->dev_audio);
2065  err_dev1:
2066         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2067  err_dma2:
2068         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2069  err_dma1:
2070         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2071
2072         ac97_release_codec(s->codec);
2073         return -1;
2074 }
2075
2076 static void __devinit
2077 au1550_remove(void)
2078 {
2079         struct au1550_state *s = &au1550_state;
2080
2081         if (!s)
2082                 return;
2083         synchronize_irq();
2084         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2085         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2086         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2087         unregister_sound_dsp(s->dev_audio);
2088         unregister_sound_mixer(s->codec->dev_mixer);
2089         ac97_release_codec(s->codec);
2090 }
2091
2092 static int __init
2093 init_au1550(void)
2094 {
2095         return au1550_probe();
2096 }
2097
2098 static void __exit
2099 cleanup_au1550(void)
2100 {
2101         au1550_remove();
2102 }
2103
2104 module_init(init_au1550);
2105 module_exit(cleanup_au1550);
2106
2107 #ifndef MODULE
2108
2109 static int __init
2110 au1550_setup(char *options)
2111 {
2112         char           *this_opt;
2113
2114         if (!options || !*options)
2115                 return 0;
2116
2117         while ((this_opt = strsep(&options, ","))) {
2118                 if (!*this_opt)
2119                         continue;
2120                 if (!strncmp(this_opt, "vra", 3)) {
2121                         vra = 1;
2122                 }
2123         }
2124
2125         return 1;
2126 }
2127
2128 __setup("au1550_audio=", au1550_setup);
2129
2130 #endif /* MODULE */