sound/mips/hal2.c

   1 /*
   2  *  Driver for A2 audio system used in SGI machines
   3  *  Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
   4  *
   5  *  Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
   6  *  was based on code from Ulf Carlsson
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/io.h>
  28
  29 #include <asm/sgi/hpc3.h>
  30 #include <asm/sgi/ip22.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/control.h>
  34 #include <sound/pcm.h>
  35 #include <sound/pcm-indirect.h>
  36 #include <sound/initval.h>
  37
  38 #include "hal2.h"
  39
  40 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  41 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  42
  43 module_param(index, int, 0444);
  44 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
  45 module_param(id, charp, 0444);
  46 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
  47 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
  48 MODULE_AUTHOR("Thomas Bogendoerfer");
  49 MODULE_LICENSE("GPL");
  50
  51
  52 #define H2_BLOCK_SIZE   1024
  53 #define H2_BUF_SIZE     16384
  54
  55 struct hal2_pbus {
  56         struct hpc3_pbus_dmacregs *pbus;
  57         int pbusnr;
  58         unsigned int ctrl;              /* Current state of pbus->pbdma_ctrl */
  59 };
  60
  61 struct hal2_desc {
  62         struct hpc_dma_desc desc;
  63         u32 pad;                        /* padding */
  64 };
  65
  66 struct hal2_codec {
  67         struct snd_pcm_indirect pcm_indirect;
  68         struct snd_pcm_substream *substream;
  69
  70         unsigned char *buffer;
  71         dma_addr_t buffer_dma;
  72         struct hal2_desc *desc;
  73         dma_addr_t desc_dma;
  74         int desc_count;
  75         struct hal2_pbus pbus;
  76         int voices;                     /* mono/stereo */
  77         unsigned int sample_rate;
  78         unsigned int master;            /* Master frequency */
  79         unsigned short mod;             /* MOD value */
  80         unsigned short inc;             /* INC value */
  81 };
  82
  83 #define H2_MIX_OUTPUT_ATT       0
  84 #define H2_MIX_INPUT_GAIN       1
  85
  86 struct snd_hal2 {
  87         struct snd_card *card;
  88
  89         struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
  90         struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
  91         struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
  92         struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
  93
  94         struct hal2_codec dac;
  95         struct hal2_codec adc;
  96 };
  97
  98 #define H2_INDIRECT_WAIT(regs)  while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
  99
 100 #define H2_READ_ADDR(addr)      (addr | (1<<7))
 101 #define H2_WRITE_ADDR(addr)     (addr)
 102
 103 static inline u32 hal2_read(u32 *reg)
 104 {
 105         return __raw_readl(reg);
 106 }
 107
 108 static inline void hal2_write(u32 val, u32 *reg)
 109 {
 110         __raw_writel(val, reg);
 111 }
 112
 113
 114 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
 115 {
 116         u32 ret;
 117         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 118
 119         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 120         H2_INDIRECT_WAIT(regs);
 121         ret = hal2_read(&regs->idr0) & 0xffff;
 122         hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
 123         H2_INDIRECT_WAIT(regs);
 124         ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
 125         return ret;
 126 }
 127
 128 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
 129 {
 130         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 131
 132         hal2_write(val, &regs->idr0);
 133         hal2_write(0, &regs->idr1);
 134         hal2_write(0, &regs->idr2);
 135         hal2_write(0, &regs->idr3);
 136         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 137         H2_INDIRECT_WAIT(regs);
 138 }
 139
 140 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
 141 {
 142         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 143
 144         hal2_write(val & 0xffff, &regs->idr0);
 145         hal2_write(val >> 16, &regs->idr1);
 146         hal2_write(0, &regs->idr2);
 147         hal2_write(0, &regs->idr3);
 148         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 149         H2_INDIRECT_WAIT(regs);
 150 }
 151
 152 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
 153 {
 154         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 155
 156         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 157         H2_INDIRECT_WAIT(regs);
 158         hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
 159         hal2_write(0, &regs->idr1);
 160         hal2_write(0, &regs->idr2);
 161         hal2_write(0, &regs->idr3);
 162         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 163         H2_INDIRECT_WAIT(regs);
 164 }
 165
 166 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
 167 {
 168         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 169
 170         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 171         H2_INDIRECT_WAIT(regs);
 172         hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
 173         hal2_write(0, &regs->idr1);
 174         hal2_write(0, &regs->idr2);
 175         hal2_write(0, &regs->idr3);
 176         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 177         H2_INDIRECT_WAIT(regs);
 178 }
 179
 180 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
 181                                struct snd_ctl_elem_info *uinfo)
 182 {
 183         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 184         uinfo->count = 2;
 185         uinfo->value.integer.min = 0;
 186         switch ((int)kcontrol->private_value) {
 187         case H2_MIX_OUTPUT_ATT:
 188                 uinfo->value.integer.max = 31;
 189                 break;
 190         case H2_MIX_INPUT_GAIN:
 191                 uinfo->value.integer.max = 15;
 192                 break;
 193         }
 194         return 0;
 195 }
 196
 197 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
 198                                struct snd_ctl_elem_value *ucontrol)
 199 {
 200         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
 201         u32 tmp;
 202         int l, r;
 203
 204         switch ((int)kcontrol->private_value) {
 205         case H2_MIX_OUTPUT_ATT:
 206                 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
 207                 if (tmp & H2I_C2_MUTE) {
 208                         l = 0;
 209                         r = 0;
 210                 } else {
 211                         l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
 212                         r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
 213                 }
 214                 break;
 215         case H2_MIX_INPUT_GAIN:
 216                 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
 217                 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
 218                 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
 219                 break;
 220         }
 221         ucontrol->value.integer.value[0] = l;
 222         ucontrol->value.integer.value[1] = r;
 223
 224         return 0;
 225 }
 226
 227 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
 228                          struct snd_ctl_elem_value *ucontrol)
 229 {
 230         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
 231         u32 old, new;
 232         int l, r;
 233
 234         l = ucontrol->value.integer.value[0];
 235         r = ucontrol->value.integer.value[1];
 236
 237         switch ((int)kcontrol->private_value) {
 238         case H2_MIX_OUTPUT_ATT:
 239                 old = hal2_i_read32(hal2, H2I_DAC_C2);
 240                 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
 241                 if (l | r) {
 242                         l = 31 - l;
 243                         r = 31 - r;
 244                         new |= (l << H2I_C2_L_ATT_SHIFT);
 245                         new |= (r << H2I_C2_R_ATT_SHIFT);
 246                 } else
 247                         new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
 248                 hal2_i_write32(hal2, H2I_DAC_C2, new);
 249                 break;
 250         case H2_MIX_INPUT_GAIN:
 251                 old = hal2_i_read32(hal2, H2I_ADC_C2);
 252                 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
 253                 new |= (l << H2I_C2_L_GAIN_SHIFT);
 254                 new |= (r << H2I_C2_R_GAIN_SHIFT);
 255                 hal2_i_write32(hal2, H2I_ADC_C2, new);
 256                 break;
 257         }
 258         return old != new;
 259 }
 260
 261 static struct snd_kcontrol_new hal2_ctrl_headphone __devinitdata = {
 262         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
 263         .name           = "Headphone Playback Volume",
 264         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 265         .private_value  = H2_MIX_OUTPUT_ATT,
 266         .info           = hal2_gain_info,
 267         .get            = hal2_gain_get,
 268         .put            = hal2_gain_put,
 269 };
 270
 271 static struct snd_kcontrol_new hal2_ctrl_mic __devinitdata = {
 272         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
 273         .name           = "Mic Capture Volume",
 274         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 275         .private_value  = H2_MIX_INPUT_GAIN,
 276         .info           = hal2_gain_info,
 277         .get            = hal2_gain_get,
 278         .put            = hal2_gain_put,
 279 };
 280
 281 static int __devinit hal2_mixer_create(struct snd_hal2 *hal2)
 282 {
 283         int err;
 284
 285         /* mute DAC */
 286         hal2_i_write32(hal2, H2I_DAC_C2,
 287                        H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
 288         /* mute ADC */
 289         hal2_i_write32(hal2, H2I_ADC_C2, 0);
 290
 291         err = snd_ctl_add(hal2->card,
 292                           snd_ctl_new1(&hal2_ctrl_headphone, hal2));
 293         if (err < 0)
 294                 return err;
 295
 296         err = snd_ctl_add(hal2->card,
 297                           snd_ctl_new1(&hal2_ctrl_mic, hal2));
 298         if (err < 0)
 299                 return err;
 300
 301         return 0;
 302 }
 303
 304 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
 305 {
 306         struct snd_hal2 *hal2 = dev_id;
 307         irqreturn_t ret = IRQ_NONE;
 308
 309         /* decide what caused this interrupt */
 310         if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
 311                 snd_pcm_period_elapsed(hal2->dac.substream);
 312                 ret = IRQ_HANDLED;
 313         }
 314         if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
 315                 snd_pcm_period_elapsed(hal2->adc.substream);
 316                 ret = IRQ_HANDLED;
 317         }
 318         return ret;
 319 }
 320
 321 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
 322 {
 323         unsigned short mod;
 324
 325         if (44100 % rate < 48000 % rate) {
 326                 mod = 4 * 44100 / rate;
 327                 codec->master = 44100;
 328         } else {
 329                 mod = 4 * 48000 / rate;
 330                 codec->master = 48000;
 331         }
 332
 333         codec->inc = 4;
 334         codec->mod = mod;
 335         rate = 4 * codec->master / mod;
 336
 337         return rate;
 338 }
 339
 340 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
 341 {
 342         unsigned int master = hal2->dac.master;
 343         int inc = hal2->dac.inc;
 344         int mod = hal2->dac.mod;
 345
 346         hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
 347         hal2_i_write32(hal2, H2I_BRES1_C2,
 348                        ((0xffff & (inc - mod - 1)) << 16) | inc);
 349 }
 350
 351 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
 352 {
 353         unsigned int master = hal2->adc.master;
 354         int inc = hal2->adc.inc;
 355         int mod = hal2->adc.mod;
 356
 357         hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
 358         hal2_i_write32(hal2, H2I_BRES2_C2,
 359                        ((0xffff & (inc - mod - 1)) << 16) | inc);
 360 }
 361
 362 static void hal2_setup_dac(struct snd_hal2 *hal2)
 363 {
 364         unsigned int fifobeg, fifoend, highwater, sample_size;
 365         struct hal2_pbus *pbus = &hal2->dac.pbus;
 366
 367         /* Now we set up some PBUS information. The PBUS needs information about
 368          * what portion of the fifo it will use. If it's receiving or
 369          * transmitting, and finally whether the stream is little endian or big
 370          * endian. The information is written later, on the start call.
 371          */
 372         sample_size = 2 * hal2->dac.voices;
 373         /* Fifo should be set to hold exactly four samples. Highwater mark
 374          * should be set to two samples. */
 375         highwater = (sample_size * 2) >> 1;     /* halfwords */
 376         fifobeg = 0;                            /* playback is first */
 377         fifoend = (sample_size * 4) >> 3;       /* doublewords */
 378         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
 379                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
 380         /* We disable everything before we do anything at all */
 381         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 382         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
 383         /* Setup the HAL2 for playback */
 384         hal2_set_dac_rate(hal2);
 385         /* Set endianess */
 386         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
 387         /* Set DMA bus */
 388         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
 389         /* We are using 1st Bresenham clock generator for playback */
 390         hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
 391                         | (1 << H2I_C1_CLKID_SHIFT)
 392                         | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
 393 }
 394
 395 static void hal2_setup_adc(struct snd_hal2 *hal2)
 396 {
 397         unsigned int fifobeg, fifoend, highwater, sample_size;
 398         struct hal2_pbus *pbus = &hal2->adc.pbus;
 399
 400         sample_size = 2 * hal2->adc.voices;
 401         highwater = (sample_size * 2) >> 1;             /* halfwords */
 402         fifobeg = (4 * 4) >> 3;                         /* record is second */
 403         fifoend = (4 * 4 + sample_size * 4) >> 3;       /* doublewords */
 404         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
 405                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
 406         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 407         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
 408         /* Setup the HAL2 for record */
 409         hal2_set_adc_rate(hal2);
 410         /* Set endianess */
 411         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
 412         /* Set DMA bus */
 413         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
 414         /* We are using 2nd Bresenham clock generator for record */
 415         hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
 416                         | (2 << H2I_C1_CLKID_SHIFT)
 417                         | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
 418 }
 419
 420 static void hal2_start_dac(struct snd_hal2 *hal2)
 421 {
 422         struct hal2_pbus *pbus = &hal2->dac.pbus;
 423
 424         pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
 425         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
 426         /* enable DAC */
 427         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
 428 }
 429
 430 static void hal2_start_adc(struct snd_hal2 *hal2)
 431 {
 432         struct hal2_pbus *pbus = &hal2->adc.pbus;
 433
 434         pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
 435         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
 436         /* enable ADC */
 437         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
 438 }
 439
 440 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
 441 {
 442         hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 443         /* The HAL2 itself may remain enabled safely */
 444 }
 445
 446 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
 447 {
 448         hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 449 }
 450
 451 static int hal2_alloc_dmabuf(struct hal2_codec *codec)
 452 {
 453         struct hal2_desc *desc;
 454         dma_addr_t desc_dma, buffer_dma;
 455         int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
 456         int i;
 457
 458         codec->buffer = dma_alloc_noncoherent(NULL, H2_BUF_SIZE,
 459                                               &buffer_dma, GFP_KERNEL);
 460         if (!codec->buffer)
 461                 return -ENOMEM;
 462         desc = dma_alloc_noncoherent(NULL, count * sizeof(struct hal2_desc),
 463                                      &desc_dma, GFP_KERNEL);
 464         if (!desc) {
 465                 dma_free_noncoherent(NULL, H2_BUF_SIZE,
 466                                      codec->buffer, buffer_dma);
 467                 return -ENOMEM;
 468         }
 469         codec->buffer_dma = buffer_dma;
 470         codec->desc_dma = desc_dma;
 471         codec->desc = desc;
 472         for (i = 0; i < count; i++) {
 473                 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
 474                 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
 475                 desc->desc.pnext = (i == count - 1) ?
 476                       desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
 477                 desc++;
 478         }
 479         dma_cache_sync(NULL, codec->desc, count * sizeof(struct hal2_desc),
 480                        DMA_TO_DEVICE);
 481         codec->desc_count = count;
 482         return 0;
 483 }
 484
 485 static void hal2_free_dmabuf(struct hal2_codec *codec)
 486 {
 487         dma_free_noncoherent(NULL, codec->desc_count * sizeof(struct hal2_desc),
 488                              codec->desc, codec->desc_dma);
 489         dma_free_noncoherent(NULL, H2_BUF_SIZE, codec->buffer,
 490                              codec->buffer_dma);
 491 }
 492
 493 static struct snd_pcm_hardware hal2_pcm_hw = {
 494         .info = (SNDRV_PCM_INFO_MMAP |
 495                  SNDRV_PCM_INFO_MMAP_VALID |
 496                  SNDRV_PCM_INFO_INTERLEAVED |
 497                  SNDRV_PCM_INFO_BLOCK_TRANSFER),
 498         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 499         .rates =            SNDRV_PCM_RATE_8000_48000,
 500         .rate_min =         8000,
 501         .rate_max =         48000,
 502         .channels_min =     2,
 503         .channels_max =     2,
 504         .buffer_bytes_max = 65536,
 505         .period_bytes_min = 1024,
 506         .period_bytes_max = 65536,
 507         .periods_min =      2,
 508         .periods_max =      1024,
 509 };
 510
 511 static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
 512                               struct snd_pcm_hw_params *params)
 513 {
 514         int err;
 515
 516         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
 517         if (err < 0)
 518                 return err;
 519
 520         return 0;
 521 }
 522
 523 static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
 524 {
 525         return snd_pcm_lib_free_pages(substream);
 526 }
 527
 528 static int hal2_playback_open(struct snd_pcm_substream *substream)
 529 {
 530         struct snd_pcm_runtime *runtime = substream->runtime;
 531         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 532         int err;
 533
 534         runtime->hw = hal2_pcm_hw;
 535
 536         err = hal2_alloc_dmabuf(&hal2->dac);
 537         if (err)
 538                 return err;
 539         return 0;
 540 }
 541
 542 static int hal2_playback_close(struct snd_pcm_substream *substream)
 543 {
 544         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 545
 546         hal2_free_dmabuf(&hal2->dac);
 547         return 0;
 548 }
 549
 550 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
 551 {
 552         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 553         struct snd_pcm_runtime *runtime = substream->runtime;
 554         struct hal2_codec *dac = &hal2->dac;
 555
 556         dac->voices = runtime->channels;
 557         dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
 558         memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
 559         dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
 560         dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
 561         dac->substream = substream;
 562         hal2_setup_dac(hal2);
 563         return 0;
 564 }
 565
 566 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
 567 {
 568         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 569
 570         switch (cmd) {
 571         case SNDRV_PCM_TRIGGER_START:
 572                 hal2->dac.pcm_indirect.hw_io = hal2->dac.buffer_dma;
 573                 hal2->dac.pcm_indirect.hw_data = 0;
 574                 substream->ops->ack(substream);
 575                 hal2_start_dac(hal2);
 576                 break;
 577         case SNDRV_PCM_TRIGGER_STOP:
 578                 hal2_stop_dac(hal2);
 579                 break;
 580         default:
 581                 return -EINVAL;
 582         }
 583         return 0;
 584 }
 585
 586 static snd_pcm_uframes_t
 587 hal2_playback_pointer(struct snd_pcm_substream *substream)
 588 {
 589         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 590         struct hal2_codec *dac = &hal2->dac;
 591
 592         return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
 593                                                  dac->pbus.pbus->pbdma_bptr);
 594 }
 595
 596 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
 597                                    struct snd_pcm_indirect *rec, size_t bytes)
 598 {
 599         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 600         unsigned char *buf = hal2->dac.buffer + rec->hw_data;
 601
 602         memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
 603         dma_cache_sync(NULL, buf, bytes, DMA_TO_DEVICE);
 604
 605 }
 606
 607 static int hal2_playback_ack(struct snd_pcm_substream *substream)
 608 {
 609         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 610         struct hal2_codec *dac = &hal2->dac;
 611
 612         dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
 613         snd_pcm_indirect_playback_transfer(substream,
 614                                            &dac->pcm_indirect,
 615                                            hal2_playback_transfer);
 616         return 0;
 617 }
 618
 619 static int hal2_capture_open(struct snd_pcm_substream *substream)
 620 {
 621         struct snd_pcm_runtime *runtime = substream->runtime;
 622         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 623         struct hal2_codec *adc = &hal2->adc;
 624         int err;
 625
 626         runtime->hw = hal2_pcm_hw;
 627
 628         err = hal2_alloc_dmabuf(adc);
 629         if (err)
 630                 return err;
 631         return 0;
 632 }
 633
 634 static int hal2_capture_close(struct snd_pcm_substream *substream)
 635 {
 636         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 637
 638         hal2_free_dmabuf(&hal2->adc);
 639         return 0;
 640 }
 641
 642 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
 643 {
 644         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 645         struct snd_pcm_runtime *runtime = substream->runtime;
 646         struct hal2_codec *adc = &hal2->adc;
 647
 648         adc->voices = runtime->channels;
 649         adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
 650         memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
 651         adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
 652         adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
 653         adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
 654         adc->substream = substream;
 655         hal2_setup_adc(hal2);
 656         return 0;
 657 }
 658
 659 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
 660 {
 661         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 662
 663         switch (cmd) {
 664         case SNDRV_PCM_TRIGGER_START:
 665                 hal2->adc.pcm_indirect.hw_io = hal2->adc.buffer_dma;
 666                 hal2->adc.pcm_indirect.hw_data = 0;
 667                 printk(KERN_DEBUG "buffer_dma %x\n", hal2->adc.buffer_dma);
 668                 hal2_start_adc(hal2);
 669                 break;
 670         case SNDRV_PCM_TRIGGER_STOP:
 671                 hal2_stop_adc(hal2);
 672                 break;
 673         default:
 674                 return -EINVAL;
 675         }
 676         return 0;
 677 }
 678
 679 static snd_pcm_uframes_t
 680 hal2_capture_pointer(struct snd_pcm_substream *substream)
 681 {
 682         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 683         struct hal2_codec *adc = &hal2->adc;
 684
 685         return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
 686                                                 adc->pbus.pbus->pbdma_bptr);
 687 }
 688
 689 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
 690                                   struct snd_pcm_indirect *rec, size_t bytes)
 691 {
 692         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 693         unsigned char *buf = hal2->adc.buffer + rec->hw_data;
 694
 695         dma_cache_sync(NULL, buf, bytes, DMA_FROM_DEVICE);
 696         memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
 697 }
 698
 699 static int hal2_capture_ack(struct snd_pcm_substream *substream)
 700 {
 701         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 702         struct hal2_codec *adc = &hal2->adc;
 703
 704         snd_pcm_indirect_capture_transfer(substream,
 705                                           &adc->pcm_indirect,
 706                                           hal2_capture_transfer);
 707         return 0;
 708 }
 709
 710 static struct snd_pcm_ops hal2_playback_ops = {
 711         .open =        hal2_playback_open,
 712         .close =       hal2_playback_close,
 713         .ioctl =       snd_pcm_lib_ioctl,
 714         .hw_params =   hal2_pcm_hw_params,
 715         .hw_free =     hal2_pcm_hw_free,
 716         .prepare =     hal2_playback_prepare,
 717         .trigger =     hal2_playback_trigger,
 718         .pointer =     hal2_playback_pointer,
 719         .ack =         hal2_playback_ack,
 720 };
 721
 722 static struct snd_pcm_ops hal2_capture_ops = {
 723         .open =        hal2_capture_open,
 724         .close =       hal2_capture_close,
 725         .ioctl =       snd_pcm_lib_ioctl,
 726         .hw_params =   hal2_pcm_hw_params,
 727         .hw_free =     hal2_pcm_hw_free,
 728         .prepare =     hal2_capture_prepare,
 729         .trigger =     hal2_capture_trigger,
 730         .pointer =     hal2_capture_pointer,
 731         .ack =         hal2_capture_ack,
 732 };
 733
 734 static int __devinit hal2_pcm_create(struct snd_hal2 *hal2)
 735 {
 736         struct snd_pcm *pcm;
 737         int err;
 738
 739         /* create first pcm device with one outputs and one input */
 740         err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
 741         if (err < 0)
 742                 return err;
 743
 744         pcm->private_data = hal2;
 745         strcpy(pcm->name, "SGI HAL2");
 746
 747         /* set operators */
 748         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 749                         &hal2_playback_ops);
 750         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 751                         &hal2_capture_ops);
 752         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
 753                                            snd_dma_continuous_data(GFP_KERNEL),
 754                                            0, 1024 * 1024);
 755
 756         return 0;
 757 }
 758
 759 static int hal2_dev_free(struct snd_device *device)
 760 {
 761         struct snd_hal2 *hal2 = device->device_data;
 762
 763         free_irq(SGI_HPCDMA_IRQ, hal2);
 764         kfree(hal2);
 765         return 0;
 766 }
 767
 768 static struct snd_device_ops hal2_ops = {
 769         .dev_free = hal2_dev_free,
 770 };
 771
 772 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
 773                             int index)
 774 {
 775         codec->pbus.pbusnr = index;
 776         codec->pbus.pbus = &hpc3->pbdma[index];
 777 }
 778
 779 static int hal2_detect(struct snd_hal2 *hal2)
 780 {
 781         unsigned short board, major, minor;
 782         unsigned short rev;
 783
 784         /* reset HAL2 */
 785         hal2_write(0, &hal2->ctl_regs->isr);
 786
 787         /* release reset */
 788         hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
 789                    &hal2->ctl_regs->isr);
 790
 791
 792         hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
 793         rev = hal2_read(&hal2->ctl_regs->rev);
 794         if (rev & H2_REV_AUDIO_PRESENT)
 795                 return -ENODEV;
 796
 797         board = (rev & H2_REV_BOARD_M) >> 12;
 798         major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
 799         minor = (rev & H2_REV_MINOR_CHIP_M);
 800
 801         printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
 802                board, major, minor);
 803
 804         return 0;
 805 }
 806
 807 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
 808 {
 809         struct snd_hal2 *hal2;
 810         struct hpc3_regs *hpc3 = hpc3c0;
 811         int err;
 812
 813         hal2 = kzalloc(sizeof(struct snd_hal2), GFP_KERNEL);
 814         if (!hal2)
 815                 return -ENOMEM;
 816
 817         hal2->card = card;
 818
 819         if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
 820                         "SGI HAL2", hal2)) {
 821                 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
 822                 kfree(hal2);
 823                 return -EAGAIN;
 824         }
 825
 826         hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
 827         hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
 828         hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
 829         hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
 830
 831         if (hal2_detect(hal2) < 0) {
 832                 kfree(hal2);
 833                 return -ENODEV;
 834         }
 835
 836         hal2_init_codec(&hal2->dac, hpc3, 0);
 837         hal2_init_codec(&hal2->adc, hpc3, 1);
 838
 839         /*
 840          * All DMA channel interfaces in HAL2 are designed to operate with
 841          * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
 842          * in D5. HAL2 is a 16-bit device which can accept both big and little
 843          * endian format. It assumes that even address bytes are on high
 844          * portion of PBUS (15:8) and assumes that HPC3 is programmed to
 845          * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
 846          */
 847 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
 848                           (2 << HPC3_DMACFG_D4R_SHIFT) | \
 849                           (2 << HPC3_DMACFG_D5R_SHIFT) | \
 850                           (0 << HPC3_DMACFG_D3W_SHIFT) | \
 851                           (2 << HPC3_DMACFG_D4W_SHIFT) | \
 852                           (2 << HPC3_DMACFG_D5W_SHIFT) | \
 853                                 HPC3_DMACFG_DS16 | \
 854                                 HPC3_DMACFG_EVENHI | \
 855                                 HPC3_DMACFG_RTIME | \
 856                           (8 << HPC3_DMACFG_BURST_SHIFT) | \
 857                                 HPC3_DMACFG_DRQLIVE)
 858         /*
 859          * Ignore what's mentioned in the specification and write value which
 860          * works in The Real World (TM)
 861          */
 862         hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
 863         hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
 864
 865         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
 866         if (err < 0) {
 867                 free_irq(SGI_HPCDMA_IRQ, hal2);
 868                 kfree(hal2);
 869                 return err;
 870         }
 871         *rchip = hal2;
 872         return 0;
 873 }
 874
 875 static int __devinit hal2_probe(struct platform_device *pdev)
 876 {
 877         struct snd_card *card;
 878         struct snd_hal2 *chip;
 879         int err;
 880
 881         err = snd_card_create(index, id, THIS_MODULE, 0, &card);
 882         if (err < 0)
 883                 return err;
 884
 885         err = hal2_create(card, &chip);
 886         if (err < 0) {
 887                 snd_card_free(card);
 888                 return err;
 889         }
 890         snd_card_set_dev(card, &pdev->dev);
 891
 892         err = hal2_pcm_create(chip);
 893         if (err < 0) {
 894                 snd_card_free(card);
 895                 return err;
 896         }
 897         err = hal2_mixer_create(chip);
 898         if (err < 0) {
 899                 snd_card_free(card);
 900                 return err;
 901         }
 902
 903         strcpy(card->driver, "SGI HAL2 Audio");
 904         strcpy(card->shortname, "SGI HAL2 Audio");
 905         sprintf(card->longname, "%s irq %i",
 906                 card->shortname,
 907                 SGI_HPCDMA_IRQ);
 908
 909         err = snd_card_register(card);
 910         if (err < 0) {
 911                 snd_card_free(card);
 912                 return err;
 913         }
 914         platform_set_drvdata(pdev, card);
 915         return 0;
 916 }
 917
 918 static int __exit hal2_remove(struct platform_device *pdev)
 919 {
 920         struct snd_card *card = platform_get_drvdata(pdev);
 921
 922         snd_card_free(card);
 923         platform_set_drvdata(pdev, NULL);
 924         return 0;
 925 }
 926
 927 static struct platform_driver hal2_driver = {
 928         .probe  = hal2_probe,
 929         .remove = __devexit_p(hal2_remove),
 930         .driver = {
 931                 .name   = "sgihal2",
 932                 .owner  = THIS_MODULE,
 933         }
 934 };
 935
 936 static int __init alsa_card_hal2_init(void)
 937 {
 938         return platform_driver_register(&hal2_driver);
 939 }
 940
 941 static void __exit alsa_card_hal2_exit(void)
 942 {
 943         platform_driver_unregister(&hal2_driver);
 944 }
 945
 946 module_init(alsa_card_hal2_init);
 947 module_exit(alsa_card_hal2_exit);