f9707fb05efe6812e9ec2ad69fb45e96b9bd9db5
[sfrench/cifs-2.6.git] / sound / hda / hdac_stream.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio stream operations
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/core.h>
11 #include <sound/pcm.h>
12 #include <sound/hdaudio.h>
13 #include <sound/hda_register.h>
14 #include "trace.h"
15
16 /**
17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
18  * @bus: HD-audio core bus
19  * @substream: PCM substream
20  */
21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
22                                    struct snd_pcm_substream *substream)
23 {
24         struct snd_pcm_runtime *runtime = substream->runtime;
25         unsigned int channels = runtime->channels,
26                      rate = runtime->rate,
27                      bits_per_sample = runtime->sample_bits,
28                      max_sdo_lines, value, sdo_line;
29
30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
32
33         /* following is from HD audio spec */
34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
35                 if (rate > 48000)
36                         value = (channels * bits_per_sample *
37                                         (rate / 48000)) / sdo_line;
38                 else
39                         value = (channels * bits_per_sample) / sdo_line;
40
41                 if (value >= 8)
42                         break;
43         }
44
45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
46         return sdo_line >> 1;
47 }
48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
49
50 /**
51  * snd_hdac_stream_init - initialize each stream (aka device)
52  * @bus: HD-audio core bus
53  * @azx_dev: HD-audio core stream object to initialize
54  * @idx: stream index number
55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
56  * @tag: the tag id to assign
57  *
58  * Assign the starting bdl address to each stream (device) and initialize.
59  */
60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
61                           int idx, int direction, int tag)
62 {
63         azx_dev->bus = bus;
64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
67         azx_dev->sd_int_sta_mask = 1 << idx;
68         azx_dev->index = idx;
69         azx_dev->direction = direction;
70         azx_dev->stream_tag = tag;
71         snd_hdac_dsp_lock_init(azx_dev);
72         list_add_tail(&azx_dev->list, &bus->stream_list);
73 }
74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
75
76 /**
77  * snd_hdac_stream_start - start a stream
78  * @azx_dev: HD-audio core stream to start
79  * @fresh_start: false = wallclock timestamp relative to period wallclock
80  *
81  * Start a stream, set start_wallclk and set the running flag.
82  */
83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
84 {
85         struct hdac_bus *bus = azx_dev->bus;
86         int stripe_ctl;
87
88         trace_snd_hdac_stream_start(bus, azx_dev);
89
90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
91         if (!fresh_start)
92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
93
94         /* enable SIE */
95         snd_hdac_chip_updatel(bus, INTCTL,
96                               1 << azx_dev->index,
97                               1 << azx_dev->index);
98         /* set stripe control */
99         if (azx_dev->stripe) {
100                 if (azx_dev->substream)
101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102                 else
103                         stripe_ctl = 0;
104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
105                                         stripe_ctl);
106         }
107         /* set DMA start and interrupt mask */
108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
110         azx_dev->running = true;
111 }
112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
113
114 /**
115  * snd_hdac_stream_clear - stop a stream DMA
116  * @azx_dev: HD-audio core stream to stop
117  */
118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
119 {
120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
123         if (azx_dev->stripe) {
124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
125                 azx_dev->stripe = 0;
126         }
127         azx_dev->running = false;
128 }
129 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
130
131 /**
132  * snd_hdac_stream_stop - stop a stream
133  * @azx_dev: HD-audio core stream to stop
134  *
135  * Stop a stream DMA and disable stream interrupt
136  */
137 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
138 {
139         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
140
141         snd_hdac_stream_clear(azx_dev);
142         /* disable SIE */
143         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
144 }
145 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
146
147 /**
148  * snd_hdac_stream_reset - reset a stream
149  * @azx_dev: HD-audio core stream to reset
150  */
151 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
152 {
153         unsigned char val;
154         int timeout;
155
156         snd_hdac_stream_clear(azx_dev);
157
158         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
159         udelay(3);
160         timeout = 300;
161         do {
162                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
163                         SD_CTL_STREAM_RESET;
164                 if (val)
165                         break;
166         } while (--timeout);
167         val &= ~SD_CTL_STREAM_RESET;
168         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
169         udelay(3);
170
171         timeout = 300;
172         /* waiting for hardware to report that the stream is out of reset */
173         do {
174                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
175                         SD_CTL_STREAM_RESET;
176                 if (!val)
177                         break;
178         } while (--timeout);
179
180         /* reset first position - may not be synced with hw at this time */
181         if (azx_dev->posbuf)
182                 *azx_dev->posbuf = 0;
183 }
184 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
185
186 /**
187  * snd_hdac_stream_setup -  set up the SD for streaming
188  * @azx_dev: HD-audio core stream to set up
189  */
190 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
191 {
192         struct hdac_bus *bus = azx_dev->bus;
193         struct snd_pcm_runtime *runtime;
194         unsigned int val;
195
196         if (azx_dev->substream)
197                 runtime = azx_dev->substream->runtime;
198         else
199                 runtime = NULL;
200         /* make sure the run bit is zero for SD */
201         snd_hdac_stream_clear(azx_dev);
202         /* program the stream_tag */
203         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
204         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
205                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
206         if (!bus->snoop)
207                 val |= SD_CTL_TRAFFIC_PRIO;
208         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
209
210         /* program the length of samples in cyclic buffer */
211         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
212
213         /* program the stream format */
214         /* this value needs to be the same as the one programmed */
215         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
216
217         /* program the stream LVI (last valid index) of the BDL */
218         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
219
220         /* program the BDL address */
221         /* lower BDL address */
222         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
223         /* upper BDL address */
224         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
225                                upper_32_bits(azx_dev->bdl.addr));
226
227         /* enable the position buffer */
228         if (bus->use_posbuf && bus->posbuf.addr) {
229                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
230                         snd_hdac_chip_writel(bus, DPLBASE,
231                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
232         }
233
234         /* set the interrupt enable bits in the descriptor control register */
235         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
236
237         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
238
239         /* when LPIB delay correction gives a small negative value,
240          * we ignore it; currently set the threshold statically to
241          * 64 frames
242          */
243         if (runtime && runtime->period_size > 64)
244                 azx_dev->delay_negative_threshold =
245                         -frames_to_bytes(runtime, 64);
246         else
247                 azx_dev->delay_negative_threshold = 0;
248
249         /* wallclk has 24Mhz clock source */
250         if (runtime)
251                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
252                                     runtime->rate) * 1000);
253
254         return 0;
255 }
256 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
257
258 /**
259  * snd_hdac_stream_cleanup - cleanup a stream
260  * @azx_dev: HD-audio core stream to clean up
261  */
262 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
263 {
264         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
265         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
266         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
267         azx_dev->bufsize = 0;
268         azx_dev->period_bytes = 0;
269         azx_dev->format_val = 0;
270 }
271 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
272
273 /**
274  * snd_hdac_stream_assign - assign a stream for the PCM
275  * @bus: HD-audio core bus
276  * @substream: PCM substream to assign
277  *
278  * Look for an unused stream for the given PCM substream, assign it
279  * and return the stream object.  If no stream is free, returns NULL.
280  * The function tries to keep using the same stream object when it's used
281  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
282  * or matching entry is returned.  This is needed for some strange codecs.
283  */
284 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
285                                            struct snd_pcm_substream *substream)
286 {
287         struct hdac_stream *azx_dev;
288         struct hdac_stream *res = NULL;
289
290         /* make a non-zero unique key for the substream */
291         int key = (substream->pcm->device << 16) | (substream->number << 2) |
292                 (substream->stream + 1);
293
294         list_for_each_entry(azx_dev, &bus->stream_list, list) {
295                 if (azx_dev->direction != substream->stream)
296                         continue;
297                 if (azx_dev->opened)
298                         continue;
299                 if (azx_dev->assigned_key == key) {
300                         res = azx_dev;
301                         break;
302                 }
303                 if (!res || bus->reverse_assign)
304                         res = azx_dev;
305         }
306         if (res) {
307                 spin_lock_irq(&bus->reg_lock);
308                 res->opened = 1;
309                 res->running = 0;
310                 res->assigned_key = key;
311                 res->substream = substream;
312                 spin_unlock_irq(&bus->reg_lock);
313         }
314         return res;
315 }
316 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
317
318 /**
319  * snd_hdac_stream_release - release the assigned stream
320  * @azx_dev: HD-audio core stream to release
321  *
322  * Release the stream that has been assigned by snd_hdac_stream_assign().
323  */
324 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
325 {
326         struct hdac_bus *bus = azx_dev->bus;
327
328         spin_lock_irq(&bus->reg_lock);
329         azx_dev->opened = 0;
330         azx_dev->running = 0;
331         azx_dev->substream = NULL;
332         spin_unlock_irq(&bus->reg_lock);
333 }
334 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
335
336 /**
337  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
338  * direction
339  *
340  * @bus: HD-audio core bus
341  * @dir: direction for the stream to be found
342  * @stream_tag: stream tag for stream to be found
343  */
344 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
345                                         int dir, int stream_tag)
346 {
347         struct hdac_stream *s;
348
349         list_for_each_entry(s, &bus->stream_list, list) {
350                 if (s->direction == dir && s->stream_tag == stream_tag)
351                         return s;
352         }
353
354         return NULL;
355 }
356 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
357
358 /*
359  * set up a BDL entry
360  */
361 static int setup_bdle(struct hdac_bus *bus,
362                       struct snd_dma_buffer *dmab,
363                       struct hdac_stream *azx_dev, __le32 **bdlp,
364                       int ofs, int size, int with_ioc)
365 {
366         __le32 *bdl = *bdlp;
367
368         while (size > 0) {
369                 dma_addr_t addr;
370                 int chunk;
371
372                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
373                         return -EINVAL;
374
375                 addr = snd_sgbuf_get_addr(dmab, ofs);
376                 /* program the address field of the BDL entry */
377                 bdl[0] = cpu_to_le32((u32)addr);
378                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
379                 /* program the size field of the BDL entry */
380                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
381                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
382                 if (bus->align_bdle_4k) {
383                         u32 remain = 0x1000 - (ofs & 0xfff);
384
385                         if (chunk > remain)
386                                 chunk = remain;
387                 }
388                 bdl[2] = cpu_to_le32(chunk);
389                 /* program the IOC to enable interrupt
390                  * only when the whole fragment is processed
391                  */
392                 size -= chunk;
393                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
394                 bdl += 4;
395                 azx_dev->frags++;
396                 ofs += chunk;
397         }
398         *bdlp = bdl;
399         return ofs;
400 }
401
402 /**
403  * snd_hdac_stream_setup_periods - set up BDL entries
404  * @azx_dev: HD-audio core stream to set up
405  *
406  * Set up the buffer descriptor table of the given stream based on the
407  * period and buffer sizes of the assigned PCM substream.
408  */
409 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
410 {
411         struct hdac_bus *bus = azx_dev->bus;
412         struct snd_pcm_substream *substream = azx_dev->substream;
413         struct snd_pcm_runtime *runtime = substream->runtime;
414         __le32 *bdl;
415         int i, ofs, periods, period_bytes;
416         int pos_adj, pos_align;
417
418         /* reset BDL address */
419         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
420         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
421
422         period_bytes = azx_dev->period_bytes;
423         periods = azx_dev->bufsize / period_bytes;
424
425         /* program the initial BDL entries */
426         bdl = (__le32 *)azx_dev->bdl.area;
427         ofs = 0;
428         azx_dev->frags = 0;
429
430         pos_adj = bus->bdl_pos_adj;
431         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
432                 pos_align = pos_adj;
433                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
434                 if (!pos_adj)
435                         pos_adj = pos_align;
436                 else
437                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
438                                 pos_align;
439                 pos_adj = frames_to_bytes(runtime, pos_adj);
440                 if (pos_adj >= period_bytes) {
441                         dev_warn(bus->dev, "Too big adjustment %d\n",
442                                  pos_adj);
443                         pos_adj = 0;
444                 } else {
445                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
446                                          azx_dev,
447                                          &bdl, ofs, pos_adj, true);
448                         if (ofs < 0)
449                                 goto error;
450                 }
451         } else
452                 pos_adj = 0;
453
454         for (i = 0; i < periods; i++) {
455                 if (i == periods - 1 && pos_adj)
456                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
457                                          azx_dev, &bdl, ofs,
458                                          period_bytes - pos_adj, 0);
459                 else
460                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
461                                          azx_dev, &bdl, ofs,
462                                          period_bytes,
463                                          !azx_dev->no_period_wakeup);
464                 if (ofs < 0)
465                         goto error;
466         }
467         return 0;
468
469  error:
470         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
471                 azx_dev->bufsize, period_bytes);
472         return -EINVAL;
473 }
474 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
475
476 /**
477  * snd_hdac_stream_set_params - set stream parameters
478  * @azx_dev: HD-audio core stream for which parameters are to be set
479  * @format_val: format value parameter
480  *
481  * Setup the HD-audio core stream parameters from substream of the stream
482  * and passed format value
483  */
484 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
485                                  unsigned int format_val)
486 {
487
488         unsigned int bufsize, period_bytes;
489         struct snd_pcm_substream *substream = azx_dev->substream;
490         struct snd_pcm_runtime *runtime;
491         int err;
492
493         if (!substream)
494                 return -EINVAL;
495         runtime = substream->runtime;
496         bufsize = snd_pcm_lib_buffer_bytes(substream);
497         period_bytes = snd_pcm_lib_period_bytes(substream);
498
499         if (bufsize != azx_dev->bufsize ||
500             period_bytes != azx_dev->period_bytes ||
501             format_val != azx_dev->format_val ||
502             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
503                 azx_dev->bufsize = bufsize;
504                 azx_dev->period_bytes = period_bytes;
505                 azx_dev->format_val = format_val;
506                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
507                 err = snd_hdac_stream_setup_periods(azx_dev);
508                 if (err < 0)
509                         return err;
510         }
511         return 0;
512 }
513 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
514
515 static u64 azx_cc_read(const struct cyclecounter *cc)
516 {
517         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
518
519         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
520 }
521
522 static void azx_timecounter_init(struct hdac_stream *azx_dev,
523                                  bool force, u64 last)
524 {
525         struct timecounter *tc = &azx_dev->tc;
526         struct cyclecounter *cc = &azx_dev->cc;
527         u64 nsec;
528
529         cc->read = azx_cc_read;
530         cc->mask = CLOCKSOURCE_MASK(32);
531
532         /*
533          * Converting from 24 MHz to ns means applying a 125/3 factor.
534          * To avoid any saturation issues in intermediate operations,
535          * the 125 factor is applied first. The division is applied
536          * last after reading the timecounter value.
537          * Applying the 1/3 factor as part of the multiplication
538          * requires at least 20 bits for a decent precision, however
539          * overflows occur after about 4 hours or less, not a option.
540          */
541
542         cc->mult = 125; /* saturation after 195 years */
543         cc->shift = 0;
544
545         nsec = 0; /* audio time is elapsed time since trigger */
546         timecounter_init(tc, cc, nsec);
547         if (force) {
548                 /*
549                  * force timecounter to use predefined value,
550                  * used for synchronized starts
551                  */
552                 tc->cycle_last = last;
553         }
554 }
555
556 /**
557  * snd_hdac_stream_timecounter_init - initialize time counter
558  * @azx_dev: HD-audio core stream (master stream)
559  * @streams: bit flags of streams to set up
560  *
561  * Initializes the time counter of streams marked by the bit flags (each
562  * bit corresponds to the stream index).
563  * The trigger timestamp of PCM substream assigned to the given stream is
564  * updated accordingly, too.
565  */
566 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
567                                       unsigned int streams)
568 {
569         struct hdac_bus *bus = azx_dev->bus;
570         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
571         struct hdac_stream *s;
572         bool inited = false;
573         u64 cycle_last = 0;
574         int i = 0;
575
576         list_for_each_entry(s, &bus->stream_list, list) {
577                 if (streams & (1 << i)) {
578                         azx_timecounter_init(s, inited, cycle_last);
579                         if (!inited) {
580                                 inited = true;
581                                 cycle_last = s->tc.cycle_last;
582                         }
583                 }
584                 i++;
585         }
586
587         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
588         runtime->trigger_tstamp_latched = true;
589 }
590 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
591
592 /**
593  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
594  * @azx_dev: HD-audio core stream (master stream)
595  * @streams: bit flags of streams to sync
596  */
597 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
598                                   unsigned int streams, unsigned int reg)
599 {
600         struct hdac_bus *bus = azx_dev->bus;
601         unsigned int val;
602
603         if (!reg)
604                 reg = AZX_REG_SSYNC;
605         val = _snd_hdac_chip_readl(bus, reg);
606         if (set)
607                 val |= streams;
608         else
609                 val &= ~streams;
610         _snd_hdac_chip_writel(bus, reg, val);
611 }
612 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
613
614 /**
615  * snd_hdac_stream_sync - sync with start/strop trigger operation
616  * @azx_dev: HD-audio core stream (master stream)
617  * @start: true = start, false = stop
618  * @streams: bit flags of streams to sync
619  *
620  * For @start = true, wait until all FIFOs get ready.
621  * For @start = false, wait until all RUN bits are cleared.
622  */
623 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
624                           unsigned int streams)
625 {
626         struct hdac_bus *bus = azx_dev->bus;
627         int i, nwait, timeout;
628         struct hdac_stream *s;
629
630         for (timeout = 5000; timeout; timeout--) {
631                 nwait = 0;
632                 i = 0;
633                 list_for_each_entry(s, &bus->stream_list, list) {
634                         if (streams & (1 << i)) {
635                                 if (start) {
636                                         /* check FIFO gets ready */
637                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
638                                               SD_STS_FIFO_READY))
639                                                 nwait++;
640                                 } else {
641                                         /* check RUN bit is cleared */
642                                         if (snd_hdac_stream_readb(s, SD_CTL) &
643                                             SD_CTL_DMA_START)
644                                                 nwait++;
645                                 }
646                         }
647                         i++;
648                 }
649                 if (!nwait)
650                         break;
651                 cpu_relax();
652         }
653 }
654 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
655
656 #ifdef CONFIG_SND_HDA_DSP_LOADER
657 /**
658  * snd_hdac_dsp_prepare - prepare for DSP loading
659  * @azx_dev: HD-audio core stream used for DSP loading
660  * @format: HD-audio stream format
661  * @byte_size: data chunk byte size
662  * @bufp: allocated buffer
663  *
664  * Allocate the buffer for the given size and set up the given stream for
665  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
666  */
667 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
668                          unsigned int byte_size, struct snd_dma_buffer *bufp)
669 {
670         struct hdac_bus *bus = azx_dev->bus;
671         __le32 *bdl;
672         int err;
673
674         snd_hdac_dsp_lock(azx_dev);
675         spin_lock_irq(&bus->reg_lock);
676         if (azx_dev->running || azx_dev->locked) {
677                 spin_unlock_irq(&bus->reg_lock);
678                 err = -EBUSY;
679                 goto unlock;
680         }
681         azx_dev->locked = true;
682         spin_unlock_irq(&bus->reg_lock);
683
684         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
685                                   byte_size, bufp);
686         if (err < 0)
687                 goto err_alloc;
688
689         azx_dev->substream = NULL;
690         azx_dev->bufsize = byte_size;
691         azx_dev->period_bytes = byte_size;
692         azx_dev->format_val = format;
693
694         snd_hdac_stream_reset(azx_dev);
695
696         /* reset BDL address */
697         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
698         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
699
700         azx_dev->frags = 0;
701         bdl = (__le32 *)azx_dev->bdl.area;
702         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
703         if (err < 0)
704                 goto error;
705
706         snd_hdac_stream_setup(azx_dev);
707         snd_hdac_dsp_unlock(azx_dev);
708         return azx_dev->stream_tag;
709
710  error:
711         snd_dma_free_pages(bufp);
712  err_alloc:
713         spin_lock_irq(&bus->reg_lock);
714         azx_dev->locked = false;
715         spin_unlock_irq(&bus->reg_lock);
716  unlock:
717         snd_hdac_dsp_unlock(azx_dev);
718         return err;
719 }
720 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
721
722 /**
723  * snd_hdac_dsp_trigger - start / stop DSP loading
724  * @azx_dev: HD-audio core stream used for DSP loading
725  * @start: trigger start or stop
726  */
727 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
728 {
729         if (start)
730                 snd_hdac_stream_start(azx_dev, true);
731         else
732                 snd_hdac_stream_stop(azx_dev);
733 }
734 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
735
736 /**
737  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
738  * @azx_dev: HD-audio core stream used for DSP loading
739  * @dmab: buffer used by DSP loading
740  */
741 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
742                           struct snd_dma_buffer *dmab)
743 {
744         struct hdac_bus *bus = azx_dev->bus;
745
746         if (!dmab->area || !azx_dev->locked)
747                 return;
748
749         snd_hdac_dsp_lock(azx_dev);
750         /* reset BDL address */
751         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
752         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
753         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
754         azx_dev->bufsize = 0;
755         azx_dev->period_bytes = 0;
756         azx_dev->format_val = 0;
757
758         snd_dma_free_pages(dmab);
759         dmab->area = NULL;
760
761         spin_lock_irq(&bus->reg_lock);
762         azx_dev->locked = false;
763         spin_unlock_irq(&bus->reg_lock);
764         snd_hdac_dsp_unlock(azx_dev);
765 }
766 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
767 #endif /* CONFIG_SND_HDA_DSP_LOADER */