sound/hda/hdac_stream.c

   1 /*
   2  * HD-audio stream operations
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <linux/clocksource.h>
   9 #include <sound/core.h>
  10 #include <sound/pcm.h>
  11 #include <sound/hdaudio.h>
  12 #include <sound/hda_register.h>
  13 #include "trace.h"
  14
  15 /**
  16  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  17  * @bus: HD-audio core bus
  18  * @substream: PCM substream
  19  */
  20 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  21                                    struct snd_pcm_substream *substream)
  22 {
  23         struct snd_pcm_runtime *runtime = substream->runtime;
  24         unsigned int channels = runtime->channels,
  25                      rate = runtime->rate,
  26                      bits_per_sample = runtime->sample_bits,
  27                      max_sdo_lines, value, sdo_line;
  28
  29         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  30         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  31
  32         /* following is from HD audio spec */
  33         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  34                 if (rate > 48000)
  35                         value = (channels * bits_per_sample *
  36                                         (rate / 48000)) / sdo_line;
  37                 else
  38                         value = (channels * bits_per_sample) / sdo_line;
  39
  40                 if (value >= 8)
  41                         break;
  42         }
  43
  44         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  45         return sdo_line >> 1;
  46 }
  47 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  48
  49 /**
  50  * snd_hdac_stream_init - initialize each stream (aka device)
  51  * @bus: HD-audio core bus
  52  * @azx_dev: HD-audio core stream object to initialize
  53  * @idx: stream index number
  54  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  55  * @tag: the tag id to assign
  56  *
  57  * Assign the starting bdl address to each stream (device) and initialize.
  58  */
  59 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  60                           int idx, int direction, int tag)
  61 {
  62         azx_dev->bus = bus;
  63         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  64         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  65         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  66         azx_dev->sd_int_sta_mask = 1 << idx;
  67         azx_dev->index = idx;
  68         azx_dev->direction = direction;
  69         azx_dev->stream_tag = tag;
  70         snd_hdac_dsp_lock_init(azx_dev);
  71         list_add_tail(&azx_dev->list, &bus->stream_list);
  72 }
  73 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  74
  75 /**
  76  * snd_hdac_stream_start - start a stream
  77  * @azx_dev: HD-audio core stream to start
  78  * @fresh_start: false = wallclock timestamp relative to period wallclock
  79  *
  80  * Start a stream, set start_wallclk and set the running flag.
  81  */
  82 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  83 {
  84         struct hdac_bus *bus = azx_dev->bus;
  85         int stripe_ctl;
  86
  87         trace_snd_hdac_stream_start(bus, azx_dev);
  88
  89         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  90         if (!fresh_start)
  91                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  92
  93         /* enable SIE */
  94         snd_hdac_chip_updatel(bus, INTCTL,
  95                               1 << azx_dev->index,
  96                               1 << azx_dev->index);
  97         /* set stripe control */
  98         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
  99         snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 100                                 stripe_ctl);
 101         /* set DMA start and interrupt mask */
 102         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 103                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 104         azx_dev->running = true;
 105 }
 106 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 107
 108 /**
 109  * snd_hdac_stream_clear - stop a stream DMA
 110  * @azx_dev: HD-audio core stream to stop
 111  */
 112 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 113 {
 114         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 115                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 116         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 117         snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 118         azx_dev->running = false;
 119 }
 120 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
 121
 122 /**
 123  * snd_hdac_stream_stop - stop a stream
 124  * @azx_dev: HD-audio core stream to stop
 125  *
 126  * Stop a stream DMA and disable stream interrupt
 127  */
 128 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 129 {
 130         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 131
 132         snd_hdac_stream_clear(azx_dev);
 133         /* disable SIE */
 134         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 135 }
 136 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 137
 138 /**
 139  * snd_hdac_stream_reset - reset a stream
 140  * @azx_dev: HD-audio core stream to reset
 141  */
 142 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 143 {
 144         unsigned char val;
 145         int timeout;
 146
 147         snd_hdac_stream_clear(azx_dev);
 148
 149         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 150         udelay(3);
 151         timeout = 300;
 152         do {
 153                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 154                         SD_CTL_STREAM_RESET;
 155                 if (val)
 156                         break;
 157         } while (--timeout);
 158         val &= ~SD_CTL_STREAM_RESET;
 159         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 160         udelay(3);
 161
 162         timeout = 300;
 163         /* waiting for hardware to report that the stream is out of reset */
 164         do {
 165                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 166                         SD_CTL_STREAM_RESET;
 167                 if (!val)
 168                         break;
 169         } while (--timeout);
 170
 171         /* reset first position - may not be synced with hw at this time */
 172         if (azx_dev->posbuf)
 173                 *azx_dev->posbuf = 0;
 174 }
 175 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 176
 177 /**
 178  * snd_hdac_stream_setup -  set up the SD for streaming
 179  * @azx_dev: HD-audio core stream to set up
 180  */
 181 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 182 {
 183         struct hdac_bus *bus = azx_dev->bus;
 184         struct snd_pcm_runtime *runtime;
 185         unsigned int val;
 186
 187         if (azx_dev->substream)
 188                 runtime = azx_dev->substream->runtime;
 189         else
 190                 runtime = NULL;
 191         /* make sure the run bit is zero for SD */
 192         snd_hdac_stream_clear(azx_dev);
 193         /* program the stream_tag */
 194         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 195         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 196                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 197         if (!bus->snoop)
 198                 val |= SD_CTL_TRAFFIC_PRIO;
 199         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 200
 201         /* program the length of samples in cyclic buffer */
 202         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 203
 204         /* program the stream format */
 205         /* this value needs to be the same as the one programmed */
 206         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 207
 208         /* program the stream LVI (last valid index) of the BDL */
 209         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 210
 211         /* program the BDL address */
 212         /* lower BDL address */
 213         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 214         /* upper BDL address */
 215         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 216                                upper_32_bits(azx_dev->bdl.addr));
 217
 218         /* enable the position buffer */
 219         if (bus->use_posbuf && bus->posbuf.addr) {
 220                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 221                         snd_hdac_chip_writel(bus, DPLBASE,
 222                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 223         }
 224
 225         /* set the interrupt enable bits in the descriptor control register */
 226         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 227
 228         if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
 229                 azx_dev->fifo_size =
 230                         snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 231         else
 232                 azx_dev->fifo_size = 0;
 233
 234         /* when LPIB delay correction gives a small negative value,
 235          * we ignore it; currently set the threshold statically to
 236          * 64 frames
 237          */
 238         if (runtime && runtime->period_size > 64)
 239                 azx_dev->delay_negative_threshold =
 240                         -frames_to_bytes(runtime, 64);
 241         else
 242                 azx_dev->delay_negative_threshold = 0;
 243
 244         /* wallclk has 24Mhz clock source */
 245         if (runtime)
 246                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 247                                     runtime->rate) * 1000);
 248
 249         return 0;
 250 }
 251 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 252
 253 /**
 254  * snd_hdac_stream_cleanup - cleanup a stream
 255  * @azx_dev: HD-audio core stream to clean up
 256  */
 257 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 258 {
 259         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 260         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 261         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 262         azx_dev->bufsize = 0;
 263         azx_dev->period_bytes = 0;
 264         azx_dev->format_val = 0;
 265 }
 266 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 267
 268 /**
 269  * snd_hdac_stream_assign - assign a stream for the PCM
 270  * @bus: HD-audio core bus
 271  * @substream: PCM substream to assign
 272  *
 273  * Look for an unused stream for the given PCM substream, assign it
 274  * and return the stream object.  If no stream is free, returns NULL.
 275  * The function tries to keep using the same stream object when it's used
 276  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 277  * or matching entry is returned.  This is needed for some strange codecs.
 278  */
 279 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 280                                            struct snd_pcm_substream *substream)
 281 {
 282         struct hdac_stream *azx_dev;
 283         struct hdac_stream *res = NULL;
 284
 285         /* make a non-zero unique key for the substream */
 286         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 287                 (substream->stream + 1);
 288
 289         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 290                 if (azx_dev->direction != substream->stream)
 291                         continue;
 292                 if (azx_dev->opened)
 293                         continue;
 294                 if (azx_dev->assigned_key == key) {
 295                         res = azx_dev;
 296                         break;
 297                 }
 298                 if (!res || bus->reverse_assign)
 299                         res = azx_dev;
 300         }
 301         if (res) {
 302                 spin_lock_irq(&bus->reg_lock);
 303                 res->opened = 1;
 304                 res->running = 0;
 305                 res->assigned_key = key;
 306                 res->substream = substream;
 307                 spin_unlock_irq(&bus->reg_lock);
 308         }
 309         return res;
 310 }
 311 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 312
 313 /**
 314  * snd_hdac_stream_release - release the assigned stream
 315  * @azx_dev: HD-audio core stream to release
 316  *
 317  * Release the stream that has been assigned by snd_hdac_stream_assign().
 318  */
 319 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 320 {
 321         struct hdac_bus *bus = azx_dev->bus;
 322
 323         spin_lock_irq(&bus->reg_lock);
 324         azx_dev->opened = 0;
 325         azx_dev->running = 0;
 326         azx_dev->substream = NULL;
 327         spin_unlock_irq(&bus->reg_lock);
 328 }
 329 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 330
 331 /**
 332  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 333  * direction
 334  *
 335  * @bus: HD-audio core bus
 336  * @dir: direction for the stream to be found
 337  * @stream_tag: stream tag for stream to be found
 338  */
 339 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 340                                         int dir, int stream_tag)
 341 {
 342         struct hdac_stream *s;
 343
 344         list_for_each_entry(s, &bus->stream_list, list) {
 345                 if (s->direction == dir && s->stream_tag == stream_tag)
 346                         return s;
 347         }
 348
 349         return NULL;
 350 }
 351 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 352
 353 /*
 354  * set up a BDL entry
 355  */
 356 static int setup_bdle(struct hdac_bus *bus,
 357                       struct snd_dma_buffer *dmab,
 358                       struct hdac_stream *azx_dev, __le32 **bdlp,
 359                       int ofs, int size, int with_ioc)
 360 {
 361         __le32 *bdl = *bdlp;
 362
 363         while (size > 0) {
 364                 dma_addr_t addr;
 365                 int chunk;
 366
 367                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 368                         return -EINVAL;
 369
 370                 addr = snd_sgbuf_get_addr(dmab, ofs);
 371                 /* program the address field of the BDL entry */
 372                 bdl[0] = cpu_to_le32((u32)addr);
 373                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 374                 /* program the size field of the BDL entry */
 375                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 376                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 377                 if (bus->align_bdle_4k) {
 378                         u32 remain = 0x1000 - (ofs & 0xfff);
 379
 380                         if (chunk > remain)
 381                                 chunk = remain;
 382                 }
 383                 bdl[2] = cpu_to_le32(chunk);
 384                 /* program the IOC to enable interrupt
 385                  * only when the whole fragment is processed
 386                  */
 387                 size -= chunk;
 388                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 389                 bdl += 4;
 390                 azx_dev->frags++;
 391                 ofs += chunk;
 392         }
 393         *bdlp = bdl;
 394         return ofs;
 395 }
 396
 397 /**
 398  * snd_hdac_stream_setup_periods - set up BDL entries
 399  * @azx_dev: HD-audio core stream to set up
 400  *
 401  * Set up the buffer descriptor table of the given stream based on the
 402  * period and buffer sizes of the assigned PCM substream.
 403  */
 404 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 405 {
 406         struct hdac_bus *bus = azx_dev->bus;
 407         struct snd_pcm_substream *substream = azx_dev->substream;
 408         struct snd_pcm_runtime *runtime = substream->runtime;
 409         __le32 *bdl;
 410         int i, ofs, periods, period_bytes;
 411         int pos_adj, pos_align;
 412
 413         /* reset BDL address */
 414         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 415         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 416
 417         period_bytes = azx_dev->period_bytes;
 418         periods = azx_dev->bufsize / period_bytes;
 419
 420         /* program the initial BDL entries */
 421         bdl = (__le32 *)azx_dev->bdl.area;
 422         ofs = 0;
 423         azx_dev->frags = 0;
 424
 425         pos_adj = bus->bdl_pos_adj;
 426         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 427                 pos_align = pos_adj;
 428                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 429                 if (!pos_adj)
 430                         pos_adj = pos_align;
 431                 else
 432                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 433                                 pos_align;
 434                 pos_adj = frames_to_bytes(runtime, pos_adj);
 435                 if (pos_adj >= period_bytes) {
 436                         dev_warn(bus->dev, "Too big adjustment %d\n",
 437                                  pos_adj);
 438                         pos_adj = 0;
 439                 } else {
 440                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 441                                          azx_dev,
 442                                          &bdl, ofs, pos_adj, true);
 443                         if (ofs < 0)
 444                                 goto error;
 445                 }
 446         } else
 447                 pos_adj = 0;
 448
 449         for (i = 0; i < periods; i++) {
 450                 if (i == periods - 1 && pos_adj)
 451                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 452                                          azx_dev, &bdl, ofs,
 453                                          period_bytes - pos_adj, 0);
 454                 else
 455                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 456                                          azx_dev, &bdl, ofs,
 457                                          period_bytes,
 458                                          !azx_dev->no_period_wakeup);
 459                 if (ofs < 0)
 460                         goto error;
 461         }
 462         return 0;
 463
 464  error:
 465         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 466                 azx_dev->bufsize, period_bytes);
 467         return -EINVAL;
 468 }
 469 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 470
 471 /**
 472  * snd_hdac_stream_set_params - set stream parameters
 473  * @azx_dev: HD-audio core stream for which parameters are to be set
 474  * @format_val: format value parameter
 475  *
 476  * Setup the HD-audio core stream parameters from substream of the stream
 477  * and passed format value
 478  */
 479 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 480                                  unsigned int format_val)
 481 {
 482
 483         unsigned int bufsize, period_bytes;
 484         struct snd_pcm_substream *substream = azx_dev->substream;
 485         struct snd_pcm_runtime *runtime;
 486         int err;
 487
 488         if (!substream)
 489                 return -EINVAL;
 490         runtime = substream->runtime;
 491         bufsize = snd_pcm_lib_buffer_bytes(substream);
 492         period_bytes = snd_pcm_lib_period_bytes(substream);
 493
 494         if (bufsize != azx_dev->bufsize ||
 495             period_bytes != azx_dev->period_bytes ||
 496             format_val != azx_dev->format_val ||
 497             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 498                 azx_dev->bufsize = bufsize;
 499                 azx_dev->period_bytes = period_bytes;
 500                 azx_dev->format_val = format_val;
 501                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 502                 err = snd_hdac_stream_setup_periods(azx_dev);
 503                 if (err < 0)
 504                         return err;
 505         }
 506         return 0;
 507 }
 508 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 509
 510 static u64 azx_cc_read(const struct cyclecounter *cc)
 511 {
 512         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 513
 514         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 515 }
 516
 517 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 518                                  bool force, u64 last)
 519 {
 520         struct timecounter *tc = &azx_dev->tc;
 521         struct cyclecounter *cc = &azx_dev->cc;
 522         u64 nsec;
 523
 524         cc->read = azx_cc_read;
 525         cc->mask = CLOCKSOURCE_MASK(32);
 526
 527         /*
 528          * Converting from 24 MHz to ns means applying a 125/3 factor.
 529          * To avoid any saturation issues in intermediate operations,
 530          * the 125 factor is applied first. The division is applied
 531          * last after reading the timecounter value.
 532          * Applying the 1/3 factor as part of the multiplication
 533          * requires at least 20 bits for a decent precision, however
 534          * overflows occur after about 4 hours or less, not a option.
 535          */
 536
 537         cc->mult = 125; /* saturation after 195 years */
 538         cc->shift = 0;
 539
 540         nsec = 0; /* audio time is elapsed time since trigger */
 541         timecounter_init(tc, cc, nsec);
 542         if (force) {
 543                 /*
 544                  * force timecounter to use predefined value,
 545                  * used for synchronized starts
 546                  */
 547                 tc->cycle_last = last;
 548         }
 549 }
 550
 551 /**
 552  * snd_hdac_stream_timecounter_init - initialize time counter
 553  * @azx_dev: HD-audio core stream (master stream)
 554  * @streams: bit flags of streams to set up
 555  *
 556  * Initializes the time counter of streams marked by the bit flags (each
 557  * bit corresponds to the stream index).
 558  * The trigger timestamp of PCM substream assigned to the given stream is
 559  * updated accordingly, too.
 560  */
 561 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 562                                       unsigned int streams)
 563 {
 564         struct hdac_bus *bus = azx_dev->bus;
 565         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 566         struct hdac_stream *s;
 567         bool inited = false;
 568         u64 cycle_last = 0;
 569         int i = 0;
 570
 571         list_for_each_entry(s, &bus->stream_list, list) {
 572                 if (streams & (1 << i)) {
 573                         azx_timecounter_init(s, inited, cycle_last);
 574                         if (!inited) {
 575                                 inited = true;
 576                                 cycle_last = s->tc.cycle_last;
 577                         }
 578                 }
 579                 i++;
 580         }
 581
 582         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 583         runtime->trigger_tstamp_latched = true;
 584 }
 585 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 586
 587 /**
 588  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 589  * @azx_dev: HD-audio core stream (master stream)
 590  * @streams: bit flags of streams to sync
 591  */
 592 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 593                                   unsigned int streams, unsigned int reg)
 594 {
 595         struct hdac_bus *bus = azx_dev->bus;
 596         unsigned int val;
 597
 598         if (!reg)
 599                 reg = AZX_REG_SSYNC;
 600         val = _snd_hdac_chip_readl(bus, reg);
 601         if (set)
 602                 val |= streams;
 603         else
 604                 val &= ~streams;
 605         _snd_hdac_chip_writel(bus, reg, val);
 606 }
 607 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 608
 609 /**
 610  * snd_hdac_stream_sync - sync with start/strop trigger operation
 611  * @azx_dev: HD-audio core stream (master stream)
 612  * @start: true = start, false = stop
 613  * @streams: bit flags of streams to sync
 614  *
 615  * For @start = true, wait until all FIFOs get ready.
 616  * For @start = false, wait until all RUN bits are cleared.
 617  */
 618 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 619                           unsigned int streams)
 620 {
 621         struct hdac_bus *bus = azx_dev->bus;
 622         int i, nwait, timeout;
 623         struct hdac_stream *s;
 624
 625         for (timeout = 5000; timeout; timeout--) {
 626                 nwait = 0;
 627                 i = 0;
 628                 list_for_each_entry(s, &bus->stream_list, list) {
 629                         if (streams & (1 << i)) {
 630                                 if (start) {
 631                                         /* check FIFO gets ready */
 632                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
 633                                               SD_STS_FIFO_READY))
 634                                                 nwait++;
 635                                 } else {
 636                                         /* check RUN bit is cleared */
 637                                         if (snd_hdac_stream_readb(s, SD_CTL) &
 638                                             SD_CTL_DMA_START)
 639                                                 nwait++;
 640                                 }
 641                         }
 642                         i++;
 643                 }
 644                 if (!nwait)
 645                         break;
 646                 cpu_relax();
 647         }
 648 }
 649 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 650
 651 #ifdef CONFIG_SND_HDA_DSP_LOADER
 652 /**
 653  * snd_hdac_dsp_prepare - prepare for DSP loading
 654  * @azx_dev: HD-audio core stream used for DSP loading
 655  * @format: HD-audio stream format
 656  * @byte_size: data chunk byte size
 657  * @bufp: allocated buffer
 658  *
 659  * Allocate the buffer for the given size and set up the given stream for
 660  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 661  */
 662 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 663                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 664 {
 665         struct hdac_bus *bus = azx_dev->bus;
 666         __le32 *bdl;
 667         int err;
 668
 669         snd_hdac_dsp_lock(azx_dev);
 670         spin_lock_irq(&bus->reg_lock);
 671         if (azx_dev->running || azx_dev->locked) {
 672                 spin_unlock_irq(&bus->reg_lock);
 673                 err = -EBUSY;
 674                 goto unlock;
 675         }
 676         azx_dev->locked = true;
 677         spin_unlock_irq(&bus->reg_lock);
 678
 679         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
 680                                            byte_size, bufp);
 681         if (err < 0)
 682                 goto err_alloc;
 683
 684         azx_dev->substream = NULL;
 685         azx_dev->bufsize = byte_size;
 686         azx_dev->period_bytes = byte_size;
 687         azx_dev->format_val = format;
 688
 689         snd_hdac_stream_reset(azx_dev);
 690
 691         /* reset BDL address */
 692         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 693         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 694
 695         azx_dev->frags = 0;
 696         bdl = (__le32 *)azx_dev->bdl.area;
 697         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 698         if (err < 0)
 699                 goto error;
 700
 701         snd_hdac_stream_setup(azx_dev);
 702         snd_hdac_dsp_unlock(azx_dev);
 703         return azx_dev->stream_tag;
 704
 705  error:
 706         bus->io_ops->dma_free_pages(bus, bufp);
 707  err_alloc:
 708         spin_lock_irq(&bus->reg_lock);
 709         azx_dev->locked = false;
 710         spin_unlock_irq(&bus->reg_lock);
 711  unlock:
 712         snd_hdac_dsp_unlock(azx_dev);
 713         return err;
 714 }
 715 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 716
 717 /**
 718  * snd_hdac_dsp_trigger - start / stop DSP loading
 719  * @azx_dev: HD-audio core stream used for DSP loading
 720  * @start: trigger start or stop
 721  */
 722 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 723 {
 724         if (start)
 725                 snd_hdac_stream_start(azx_dev, true);
 726         else
 727                 snd_hdac_stream_stop(azx_dev);
 728 }
 729 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 730
 731 /**
 732  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 733  * @azx_dev: HD-audio core stream used for DSP loading
 734  * @dmab: buffer used by DSP loading
 735  */
 736 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 737                           struct snd_dma_buffer *dmab)
 738 {
 739         struct hdac_bus *bus = azx_dev->bus;
 740
 741         if (!dmab->area || !azx_dev->locked)
 742                 return;
 743
 744         snd_hdac_dsp_lock(azx_dev);
 745         /* reset BDL address */
 746         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 747         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 748         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 749         azx_dev->bufsize = 0;
 750         azx_dev->period_bytes = 0;
 751         azx_dev->format_val = 0;
 752
 753         bus->io_ops->dma_free_pages(bus, dmab);
 754         dmab->area = NULL;
 755
 756         spin_lock_irq(&bus->reg_lock);
 757         azx_dev->locked = false;
 758         spin_unlock_irq(&bus->reg_lock);
 759         snd_hdac_dsp_unlock(azx_dev);
 760 }
 761 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 762 #endif /* CONFIG_SND_HDA_DSP_LOADER */