sound/hda/hdac_stream.c

   1 /*
   2  * HD-audio stream operations
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <linux/clocksource.h>
   9 #include <sound/core.h>
  10 #include <sound/pcm.h>
  11 #include <sound/hdaudio.h>
  12 #include <sound/hda_register.h>
  13 #include "trace.h"
  14
  15 /**
  16  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  17  * @bus: HD-audio core bus
  18  * @substream: PCM substream
  19  */
  20 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  21                                    struct snd_pcm_substream *substream)
  22 {
  23         struct snd_pcm_runtime *runtime = substream->runtime;
  24         unsigned int channels = runtime->channels,
  25                      rate = runtime->rate,
  26                      bits_per_sample = runtime->sample_bits,
  27                      max_sdo_lines, value, sdo_line;
  28
  29         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  30         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  31
  32         /* following is from HD audio spec */
  33         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  34                 if (rate > 48000)
  35                         value = (channels * bits_per_sample *
  36                                         (rate / 48000)) / sdo_line;
  37                 else
  38                         value = (channels * bits_per_sample) / sdo_line;
  39
  40                 if (value >= 8)
  41                         break;
  42         }
  43
  44         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  45         return sdo_line >> 1;
  46 }
  47 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  48
  49 /**
  50  * snd_hdac_stream_init - initialize each stream (aka device)
  51  * @bus: HD-audio core bus
  52  * @azx_dev: HD-audio core stream object to initialize
  53  * @idx: stream index number
  54  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  55  * @tag: the tag id to assign
  56  *
  57  * Assign the starting bdl address to each stream (device) and initialize.
  58  */
  59 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  60                           int idx, int direction, int tag)
  61 {
  62         azx_dev->bus = bus;
  63         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  64         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  65         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  66         azx_dev->sd_int_sta_mask = 1 << idx;
  67         azx_dev->index = idx;
  68         azx_dev->direction = direction;
  69         azx_dev->stream_tag = tag;
  70         snd_hdac_dsp_lock_init(azx_dev);
  71         list_add_tail(&azx_dev->list, &bus->stream_list);
  72 }
  73 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  74
  75 /**
  76  * snd_hdac_stream_start - start a stream
  77  * @azx_dev: HD-audio core stream to start
  78  * @fresh_start: false = wallclock timestamp relative to period wallclock
  79  *
  80  * Start a stream, set start_wallclk and set the running flag.
  81  */
  82 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  83 {
  84         struct hdac_bus *bus = azx_dev->bus;
  85         int stripe_ctl;
  86
  87         trace_snd_hdac_stream_start(bus, azx_dev);
  88
  89         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  90         if (!fresh_start)
  91                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  92
  93         /* enable SIE */
  94         snd_hdac_chip_updatel(bus, INTCTL,
  95                               1 << azx_dev->index,
  96                               1 << azx_dev->index);
  97         /* set stripe control */
  98         if (azx_dev->substream)
  99                 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
 100         else
 101                 stripe_ctl = 0;
 102         snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 103                                 stripe_ctl);
 104         /* set DMA start and interrupt mask */
 105         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 106                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 107         azx_dev->running = true;
 108 }
 109 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 110
 111 /**
 112  * snd_hdac_stream_clear - stop a stream DMA
 113  * @azx_dev: HD-audio core stream to stop
 114  */
 115 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 116 {
 117         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 118                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 119         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 120         snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 121         azx_dev->running = false;
 122 }
 123 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
 124
 125 /**
 126  * snd_hdac_stream_stop - stop a stream
 127  * @azx_dev: HD-audio core stream to stop
 128  *
 129  * Stop a stream DMA and disable stream interrupt
 130  */
 131 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 132 {
 133         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 134
 135         snd_hdac_stream_clear(azx_dev);
 136         /* disable SIE */
 137         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 138 }
 139 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 140
 141 /**
 142  * snd_hdac_stream_reset - reset a stream
 143  * @azx_dev: HD-audio core stream to reset
 144  */
 145 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 146 {
 147         unsigned char val;
 148         int timeout;
 149
 150         snd_hdac_stream_clear(azx_dev);
 151
 152         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 153         udelay(3);
 154         timeout = 300;
 155         do {
 156                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 157                         SD_CTL_STREAM_RESET;
 158                 if (val)
 159                         break;
 160         } while (--timeout);
 161         val &= ~SD_CTL_STREAM_RESET;
 162         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 163         udelay(3);
 164
 165         timeout = 300;
 166         /* waiting for hardware to report that the stream is out of reset */
 167         do {
 168                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 169                         SD_CTL_STREAM_RESET;
 170                 if (!val)
 171                         break;
 172         } while (--timeout);
 173
 174         /* reset first position - may not be synced with hw at this time */
 175         if (azx_dev->posbuf)
 176                 *azx_dev->posbuf = 0;
 177 }
 178 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 179
 180 /**
 181  * snd_hdac_stream_setup -  set up the SD for streaming
 182  * @azx_dev: HD-audio core stream to set up
 183  */
 184 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 185 {
 186         struct hdac_bus *bus = azx_dev->bus;
 187         struct snd_pcm_runtime *runtime;
 188         unsigned int val;
 189
 190         if (azx_dev->substream)
 191                 runtime = azx_dev->substream->runtime;
 192         else
 193                 runtime = NULL;
 194         /* make sure the run bit is zero for SD */
 195         snd_hdac_stream_clear(azx_dev);
 196         /* program the stream_tag */
 197         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 198         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 199                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 200         if (!bus->snoop)
 201                 val |= SD_CTL_TRAFFIC_PRIO;
 202         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 203
 204         /* program the length of samples in cyclic buffer */
 205         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 206
 207         /* program the stream format */
 208         /* this value needs to be the same as the one programmed */
 209         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 210
 211         /* program the stream LVI (last valid index) of the BDL */
 212         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 213
 214         /* program the BDL address */
 215         /* lower BDL address */
 216         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 217         /* upper BDL address */
 218         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 219                                upper_32_bits(azx_dev->bdl.addr));
 220
 221         /* enable the position buffer */
 222         if (bus->use_posbuf && bus->posbuf.addr) {
 223                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 224                         snd_hdac_chip_writel(bus, DPLBASE,
 225                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 226         }
 227
 228         /* set the interrupt enable bits in the descriptor control register */
 229         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 230
 231         if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
 232                 azx_dev->fifo_size =
 233                         snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 234         else
 235                 azx_dev->fifo_size = 0;
 236
 237         /* when LPIB delay correction gives a small negative value,
 238          * we ignore it; currently set the threshold statically to
 239          * 64 frames
 240          */
 241         if (runtime && runtime->period_size > 64)
 242                 azx_dev->delay_negative_threshold =
 243                         -frames_to_bytes(runtime, 64);
 244         else
 245                 azx_dev->delay_negative_threshold = 0;
 246
 247         /* wallclk has 24Mhz clock source */
 248         if (runtime)
 249                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 250                                     runtime->rate) * 1000);
 251
 252         return 0;
 253 }
 254 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 255
 256 /**
 257  * snd_hdac_stream_cleanup - cleanup a stream
 258  * @azx_dev: HD-audio core stream to clean up
 259  */
 260 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 261 {
 262         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 263         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 264         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 265         azx_dev->bufsize = 0;
 266         azx_dev->period_bytes = 0;
 267         azx_dev->format_val = 0;
 268 }
 269 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 270
 271 /**
 272  * snd_hdac_stream_assign - assign a stream for the PCM
 273  * @bus: HD-audio core bus
 274  * @substream: PCM substream to assign
 275  *
 276  * Look for an unused stream for the given PCM substream, assign it
 277  * and return the stream object.  If no stream is free, returns NULL.
 278  * The function tries to keep using the same stream object when it's used
 279  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 280  * or matching entry is returned.  This is needed for some strange codecs.
 281  */
 282 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 283                                            struct snd_pcm_substream *substream)
 284 {
 285         struct hdac_stream *azx_dev;
 286         struct hdac_stream *res = NULL;
 287
 288         /* make a non-zero unique key for the substream */
 289         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 290                 (substream->stream + 1);
 291
 292         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 293                 if (azx_dev->direction != substream->stream)
 294                         continue;
 295                 if (azx_dev->opened)
 296                         continue;
 297                 if (azx_dev->assigned_key == key) {
 298                         res = azx_dev;
 299                         break;
 300                 }
 301                 if (!res || bus->reverse_assign)
 302                         res = azx_dev;
 303         }
 304         if (res) {
 305                 spin_lock_irq(&bus->reg_lock);
 306                 res->opened = 1;
 307                 res->running = 0;
 308                 res->assigned_key = key;
 309                 res->substream = substream;
 310                 spin_unlock_irq(&bus->reg_lock);
 311         }
 312         return res;
 313 }
 314 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 315
 316 /**
 317  * snd_hdac_stream_release - release the assigned stream
 318  * @azx_dev: HD-audio core stream to release
 319  *
 320  * Release the stream that has been assigned by snd_hdac_stream_assign().
 321  */
 322 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 323 {
 324         struct hdac_bus *bus = azx_dev->bus;
 325
 326         spin_lock_irq(&bus->reg_lock);
 327         azx_dev->opened = 0;
 328         azx_dev->running = 0;
 329         azx_dev->substream = NULL;
 330         spin_unlock_irq(&bus->reg_lock);
 331 }
 332 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 333
 334 /**
 335  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 336  * direction
 337  *
 338  * @bus: HD-audio core bus
 339  * @dir: direction for the stream to be found
 340  * @stream_tag: stream tag for stream to be found
 341  */
 342 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 343                                         int dir, int stream_tag)
 344 {
 345         struct hdac_stream *s;
 346
 347         list_for_each_entry(s, &bus->stream_list, list) {
 348                 if (s->direction == dir && s->stream_tag == stream_tag)
 349                         return s;
 350         }
 351
 352         return NULL;
 353 }
 354 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 355
 356 /*
 357  * set up a BDL entry
 358  */
 359 static int setup_bdle(struct hdac_bus *bus,
 360                       struct snd_dma_buffer *dmab,
 361                       struct hdac_stream *azx_dev, __le32 **bdlp,
 362                       int ofs, int size, int with_ioc)
 363 {
 364         __le32 *bdl = *bdlp;
 365
 366         while (size > 0) {
 367                 dma_addr_t addr;
 368                 int chunk;
 369
 370                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 371                         return -EINVAL;
 372
 373                 addr = snd_sgbuf_get_addr(dmab, ofs);
 374                 /* program the address field of the BDL entry */
 375                 bdl[0] = cpu_to_le32((u32)addr);
 376                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 377                 /* program the size field of the BDL entry */
 378                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 379                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 380                 if (bus->align_bdle_4k) {
 381                         u32 remain = 0x1000 - (ofs & 0xfff);
 382
 383                         if (chunk > remain)
 384                                 chunk = remain;
 385                 }
 386                 bdl[2] = cpu_to_le32(chunk);
 387                 /* program the IOC to enable interrupt
 388                  * only when the whole fragment is processed
 389                  */
 390                 size -= chunk;
 391                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 392                 bdl += 4;
 393                 azx_dev->frags++;
 394                 ofs += chunk;
 395         }
 396         *bdlp = bdl;
 397         return ofs;
 398 }
 399
 400 /**
 401  * snd_hdac_stream_setup_periods - set up BDL entries
 402  * @azx_dev: HD-audio core stream to set up
 403  *
 404  * Set up the buffer descriptor table of the given stream based on the
 405  * period and buffer sizes of the assigned PCM substream.
 406  */
 407 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 408 {
 409         struct hdac_bus *bus = azx_dev->bus;
 410         struct snd_pcm_substream *substream = azx_dev->substream;
 411         struct snd_pcm_runtime *runtime = substream->runtime;
 412         __le32 *bdl;
 413         int i, ofs, periods, period_bytes;
 414         int pos_adj, pos_align;
 415
 416         /* reset BDL address */
 417         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 418         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 419
 420         period_bytes = azx_dev->period_bytes;
 421         periods = azx_dev->bufsize / period_bytes;
 422
 423         /* program the initial BDL entries */
 424         bdl = (__le32 *)azx_dev->bdl.area;
 425         ofs = 0;
 426         azx_dev->frags = 0;
 427
 428         pos_adj = bus->bdl_pos_adj;
 429         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 430                 pos_align = pos_adj;
 431                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 432                 if (!pos_adj)
 433                         pos_adj = pos_align;
 434                 else
 435                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 436                                 pos_align;
 437                 pos_adj = frames_to_bytes(runtime, pos_adj);
 438                 if (pos_adj >= period_bytes) {
 439                         dev_warn(bus->dev, "Too big adjustment %d\n",
 440                                  pos_adj);
 441                         pos_adj = 0;
 442                 } else {
 443                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 444                                          azx_dev,
 445                                          &bdl, ofs, pos_adj, true);
 446                         if (ofs < 0)
 447                                 goto error;
 448                 }
 449         } else
 450                 pos_adj = 0;
 451
 452         for (i = 0; i < periods; i++) {
 453                 if (i == periods - 1 && pos_adj)
 454                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 455                                          azx_dev, &bdl, ofs,
 456                                          period_bytes - pos_adj, 0);
 457                 else
 458                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 459                                          azx_dev, &bdl, ofs,
 460                                          period_bytes,
 461                                          !azx_dev->no_period_wakeup);
 462                 if (ofs < 0)
 463                         goto error;
 464         }
 465         return 0;
 466
 467  error:
 468         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 469                 azx_dev->bufsize, period_bytes);
 470         return -EINVAL;
 471 }
 472 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 473
 474 /**
 475  * snd_hdac_stream_set_params - set stream parameters
 476  * @azx_dev: HD-audio core stream for which parameters are to be set
 477  * @format_val: format value parameter
 478  *
 479  * Setup the HD-audio core stream parameters from substream of the stream
 480  * and passed format value
 481  */
 482 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 483                                  unsigned int format_val)
 484 {
 485
 486         unsigned int bufsize, period_bytes;
 487         struct snd_pcm_substream *substream = azx_dev->substream;
 488         struct snd_pcm_runtime *runtime;
 489         int err;
 490
 491         if (!substream)
 492                 return -EINVAL;
 493         runtime = substream->runtime;
 494         bufsize = snd_pcm_lib_buffer_bytes(substream);
 495         period_bytes = snd_pcm_lib_period_bytes(substream);
 496
 497         if (bufsize != azx_dev->bufsize ||
 498             period_bytes != azx_dev->period_bytes ||
 499             format_val != azx_dev->format_val ||
 500             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 501                 azx_dev->bufsize = bufsize;
 502                 azx_dev->period_bytes = period_bytes;
 503                 azx_dev->format_val = format_val;
 504                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 505                 err = snd_hdac_stream_setup_periods(azx_dev);
 506                 if (err < 0)
 507                         return err;
 508         }
 509         return 0;
 510 }
 511 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 512
 513 static u64 azx_cc_read(const struct cyclecounter *cc)
 514 {
 515         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 516
 517         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 518 }
 519
 520 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 521                                  bool force, u64 last)
 522 {
 523         struct timecounter *tc = &azx_dev->tc;
 524         struct cyclecounter *cc = &azx_dev->cc;
 525         u64 nsec;
 526
 527         cc->read = azx_cc_read;
 528         cc->mask = CLOCKSOURCE_MASK(32);
 529
 530         /*
 531          * Converting from 24 MHz to ns means applying a 125/3 factor.
 532          * To avoid any saturation issues in intermediate operations,
 533          * the 125 factor is applied first. The division is applied
 534          * last after reading the timecounter value.
 535          * Applying the 1/3 factor as part of the multiplication
 536          * requires at least 20 bits for a decent precision, however
 537          * overflows occur after about 4 hours or less, not a option.
 538          */
 539
 540         cc->mult = 125; /* saturation after 195 years */
 541         cc->shift = 0;
 542
 543         nsec = 0; /* audio time is elapsed time since trigger */
 544         timecounter_init(tc, cc, nsec);
 545         if (force) {
 546                 /*
 547                  * force timecounter to use predefined value,
 548                  * used for synchronized starts
 549                  */
 550                 tc->cycle_last = last;
 551         }
 552 }
 553
 554 /**
 555  * snd_hdac_stream_timecounter_init - initialize time counter
 556  * @azx_dev: HD-audio core stream (master stream)
 557  * @streams: bit flags of streams to set up
 558  *
 559  * Initializes the time counter of streams marked by the bit flags (each
 560  * bit corresponds to the stream index).
 561  * The trigger timestamp of PCM substream assigned to the given stream is
 562  * updated accordingly, too.
 563  */
 564 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 565                                       unsigned int streams)
 566 {
 567         struct hdac_bus *bus = azx_dev->bus;
 568         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 569         struct hdac_stream *s;
 570         bool inited = false;
 571         u64 cycle_last = 0;
 572         int i = 0;
 573
 574         list_for_each_entry(s, &bus->stream_list, list) {
 575                 if (streams & (1 << i)) {
 576                         azx_timecounter_init(s, inited, cycle_last);
 577                         if (!inited) {
 578                                 inited = true;
 579                                 cycle_last = s->tc.cycle_last;
 580                         }
 581                 }
 582                 i++;
 583         }
 584
 585         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 586         runtime->trigger_tstamp_latched = true;
 587 }
 588 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 589
 590 /**
 591  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 592  * @azx_dev: HD-audio core stream (master stream)
 593  * @streams: bit flags of streams to sync
 594  */
 595 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 596                                   unsigned int streams, unsigned int reg)
 597 {
 598         struct hdac_bus *bus = azx_dev->bus;
 599         unsigned int val;
 600
 601         if (!reg)
 602                 reg = AZX_REG_SSYNC;
 603         val = _snd_hdac_chip_readl(bus, reg);
 604         if (set)
 605                 val |= streams;
 606         else
 607                 val &= ~streams;
 608         _snd_hdac_chip_writel(bus, reg, val);
 609 }
 610 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 611
 612 /**
 613  * snd_hdac_stream_sync - sync with start/strop trigger operation
 614  * @azx_dev: HD-audio core stream (master stream)
 615  * @start: true = start, false = stop
 616  * @streams: bit flags of streams to sync
 617  *
 618  * For @start = true, wait until all FIFOs get ready.
 619  * For @start = false, wait until all RUN bits are cleared.
 620  */
 621 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 622                           unsigned int streams)
 623 {
 624         struct hdac_bus *bus = azx_dev->bus;
 625         int i, nwait, timeout;
 626         struct hdac_stream *s;
 627
 628         for (timeout = 5000; timeout; timeout--) {
 629                 nwait = 0;
 630                 i = 0;
 631                 list_for_each_entry(s, &bus->stream_list, list) {
 632                         if (streams & (1 << i)) {
 633                                 if (start) {
 634                                         /* check FIFO gets ready */
 635                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
 636                                               SD_STS_FIFO_READY))
 637                                                 nwait++;
 638                                 } else {
 639                                         /* check RUN bit is cleared */
 640                                         if (snd_hdac_stream_readb(s, SD_CTL) &
 641                                             SD_CTL_DMA_START)
 642                                                 nwait++;
 643                                 }
 644                         }
 645                         i++;
 646                 }
 647                 if (!nwait)
 648                         break;
 649                 cpu_relax();
 650         }
 651 }
 652 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 653
 654 #ifdef CONFIG_SND_HDA_DSP_LOADER
 655 /**
 656  * snd_hdac_dsp_prepare - prepare for DSP loading
 657  * @azx_dev: HD-audio core stream used for DSP loading
 658  * @format: HD-audio stream format
 659  * @byte_size: data chunk byte size
 660  * @bufp: allocated buffer
 661  *
 662  * Allocate the buffer for the given size and set up the given stream for
 663  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 664  */
 665 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 666                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 667 {
 668         struct hdac_bus *bus = azx_dev->bus;
 669         __le32 *bdl;
 670         int err;
 671
 672         snd_hdac_dsp_lock(azx_dev);
 673         spin_lock_irq(&bus->reg_lock);
 674         if (azx_dev->running || azx_dev->locked) {
 675                 spin_unlock_irq(&bus->reg_lock);
 676                 err = -EBUSY;
 677                 goto unlock;
 678         }
 679         azx_dev->locked = true;
 680         spin_unlock_irq(&bus->reg_lock);
 681
 682         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
 683                                            byte_size, bufp);
 684         if (err < 0)
 685                 goto err_alloc;
 686
 687         azx_dev->substream = NULL;
 688         azx_dev->bufsize = byte_size;
 689         azx_dev->period_bytes = byte_size;
 690         azx_dev->format_val = format;
 691
 692         snd_hdac_stream_reset(azx_dev);
 693
 694         /* reset BDL address */
 695         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 696         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 697
 698         azx_dev->frags = 0;
 699         bdl = (__le32 *)azx_dev->bdl.area;
 700         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 701         if (err < 0)
 702                 goto error;
 703
 704         snd_hdac_stream_setup(azx_dev);
 705         snd_hdac_dsp_unlock(azx_dev);
 706         return azx_dev->stream_tag;
 707
 708  error:
 709         bus->io_ops->dma_free_pages(bus, bufp);
 710  err_alloc:
 711         spin_lock_irq(&bus->reg_lock);
 712         azx_dev->locked = false;
 713         spin_unlock_irq(&bus->reg_lock);
 714  unlock:
 715         snd_hdac_dsp_unlock(azx_dev);
 716         return err;
 717 }
 718 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 719
 720 /**
 721  * snd_hdac_dsp_trigger - start / stop DSP loading
 722  * @azx_dev: HD-audio core stream used for DSP loading
 723  * @start: trigger start or stop
 724  */
 725 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 726 {
 727         if (start)
 728                 snd_hdac_stream_start(azx_dev, true);
 729         else
 730                 snd_hdac_stream_stop(azx_dev);
 731 }
 732 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 733
 734 /**
 735  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 736  * @azx_dev: HD-audio core stream used for DSP loading
 737  * @dmab: buffer used by DSP loading
 738  */
 739 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 740                           struct snd_dma_buffer *dmab)
 741 {
 742         struct hdac_bus *bus = azx_dev->bus;
 743
 744         if (!dmab->area || !azx_dev->locked)
 745                 return;
 746
 747         snd_hdac_dsp_lock(azx_dev);
 748         /* reset BDL address */
 749         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 750         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 751         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 752         azx_dev->bufsize = 0;
 753         azx_dev->period_bytes = 0;
 754         azx_dev->format_val = 0;
 755
 756         bus->io_ops->dma_free_pages(bus, dmab);
 757         dmab->area = NULL;
 758
 759         spin_lock_irq(&bus->reg_lock);
 760         azx_dev->locked = false;
 761         spin_unlock_irq(&bus->reg_lock);
 762         snd_hdac_dsp_unlock(azx_dev);
 763 }
 764 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 765 #endif /* CONFIG_SND_HDA_DSP_LOADER */