ALSA: hda: Fix regression by strip mask fix
[sfrench/cifs-2.6.git] / sound / hda / hdac_stream.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio stream operations
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/core.h>
11 #include <sound/pcm.h>
12 #include <sound/hdaudio.h>
13 #include <sound/hda_register.h>
14 #include "trace.h"
15
16 /**
17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
18  * @bus: HD-audio core bus
19  * @substream: PCM substream
20  */
21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
22                                    struct snd_pcm_substream *substream)
23 {
24         struct snd_pcm_runtime *runtime = substream->runtime;
25         unsigned int channels = runtime->channels,
26                      rate = runtime->rate,
27                      bits_per_sample = runtime->sample_bits,
28                      max_sdo_lines, value, sdo_line;
29
30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
32
33         /* following is from HD audio spec */
34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
35                 if (rate > 48000)
36                         value = (channels * bits_per_sample *
37                                         (rate / 48000)) / sdo_line;
38                 else
39                         value = (channels * bits_per_sample) / sdo_line;
40
41                 if (value >= 8)
42                         break;
43         }
44
45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
46         return sdo_line >> 1;
47 }
48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
49
50 /**
51  * snd_hdac_stream_init - initialize each stream (aka device)
52  * @bus: HD-audio core bus
53  * @azx_dev: HD-audio core stream object to initialize
54  * @idx: stream index number
55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
56  * @tag: the tag id to assign
57  *
58  * Assign the starting bdl address to each stream (device) and initialize.
59  */
60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
61                           int idx, int direction, int tag)
62 {
63         azx_dev->bus = bus;
64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
67         azx_dev->sd_int_sta_mask = 1 << idx;
68         azx_dev->index = idx;
69         azx_dev->direction = direction;
70         azx_dev->stream_tag = tag;
71         snd_hdac_dsp_lock_init(azx_dev);
72         list_add_tail(&azx_dev->list, &bus->stream_list);
73 }
74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
75
76 /**
77  * snd_hdac_stream_start - start a stream
78  * @azx_dev: HD-audio core stream to start
79  * @fresh_start: false = wallclock timestamp relative to period wallclock
80  *
81  * Start a stream, set start_wallclk and set the running flag.
82  */
83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
84 {
85         struct hdac_bus *bus = azx_dev->bus;
86         int stripe_ctl;
87
88         trace_snd_hdac_stream_start(bus, azx_dev);
89
90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
91         if (!fresh_start)
92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
93
94         /* enable SIE */
95         snd_hdac_chip_updatel(bus, INTCTL,
96                               1 << azx_dev->index,
97                               1 << azx_dev->index);
98         /* set stripe control */
99         if (azx_dev->stripe) {
100                 if (azx_dev->substream)
101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102                 else
103                         stripe_ctl = 0;
104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
105                                         stripe_ctl);
106         }
107         /* set DMA start and interrupt mask */
108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
110         azx_dev->running = true;
111 }
112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
113
114 /**
115  * snd_hdac_stream_clear - stop a stream DMA
116  * @azx_dev: HD-audio core stream to stop
117  */
118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
119 {
120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
123         if (azx_dev->stripe)
124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
125         azx_dev->running = false;
126 }
127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
128
129 /**
130  * snd_hdac_stream_stop - stop a stream
131  * @azx_dev: HD-audio core stream to stop
132  *
133  * Stop a stream DMA and disable stream interrupt
134  */
135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
136 {
137         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
138
139         snd_hdac_stream_clear(azx_dev);
140         /* disable SIE */
141         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
142 }
143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
144
145 /**
146  * snd_hdac_stream_reset - reset a stream
147  * @azx_dev: HD-audio core stream to reset
148  */
149 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
150 {
151         unsigned char val;
152         int timeout;
153
154         snd_hdac_stream_clear(azx_dev);
155
156         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
157         udelay(3);
158         timeout = 300;
159         do {
160                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
161                         SD_CTL_STREAM_RESET;
162                 if (val)
163                         break;
164         } while (--timeout);
165         val &= ~SD_CTL_STREAM_RESET;
166         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
167         udelay(3);
168
169         timeout = 300;
170         /* waiting for hardware to report that the stream is out of reset */
171         do {
172                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
173                         SD_CTL_STREAM_RESET;
174                 if (!val)
175                         break;
176         } while (--timeout);
177
178         /* reset first position - may not be synced with hw at this time */
179         if (azx_dev->posbuf)
180                 *azx_dev->posbuf = 0;
181 }
182 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
183
184 /**
185  * snd_hdac_stream_setup -  set up the SD for streaming
186  * @azx_dev: HD-audio core stream to set up
187  */
188 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
189 {
190         struct hdac_bus *bus = azx_dev->bus;
191         struct snd_pcm_runtime *runtime;
192         unsigned int val;
193
194         if (azx_dev->substream)
195                 runtime = azx_dev->substream->runtime;
196         else
197                 runtime = NULL;
198         /* make sure the run bit is zero for SD */
199         snd_hdac_stream_clear(azx_dev);
200         /* program the stream_tag */
201         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
202         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
203                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
204         if (!bus->snoop)
205                 val |= SD_CTL_TRAFFIC_PRIO;
206         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
207
208         /* program the length of samples in cyclic buffer */
209         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
210
211         /* program the stream format */
212         /* this value needs to be the same as the one programmed */
213         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
214
215         /* program the stream LVI (last valid index) of the BDL */
216         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
217
218         /* program the BDL address */
219         /* lower BDL address */
220         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
221         /* upper BDL address */
222         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
223                                upper_32_bits(azx_dev->bdl.addr));
224
225         /* enable the position buffer */
226         if (bus->use_posbuf && bus->posbuf.addr) {
227                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
228                         snd_hdac_chip_writel(bus, DPLBASE,
229                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
230         }
231
232         /* set the interrupt enable bits in the descriptor control register */
233         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
234
235         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
236
237         /* when LPIB delay correction gives a small negative value,
238          * we ignore it; currently set the threshold statically to
239          * 64 frames
240          */
241         if (runtime && runtime->period_size > 64)
242                 azx_dev->delay_negative_threshold =
243                         -frames_to_bytes(runtime, 64);
244         else
245                 azx_dev->delay_negative_threshold = 0;
246
247         /* wallclk has 24Mhz clock source */
248         if (runtime)
249                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
250                                     runtime->rate) * 1000);
251
252         return 0;
253 }
254 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
255
256 /**
257  * snd_hdac_stream_cleanup - cleanup a stream
258  * @azx_dev: HD-audio core stream to clean up
259  */
260 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
261 {
262         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
263         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
264         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
265         azx_dev->bufsize = 0;
266         azx_dev->period_bytes = 0;
267         azx_dev->format_val = 0;
268 }
269 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
270
271 /**
272  * snd_hdac_stream_assign - assign a stream for the PCM
273  * @bus: HD-audio core bus
274  * @substream: PCM substream to assign
275  *
276  * Look for an unused stream for the given PCM substream, assign it
277  * and return the stream object.  If no stream is free, returns NULL.
278  * The function tries to keep using the same stream object when it's used
279  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
280  * or matching entry is returned.  This is needed for some strange codecs.
281  */
282 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
283                                            struct snd_pcm_substream *substream)
284 {
285         struct hdac_stream *azx_dev;
286         struct hdac_stream *res = NULL;
287
288         /* make a non-zero unique key for the substream */
289         int key = (substream->pcm->device << 16) | (substream->number << 2) |
290                 (substream->stream + 1);
291
292         list_for_each_entry(azx_dev, &bus->stream_list, list) {
293                 if (azx_dev->direction != substream->stream)
294                         continue;
295                 if (azx_dev->opened)
296                         continue;
297                 if (azx_dev->assigned_key == key) {
298                         res = azx_dev;
299                         break;
300                 }
301                 if (!res || bus->reverse_assign)
302                         res = azx_dev;
303         }
304         if (res) {
305                 spin_lock_irq(&bus->reg_lock);
306                 res->opened = 1;
307                 res->running = 0;
308                 res->assigned_key = key;
309                 res->substream = substream;
310                 spin_unlock_irq(&bus->reg_lock);
311         }
312         return res;
313 }
314 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
315
316 /**
317  * snd_hdac_stream_release - release the assigned stream
318  * @azx_dev: HD-audio core stream to release
319  *
320  * Release the stream that has been assigned by snd_hdac_stream_assign().
321  */
322 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
323 {
324         struct hdac_bus *bus = azx_dev->bus;
325
326         spin_lock_irq(&bus->reg_lock);
327         azx_dev->opened = 0;
328         azx_dev->running = 0;
329         azx_dev->substream = NULL;
330         spin_unlock_irq(&bus->reg_lock);
331 }
332 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
333
334 /**
335  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
336  * direction
337  *
338  * @bus: HD-audio core bus
339  * @dir: direction for the stream to be found
340  * @stream_tag: stream tag for stream to be found
341  */
342 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
343                                         int dir, int stream_tag)
344 {
345         struct hdac_stream *s;
346
347         list_for_each_entry(s, &bus->stream_list, list) {
348                 if (s->direction == dir && s->stream_tag == stream_tag)
349                         return s;
350         }
351
352         return NULL;
353 }
354 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
355
356 /*
357  * set up a BDL entry
358  */
359 static int setup_bdle(struct hdac_bus *bus,
360                       struct snd_dma_buffer *dmab,
361                       struct hdac_stream *azx_dev, __le32 **bdlp,
362                       int ofs, int size, int with_ioc)
363 {
364         __le32 *bdl = *bdlp;
365
366         while (size > 0) {
367                 dma_addr_t addr;
368                 int chunk;
369
370                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
371                         return -EINVAL;
372
373                 addr = snd_sgbuf_get_addr(dmab, ofs);
374                 /* program the address field of the BDL entry */
375                 bdl[0] = cpu_to_le32((u32)addr);
376                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
377                 /* program the size field of the BDL entry */
378                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
379                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
380                 if (bus->align_bdle_4k) {
381                         u32 remain = 0x1000 - (ofs & 0xfff);
382
383                         if (chunk > remain)
384                                 chunk = remain;
385                 }
386                 bdl[2] = cpu_to_le32(chunk);
387                 /* program the IOC to enable interrupt
388                  * only when the whole fragment is processed
389                  */
390                 size -= chunk;
391                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
392                 bdl += 4;
393                 azx_dev->frags++;
394                 ofs += chunk;
395         }
396         *bdlp = bdl;
397         return ofs;
398 }
399
400 /**
401  * snd_hdac_stream_setup_periods - set up BDL entries
402  * @azx_dev: HD-audio core stream to set up
403  *
404  * Set up the buffer descriptor table of the given stream based on the
405  * period and buffer sizes of the assigned PCM substream.
406  */
407 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
408 {
409         struct hdac_bus *bus = azx_dev->bus;
410         struct snd_pcm_substream *substream = azx_dev->substream;
411         struct snd_pcm_runtime *runtime = substream->runtime;
412         __le32 *bdl;
413         int i, ofs, periods, period_bytes;
414         int pos_adj, pos_align;
415
416         /* reset BDL address */
417         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
418         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
419
420         period_bytes = azx_dev->period_bytes;
421         periods = azx_dev->bufsize / period_bytes;
422
423         /* program the initial BDL entries */
424         bdl = (__le32 *)azx_dev->bdl.area;
425         ofs = 0;
426         azx_dev->frags = 0;
427
428         pos_adj = bus->bdl_pos_adj;
429         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
430                 pos_align = pos_adj;
431                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
432                 if (!pos_adj)
433                         pos_adj = pos_align;
434                 else
435                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
436                                 pos_align;
437                 pos_adj = frames_to_bytes(runtime, pos_adj);
438                 if (pos_adj >= period_bytes) {
439                         dev_warn(bus->dev, "Too big adjustment %d\n",
440                                  pos_adj);
441                         pos_adj = 0;
442                 } else {
443                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
444                                          azx_dev,
445                                          &bdl, ofs, pos_adj, true);
446                         if (ofs < 0)
447                                 goto error;
448                 }
449         } else
450                 pos_adj = 0;
451
452         for (i = 0; i < periods; i++) {
453                 if (i == periods - 1 && pos_adj)
454                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
455                                          azx_dev, &bdl, ofs,
456                                          period_bytes - pos_adj, 0);
457                 else
458                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
459                                          azx_dev, &bdl, ofs,
460                                          period_bytes,
461                                          !azx_dev->no_period_wakeup);
462                 if (ofs < 0)
463                         goto error;
464         }
465         return 0;
466
467  error:
468         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
469                 azx_dev->bufsize, period_bytes);
470         return -EINVAL;
471 }
472 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
473
474 /**
475  * snd_hdac_stream_set_params - set stream parameters
476  * @azx_dev: HD-audio core stream for which parameters are to be set
477  * @format_val: format value parameter
478  *
479  * Setup the HD-audio core stream parameters from substream of the stream
480  * and passed format value
481  */
482 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
483                                  unsigned int format_val)
484 {
485
486         unsigned int bufsize, period_bytes;
487         struct snd_pcm_substream *substream = azx_dev->substream;
488         struct snd_pcm_runtime *runtime;
489         int err;
490
491         if (!substream)
492                 return -EINVAL;
493         runtime = substream->runtime;
494         bufsize = snd_pcm_lib_buffer_bytes(substream);
495         period_bytes = snd_pcm_lib_period_bytes(substream);
496
497         if (bufsize != azx_dev->bufsize ||
498             period_bytes != azx_dev->period_bytes ||
499             format_val != azx_dev->format_val ||
500             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
501                 azx_dev->bufsize = bufsize;
502                 azx_dev->period_bytes = period_bytes;
503                 azx_dev->format_val = format_val;
504                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
505                 err = snd_hdac_stream_setup_periods(azx_dev);
506                 if (err < 0)
507                         return err;
508         }
509         return 0;
510 }
511 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
512
513 static u64 azx_cc_read(const struct cyclecounter *cc)
514 {
515         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
516
517         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
518 }
519
520 static void azx_timecounter_init(struct hdac_stream *azx_dev,
521                                  bool force, u64 last)
522 {
523         struct timecounter *tc = &azx_dev->tc;
524         struct cyclecounter *cc = &azx_dev->cc;
525         u64 nsec;
526
527         cc->read = azx_cc_read;
528         cc->mask = CLOCKSOURCE_MASK(32);
529
530         /*
531          * Converting from 24 MHz to ns means applying a 125/3 factor.
532          * To avoid any saturation issues in intermediate operations,
533          * the 125 factor is applied first. The division is applied
534          * last after reading the timecounter value.
535          * Applying the 1/3 factor as part of the multiplication
536          * requires at least 20 bits for a decent precision, however
537          * overflows occur after about 4 hours or less, not a option.
538          */
539
540         cc->mult = 125; /* saturation after 195 years */
541         cc->shift = 0;
542
543         nsec = 0; /* audio time is elapsed time since trigger */
544         timecounter_init(tc, cc, nsec);
545         if (force) {
546                 /*
547                  * force timecounter to use predefined value,
548                  * used for synchronized starts
549                  */
550                 tc->cycle_last = last;
551         }
552 }
553
554 /**
555  * snd_hdac_stream_timecounter_init - initialize time counter
556  * @azx_dev: HD-audio core stream (master stream)
557  * @streams: bit flags of streams to set up
558  *
559  * Initializes the time counter of streams marked by the bit flags (each
560  * bit corresponds to the stream index).
561  * The trigger timestamp of PCM substream assigned to the given stream is
562  * updated accordingly, too.
563  */
564 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
565                                       unsigned int streams)
566 {
567         struct hdac_bus *bus = azx_dev->bus;
568         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
569         struct hdac_stream *s;
570         bool inited = false;
571         u64 cycle_last = 0;
572         int i = 0;
573
574         list_for_each_entry(s, &bus->stream_list, list) {
575                 if (streams & (1 << i)) {
576                         azx_timecounter_init(s, inited, cycle_last);
577                         if (!inited) {
578                                 inited = true;
579                                 cycle_last = s->tc.cycle_last;
580                         }
581                 }
582                 i++;
583         }
584
585         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
586         runtime->trigger_tstamp_latched = true;
587 }
588 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
589
590 /**
591  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
592  * @azx_dev: HD-audio core stream (master stream)
593  * @streams: bit flags of streams to sync
594  */
595 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
596                                   unsigned int streams, unsigned int reg)
597 {
598         struct hdac_bus *bus = azx_dev->bus;
599         unsigned int val;
600
601         if (!reg)
602                 reg = AZX_REG_SSYNC;
603         val = _snd_hdac_chip_readl(bus, reg);
604         if (set)
605                 val |= streams;
606         else
607                 val &= ~streams;
608         _snd_hdac_chip_writel(bus, reg, val);
609 }
610 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
611
612 /**
613  * snd_hdac_stream_sync - sync with start/strop trigger operation
614  * @azx_dev: HD-audio core stream (master stream)
615  * @start: true = start, false = stop
616  * @streams: bit flags of streams to sync
617  *
618  * For @start = true, wait until all FIFOs get ready.
619  * For @start = false, wait until all RUN bits are cleared.
620  */
621 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
622                           unsigned int streams)
623 {
624         struct hdac_bus *bus = azx_dev->bus;
625         int i, nwait, timeout;
626         struct hdac_stream *s;
627
628         for (timeout = 5000; timeout; timeout--) {
629                 nwait = 0;
630                 i = 0;
631                 list_for_each_entry(s, &bus->stream_list, list) {
632                         if (streams & (1 << i)) {
633                                 if (start) {
634                                         /* check FIFO gets ready */
635                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
636                                               SD_STS_FIFO_READY))
637                                                 nwait++;
638                                 } else {
639                                         /* check RUN bit is cleared */
640                                         if (snd_hdac_stream_readb(s, SD_CTL) &
641                                             SD_CTL_DMA_START)
642                                                 nwait++;
643                                 }
644                         }
645                         i++;
646                 }
647                 if (!nwait)
648                         break;
649                 cpu_relax();
650         }
651 }
652 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
653
654 #ifdef CONFIG_SND_HDA_DSP_LOADER
655 /**
656  * snd_hdac_dsp_prepare - prepare for DSP loading
657  * @azx_dev: HD-audio core stream used for DSP loading
658  * @format: HD-audio stream format
659  * @byte_size: data chunk byte size
660  * @bufp: allocated buffer
661  *
662  * Allocate the buffer for the given size and set up the given stream for
663  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
664  */
665 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
666                          unsigned int byte_size, struct snd_dma_buffer *bufp)
667 {
668         struct hdac_bus *bus = azx_dev->bus;
669         __le32 *bdl;
670         int err;
671
672         snd_hdac_dsp_lock(azx_dev);
673         spin_lock_irq(&bus->reg_lock);
674         if (azx_dev->running || azx_dev->locked) {
675                 spin_unlock_irq(&bus->reg_lock);
676                 err = -EBUSY;
677                 goto unlock;
678         }
679         azx_dev->locked = true;
680         spin_unlock_irq(&bus->reg_lock);
681
682         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
683                                   byte_size, bufp);
684         if (err < 0)
685                 goto err_alloc;
686
687         azx_dev->substream = NULL;
688         azx_dev->bufsize = byte_size;
689         azx_dev->period_bytes = byte_size;
690         azx_dev->format_val = format;
691
692         snd_hdac_stream_reset(azx_dev);
693
694         /* reset BDL address */
695         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
696         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
697
698         azx_dev->frags = 0;
699         bdl = (__le32 *)azx_dev->bdl.area;
700         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
701         if (err < 0)
702                 goto error;
703
704         snd_hdac_stream_setup(azx_dev);
705         snd_hdac_dsp_unlock(azx_dev);
706         return azx_dev->stream_tag;
707
708  error:
709         snd_dma_free_pages(bufp);
710  err_alloc:
711         spin_lock_irq(&bus->reg_lock);
712         azx_dev->locked = false;
713         spin_unlock_irq(&bus->reg_lock);
714  unlock:
715         snd_hdac_dsp_unlock(azx_dev);
716         return err;
717 }
718 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
719
720 /**
721  * snd_hdac_dsp_trigger - start / stop DSP loading
722  * @azx_dev: HD-audio core stream used for DSP loading
723  * @start: trigger start or stop
724  */
725 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
726 {
727         if (start)
728                 snd_hdac_stream_start(azx_dev, true);
729         else
730                 snd_hdac_stream_stop(azx_dev);
731 }
732 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
733
734 /**
735  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
736  * @azx_dev: HD-audio core stream used for DSP loading
737  * @dmab: buffer used by DSP loading
738  */
739 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
740                           struct snd_dma_buffer *dmab)
741 {
742         struct hdac_bus *bus = azx_dev->bus;
743
744         if (!dmab->area || !azx_dev->locked)
745                 return;
746
747         snd_hdac_dsp_lock(azx_dev);
748         /* reset BDL address */
749         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
750         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
751         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
752         azx_dev->bufsize = 0;
753         azx_dev->period_bytes = 0;
754         azx_dev->format_val = 0;
755
756         snd_dma_free_pages(dmab);
757         dmab->area = NULL;
758
759         spin_lock_irq(&bus->reg_lock);
760         azx_dev->locked = false;
761         spin_unlock_irq(&bus->reg_lock);
762         snd_hdac_dsp_unlock(azx_dev);
763 }
764 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
765 #endif /* CONFIG_SND_HDA_DSP_LOADER */