2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * the GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * MOCS indexes used for GPU surfaces, defining the cacheability of the
67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
69 enum i915_mocs_table_index {
71 * Not cached anywhere, coherency between CPU and GPU accesses is
76 * Cacheability and coherency controlled by the kernel automatically
77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
78 * usage of the surface (used for display scanout or not).
82 * Cached in all GPU caches available on the platform.
83 * Coherency between CPU and GPU accesses to the surface is not
84 * guaranteed without extra synchronization.
90 * Different engines serve different roles, and there may be more than one
91 * engine serving each role. enum drm_i915_gem_engine_class provides a
92 * classification of the role of the engine, which may be used when requesting
93 * operations to be performed on a certain subset of engines, or for providing
94 * information about that group.
96 enum drm_i915_gem_engine_class {
97 I915_ENGINE_CLASS_RENDER = 0,
98 I915_ENGINE_CLASS_COPY = 1,
99 I915_ENGINE_CLASS_VIDEO = 2,
100 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
102 /* should be kept compact */
104 I915_ENGINE_CLASS_INVALID = -1
108 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
112 enum drm_i915_pmu_engine_sample {
113 I915_SAMPLE_BUSY = 0,
114 I915_SAMPLE_WAIT = 1,
118 #define I915_PMU_SAMPLE_BITS (4)
119 #define I915_PMU_SAMPLE_MASK (0xf)
120 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
121 #define I915_PMU_CLASS_SHIFT \
122 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
124 #define __I915_PMU_ENGINE(class, instance, sample) \
125 ((class) << I915_PMU_CLASS_SHIFT | \
126 (instance) << I915_PMU_SAMPLE_BITS | \
129 #define I915_PMU_ENGINE_BUSY(class, instance) \
130 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
132 #define I915_PMU_ENGINE_WAIT(class, instance) \
133 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
135 #define I915_PMU_ENGINE_SEMA(class, instance) \
136 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
138 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
140 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
141 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
142 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
143 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
145 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
147 /* Each region is a minimum of 16k, and there are at most 255 of them.
149 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
150 * of chars for next/prev indices */
151 #define I915_LOG_MIN_TEX_REGION_SIZE 14
153 typedef struct _drm_i915_init {
155 I915_INIT_DMA = 0x01,
156 I915_CLEANUP_DMA = 0x02,
157 I915_RESUME_DMA = 0x03
159 unsigned int mmio_offset;
160 int sarea_priv_offset;
161 unsigned int ring_start;
162 unsigned int ring_end;
163 unsigned int ring_size;
164 unsigned int front_offset;
165 unsigned int back_offset;
166 unsigned int depth_offset;
170 unsigned int pitch_bits;
171 unsigned int back_pitch;
172 unsigned int depth_pitch;
174 unsigned int chipset;
177 typedef struct _drm_i915_sarea {
178 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
179 int last_upload; /* last time texture was uploaded */
180 int last_enqueue; /* last time a buffer was enqueued */
181 int last_dispatch; /* age of the most recently dispatched buffer */
182 int ctxOwner; /* last context to upload state */
184 int pf_enabled; /* is pageflipping allowed? */
186 int pf_current_page; /* which buffer is being displayed? */
187 int perf_boxes; /* performance boxes to be displayed */
188 int width, height; /* screen size in pixels */
190 drm_handle_t front_handle;
194 drm_handle_t back_handle;
198 drm_handle_t depth_handle;
202 drm_handle_t tex_handle;
205 int log_tex_granularity;
207 int rotation; /* 0, 90, 180 or 270 */
211 int virtualX, virtualY;
213 unsigned int front_tiled;
214 unsigned int back_tiled;
215 unsigned int depth_tiled;
216 unsigned int rotated_tiled;
217 unsigned int rotated2_tiled;
228 /* fill out some space for old userspace triple buffer */
229 drm_handle_t unused_handle;
230 __u32 unused1, unused2, unused3;
232 /* buffer object handles for static buffers. May change
233 * over the lifetime of the client.
235 __u32 front_bo_handle;
236 __u32 back_bo_handle;
237 __u32 unused_bo_handle;
238 __u32 depth_bo_handle;
242 /* due to userspace building against these headers we need some compat here */
243 #define planeA_x pipeA_x
244 #define planeA_y pipeA_y
245 #define planeA_w pipeA_w
246 #define planeA_h pipeA_h
247 #define planeB_x pipeB_x
248 #define planeB_y pipeB_y
249 #define planeB_w pipeB_w
250 #define planeB_h pipeB_h
252 /* Flags for perf_boxes
254 #define I915_BOX_RING_EMPTY 0x1
255 #define I915_BOX_FLIP 0x2
256 #define I915_BOX_WAIT 0x4
257 #define I915_BOX_TEXTURE_LOAD 0x8
258 #define I915_BOX_LOST_CONTEXT 0x10
261 * i915 specific ioctls.
263 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
264 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
265 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
267 #define DRM_I915_INIT 0x00
268 #define DRM_I915_FLUSH 0x01
269 #define DRM_I915_FLIP 0x02
270 #define DRM_I915_BATCHBUFFER 0x03
271 #define DRM_I915_IRQ_EMIT 0x04
272 #define DRM_I915_IRQ_WAIT 0x05
273 #define DRM_I915_GETPARAM 0x06
274 #define DRM_I915_SETPARAM 0x07
275 #define DRM_I915_ALLOC 0x08
276 #define DRM_I915_FREE 0x09
277 #define DRM_I915_INIT_HEAP 0x0a
278 #define DRM_I915_CMDBUFFER 0x0b
279 #define DRM_I915_DESTROY_HEAP 0x0c
280 #define DRM_I915_SET_VBLANK_PIPE 0x0d
281 #define DRM_I915_GET_VBLANK_PIPE 0x0e
282 #define DRM_I915_VBLANK_SWAP 0x0f
283 #define DRM_I915_HWS_ADDR 0x11
284 #define DRM_I915_GEM_INIT 0x13
285 #define DRM_I915_GEM_EXECBUFFER 0x14
286 #define DRM_I915_GEM_PIN 0x15
287 #define DRM_I915_GEM_UNPIN 0x16
288 #define DRM_I915_GEM_BUSY 0x17
289 #define DRM_I915_GEM_THROTTLE 0x18
290 #define DRM_I915_GEM_ENTERVT 0x19
291 #define DRM_I915_GEM_LEAVEVT 0x1a
292 #define DRM_I915_GEM_CREATE 0x1b
293 #define DRM_I915_GEM_PREAD 0x1c
294 #define DRM_I915_GEM_PWRITE 0x1d
295 #define DRM_I915_GEM_MMAP 0x1e
296 #define DRM_I915_GEM_SET_DOMAIN 0x1f
297 #define DRM_I915_GEM_SW_FINISH 0x20
298 #define DRM_I915_GEM_SET_TILING 0x21
299 #define DRM_I915_GEM_GET_TILING 0x22
300 #define DRM_I915_GEM_GET_APERTURE 0x23
301 #define DRM_I915_GEM_MMAP_GTT 0x24
302 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
303 #define DRM_I915_GEM_MADVISE 0x26
304 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
305 #define DRM_I915_OVERLAY_ATTRS 0x28
306 #define DRM_I915_GEM_EXECBUFFER2 0x29
307 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
308 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
309 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
310 #define DRM_I915_GEM_WAIT 0x2c
311 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
312 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
313 #define DRM_I915_GEM_SET_CACHING 0x2f
314 #define DRM_I915_GEM_GET_CACHING 0x30
315 #define DRM_I915_REG_READ 0x31
316 #define DRM_I915_GET_RESET_STATS 0x32
317 #define DRM_I915_GEM_USERPTR 0x33
318 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
319 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
320 #define DRM_I915_PERF_OPEN 0x36
321 #define DRM_I915_PERF_ADD_CONFIG 0x37
322 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
323 #define DRM_I915_QUERY 0x39
324 /* Must be kept compact -- no holes */
326 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
327 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
328 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
329 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
330 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
331 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
332 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
333 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
334 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
335 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
336 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
337 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
338 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
339 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
340 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
341 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
342 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
343 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
344 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
345 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
346 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
347 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
348 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
349 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
350 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
351 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
352 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
353 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
354 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
355 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
356 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
357 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
358 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
359 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
360 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
361 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
362 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
363 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
364 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
365 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
366 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
367 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
368 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
369 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
370 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
371 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
372 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
373 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
374 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
375 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
376 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
377 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
378 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
379 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
380 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
381 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
382 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
384 /* Allow drivers to submit batchbuffers directly to hardware, relying
385 * on the security mechanisms provided by hardware.
387 typedef struct drm_i915_batchbuffer {
388 int start; /* agp offset */
389 int used; /* nr bytes in use */
390 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
391 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
392 int num_cliprects; /* mulitpass with multiple cliprects? */
393 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
394 } drm_i915_batchbuffer_t;
396 /* As above, but pass a pointer to userspace buffer which can be
397 * validated by the kernel prior to sending to hardware.
399 typedef struct _drm_i915_cmdbuffer {
400 char __user *buf; /* pointer to userspace command buffer */
401 int sz; /* nr bytes in buf */
402 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
403 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
404 int num_cliprects; /* mulitpass with multiple cliprects? */
405 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
406 } drm_i915_cmdbuffer_t;
408 /* Userspace can request & wait on irq's:
410 typedef struct drm_i915_irq_emit {
412 } drm_i915_irq_emit_t;
414 typedef struct drm_i915_irq_wait {
416 } drm_i915_irq_wait_t;
419 * Different modes of per-process Graphics Translation Table,
420 * see I915_PARAM_HAS_ALIASING_PPGTT
422 #define I915_GEM_PPGTT_NONE 0
423 #define I915_GEM_PPGTT_ALIASING 1
424 #define I915_GEM_PPGTT_FULL 2
426 /* Ioctl to query kernel params:
428 #define I915_PARAM_IRQ_ACTIVE 1
429 #define I915_PARAM_ALLOW_BATCHBUFFER 2
430 #define I915_PARAM_LAST_DISPATCH 3
431 #define I915_PARAM_CHIPSET_ID 4
432 #define I915_PARAM_HAS_GEM 5
433 #define I915_PARAM_NUM_FENCES_AVAIL 6
434 #define I915_PARAM_HAS_OVERLAY 7
435 #define I915_PARAM_HAS_PAGEFLIPPING 8
436 #define I915_PARAM_HAS_EXECBUF2 9
437 #define I915_PARAM_HAS_BSD 10
438 #define I915_PARAM_HAS_BLT 11
439 #define I915_PARAM_HAS_RELAXED_FENCING 12
440 #define I915_PARAM_HAS_COHERENT_RINGS 13
441 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
442 #define I915_PARAM_HAS_RELAXED_DELTA 15
443 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
444 #define I915_PARAM_HAS_LLC 17
445 #define I915_PARAM_HAS_ALIASING_PPGTT 18
446 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
447 #define I915_PARAM_HAS_SEMAPHORES 20
448 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
449 #define I915_PARAM_HAS_VEBOX 22
450 #define I915_PARAM_HAS_SECURE_BATCHES 23
451 #define I915_PARAM_HAS_PINNED_BATCHES 24
452 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
453 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
454 #define I915_PARAM_HAS_WT 27
455 #define I915_PARAM_CMD_PARSER_VERSION 28
456 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
457 #define I915_PARAM_MMAP_VERSION 30
458 #define I915_PARAM_HAS_BSD2 31
459 #define I915_PARAM_REVISION 32
460 #define I915_PARAM_SUBSLICE_TOTAL 33
461 #define I915_PARAM_EU_TOTAL 34
462 #define I915_PARAM_HAS_GPU_RESET 35
463 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
464 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
465 #define I915_PARAM_HAS_POOLED_EU 38
466 #define I915_PARAM_MIN_EU_IN_POOL 39
467 #define I915_PARAM_MMAP_GTT_VERSION 40
470 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
471 * priorities and the driver will attempt to execute batches in priority order.
472 * The param returns a capability bitmask, nonzero implies that the scheduler
473 * is enabled, with different features present according to the mask.
475 * The initial priority for each batch is supplied by the context and is
476 * controlled via I915_CONTEXT_PARAM_PRIORITY.
478 #define I915_PARAM_HAS_SCHEDULER 41
479 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
480 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
481 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
482 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
484 #define I915_PARAM_HUC_STATUS 42
486 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
487 * synchronisation with implicit fencing on individual objects.
488 * See EXEC_OBJECT_ASYNC.
490 #define I915_PARAM_HAS_EXEC_ASYNC 43
492 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
493 * both being able to pass in a sync_file fd to wait upon before executing,
494 * and being able to return a new sync_file fd that is signaled when the
495 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
497 #define I915_PARAM_HAS_EXEC_FENCE 44
499 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
500 * user specified bufffers for post-mortem debugging of GPU hangs. See
501 * EXEC_OBJECT_CAPTURE.
503 #define I915_PARAM_HAS_EXEC_CAPTURE 45
505 #define I915_PARAM_SLICE_MASK 46
507 /* Assuming it's uniform for each slice, this queries the mask of subslices
508 * per-slice for this system.
510 #define I915_PARAM_SUBSLICE_MASK 47
513 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
514 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
516 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
518 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
519 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
521 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
524 * Query whether every context (both per-file default and user created) is
525 * isolated (insofar as HW supports). If this parameter is not true, then
526 * freshly created contexts may inherit values from an existing context,
527 * rather than default HW values. If true, it also ensures (insofar as HW
528 * supports) that all state set by this context will not leak to any other
531 * As not every engine across every gen support contexts, the returned
532 * value reports the support of context isolation for individual engines by
533 * returning a bitmask of each engine class set to true if that class supports
536 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
538 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
539 * registers. This used to be fixed per platform but from CNL onwards, this
540 * might vary depending on the parts.
542 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
545 * Once upon a time we supposed that writes through the GGTT would be
546 * immediately in physical memory (once flushed out of the CPU path). However,
547 * on a few different processors and chipsets, this is not necessarily the case
548 * as the writes appear to be buffered internally. Thus a read of the backing
549 * storage (physical memory) via a different path (with different physical tags
550 * to the indirect write via the GGTT) will see stale values from before
551 * the GGTT write. Inside the kernel, we can for the most part keep track of
552 * the different read/write domains in use (e.g. set-domain), but the assumption
553 * of coherency is baked into the ABI, hence reporting its true state in this
556 * Reports true when writes via mmap_gtt are immediately visible following an
557 * lfence to flush the WCB.
559 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
560 * internal buffer and are _not_ immediately visible to third parties accessing
561 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
562 * communications channel when reporting false is strongly disadvised.
564 #define I915_PARAM_MMAP_GTT_COHERENT 52
566 /* Must be kept compact -- no holes and well documented */
568 typedef struct drm_i915_getparam {
571 * WARNING: Using pointers instead of fixed-size u64 means we need to write
572 * compat32 code. Don't repeat this mistake.
575 } drm_i915_getparam_t;
577 /* Ioctl to set kernel params:
579 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
580 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
581 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
582 #define I915_SETPARAM_NUM_USED_FENCES 4
583 /* Must be kept compact -- no holes */
585 typedef struct drm_i915_setparam {
588 } drm_i915_setparam_t;
590 /* A memory manager for regions of shared memory:
592 #define I915_MEM_REGION_AGP 1
594 typedef struct drm_i915_mem_alloc {
598 int __user *region_offset; /* offset from start of fb or agp */
599 } drm_i915_mem_alloc_t;
601 typedef struct drm_i915_mem_free {
604 } drm_i915_mem_free_t;
606 typedef struct drm_i915_mem_init_heap {
610 } drm_i915_mem_init_heap_t;
612 /* Allow memory manager to be torn down and re-initialized (eg on
615 typedef struct drm_i915_mem_destroy_heap {
617 } drm_i915_mem_destroy_heap_t;
619 /* Allow X server to configure which pipes to monitor for vblank signals
621 #define DRM_I915_VBLANK_PIPE_A 1
622 #define DRM_I915_VBLANK_PIPE_B 2
624 typedef struct drm_i915_vblank_pipe {
626 } drm_i915_vblank_pipe_t;
628 /* Schedule buffer swap at given vertical blank:
630 typedef struct drm_i915_vblank_swap {
631 drm_drawable_t drawable;
632 enum drm_vblank_seq_type seqtype;
633 unsigned int sequence;
634 } drm_i915_vblank_swap_t;
636 typedef struct drm_i915_hws_addr {
638 } drm_i915_hws_addr_t;
640 struct drm_i915_gem_init {
642 * Beginning offset in the GTT to be managed by the DRM memory
647 * Ending offset in the GTT to be managed by the DRM memory
653 struct drm_i915_gem_create {
655 * Requested size for the object.
657 * The (page-aligned) allocated size for the object will be returned.
661 * Returned handle for the object.
663 * Object handles are nonzero.
669 struct drm_i915_gem_pread {
670 /** Handle for the object being read. */
673 /** Offset into the object to read from */
675 /** Length of data to read */
678 * Pointer to write the data into.
680 * This is a fixed-size type for 32/64 compatibility.
685 struct drm_i915_gem_pwrite {
686 /** Handle for the object being written to. */
689 /** Offset into the object to write to */
691 /** Length of data to write */
694 * Pointer to read the data from.
696 * This is a fixed-size type for 32/64 compatibility.
701 struct drm_i915_gem_mmap {
702 /** Handle for the object being mapped. */
705 /** Offset in the object to map. */
708 * Length of data to map.
710 * The value will be page-aligned.
714 * Returned pointer the data was mapped at.
716 * This is a fixed-size type for 32/64 compatibility.
721 * Flags for extended behaviour.
723 * Added in version 2.
726 #define I915_MMAP_WC 0x1
729 struct drm_i915_gem_mmap_gtt {
730 /** Handle for the object being mapped. */
734 * Fake offset to use for subsequent mmap call
736 * This is a fixed-size type for 32/64 compatibility.
741 struct drm_i915_gem_set_domain {
742 /** Handle for the object */
745 /** New read domains */
748 /** New write domain */
752 struct drm_i915_gem_sw_finish {
753 /** Handle for the object */
757 struct drm_i915_gem_relocation_entry {
759 * Handle of the buffer being pointed to by this relocation entry.
761 * It's appealing to make this be an index into the mm_validate_entry
762 * list to refer to the buffer, but this allows the driver to create
763 * a relocation list for state buffers and not re-write it per
764 * exec using the buffer.
769 * Value to be added to the offset of the target buffer to make up
770 * the relocation entry.
774 /** Offset in the buffer the relocation entry will be written into */
778 * Offset value of the target buffer that the relocation entry was last
781 * If the buffer has the same offset as last time, we can skip syncing
782 * and writing the relocation. This value is written back out by
783 * the execbuffer ioctl when the relocation is written.
785 __u64 presumed_offset;
788 * Target memory domains read by this operation.
793 * Target memory domains written by this operation.
795 * Note that only one domain may be written by the whole
796 * execbuffer operation, so that where there are conflicts,
797 * the application will get -EINVAL back.
803 * Intel memory domains
805 * Most of these just align with the various caches in
806 * the system and are used to flush and invalidate as
807 * objects end up cached in different domains.
810 #define I915_GEM_DOMAIN_CPU 0x00000001
811 /** Render cache, used by 2D and 3D drawing */
812 #define I915_GEM_DOMAIN_RENDER 0x00000002
813 /** Sampler cache, used by texture engine */
814 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
815 /** Command queue, used to load batch buffers */
816 #define I915_GEM_DOMAIN_COMMAND 0x00000008
817 /** Instruction cache, used by shader programs */
818 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
819 /** Vertex address cache */
820 #define I915_GEM_DOMAIN_VERTEX 0x00000020
821 /** GTT domain - aperture and scanout */
822 #define I915_GEM_DOMAIN_GTT 0x00000040
823 /** WC domain - uncached access */
824 #define I915_GEM_DOMAIN_WC 0x00000080
827 struct drm_i915_gem_exec_object {
829 * User's handle for a buffer to be bound into the GTT for this
834 /** Number of relocations to be performed on this buffer */
835 __u32 relocation_count;
837 * Pointer to array of struct drm_i915_gem_relocation_entry containing
838 * the relocations to be performed in this buffer.
842 /** Required alignment in graphics aperture */
846 * Returned value of the updated offset of the object, for future
847 * presumed_offset writes.
852 struct drm_i915_gem_execbuffer {
854 * List of buffers to be validated with their relocations to be
855 * performend on them.
857 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
859 * These buffers must be listed in an order such that all relocations
860 * a buffer is performing refer to buffers that have already appeared
861 * in the validate list.
866 /** Offset in the batchbuffer to start execution from. */
867 __u32 batch_start_offset;
868 /** Bytes used in batchbuffer from batch_start_offset */
873 /** This is a struct drm_clip_rect *cliprects */
877 struct drm_i915_gem_exec_object2 {
879 * User's handle for a buffer to be bound into the GTT for this
884 /** Number of relocations to be performed on this buffer */
885 __u32 relocation_count;
887 * Pointer to array of struct drm_i915_gem_relocation_entry containing
888 * the relocations to be performed in this buffer.
892 /** Required alignment in graphics aperture */
896 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
897 * the user with the GTT offset at which this object will be pinned.
898 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
899 * presumed_offset of the object.
900 * During execbuffer2 the kernel populates it with the value of the
901 * current GTT offset of the object, for future presumed_offset writes.
905 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
906 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
907 #define EXEC_OBJECT_WRITE (1<<2)
908 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
909 #define EXEC_OBJECT_PINNED (1<<4)
910 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
911 /* The kernel implicitly tracks GPU activity on all GEM objects, and
912 * synchronises operations with outstanding rendering. This includes
913 * rendering on other devices if exported via dma-buf. However, sometimes
914 * this tracking is too coarse and the user knows better. For example,
915 * if the object is split into non-overlapping ranges shared between different
916 * clients or engines (i.e. suballocating objects), the implicit tracking
917 * by kernel assumes that each operation affects the whole object rather
918 * than an individual range, causing needless synchronisation between clients.
919 * The kernel will also forgo any CPU cache flushes prior to rendering from
920 * the object as the client is expected to be also handling such domain
923 * The kernel maintains the implicit tracking in order to manage resources
924 * used by the GPU - this flag only disables the synchronisation prior to
925 * rendering with this object in this execbuf.
927 * Opting out of implicit synhronisation requires the user to do its own
928 * explicit tracking to avoid rendering corruption. See, for example,
929 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
931 #define EXEC_OBJECT_ASYNC (1<<6)
932 /* Request that the contents of this execobject be copied into the error
933 * state upon a GPU hang involving this batch for post-mortem debugging.
934 * These buffers are recorded in no particular order as "user" in
935 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
936 * if the kernel supports this flag.
938 #define EXEC_OBJECT_CAPTURE (1<<7)
939 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
940 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
950 struct drm_i915_gem_exec_fence {
952 * User's handle for a drm_syncobj to wait on or signal.
956 #define I915_EXEC_FENCE_WAIT (1<<0)
957 #define I915_EXEC_FENCE_SIGNAL (1<<1)
958 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
962 struct drm_i915_gem_execbuffer2 {
964 * List of gem_exec_object2 structs
969 /** Offset in the batchbuffer to start execution from. */
970 __u32 batch_start_offset;
971 /** Bytes used in batchbuffer from batch_start_offset */
977 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
978 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
979 * struct drm_i915_gem_exec_fence *fences.
982 #define I915_EXEC_RING_MASK (0x3f)
983 #define I915_EXEC_DEFAULT (0<<0)
984 #define I915_EXEC_RENDER (1<<0)
985 #define I915_EXEC_BSD (2<<0)
986 #define I915_EXEC_BLT (3<<0)
987 #define I915_EXEC_VEBOX (4<<0)
989 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
990 * Gen6+ only supports relative addressing to dynamic state (default) and
991 * absolute addressing.
993 * These flags are ignored for the BSD and BLT rings.
995 #define I915_EXEC_CONSTANTS_MASK (3<<6)
996 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
997 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
998 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1000 __u64 rsvd1; /* now used for context info */
1004 /** Resets the SO write offset registers for transform feedback on gen7. */
1005 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
1007 /** Request a privileged ("secure") batch buffer. Note only available for
1008 * DRM_ROOT_ONLY | DRM_MASTER processes.
1010 #define I915_EXEC_SECURE (1<<9)
1012 /** Inform the kernel that the batch is and will always be pinned. This
1013 * negates the requirement for a workaround to be performed to avoid
1014 * an incoherent CS (such as can be found on 830/845). If this flag is
1015 * not passed, the kernel will endeavour to make sure the batch is
1016 * coherent with the CS before execution. If this flag is passed,
1017 * userspace assumes the responsibility for ensuring the same.
1019 #define I915_EXEC_IS_PINNED (1<<10)
1021 /** Provide a hint to the kernel that the command stream and auxiliary
1022 * state buffers already holds the correct presumed addresses and so the
1023 * relocation process may be skipped if no buffers need to be moved in
1024 * preparation for the execbuffer.
1026 #define I915_EXEC_NO_RELOC (1<<11)
1028 /** Use the reloc.handle as an index into the exec object array rather
1029 * than as the per-file handle.
1031 #define I915_EXEC_HANDLE_LUT (1<<12)
1033 /** Used for switching BSD rings on the platforms with two BSD rings */
1034 #define I915_EXEC_BSD_SHIFT (13)
1035 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1036 /* default ping-pong mode */
1037 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1038 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1039 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1041 /** Tell the kernel that the batchbuffer is processed by
1042 * the resource streamer.
1044 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
1046 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1047 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1050 * Returns -EINVAL if the sync_file fd cannot be found.
1052 #define I915_EXEC_FENCE_IN (1<<16)
1054 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1055 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1056 * to the caller, and it should be close() after use. (The fd is a regular
1057 * file descriptor and will be cleaned up on process termination. It holds
1058 * a reference to the request, but nothing else.)
1060 * The sync_file fd can be combined with other sync_file and passed either
1061 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1062 * will only occur after this request completes), or to other devices.
1064 * Using I915_EXEC_FENCE_OUT requires use of
1065 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1066 * back to userspace. Failure to do so will cause the out-fence to always
1067 * be reported as zero, and the real fence fd to be leaked.
1069 #define I915_EXEC_FENCE_OUT (1<<17)
1072 * Traditionally the execbuf ioctl has only considered the final element in
1073 * the execobject[] to be the executable batch. Often though, the client
1074 * will known the batch object prior to construction and being able to place
1075 * it into the execobject[] array first can simplify the relocation tracking.
1076 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1077 * execobject[] as the * batch instead (the default is to use the last
1080 #define I915_EXEC_BATCH_FIRST (1<<18)
1082 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1083 * define an array of i915_gem_exec_fence structures which specify a set of
1084 * dma fences to wait upon or signal.
1086 #define I915_EXEC_FENCE_ARRAY (1<<19)
1088 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
1090 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1091 #define i915_execbuffer2_set_context_id(eb2, context) \
1092 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1093 #define i915_execbuffer2_get_context_id(eb2) \
1094 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1096 struct drm_i915_gem_pin {
1097 /** Handle of the buffer to be pinned. */
1101 /** alignment required within the aperture */
1104 /** Returned GTT offset of the buffer. */
1108 struct drm_i915_gem_unpin {
1109 /** Handle of the buffer to be unpinned. */
1114 struct drm_i915_gem_busy {
1115 /** Handle of the buffer to check for busy */
1118 /** Return busy status
1120 * A return of 0 implies that the object is idle (after
1121 * having flushed any pending activity), and a non-zero return that
1122 * the object is still in-flight on the GPU. (The GPU has not yet
1123 * signaled completion for all pending requests that reference the
1124 * object.) An object is guaranteed to become idle eventually (so
1125 * long as no new GPU commands are executed upon it). Due to the
1126 * asynchronous nature of the hardware, an object reported
1127 * as busy may become idle before the ioctl is completed.
1129 * Furthermore, if the object is busy, which engine is busy is only
1130 * provided as a guide and only indirectly by reporting its class
1131 * (there may be more than one engine in each class). There are race
1132 * conditions which prevent the report of which engines are busy from
1133 * being always accurate. However, the converse is not true. If the
1134 * object is idle, the result of the ioctl, that all engines are idle,
1137 * The returned dword is split into two fields to indicate both
1138 * the engine classess on which the object is being read, and the
1139 * engine class on which it is currently being written (if any).
1141 * The low word (bits 0:15) indicate if the object is being written
1142 * to by any engine (there can only be one, as the GEM implicit
1143 * synchronisation rules force writes to be serialised). Only the
1144 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1145 * 1 not 0 etc) for the last write is reported.
1147 * The high word (bits 16:31) are a bitmask of which engines classes
1148 * are currently reading from the object. Multiple engines may be
1149 * reading from the object simultaneously.
1151 * The value of each engine class is the same as specified in the
1152 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1153 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1154 * reported as active itself. Some hardware may have parallel
1155 * execution engines, e.g. multiple media engines, which are
1156 * mapped to the same class identifier and so are not separately
1157 * reported for busyness.
1160 * Only the boolean result of this query is reliable; that is whether
1161 * the object is idle or busy. The report of which engines are busy
1162 * should be only used as a heuristic.
1170 * GPU access is not coherent with cpu caches. Default for machines without an
1173 #define I915_CACHING_NONE 0
1175 * I915_CACHING_CACHED
1177 * GPU access is coherent with cpu caches and furthermore the data is cached in
1178 * last-level caches shared between cpu cores and the gpu GT. Default on
1179 * machines with HAS_LLC.
1181 #define I915_CACHING_CACHED 1
1183 * I915_CACHING_DISPLAY
1185 * Special GPU caching mode which is coherent with the scanout engines.
1186 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1187 * cache mode (like write-through or gfdt flushing) is available. The kernel
1188 * automatically sets this mode when using a buffer as a scanout target.
1189 * Userspace can manually set this mode to avoid a costly stall and clflush in
1190 * the hotpath of drawing the first frame.
1192 #define I915_CACHING_DISPLAY 2
1194 struct drm_i915_gem_caching {
1196 * Handle of the buffer to set/get the caching level of. */
1200 * Cacheing level to apply or return value
1202 * bits0-15 are for generic caching control (i.e. the above defined
1203 * values). bits16-31 are reserved for platform-specific variations
1204 * (e.g. l3$ caching on gen7). */
1208 #define I915_TILING_NONE 0
1209 #define I915_TILING_X 1
1210 #define I915_TILING_Y 2
1211 #define I915_TILING_LAST I915_TILING_Y
1213 #define I915_BIT_6_SWIZZLE_NONE 0
1214 #define I915_BIT_6_SWIZZLE_9 1
1215 #define I915_BIT_6_SWIZZLE_9_10 2
1216 #define I915_BIT_6_SWIZZLE_9_11 3
1217 #define I915_BIT_6_SWIZZLE_9_10_11 4
1218 /* Not seen by userland */
1219 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1220 /* Seen by userland. */
1221 #define I915_BIT_6_SWIZZLE_9_17 6
1222 #define I915_BIT_6_SWIZZLE_9_10_17 7
1224 struct drm_i915_gem_set_tiling {
1225 /** Handle of the buffer to have its tiling state updated */
1229 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1232 * This value is to be set on request, and will be updated by the
1233 * kernel on successful return with the actual chosen tiling layout.
1235 * The tiling mode may be demoted to I915_TILING_NONE when the system
1236 * has bit 6 swizzling that can't be managed correctly by GEM.
1238 * Buffer contents become undefined when changing tiling_mode.
1243 * Stride in bytes for the object when in I915_TILING_X or
1249 * Returned address bit 6 swizzling required for CPU access through
1255 struct drm_i915_gem_get_tiling {
1256 /** Handle of the buffer to get tiling state for. */
1260 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1266 * Returned address bit 6 swizzling required for CPU access through
1272 * Returned address bit 6 swizzling required for CPU access through
1273 * mmap mapping whilst bound.
1275 __u32 phys_swizzle_mode;
1278 struct drm_i915_gem_get_aperture {
1279 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1283 * Available space in the aperture used by i915_gem_execbuffer, in
1286 __u64 aper_available_size;
1289 struct drm_i915_get_pipe_from_crtc_id {
1290 /** ID of CRTC being requested **/
1293 /** pipe of requested CRTC **/
1297 #define I915_MADV_WILLNEED 0
1298 #define I915_MADV_DONTNEED 1
1299 #define __I915_MADV_PURGED 2 /* internal state */
1301 struct drm_i915_gem_madvise {
1302 /** Handle of the buffer to change the backing store advice */
1305 /* Advice: either the buffer will be needed again in the near future,
1306 * or wont be and could be discarded under memory pressure.
1310 /** Whether the backing store still exists. */
1315 #define I915_OVERLAY_TYPE_MASK 0xff
1316 #define I915_OVERLAY_YUV_PLANAR 0x01
1317 #define I915_OVERLAY_YUV_PACKED 0x02
1318 #define I915_OVERLAY_RGB 0x03
1320 #define I915_OVERLAY_DEPTH_MASK 0xff00
1321 #define I915_OVERLAY_RGB24 0x1000
1322 #define I915_OVERLAY_RGB16 0x2000
1323 #define I915_OVERLAY_RGB15 0x3000
1324 #define I915_OVERLAY_YUV422 0x0100
1325 #define I915_OVERLAY_YUV411 0x0200
1326 #define I915_OVERLAY_YUV420 0x0300
1327 #define I915_OVERLAY_YUV410 0x0400
1329 #define I915_OVERLAY_SWAP_MASK 0xff0000
1330 #define I915_OVERLAY_NO_SWAP 0x000000
1331 #define I915_OVERLAY_UV_SWAP 0x010000
1332 #define I915_OVERLAY_Y_SWAP 0x020000
1333 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1335 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1336 #define I915_OVERLAY_ENABLE 0x01000000
1338 struct drm_intel_overlay_put_image {
1339 /* various flags and src format description */
1341 /* source picture description */
1343 /* stride values and offsets are in bytes, buffer relative */
1344 __u16 stride_Y; /* stride for packed formats */
1346 __u32 offset_Y; /* offset for packet formats */
1352 /* to compensate the scaling factors for partially covered surfaces */
1353 __u16 src_scan_width;
1354 __u16 src_scan_height;
1355 /* output crtc description */
1364 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1365 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1366 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1367 struct drm_intel_overlay_attrs {
1382 * Intel sprite handling
1384 * Color keying works with a min/mask/max tuple. Both source and destination
1385 * color keying is allowed.
1388 * Sprite pixels within the min & max values, masked against the color channels
1389 * specified in the mask field, will be transparent. All other pixels will
1390 * be displayed on top of the primary plane. For RGB surfaces, only the min
1391 * and mask fields will be used; ranged compares are not allowed.
1393 * Destination keying:
1394 * Primary plane pixels that match the min value, masked against the color
1395 * channels specified in the mask field, will be replaced by corresponding
1396 * pixels from the sprite plane.
1398 * Note that source & destination keying are exclusive; only one can be
1399 * active on a given plane.
1402 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1403 * flags==0 to disable colorkeying.
1405 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1406 #define I915_SET_COLORKEY_SOURCE (1<<2)
1407 struct drm_intel_sprite_colorkey {
1415 struct drm_i915_gem_wait {
1416 /** Handle of BO we shall wait on */
1419 /** Number of nanoseconds to wait, Returns time remaining. */
1423 struct drm_i915_gem_context_create {
1424 /* output: id of new context*/
1429 struct drm_i915_gem_context_destroy {
1434 struct drm_i915_reg_read {
1437 * For 64bit wide registers where the upper 32bits don't immediately
1438 * follow the lower 32bits, the offset of the lower 32bits must
1442 #define I915_REG_READ_8B_WA (1ul << 0)
1444 __u64 val; /* Return value */
1448 * Render engine timestamp - 0x2358 + 64bit - gen7+
1449 * - Note this register returns an invalid value if using the default
1450 * single instruction 8byte read, in order to workaround that pass
1451 * flag I915_REG_READ_8B_WA in offset field.
1455 struct drm_i915_reset_stats {
1459 /* All resets since boot/module reload, for all contexts */
1462 /* Number of batches lost when active in GPU, for this context */
1465 /* Number of batches lost pending for execution, for this context */
1466 __u32 batch_pending;
1471 struct drm_i915_gem_userptr {
1475 #define I915_USERPTR_READ_ONLY 0x1
1476 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1478 * Returned handle for the object.
1480 * Object handles are nonzero.
1485 struct drm_i915_gem_context_param {
1489 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1490 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1491 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1492 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1493 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1494 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1495 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1496 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1497 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1499 * When using the following param, value should be a pointer to
1500 * drm_i915_gem_context_param_sseu.
1502 #define I915_CONTEXT_PARAM_SSEU 0x7
1505 * Not all clients may want to attempt automatic recover of a context after
1506 * a hang (for example, some clients may only submit very small incremental
1507 * batches relying on known logical state of previous batches which will never
1508 * recover correctly and each attempt will hang), and so would prefer that
1509 * the context is forever banned instead.
1511 * If set to false (0), after a reset, subsequent (and in flight) rendering
1512 * from this context is discarded, and the client will need to create a new
1513 * context to use instead.
1515 * If set to true (1), the kernel will automatically attempt to recover the
1516 * context by skipping the hanging batch and executing the next batch starting
1517 * from the default context state (discarding the incomplete logical context
1518 * state lost due to the reset).
1520 * On creation, all new contexts are marked as recoverable.
1522 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1523 /* Must be kept compact -- no holes and well documented */
1528 * Context SSEU programming
1530 * It may be necessary for either functional or performance reason to configure
1531 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1534 * This is done by configuring SSEU configuration using the below
1535 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1536 * userspace intends to use.
1538 * Not all GPUs or engines support this functionality in which case an error
1539 * code -ENODEV will be returned.
1541 * Also, flexibility of possible SSEU configuration permutations varies between
1542 * GPU generations and software imposed limitations. Requesting such a
1543 * combination will return an error code of -EINVAL.
1545 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1546 * favour of a single global setting.
1548 struct drm_i915_gem_context_param_sseu {
1550 * Engine class & instance to be configured or queried.
1553 __u16 engine_instance;
1556 * Unused for now. Must be cleared to zero.
1561 * Mask of slices to enable for the context. Valid values are a subset
1562 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1567 * Mask of subslices to enable for the context. Valid values are a
1568 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1570 __u64 subslice_mask;
1573 * Minimum/Maximum number of EUs to enable per subslice for the
1574 * context. min_eus_per_subslice must be inferior or equal to
1575 * max_eus_per_subslice.
1577 __u16 min_eus_per_subslice;
1578 __u16 max_eus_per_subslice;
1581 * Unused for now. Must be cleared to zero.
1586 enum drm_i915_oa_format {
1587 I915_OA_FORMAT_A13 = 1, /* HSW only */
1588 I915_OA_FORMAT_A29, /* HSW only */
1589 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
1590 I915_OA_FORMAT_B4_C8, /* HSW only */
1591 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
1592 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
1593 I915_OA_FORMAT_C4_B8, /* HSW+ */
1597 I915_OA_FORMAT_A12_B8_C8,
1598 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1600 I915_OA_FORMAT_MAX /* non-ABI */
1603 enum drm_i915_perf_property_id {
1605 * Open the stream for a specific context handle (as used with
1606 * execbuffer2). A stream opened for a specific context this way
1607 * won't typically require root privileges.
1609 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1612 * A value of 1 requests the inclusion of raw OA unit reports as
1613 * part of stream samples.
1615 DRM_I915_PERF_PROP_SAMPLE_OA,
1618 * The value specifies which set of OA unit metrics should be
1619 * be configured, defining the contents of any OA unit reports.
1621 DRM_I915_PERF_PROP_OA_METRICS_SET,
1624 * The value specifies the size and layout of OA unit reports.
1626 DRM_I915_PERF_PROP_OA_FORMAT,
1629 * Specifying this property implicitly requests periodic OA unit
1630 * sampling and (at least on Haswell) the sampling frequency is derived
1631 * from this exponent as follows:
1633 * 80ns * 2^(period_exponent + 1)
1635 DRM_I915_PERF_PROP_OA_EXPONENT,
1637 DRM_I915_PERF_PROP_MAX /* non-ABI */
1640 struct drm_i915_perf_open_param {
1642 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1643 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1644 #define I915_PERF_FLAG_DISABLED (1<<2)
1646 /** The number of u64 (id, value) pairs */
1647 __u32 num_properties;
1650 * Pointer to array of u64 (id, value) pairs configuring the stream
1653 __u64 properties_ptr;
1657 * Enable data capture for a stream that was either opened in a disabled state
1658 * via I915_PERF_FLAG_DISABLED or was later disabled via
1659 * I915_PERF_IOCTL_DISABLE.
1661 * It is intended to be cheaper to disable and enable a stream than it may be
1662 * to close and re-open a stream with the same configuration.
1664 * It's undefined whether any pending data for the stream will be lost.
1666 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1669 * Disable data capture for a stream.
1671 * It is an error to try and read a stream that is disabled.
1673 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1676 * Common to all i915 perf records
1678 struct drm_i915_perf_record_header {
1684 enum drm_i915_perf_record_type {
1687 * Samples are the work horse record type whose contents are extensible
1688 * and defined when opening an i915 perf stream based on the given
1691 * Boolean properties following the naming convention
1692 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1695 * The order of these sample properties given by userspace has no
1696 * affect on the ordering of data within a sample. The order is
1700 * struct drm_i915_perf_record_header header;
1702 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1705 DRM_I915_PERF_RECORD_SAMPLE = 1,
1708 * Indicates that one or more OA reports were not written by the
1709 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1710 * command collides with periodic sampling - which would be more likely
1711 * at higher sampling frequencies.
1713 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1716 * An error occurred that resulted in all pending OA reports being lost.
1718 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1720 DRM_I915_PERF_RECORD_MAX /* non-ABI */
1724 * Structure to upload perf dynamic configuration into the kernel.
1726 struct drm_i915_perf_oa_config {
1727 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
1731 __u32 n_boolean_regs;
1735 * These fields are pointers to tuples of u32 values (register address,
1736 * value). For example the expected length of the buffer pointed by
1737 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
1740 __u64 boolean_regs_ptr;
1741 __u64 flex_regs_ptr;
1744 struct drm_i915_query_item {
1746 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
1747 /* Must be kept compact -- no holes and well documented */
1750 * When set to zero by userspace, this is filled with the size of the
1751 * data to be written at the data_ptr pointer. The kernel sets this
1752 * value to a negative value to signal an error on a particular query
1758 * Unused for now. Must be cleared to zero.
1763 * Data will be written at the location pointed by data_ptr when the
1764 * value of length matches the length of the data to be written by the
1770 struct drm_i915_query {
1774 * Unused for now. Must be cleared to zero.
1779 * This points to an array of num_items drm_i915_query_item structures.
1785 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
1787 * data: contains the 3 pieces of information :
1789 * - the slice mask with one bit per slice telling whether a slice is
1790 * available. The availability of slice X can be queried with the following
1793 * (data[X / 8] >> (X % 8)) & 1
1795 * - the subslice mask for each slice with one bit per subslice telling
1796 * whether a subslice is available. The availability of subslice Y in slice
1797 * X can be queried with the following formula :
1799 * (data[subslice_offset +
1800 * X * subslice_stride +
1801 * Y / 8] >> (Y % 8)) & 1
1803 * - the EU mask for each subslice in each slice with one bit per EU telling
1804 * whether an EU is available. The availability of EU Z in subslice Y in
1805 * slice X can be queried with the following formula :
1808 * (X * max_subslices + Y) * eu_stride +
1809 * Z / 8] >> (Z % 8)) & 1
1811 struct drm_i915_query_topology_info {
1813 * Unused for now. Must be cleared to zero.
1818 __u16 max_subslices;
1819 __u16 max_eus_per_subslice;
1822 * Offset in data[] at which the subslice masks are stored.
1824 __u16 subslice_offset;
1827 * Stride at which each of the subslice masks for each slice are
1830 __u16 subslice_stride;
1833 * Offset in data[] at which the EU masks are stored.
1838 * Stride at which each of the EU masks for each subslice are stored.
1845 #if defined(__cplusplus)
1849 #endif /* _UAPI_I915_DRM_H_ */