2 * RapidIO register definitions
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef LINUX_RIO_REGS_H
14 #define LINUX_RIO_REGS_H
17 * In RapidIO, each device has a 16MB configuration space that is
18 * accessed via maintenance transactions. Portions of configuration
19 * space are standardized and/or reserved.
21 #define RIO_MAINT_SPACE_SZ 0x1000000 /* 16MB of RapidIO mainenance space */
23 #define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */
24 #define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */
25 #define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */
26 #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
27 #define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
29 #define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */
30 #define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
31 #define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
33 #define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */
34 #define RIO_PEF_BRIDGE 0x80000000 /* [I] Bridge */
35 #define RIO_PEF_MEMORY 0x40000000 /* [I] MMIO */
36 #define RIO_PEF_PROCESSOR 0x20000000 /* [I] Processor */
37 #define RIO_PEF_SWITCH 0x10000000 /* [I] Switch */
38 #define RIO_PEF_MULTIPORT 0x08000000 /* [VI, 2.1] Multiport */
39 #define RIO_PEF_INB_MBOX 0x00f00000 /* [II, <= 1.2] Mailboxes */
40 #define RIO_PEF_INB_MBOX0 0x00800000 /* [II, <= 1.2] Mailbox 0 */
41 #define RIO_PEF_INB_MBOX1 0x00400000 /* [II, <= 1.2] Mailbox 1 */
42 #define RIO_PEF_INB_MBOX2 0x00200000 /* [II, <= 1.2] Mailbox 2 */
43 #define RIO_PEF_INB_MBOX3 0x00100000 /* [II, <= 1.2] Mailbox 3 */
44 #define RIO_PEF_INB_DOORBELL 0x00080000 /* [II, <= 1.2] Doorbells */
45 #define RIO_PEF_DEV32 0x00001000 /* [III] PE supports Common TRansport Dev32 */
46 #define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */
47 #define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */
48 #define RIO_PEF_CTLS 0x00000010 /* [III] Common Transport Large System (< rev.3) */
49 #define RIO_PEF_DEV16 0x00000010 /* [III] PE Supports Common Transport Dev16 (rev.3) */
50 #define RIO_PEF_EXT_FEATURES 0x00000008 /* [I] EFT_PTR valid */
51 #define RIO_PEF_ADDR_66 0x00000004 /* [I] 66 bits */
52 #define RIO_PEF_ADDR_50 0x00000002 /* [I] 50 bits */
53 #define RIO_PEF_ADDR_34 0x00000001 /* [I] 34 bits */
55 #define RIO_SWP_INFO_CAR 0x14 /* [I] Switch Port Information CAR */
56 #define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 /* [I] Total number of ports */
57 #define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff /* [I] Maintenance transaction port number */
58 #define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
59 #define RIO_GET_PORT_NUM(x) (x & RIO_SWP_INFO_PORT_NUM_MASK)
61 #define RIO_SRC_OPS_CAR 0x18 /* [I] Source Operations CAR */
62 #define RIO_SRC_OPS_READ 0x00008000 /* [I] Read op */
63 #define RIO_SRC_OPS_WRITE 0x00004000 /* [I] Write op */
64 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
65 #define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
66 #define RIO_SRC_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
67 #define RIO_SRC_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
68 #define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
69 #define RIO_SRC_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
70 #define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
71 #define RIO_SRC_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
72 #define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
73 #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
75 #define RIO_DST_OPS_CAR 0x1c /* Destination Operations CAR */
76 #define RIO_DST_OPS_READ 0x00008000 /* [I] Read op */
77 #define RIO_DST_OPS_WRITE 0x00004000 /* [I] Write op */
78 #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
79 #define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
80 #define RIO_DST_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
81 #define RIO_DST_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
82 #define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
83 #define RIO_DST_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
84 #define RIO_DST_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
85 #define RIO_DST_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
86 #define RIO_DST_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
87 #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
89 #define RIO_OPS_READ 0x00008000 /* [I] Read op */
90 #define RIO_OPS_WRITE 0x00004000 /* [I] Write op */
91 #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
92 #define RIO_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
93 #define RIO_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
94 #define RIO_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
95 #define RIO_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
96 #define RIO_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
97 #define RIO_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
98 #define RIO_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
99 #define RIO_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
100 #define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
102 /* 0x20-0x30 *//* Reserved */
104 #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
105 #define RIO_RT_MAX_DESTID 0x0000ffff
107 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
108 #define RIO_MBOX0_AVAIL 0x80000000 /* [II] Mbox 0 avail */
109 #define RIO_MBOX0_FULL 0x40000000 /* [II] Mbox 0 full */
110 #define RIO_MBOX0_EMPTY 0x20000000 /* [II] Mbox 0 empty */
111 #define RIO_MBOX0_BUSY 0x10000000 /* [II] Mbox 0 busy */
112 #define RIO_MBOX0_FAIL 0x08000000 /* [II] Mbox 0 fail */
113 #define RIO_MBOX0_ERROR 0x04000000 /* [II] Mbox 0 error */
114 #define RIO_MBOX1_AVAIL 0x00800000 /* [II] Mbox 1 avail */
115 #define RIO_MBOX1_FULL 0x00200000 /* [II] Mbox 1 full */
116 #define RIO_MBOX1_EMPTY 0x00200000 /* [II] Mbox 1 empty */
117 #define RIO_MBOX1_BUSY 0x00100000 /* [II] Mbox 1 busy */
118 #define RIO_MBOX1_FAIL 0x00080000 /* [II] Mbox 1 fail */
119 #define RIO_MBOX1_ERROR 0x00040000 /* [II] Mbox 1 error */
120 #define RIO_MBOX2_AVAIL 0x00008000 /* [II] Mbox 2 avail */
121 #define RIO_MBOX2_FULL 0x00004000 /* [II] Mbox 2 full */
122 #define RIO_MBOX2_EMPTY 0x00002000 /* [II] Mbox 2 empty */
123 #define RIO_MBOX2_BUSY 0x00001000 /* [II] Mbox 2 busy */
124 #define RIO_MBOX2_FAIL 0x00000800 /* [II] Mbox 2 fail */
125 #define RIO_MBOX2_ERROR 0x00000400 /* [II] Mbox 2 error */
126 #define RIO_MBOX3_AVAIL 0x00000080 /* [II] Mbox 3 avail */
127 #define RIO_MBOX3_FULL 0x00000040 /* [II] Mbox 3 full */
128 #define RIO_MBOX3_EMPTY 0x00000020 /* [II] Mbox 3 empty */
129 #define RIO_MBOX3_BUSY 0x00000010 /* [II] Mbox 3 busy */
130 #define RIO_MBOX3_FAIL 0x00000008 /* [II] Mbox 3 fail */
131 #define RIO_MBOX3_ERROR 0x00000004 /* [II] Mbox 3 error */
133 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
134 #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */
135 #define RIO_DOORBELL_AVAIL 0x80000000 /* [II] Doorbell avail */
136 #define RIO_DOORBELL_FULL 0x40000000 /* [II] Doorbell full */
137 #define RIO_DOORBELL_EMPTY 0x20000000 /* [II] Doorbell empty */
138 #define RIO_DOORBELL_BUSY 0x10000000 /* [II] Doorbell busy */
139 #define RIO_DOORBELL_FAILED 0x08000000 /* [II] Doorbell failed */
140 #define RIO_DOORBELL_ERROR 0x04000000 /* [II] Doorbell error */
141 #define RIO_WRITE_PORT_AVAILABLE 0x00000080 /* [I] Write Port Available */
142 #define RIO_WRITE_PORT_FULL 0x00000040 /* [I] Write Port Full */
143 #define RIO_WRITE_PORT_EMPTY 0x00000020 /* [I] Write Port Empty */
144 #define RIO_WRITE_PORT_BUSY 0x00000010 /* [I] Write Port Busy */
145 #define RIO_WRITE_PORT_FAILED 0x00000008 /* [I] Write Port Failed */
146 #define RIO_WRITE_PORT_ERROR 0x00000004 /* [I] Write Port Error */
148 /* 0x48 *//* Reserved */
150 #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
151 #define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */
152 #define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */
153 #define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */
155 /* 0x50-0x54 *//* Reserved */
157 #define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */
158 #define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */
160 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
162 /* 0x64 *//* Reserved */
164 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
165 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
167 #define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70
168 #define RIO_STD_RTE_CONF_EXTCFGEN 0x80000000
169 #define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74
170 #define RIO_STD_RTE_DEFAULT_PORT 0x78
172 /* 0x7c-0xf8 *//* Reserved */
173 /* 0x100-0xfff8 *//* [I] Extended Features Space */
174 /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
177 * Extended Features Space is a configuration space area where
178 * functionality is mapped into extended feature blocks via a
179 * singly linked list of extended feature pointers (EFT_PTR).
181 * Each extended feature block can be identified/located in
182 * Extended Features Space by walking the extended feature
183 * list starting with the Extended Feature Pointer located
184 * in the Assembly Information CAR.
186 * Extended Feature Blocks (EFBs) are identified with an assigned
187 * EFB ID. Extended feature block offsets in the definitions are
188 * relative to the offset of the EFB within the Extended Features
192 /* Helper macros to parse the Extended Feature Block header */
193 #define RIO_EFB_PTR_MASK 0xffff0000
194 #define RIO_EFB_ID_MASK 0x0000ffff
195 #define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16)
196 #define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK)
198 /* Extended Feature Block IDs */
199 #define RIO_EFB_SER_EP_M1_ID 0x0001 /* [VI] LP-Serial EP Devices, Map I */
200 #define RIO_EFB_SER_EP_SW_M1_ID 0x0002 /* [VI] LP-Serial EP w SW Recovery Devices, Map I */
201 #define RIO_EFB_SER_EPF_M1_ID 0x0003 /* [VI] LP-Serial EP Free Devices, Map I */
202 #define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP-Serial EP Devices, RIO 1.2 */
203 #define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP-Serial EP w SW Recovery Devices, RIO 1.2 */
204 #define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP-Serial EP Free Devices, RIO 1.2 */
205 #define RIO_EFB_ERR_MGMNT 0x0007 /* [VIII] Error Management Extensions */
206 #define RIO_EFB_SER_EPF_SW_M1_ID 0x0009 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map I */
207 #define RIO_EFB_SW_ROUTING_TBL 0x000E /* [III] Switch Routing Table Block */
208 #define RIO_EFB_SER_EP_M2_ID 0x0011 /* [VI] LP-Serial EP Devices, Map II */
209 #define RIO_EFB_SER_EP_SW_M2_ID 0x0012 /* [VI] LP-Serial EP w SW Recovery Devices, Map II */
210 #define RIO_EFB_SER_EPF_M2_ID 0x0013 /* [VI] LP-Serial EP Free Devices, Map II */
211 #define RIO_EFB_ERR_MGMNT_HS 0x0017 /* [VIII] Error Management Extensions, Hot-Swap only */
212 #define RIO_EFB_SER_EPF_SW_M2_ID 0x0019 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map II */
215 * Physical LP-Serial Registers Definitions
216 * Parameters in register macros:
217 * n - port number, m - Register Map Type (1 or 2)
219 #define RIO_PORT_MNT_HEADER 0x0000
220 #define RIO_PORT_REQ_CTL_CSR 0x0020
221 #define RIO_PORT_RSP_CTL_CSR 0x0024
222 #define RIO_PORT_LINKTO_CTL_CSR 0x0020
223 #define RIO_PORT_RSPTO_CTL_CSR 0x0024
224 #define RIO_PORT_GEN_CTL_CSR 0x003c
225 #define RIO_PORT_GEN_HOST 0x80000000
226 #define RIO_PORT_GEN_MASTER 0x40000000
227 #define RIO_PORT_GEN_DISCOVERED 0x20000000
228 #define RIO_PORT_N_MNT_REQ_CSR(n, m) (0x40 + (n) * (0x20 * (m)))
229 #define RIO_MNT_REQ_CMD_RD 0x03 /* Reset-device command */
230 #define RIO_MNT_REQ_CMD_IS 0x04 /* Input-status command */
231 #define RIO_PORT_N_MNT_RSP_CSR(n, m) (0x44 + (n) * (0x20 * (m)))
232 #define RIO_PORT_N_MNT_RSP_RVAL 0x80000000 /* Response Valid */
233 #define RIO_PORT_N_MNT_RSP_ASTAT 0x000007e0 /* ackID Status */
234 #define RIO_PORT_N_MNT_RSP_LSTAT 0x0000001f /* Link Status */
235 #define RIO_PORT_N_ACK_STS_CSR(n) (0x48 + (n) * 0x20) /* Only in RM-I */
236 #define RIO_PORT_N_ACK_CLEAR 0x80000000
237 #define RIO_PORT_N_ACK_INBOUND 0x3f000000
238 #define RIO_PORT_N_ACK_OUTSTAND 0x00003f00
239 #define RIO_PORT_N_ACK_OUTBOUND 0x0000003f
240 #define RIO_PORT_N_CTL2_CSR(n, m) (0x54 + (n) * (0x20 * (m)))
241 #define RIO_PORT_N_CTL2_SEL_BAUD 0xf0000000
242 #define RIO_PORT_N_ERR_STS_CSR(n, m) (0x58 + (n) * (0x20 * (m)))
243 #define RIO_PORT_N_ERR_STS_OUT_ES 0x00010000 /* Output Error-stopped */
244 #define RIO_PORT_N_ERR_STS_INP_ES 0x00000100 /* Input Error-stopped */
245 #define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010 /* Port-Write Pending */
246 #define RIO_PORT_N_ERR_STS_PORT_UA 0x00000008 /* Port Unavailable */
247 #define RIO_PORT_N_ERR_STS_PORT_ERR 0x00000004
248 #define RIO_PORT_N_ERR_STS_PORT_OK 0x00000002
249 #define RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001
250 #define RIO_PORT_N_CTL_CSR(n, m) (0x5c + (n) * (0x20 * (m)))
251 #define RIO_PORT_N_CTL_PWIDTH 0xc0000000
252 #define RIO_PORT_N_CTL_PWIDTH_1 0x00000000
253 #define RIO_PORT_N_CTL_PWIDTH_4 0x40000000
254 #define RIO_PORT_N_CTL_IPW 0x38000000 /* Initialized Port Width */
255 #define RIO_PORT_N_CTL_P_TYP_SER 0x00000001
256 #define RIO_PORT_N_CTL_LOCKOUT 0x00000002
257 #define RIO_PORT_N_CTL_EN_RX 0x00200000
258 #define RIO_PORT_N_CTL_EN_TX 0x00400000
259 #define RIO_PORT_N_OB_ACK_CSR(n) (0x60 + (n) * 0x40) /* Only in RM-II */
260 #define RIO_PORT_N_OB_ACK_CLEAR 0x80000000
261 #define RIO_PORT_N_OB_ACK_OUTSTD 0x00fff000
262 #define RIO_PORT_N_OB_ACK_OUTBND 0x00000fff
263 #define RIO_PORT_N_IB_ACK_CSR(n) (0x64 + (n) * 0x40) /* Only in RM-II */
264 #define RIO_PORT_N_IB_ACK_INBND 0x00000fff
267 * Device-based helper macros for serial port register access.
268 * d - pointer to rapidio device object, n - port number
271 #define RIO_DEV_PORT_N_MNT_REQ_CSR(d, n) \
272 (d->phys_efptr + RIO_PORT_N_MNT_REQ_CSR(n, d->phys_rmap))
274 #define RIO_DEV_PORT_N_MNT_RSP_CSR(d, n) \
275 (d->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(n, d->phys_rmap))
277 #define RIO_DEV_PORT_N_ACK_STS_CSR(d, n) \
278 (d->phys_efptr + RIO_PORT_N_ACK_STS_CSR(n))
280 #define RIO_DEV_PORT_N_CTL2_CSR(d, n) \
281 (d->phys_efptr + RIO_PORT_N_CTL2_CSR(n, d->phys_rmap))
283 #define RIO_DEV_PORT_N_ERR_STS_CSR(d, n) \
284 (d->phys_efptr + RIO_PORT_N_ERR_STS_CSR(n, d->phys_rmap))
286 #define RIO_DEV_PORT_N_CTL_CSR(d, n) \
287 (d->phys_efptr + RIO_PORT_N_CTL_CSR(n, d->phys_rmap))
289 #define RIO_DEV_PORT_N_OB_ACK_CSR(d, n) \
290 (d->phys_efptr + RIO_PORT_N_OB_ACK_CSR(n))
292 #define RIO_DEV_PORT_N_IB_ACK_CSR(d, n) \
293 (d->phys_efptr + RIO_PORT_N_IB_ACK_CSR(n))
296 * Error Management Extensions (RapidIO 1.3+, Part 8)
298 * Extended Features Block ID=0x0007
301 /* General EM Registers (Common for all Ports) */
303 #define RIO_EM_EFB_HEADER 0x000 /* Error Management Extensions Block Header */
304 #define RIO_EM_EMHS_CAR 0x004 /* EM Functionality CAR */
305 #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */
306 #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */
307 #define REM_LTL_ERR_ILLTRAN 0x08000000 /* Illegal Transaction decode */
308 #define REM_LTL_ERR_UNSOLR 0x00800000 /* Unsolicited Response */
309 #define REM_LTL_ERR_UNSUPTR 0x00400000 /* Unsupported Transaction */
310 #define REM_LTL_ERR_IMPSPEC 0x000000ff /* Implementation Specific */
311 #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */
312 #define RIO_EM_LTL_ADDR_CAP 0x014 /* Logical/Transport Layer Address Capture CSR */
313 #define RIO_EM_LTL_DEVID_CAP 0x018 /* Logical/Transport Layer Device ID Capture CSR */
314 #define RIO_EM_LTL_CTRL_CAP 0x01c /* Logical/Transport Layer Control Capture CSR */
315 #define RIO_EM_LTL_DID32_CAP 0x020 /* Logical/Transport Layer Dev32 DestID Capture CSR */
316 #define RIO_EM_LTL_SID32_CAP 0x024 /* Logical/Transport Layer Dev32 source ID Capture CSR */
317 #define RIO_EM_PW_TGT_DEVID 0x028 /* Port-write Target deviceID CSR */
318 #define RIO_EM_PW_TGT_DEVID_D16M 0xff000000 /* Port-write Target DID16 MSB */
319 #define RIO_EM_PW_TGT_DEVID_D8 0x00ff0000 /* Port-write Target DID16 LSB or DID8 */
320 #define RIO_EM_PW_TGT_DEVID_DEV16 0x00008000 /* Port-write Target DID16 LSB or DID8 */
321 #define RIO_EM_PW_TGT_DEVID_DEV32 0x00004000 /* Port-write Target DID16 LSB or DID8 */
322 #define RIO_EM_PKT_TTL 0x02c /* Packet Time-to-live CSR */
323 #define RIO_EM_PKT_TTL_VAL 0xffff0000 /* Packet Time-to-live value */
324 #define RIO_EM_PW_TGT32_DEVID 0x030 /* Port-write Dev32 Target deviceID CSR */
325 #define RIO_EM_PW_TX_CTRL 0x034 /* Port-write Transmission Control CSR */
326 #define RIO_EM_PW_TX_CTRL_PW_DIS 0x00000001 /* Port-write Transmission Disable bit */
328 /* Per-Port EM Registers */
330 #define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) /* Port N Error Detect CSR */
331 #define REM_PED_IMPL_SPEC 0x80000000
332 #define REM_PED_LINK_OK2U 0x40000000 /* Link OK to Uninit transition */
333 #define REM_PED_LINK_UPDA 0x20000000 /* Link Uninit Packet Discard Active */
334 #define REM_PED_LINK_U2OK 0x10000000 /* Link Uninit to OK transition */
335 #define REM_PED_LINK_TO 0x00000001
337 #define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */
338 #define RIO_EM_PN_ERRRATE_EN_OK2U 0x40000000 /* Enable notification for OK2U */
339 #define RIO_EM_PN_ERRRATE_EN_UPDA 0x20000000 /* Enable notification for UPDA */
340 #define RIO_EM_PN_ERRRATE_EN_U2OK 0x10000000 /* Enable notification for U2OK */
342 #define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) /* Port N Attributes Capture CSR */
343 #define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */
344 #define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40) /* Port N Packet Capture 1 CSR */
345 #define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40) /* Port N Packet Capture 2 CSR */
346 #define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40) /* Port N Packet Capture 3 CSR */
347 #define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40) /* Port N Error Rate CSR */
348 #define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */
349 #define RIO_EM_PN_LINK_UDT(x) (0x070 + x*0x40) /* Port N Link Uninit Discard Timer CSR */
350 #define RIO_EM_PN_LINK_UDT_TO 0xffffff00 /* Link Uninit Timeout value */
353 * Switch Routing Table Register Block ID=0x000E (RapidIO 3.0+, part 3)
354 * Register offsets are defined from beginning of the block.
357 /* Broadcast Routing Table Control CSR */
358 #define RIO_BC_RT_CTL_CSR 0x020
359 #define RIO_RT_CTL_THREE_LVL 0x80000000
360 #define RIO_RT_CTL_DEV32_RT_CTRL 0x40000000
361 #define RIO_RT_CTL_MC_MASK_SZ 0x03000000 /* 3.0+ Part 11: Multicast */
363 /* Broadcast Level 0 Info CSR */
364 #define RIO_BC_RT_LVL0_INFO_CSR 0x030
365 #define RIO_RT_L0I_NUM_GR 0xff000000
366 #define RIO_RT_L0I_GR_PTR 0x00fffc00
368 /* Broadcast Level 1 Info CSR */
369 #define RIO_BC_RT_LVL1_INFO_CSR 0x034
370 #define RIO_RT_L1I_NUM_GR 0xff000000
371 #define RIO_RT_L1I_GR_PTR 0x00fffc00
373 /* Broadcast Level 2 Info CSR */
374 #define RIO_BC_RT_LVL2_INFO_CSR 0x038
375 #define RIO_RT_L2I_NUM_GR 0xff000000
376 #define RIO_RT_L2I_GR_PTR 0x00fffc00
378 /* Per-Port Routing Table registers.
379 * Register fields defined in the broadcast section above are
380 * applicable to the corresponding registers below.
382 #define RIO_SPx_RT_CTL_CSR(x) (0x040 + (0x20 * x))
383 #define RIO_SPx_RT_LVL0_INFO_CSR(x) (0x50 + (0x20 * x))
384 #define RIO_SPx_RT_LVL1_INFO_CSR(x) (0x54 + (0x20 * x))
385 #define RIO_SPx_RT_LVL2_INFO_CSR(x) (0x58 + (0x20 * x))
387 /* Register Formats for Routing Table Group entry.
388 * Register offsets are calculated using GR_PTR field in the corresponding
389 * table Level_N and group/entry numbers (see RapidIO 3.0+ Part 3).
391 #define RIO_RT_Ln_ENTRY_IMPL_DEF 0xf0000000
392 #define RIO_RT_Ln_ENTRY_RTE_VAL 0x000003ff
393 #define RIO_RT_ENTRY_DROP_PKT 0x300
395 #endif /* LINUX_RIO_REGS_H */
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