4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
195 /* These values come from the PCI Express Spec */
196 enum pcie_link_width {
197 PCIE_LNK_WIDTH_RESRV = 0x00,
205 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
208 /* Based on the PCI Hotplug Spec, but some values are made up by us */
210 PCI_SPEED_33MHz = 0x00,
211 PCI_SPEED_66MHz = 0x01,
212 PCI_SPEED_66MHz_PCIX = 0x02,
213 PCI_SPEED_100MHz_PCIX = 0x03,
214 PCI_SPEED_133MHz_PCIX = 0x04,
215 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
216 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
217 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
218 PCI_SPEED_66MHz_PCIX_266 = 0x09,
219 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
220 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
226 PCI_SPEED_66MHz_PCIX_533 = 0x11,
227 PCI_SPEED_100MHz_PCIX_533 = 0x12,
228 PCI_SPEED_133MHz_PCIX_533 = 0x13,
229 PCIE_SPEED_2_5GT = 0x14,
230 PCIE_SPEED_5_0GT = 0x15,
231 PCIE_SPEED_8_0GT = 0x16,
232 PCI_SPEED_UNKNOWN = 0xff,
235 struct pci_cap_saved_data {
242 struct pci_cap_saved_state {
243 struct hlist_node next;
244 struct pci_cap_saved_data cap;
247 struct pcie_link_state;
253 * The pci_dev structure is used to describe PCI devices.
256 struct list_head bus_list; /* node in per-bus list */
257 struct pci_bus *bus; /* bus this device is on */
258 struct pci_bus *subordinate; /* bus this device bridges to */
260 void *sysdata; /* hook for sys-specific extension */
261 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
262 struct pci_slot *slot; /* Physical slot this device is in */
264 unsigned int devfn; /* encoded device & function index */
265 unsigned short vendor;
266 unsigned short device;
267 unsigned short subsystem_vendor;
268 unsigned short subsystem_device;
269 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
270 u8 revision; /* PCI revision, low byte of class word */
271 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
272 #ifdef CONFIG_PCIEAER
273 u16 aer_cap; /* AER capability offset */
275 u8 pcie_cap; /* PCIe capability offset */
276 u8 msi_cap; /* MSI capability offset */
277 u8 msix_cap; /* MSI-X capability offset */
278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
279 u8 rom_base_reg; /* which config register controls the ROM */
280 u8 pin; /* which interrupt pin this device uses */
281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
282 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
284 struct pci_driver *driver; /* which driver has allocated this device */
285 u64 dma_mask; /* Mask of the bits of bus address this
286 device implements. Normally this is
287 0xffffffff. You only need to change
288 this if your device has broken DMA
289 or supports 64-bit transfers. */
291 struct device_dma_parameters dma_parms;
293 pci_power_t current_state; /* Current operating state. In ACPI-speak,
294 this is D0-D3, D0 being fully functional,
296 u8 pm_cap; /* PM capability offset */
297 unsigned int pme_support:5; /* Bitmask of states from which PME#
299 unsigned int pme_interrupt:1;
300 unsigned int pme_poll:1; /* Poll device's PME status bit */
301 unsigned int d1_support:1; /* Low power state D1 is supported */
302 unsigned int d2_support:1; /* Low power state D2 is supported */
303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
304 unsigned int no_d3cold:1; /* D3cold is forbidden */
305 unsigned int bridge_d3:1; /* Allow D3 for bridge */
306 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
307 unsigned int mmio_always_on:1; /* disallow turning off io/mem
308 decoding during bar sizing */
309 unsigned int wakeup_prepared:1;
310 unsigned int runtime_d3cold:1; /* whether go through runtime
311 D3cold, not set for devices
312 powered on/off by the
313 corresponding bridge */
314 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
315 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
316 controlled exclusively by
318 unsigned int d3_delay; /* D3->D0 transition time in ms */
319 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
321 #ifdef CONFIG_PCIEASPM
322 struct pcie_link_state *link_state; /* ASPM link state */
325 pci_channel_state_t error_state; /* current connectivity state */
326 struct device dev; /* Generic device interface */
328 int cfg_size; /* Size of configuration space */
331 * Instead of touching interrupt line and base address registers
332 * directly, use the values stored here. They might be different!
335 struct cpumask *irq_affinity;
336 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
338 bool match_driver; /* Skip attaching driver */
339 /* These fields are used by common fixups */
340 unsigned int transparent:1; /* Subtractive decode PCI bridge */
341 unsigned int multifunction:1;/* Part of multi-function device */
342 /* keep track of device state */
343 unsigned int is_added:1;
344 unsigned int is_busmaster:1; /* device is busmaster */
345 unsigned int no_msi:1; /* device may not use msi */
346 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
347 unsigned int block_cfg_access:1; /* config space access is blocked */
348 unsigned int broken_parity_status:1; /* Device generates false positive parity */
349 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
350 unsigned int msi_enabled:1;
351 unsigned int msix_enabled:1;
352 unsigned int ari_enabled:1; /* ARI forwarding */
353 unsigned int ats_enabled:1; /* Address Translation Service */
354 unsigned int is_managed:1;
355 unsigned int needs_freset:1; /* Dev requires fundamental reset */
356 unsigned int state_saved:1;
357 unsigned int is_physfn:1;
358 unsigned int is_virtfn:1;
359 unsigned int reset_fn:1;
360 unsigned int is_hotplug_bridge:1;
361 unsigned int __aer_firmware_first_valid:1;
362 unsigned int __aer_firmware_first:1;
363 unsigned int broken_intx_masking:1;
364 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
365 unsigned int irq_managed:1;
366 unsigned int has_secondary_link:1;
367 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
368 pci_dev_flags_t dev_flags;
369 atomic_t enable_cnt; /* pci_enable_device has been called */
371 u32 saved_config_space[16]; /* config space saved at suspend time */
372 struct hlist_head saved_cap_space;
373 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
374 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
375 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
376 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
378 #ifdef CONFIG_PCIE_PTM
379 unsigned int ptm_root:1;
380 unsigned int ptm_enabled:1;
383 #ifdef CONFIG_PCI_MSI
384 const struct attribute_group **msi_irq_groups;
387 #ifdef CONFIG_PCI_ATS
389 struct pci_sriov *sriov; /* SR-IOV capability related */
390 struct pci_dev *physfn; /* the PF this VF is associated with */
392 u16 ats_cap; /* ATS Capability offset */
393 u8 ats_stu; /* ATS Smallest Translation Unit */
394 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
396 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
397 size_t romlen; /* Length of ROM if it's not from the BAR */
398 char *driver_override; /* Driver name to force a match */
401 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
403 #ifdef CONFIG_PCI_IOV
410 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
412 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
413 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
415 static inline int pci_channel_offline(struct pci_dev *pdev)
417 return (pdev->error_state != pci_channel_io_normal);
420 struct pci_host_bridge {
422 struct pci_bus *bus; /* root bus */
423 struct list_head windows; /* resource_entry */
424 void (*release_fn)(struct pci_host_bridge *);
426 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
427 /* Resource alignment requirements */
428 resource_size_t (*align_resource)(struct pci_dev *dev,
429 const struct resource *res,
430 resource_size_t start,
431 resource_size_t size,
432 resource_size_t align);
435 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
437 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
439 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
440 void (*release_fn)(struct pci_host_bridge *),
443 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
446 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
447 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
448 * buses below host bridges or subtractive decode bridges) go in the list.
449 * Use pci_bus_for_each_resource() to iterate through all the resources.
453 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
454 * and there's no way to program the bridge with the details of the window.
455 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
456 * decode bit set, because they are explicit and can be programmed with _SRS.
458 #define PCI_SUBTRACTIVE_DECODE 0x1
460 struct pci_bus_resource {
461 struct list_head list;
462 struct resource *res;
466 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
469 struct list_head node; /* node in list of buses */
470 struct pci_bus *parent; /* parent bus this bridge is on */
471 struct list_head children; /* list of child buses */
472 struct list_head devices; /* list of devices on this bus */
473 struct pci_dev *self; /* bridge device as seen by parent */
474 struct list_head slots; /* list of slots on this bus;
475 protected by pci_slot_mutex */
476 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
477 struct list_head resources; /* address space routed to this bus */
478 struct resource busn_res; /* bus numbers routed to this bus */
480 struct pci_ops *ops; /* configuration access functions */
481 struct msi_controller *msi; /* MSI controller */
482 void *sysdata; /* hook for sys-specific extension */
483 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
485 unsigned char number; /* bus number */
486 unsigned char primary; /* number of primary bridge */
487 unsigned char max_bus_speed; /* enum pci_bus_speed */
488 unsigned char cur_bus_speed; /* enum pci_bus_speed */
489 #ifdef CONFIG_PCI_DOMAINS_GENERIC
495 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
496 pci_bus_flags_t bus_flags; /* inherited by child buses */
497 struct device *bridge;
499 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
500 struct bin_attribute *legacy_mem; /* legacy mem */
501 unsigned int is_added:1;
504 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
507 * Returns true if the PCI bus is root (behind host-PCI bridge),
510 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
511 * This is incorrect because "virtual" buses added for SR-IOV (via
512 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
514 static inline bool pci_is_root_bus(struct pci_bus *pbus)
516 return !(pbus->parent);
520 * pci_is_bridge - check if the PCI device is a bridge
523 * Return true if the PCI device is bridge whether it has subordinate
526 static inline bool pci_is_bridge(struct pci_dev *dev)
528 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
529 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
532 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
534 dev = pci_physfn(dev);
535 if (pci_is_root_bus(dev->bus))
538 return dev->bus->self;
541 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
542 void pci_put_host_bridge_device(struct device *dev);
544 #ifdef CONFIG_PCI_MSI
545 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
547 return pci_dev->msi_enabled || pci_dev->msix_enabled;
550 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
554 * Error values that may be returned by PCI functions.
556 #define PCIBIOS_SUCCESSFUL 0x00
557 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
558 #define PCIBIOS_BAD_VENDOR_ID 0x83
559 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
560 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
561 #define PCIBIOS_SET_FAILED 0x88
562 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
565 * Translate above to generic errno for passing back through non-PCI code.
567 static inline int pcibios_err_to_errno(int err)
569 if (err <= PCIBIOS_SUCCESSFUL)
570 return err; /* Assume already errno */
573 case PCIBIOS_FUNC_NOT_SUPPORTED:
575 case PCIBIOS_BAD_VENDOR_ID:
577 case PCIBIOS_DEVICE_NOT_FOUND:
579 case PCIBIOS_BAD_REGISTER_NUMBER:
581 case PCIBIOS_SET_FAILED:
583 case PCIBIOS_BUFFER_TOO_SMALL:
590 /* Low-level architecture-dependent routines */
593 int (*add_bus)(struct pci_bus *bus);
594 void (*remove_bus)(struct pci_bus *bus);
595 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
596 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
597 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
601 * ACPI needs to be able to access PCI config space before we've done a
602 * PCI bus scan and created pci_bus structures.
604 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
605 int reg, int len, u32 *val);
606 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
607 int reg, int len, u32 val);
609 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
610 typedef u64 pci_bus_addr_t;
612 typedef u32 pci_bus_addr_t;
615 struct pci_bus_region {
616 pci_bus_addr_t start;
621 spinlock_t lock; /* protects list, index */
622 struct list_head list; /* for IDs added at runtime */
627 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
628 * a set of callbacks in struct pci_error_handlers, that device driver
629 * will be notified of PCI bus errors, and will be driven to recovery
630 * when an error occurs.
633 typedef unsigned int __bitwise pci_ers_result_t;
635 enum pci_ers_result {
636 /* no result/none/not supported in device driver */
637 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
639 /* Device driver can recover without slot reset */
640 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
642 /* Device driver wants slot to be reset. */
643 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
645 /* Device has completely failed, is unrecoverable */
646 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
648 /* Device driver is fully recovered and operational */
649 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
651 /* No AER capabilities registered for the driver */
652 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
655 /* PCI bus error event callbacks */
656 struct pci_error_handlers {
657 /* PCI bus error detected on this device */
658 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
659 enum pci_channel_state error);
661 /* MMIO has been re-enabled, but not DMA */
662 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
664 /* PCI Express link has been reset */
665 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
667 /* PCI slot has been reset */
668 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
670 /* PCI function reset prepare or completed */
671 void (*reset_notify)(struct pci_dev *dev, bool prepare);
673 /* Device driver may resume normal operations */
674 void (*resume)(struct pci_dev *dev);
680 struct list_head node;
682 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
683 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
684 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
685 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
686 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
687 int (*resume_early) (struct pci_dev *dev);
688 int (*resume) (struct pci_dev *dev); /* Device woken up */
689 void (*shutdown) (struct pci_dev *dev);
690 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
691 const struct pci_error_handlers *err_handler;
692 struct device_driver driver;
693 struct pci_dynids dynids;
696 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
699 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
700 * @_table: device table name
702 * This macro is deprecated and should not be used in new code.
704 #define DEFINE_PCI_DEVICE_TABLE(_table) \
705 const struct pci_device_id _table[]
708 * PCI_DEVICE - macro used to describe a specific pci device
709 * @vend: the 16 bit PCI Vendor ID
710 * @dev: the 16 bit PCI Device ID
712 * This macro is used to create a struct pci_device_id that matches a
713 * specific device. The subvendor and subdevice fields will be set to
716 #define PCI_DEVICE(vend,dev) \
717 .vendor = (vend), .device = (dev), \
718 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
721 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
722 * @vend: the 16 bit PCI Vendor ID
723 * @dev: the 16 bit PCI Device ID
724 * @subvend: the 16 bit PCI Subvendor ID
725 * @subdev: the 16 bit PCI Subdevice ID
727 * This macro is used to create a struct pci_device_id that matches a
728 * specific device with subsystem information.
730 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
731 .vendor = (vend), .device = (dev), \
732 .subvendor = (subvend), .subdevice = (subdev)
735 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
736 * @dev_class: the class, subclass, prog-if triple for this device
737 * @dev_class_mask: the class mask for this device
739 * This macro is used to create a struct pci_device_id that matches a
740 * specific PCI class. The vendor, device, subvendor, and subdevice
741 * fields will be set to PCI_ANY_ID.
743 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
744 .class = (dev_class), .class_mask = (dev_class_mask), \
745 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
746 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
749 * PCI_VDEVICE - macro used to describe a specific pci device in short form
750 * @vend: the vendor name
751 * @dev: the 16 bit PCI Device ID
753 * This macro is used to create a struct pci_device_id that matches a
754 * specific PCI device. The subvendor, and subdevice fields will be set
755 * to PCI_ANY_ID. The macro allows the next field to follow as the device
759 #define PCI_VDEVICE(vend, dev) \
760 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
761 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
764 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
765 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
766 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
767 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
768 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
769 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
770 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
773 /* these external functions are only available when PCI support is enabled */
776 extern unsigned int pci_flags;
778 static inline void pci_set_flags(int flags) { pci_flags = flags; }
779 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
780 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
781 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
783 void pcie_bus_configure_settings(struct pci_bus *bus);
785 enum pcie_bus_config_types {
786 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
787 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
788 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
789 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
790 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
793 extern enum pcie_bus_config_types pcie_bus_config;
795 extern struct bus_type pci_bus_type;
797 /* Do NOT directly access these two variables, unless you are arch-specific PCI
798 * code, or PCI core code. */
799 extern struct list_head pci_root_buses; /* list of all known PCI buses */
800 /* Some device drivers need know if PCI is initiated */
801 int no_pci_devices(void);
803 void pcibios_resource_survey_bus(struct pci_bus *bus);
804 void pcibios_bus_add_device(struct pci_dev *pdev);
805 void pcibios_add_bus(struct pci_bus *bus);
806 void pcibios_remove_bus(struct pci_bus *bus);
807 void pcibios_fixup_bus(struct pci_bus *);
808 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
809 /* Architecture-specific versions may override this (weak) */
810 char *pcibios_setup(char *str);
812 /* Used only when drivers/pci/setup.c is used */
813 resource_size_t pcibios_align_resource(void *, const struct resource *,
816 void pcibios_update_irq(struct pci_dev *, int irq);
818 /* Weak but can be overriden by arch */
819 void pci_fixup_cardbus(struct pci_bus *);
821 /* Generic PCI functions used internally */
823 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
824 struct resource *res);
825 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
826 struct pci_bus_region *region);
827 void pcibios_scan_specific_bus(int busn);
828 struct pci_bus *pci_find_bus(int domain, int busnr);
829 void pci_bus_add_devices(const struct pci_bus *bus);
830 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
831 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
832 struct pci_ops *ops, void *sysdata,
833 struct list_head *resources);
834 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
835 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
836 void pci_bus_release_busn_res(struct pci_bus *b);
837 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
838 struct pci_ops *ops, void *sysdata,
839 struct list_head *resources,
840 struct msi_controller *msi);
841 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
842 struct pci_ops *ops, void *sysdata,
843 struct list_head *resources);
844 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
846 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
847 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
849 struct hotplug_slot *hotplug);
850 void pci_destroy_slot(struct pci_slot *slot);
852 void pci_dev_assign_slot(struct pci_dev *dev);
854 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
856 int pci_scan_slot(struct pci_bus *bus, int devfn);
857 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
858 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
859 unsigned int pci_scan_child_bus(struct pci_bus *bus);
860 void pci_bus_add_device(struct pci_dev *dev);
861 void pci_read_bridge_bases(struct pci_bus *child);
862 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
863 struct resource *res);
864 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
865 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
866 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
867 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
868 struct pci_dev *pci_dev_get(struct pci_dev *dev);
869 void pci_dev_put(struct pci_dev *dev);
870 void pci_remove_bus(struct pci_bus *b);
871 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
872 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
873 void pci_stop_root_bus(struct pci_bus *bus);
874 void pci_remove_root_bus(struct pci_bus *bus);
875 void pci_setup_cardbus(struct pci_bus *bus);
876 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
877 void pci_sort_breadthfirst(void);
878 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
879 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
880 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
882 /* Generic PCI functions exported to card drivers */
884 enum pci_lost_interrupt_reason {
885 PCI_LOST_IRQ_NO_INFORMATION = 0,
886 PCI_LOST_IRQ_DISABLE_MSI,
887 PCI_LOST_IRQ_DISABLE_MSIX,
888 PCI_LOST_IRQ_DISABLE_ACPI,
890 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
891 int pci_find_capability(struct pci_dev *dev, int cap);
892 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
893 int pci_find_ext_capability(struct pci_dev *dev, int cap);
894 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
895 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
896 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
897 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
899 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
900 struct pci_dev *from);
901 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
902 unsigned int ss_vendor, unsigned int ss_device,
903 struct pci_dev *from);
904 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
905 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
907 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
910 return pci_get_domain_bus_and_slot(0, bus, devfn);
912 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
913 int pci_dev_present(const struct pci_device_id *ids);
915 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
917 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
918 int where, u16 *val);
919 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
920 int where, u32 *val);
921 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
923 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
925 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
928 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
929 int where, int size, u32 *val);
930 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
931 int where, int size, u32 val);
932 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
933 int where, int size, u32 *val);
934 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
935 int where, int size, u32 val);
937 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
939 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
941 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
943 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
945 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
947 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
950 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
952 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
954 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
956 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
958 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
960 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
963 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
966 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
967 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
968 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
969 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
970 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
972 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
975 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
978 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
981 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
984 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
987 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
990 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
993 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
996 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
999 /* user-space driven config access */
1000 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1001 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1002 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1003 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1004 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1005 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1007 int __must_check pci_enable_device(struct pci_dev *dev);
1008 int __must_check pci_enable_device_io(struct pci_dev *dev);
1009 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1010 int __must_check pci_reenable_device(struct pci_dev *);
1011 int __must_check pcim_enable_device(struct pci_dev *pdev);
1012 void pcim_pin_device(struct pci_dev *pdev);
1014 static inline int pci_is_enabled(struct pci_dev *pdev)
1016 return (atomic_read(&pdev->enable_cnt) > 0);
1019 static inline int pci_is_managed(struct pci_dev *pdev)
1021 return pdev->is_managed;
1024 void pci_disable_device(struct pci_dev *dev);
1026 extern unsigned int pcibios_max_latency;
1027 void pci_set_master(struct pci_dev *dev);
1028 void pci_clear_master(struct pci_dev *dev);
1030 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1031 int pci_set_cacheline_size(struct pci_dev *dev);
1032 #define HAVE_PCI_SET_MWI
1033 int __must_check pci_set_mwi(struct pci_dev *dev);
1034 int pci_try_set_mwi(struct pci_dev *dev);
1035 void pci_clear_mwi(struct pci_dev *dev);
1036 void pci_intx(struct pci_dev *dev, int enable);
1037 bool pci_intx_mask_supported(struct pci_dev *dev);
1038 bool pci_check_and_mask_intx(struct pci_dev *dev);
1039 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1040 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1041 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1042 int pcix_get_max_mmrbc(struct pci_dev *dev);
1043 int pcix_get_mmrbc(struct pci_dev *dev);
1044 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1045 int pcie_get_readrq(struct pci_dev *dev);
1046 int pcie_set_readrq(struct pci_dev *dev, int rq);
1047 int pcie_get_mps(struct pci_dev *dev);
1048 int pcie_set_mps(struct pci_dev *dev, int mps);
1049 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1050 enum pcie_link_width *width);
1051 int __pci_reset_function(struct pci_dev *dev);
1052 int __pci_reset_function_locked(struct pci_dev *dev);
1053 int pci_reset_function(struct pci_dev *dev);
1054 int pci_try_reset_function(struct pci_dev *dev);
1055 int pci_probe_reset_slot(struct pci_slot *slot);
1056 int pci_reset_slot(struct pci_slot *slot);
1057 int pci_try_reset_slot(struct pci_slot *slot);
1058 int pci_probe_reset_bus(struct pci_bus *bus);
1059 int pci_reset_bus(struct pci_bus *bus);
1060 int pci_try_reset_bus(struct pci_bus *bus);
1061 void pci_reset_secondary_bus(struct pci_dev *dev);
1062 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1063 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1064 void pci_update_resource(struct pci_dev *dev, int resno);
1065 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1066 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1067 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1068 bool pci_device_is_present(struct pci_dev *pdev);
1069 void pci_ignore_hotplug(struct pci_dev *dev);
1071 /* ROM control related routines */
1072 int pci_enable_rom(struct pci_dev *pdev);
1073 void pci_disable_rom(struct pci_dev *pdev);
1074 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1075 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1076 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1077 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1079 /* Power management related routines */
1080 int pci_save_state(struct pci_dev *dev);
1081 void pci_restore_state(struct pci_dev *dev);
1082 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1083 int pci_load_saved_state(struct pci_dev *dev,
1084 struct pci_saved_state *state);
1085 int pci_load_and_free_saved_state(struct pci_dev *dev,
1086 struct pci_saved_state **state);
1087 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1088 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1090 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1091 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1092 u16 cap, unsigned int size);
1093 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1094 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1095 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1096 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1097 void pci_pme_active(struct pci_dev *dev, bool enable);
1098 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1099 bool runtime, bool enable);
1100 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1101 int pci_prepare_to_sleep(struct pci_dev *dev);
1102 int pci_back_from_sleep(struct pci_dev *dev);
1103 bool pci_dev_run_wake(struct pci_dev *dev);
1104 bool pci_check_pme_status(struct pci_dev *dev);
1105 void pci_pme_wakeup_bus(struct pci_bus *bus);
1106 void pci_d3cold_enable(struct pci_dev *dev);
1107 void pci_d3cold_disable(struct pci_dev *dev);
1109 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1112 return __pci_enable_wake(dev, state, false, enable);
1115 /* PCI Virtual Channel */
1116 int pci_save_vc_state(struct pci_dev *dev);
1117 void pci_restore_vc_state(struct pci_dev *dev);
1118 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1120 /* For use by arch with custom probe code */
1121 void set_pcie_port_type(struct pci_dev *pdev);
1122 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1124 /* Functions for PCI Hotplug drivers to use */
1125 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1126 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1127 unsigned int pci_rescan_bus(struct pci_bus *bus);
1128 void pci_lock_rescan_remove(void);
1129 void pci_unlock_rescan_remove(void);
1131 /* Vital product data routines */
1132 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1133 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1134 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1136 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1137 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1138 void pci_bus_assign_resources(const struct pci_bus *bus);
1139 void pci_bus_claim_resources(struct pci_bus *bus);
1140 void pci_bus_size_bridges(struct pci_bus *bus);
1141 int pci_claim_resource(struct pci_dev *, int);
1142 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1143 void pci_assign_unassigned_resources(void);
1144 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1145 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1146 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1147 void pdev_enable_device(struct pci_dev *);
1148 int pci_enable_resources(struct pci_dev *, int mask);
1149 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1150 int (*)(const struct pci_dev *, u8, u8));
1151 #define HAVE_PCI_REQ_REGIONS 2
1152 int __must_check pci_request_regions(struct pci_dev *, const char *);
1153 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1154 void pci_release_regions(struct pci_dev *);
1155 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1156 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1157 void pci_release_region(struct pci_dev *, int);
1158 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1159 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1160 void pci_release_selected_regions(struct pci_dev *, int);
1162 /* drivers/pci/bus.c */
1163 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1164 void pci_bus_put(struct pci_bus *bus);
1165 void pci_add_resource(struct list_head *resources, struct resource *res);
1166 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1167 resource_size_t offset);
1168 void pci_free_resource_list(struct list_head *resources);
1169 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1170 unsigned int flags);
1171 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1172 void pci_bus_remove_resources(struct pci_bus *bus);
1173 int devm_request_pci_bus_resources(struct device *dev,
1174 struct list_head *resources);
1176 #define pci_bus_for_each_resource(bus, res, i) \
1178 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1181 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1182 struct resource *res, resource_size_t size,
1183 resource_size_t align, resource_size_t min,
1184 unsigned long type_mask,
1185 resource_size_t (*alignf)(void *,
1186 const struct resource *,
1192 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1193 unsigned long pci_address_to_pio(phys_addr_t addr);
1194 phys_addr_t pci_pio_to_address(unsigned long pio);
1195 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1196 void pci_unmap_iospace(struct resource *res);
1198 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1200 struct pci_bus_region region;
1202 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1203 return region.start;
1206 /* Proper probing supporting hot-pluggable devices */
1207 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1208 const char *mod_name);
1211 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1213 #define pci_register_driver(driver) \
1214 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1216 void pci_unregister_driver(struct pci_driver *dev);
1219 * module_pci_driver() - Helper macro for registering a PCI driver
1220 * @__pci_driver: pci_driver struct
1222 * Helper macro for PCI drivers which do not do anything special in module
1223 * init/exit. This eliminates a lot of boilerplate. Each module may only
1224 * use this macro once, and calling it replaces module_init() and module_exit()
1226 #define module_pci_driver(__pci_driver) \
1227 module_driver(__pci_driver, pci_register_driver, \
1228 pci_unregister_driver)
1231 * builtin_pci_driver() - Helper macro for registering a PCI driver
1232 * @__pci_driver: pci_driver struct
1234 * Helper macro for PCI drivers which do not do anything special in their
1235 * init code. This eliminates a lot of boilerplate. Each driver may only
1236 * use this macro once, and calling it replaces device_initcall(...)
1238 #define builtin_pci_driver(__pci_driver) \
1239 builtin_driver(__pci_driver, pci_register_driver)
1241 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1242 int pci_add_dynid(struct pci_driver *drv,
1243 unsigned int vendor, unsigned int device,
1244 unsigned int subvendor, unsigned int subdevice,
1245 unsigned int class, unsigned int class_mask,
1246 unsigned long driver_data);
1247 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1248 struct pci_dev *dev);
1249 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1252 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1254 int pci_cfg_space_size(struct pci_dev *dev);
1255 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1256 void pci_setup_bridge(struct pci_bus *bus);
1257 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1258 unsigned long type);
1259 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1261 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1262 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1264 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1265 unsigned int command_bits, u32 flags);
1267 #define PCI_IRQ_NOLEGACY (1 << 0) /* don't use legacy interrupts */
1268 #define PCI_IRQ_NOMSI (1 << 1) /* don't use MSI interrupts */
1269 #define PCI_IRQ_NOMSIX (1 << 2) /* don't use MSI-X interrupts */
1270 #define PCI_IRQ_NOAFFINITY (1 << 3) /* don't auto-assign affinity */
1272 /* kmem_cache style wrapper around pci_alloc_consistent() */
1274 #include <linux/pci-dma.h>
1275 #include <linux/dmapool.h>
1277 #define pci_pool dma_pool
1278 #define pci_pool_create(name, pdev, size, align, allocation) \
1279 dma_pool_create(name, &pdev->dev, size, align, allocation)
1280 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1281 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1282 #define pci_pool_zalloc(pool, flags, handle) \
1283 dma_pool_zalloc(pool, flags, handle)
1284 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1287 u32 vector; /* kernel uses to write allocated vector */
1288 u16 entry; /* driver uses to specify entry, OS writes */
1291 #ifdef CONFIG_PCI_MSI
1292 int pci_msi_vec_count(struct pci_dev *dev);
1293 void pci_msi_shutdown(struct pci_dev *dev);
1294 void pci_disable_msi(struct pci_dev *dev);
1295 int pci_msix_vec_count(struct pci_dev *dev);
1296 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1297 void pci_msix_shutdown(struct pci_dev *dev);
1298 void pci_disable_msix(struct pci_dev *dev);
1299 void pci_restore_msi_state(struct pci_dev *dev);
1300 int pci_msi_enabled(void);
1301 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1302 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1304 int rc = pci_enable_msi_range(dev, nvec, nvec);
1309 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1310 int minvec, int maxvec);
1311 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1312 struct msix_entry *entries, int nvec)
1314 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1319 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1320 unsigned int max_vecs, unsigned int flags);
1321 void pci_free_irq_vectors(struct pci_dev *dev);
1322 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1325 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1326 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1327 static inline void pci_disable_msi(struct pci_dev *dev) { }
1328 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1329 static inline int pci_enable_msix(struct pci_dev *dev,
1330 struct msix_entry *entries, int nvec)
1332 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1333 static inline void pci_disable_msix(struct pci_dev *dev) { }
1334 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1335 static inline int pci_msi_enabled(void) { return 0; }
1336 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1339 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1341 static inline int pci_enable_msix_range(struct pci_dev *dev,
1342 struct msix_entry *entries, int minvec, int maxvec)
1344 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1345 struct msix_entry *entries, int nvec)
1347 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1348 unsigned int min_vecs, unsigned int max_vecs,
1355 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1359 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1361 if (WARN_ON_ONCE(nr > 0))
1367 #ifdef CONFIG_PCIEPORTBUS
1368 extern bool pcie_ports_disabled;
1369 extern bool pcie_ports_auto;
1371 #define pcie_ports_disabled true
1372 #define pcie_ports_auto false
1375 #ifdef CONFIG_PCIEASPM
1376 bool pcie_aspm_support_enabled(void);
1378 static inline bool pcie_aspm_support_enabled(void) { return false; }
1381 #ifdef CONFIG_PCIEAER
1382 void pci_no_aer(void);
1383 bool pci_aer_available(void);
1384 int pci_aer_init(struct pci_dev *dev);
1386 static inline void pci_no_aer(void) { }
1387 static inline bool pci_aer_available(void) { return false; }
1388 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1391 #ifdef CONFIG_PCIE_ECRC
1392 void pcie_set_ecrc_checking(struct pci_dev *dev);
1393 void pcie_ecrc_get_policy(char *str);
1395 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1396 static inline void pcie_ecrc_get_policy(char *str) { }
1399 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1401 #ifdef CONFIG_HT_IRQ
1402 /* The functions a driver should call */
1403 int ht_create_irq(struct pci_dev *dev, int idx);
1404 void ht_destroy_irq(unsigned int irq);
1405 #endif /* CONFIG_HT_IRQ */
1407 #ifdef CONFIG_PCI_ATS
1408 /* Address Translation Service */
1409 void pci_ats_init(struct pci_dev *dev);
1410 int pci_enable_ats(struct pci_dev *dev, int ps);
1411 void pci_disable_ats(struct pci_dev *dev);
1412 int pci_ats_queue_depth(struct pci_dev *dev);
1414 static inline void pci_ats_init(struct pci_dev *d) { }
1415 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1416 static inline void pci_disable_ats(struct pci_dev *d) { }
1417 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1420 #ifdef CONFIG_PCIE_PTM
1421 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1423 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1427 void pci_cfg_access_lock(struct pci_dev *dev);
1428 bool pci_cfg_access_trylock(struct pci_dev *dev);
1429 void pci_cfg_access_unlock(struct pci_dev *dev);
1432 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1433 * a PCI domain is defined to be a set of PCI buses which share
1434 * configuration space.
1436 #ifdef CONFIG_PCI_DOMAINS
1437 extern int pci_domains_supported;
1438 int pci_get_new_domain_nr(void);
1440 enum { pci_domains_supported = 0 };
1441 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1442 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1443 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1444 #endif /* CONFIG_PCI_DOMAINS */
1447 * Generic implementation for PCI domain support. If your
1448 * architecture does not need custom management of PCI
1449 * domains then this implementation will be used
1451 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1452 static inline int pci_domain_nr(struct pci_bus *bus)
1454 return bus->domain_nr;
1457 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1459 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1462 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1465 /* some architectures require additional setup to direct VGA traffic */
1466 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1467 unsigned int command_bits, u32 flags);
1468 void pci_register_set_vga_state(arch_set_vga_state_t func);
1471 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1473 return pci_request_selected_regions(pdev,
1474 pci_select_bars(pdev, IORESOURCE_IO), name);
1478 pci_release_io_regions(struct pci_dev *pdev)
1480 return pci_release_selected_regions(pdev,
1481 pci_select_bars(pdev, IORESOURCE_IO));
1485 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1487 return pci_request_selected_regions(pdev,
1488 pci_select_bars(pdev, IORESOURCE_MEM), name);
1492 pci_release_mem_regions(struct pci_dev *pdev)
1494 return pci_release_selected_regions(pdev,
1495 pci_select_bars(pdev, IORESOURCE_MEM));
1498 #else /* CONFIG_PCI is not enabled */
1500 static inline void pci_set_flags(int flags) { }
1501 static inline void pci_add_flags(int flags) { }
1502 static inline void pci_clear_flags(int flags) { }
1503 static inline int pci_has_flag(int flag) { return 0; }
1506 * If the system does not have PCI, clearly these return errors. Define
1507 * these as simple inline functions to avoid hair in drivers.
1510 #define _PCI_NOP(o, s, t) \
1511 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1513 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1515 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1516 _PCI_NOP(o, word, u16 x) \
1517 _PCI_NOP(o, dword, u32 x)
1518 _PCI_NOP_ALL(read, *)
1519 _PCI_NOP_ALL(write,)
1521 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1522 unsigned int device,
1523 struct pci_dev *from)
1526 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1527 unsigned int device,
1528 unsigned int ss_vendor,
1529 unsigned int ss_device,
1530 struct pci_dev *from)
1533 static inline struct pci_dev *pci_get_class(unsigned int class,
1534 struct pci_dev *from)
1537 #define pci_dev_present(ids) (0)
1538 #define no_pci_devices() (1)
1539 #define pci_dev_put(dev) do { } while (0)
1541 static inline void pci_set_master(struct pci_dev *dev) { }
1542 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1543 static inline void pci_disable_device(struct pci_dev *dev) { }
1544 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1546 static inline int __pci_register_driver(struct pci_driver *drv,
1547 struct module *owner)
1549 static inline int pci_register_driver(struct pci_driver *drv)
1551 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1552 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1554 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1557 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1560 /* Power management related routines */
1561 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1562 static inline void pci_restore_state(struct pci_dev *dev) { }
1563 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1565 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1567 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1570 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1574 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1576 static inline void pci_release_regions(struct pci_dev *dev) { }
1578 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1580 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1581 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1583 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1585 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1587 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1590 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1594 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1595 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1596 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1598 #define dev_is_pci(d) (false)
1599 #define dev_is_pf(d) (false)
1600 #define dev_num_vf(d) (0)
1601 #endif /* CONFIG_PCI */
1603 /* Include architecture-dependent settings and functions */
1605 #include <asm/pci.h>
1607 #ifndef pci_root_bus_fwnode
1608 #define pci_root_bus_fwnode(bus) NULL
1611 /* these helpers provide future and backwards compatibility
1612 * for accessing popular PCI BAR info */
1613 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1614 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1615 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1616 #define pci_resource_len(dev,bar) \
1617 ((pci_resource_start((dev), (bar)) == 0 && \
1618 pci_resource_end((dev), (bar)) == \
1619 pci_resource_start((dev), (bar))) ? 0 : \
1621 (pci_resource_end((dev), (bar)) - \
1622 pci_resource_start((dev), (bar)) + 1))
1624 /* Similar to the helpers above, these manipulate per-pci_dev
1625 * driver-specific data. They are really just a wrapper around
1626 * the generic device structure functions of these calls.
1628 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1630 return dev_get_drvdata(&pdev->dev);
1633 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1635 dev_set_drvdata(&pdev->dev, data);
1638 /* If you want to know what to call your pci_dev, ask this function.
1639 * Again, it's a wrapper around the generic device.
1641 static inline const char *pci_name(const struct pci_dev *pdev)
1643 return dev_name(&pdev->dev);
1647 /* Some archs don't want to expose struct resource to userland as-is
1648 * in sysfs and /proc
1650 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1651 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1652 const struct resource *rsrc,
1653 resource_size_t *start, resource_size_t *end);
1655 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1656 const struct resource *rsrc, resource_size_t *start,
1657 resource_size_t *end)
1659 *start = rsrc->start;
1662 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1666 * The world is not perfect and supplies us with broken PCI devices.
1667 * For at least a part of these bugs we need a work-around, so both
1668 * generic (drivers/pci/quirks.c) and per-architecture code can define
1669 * fixup hooks to be called for particular buggy devices.
1673 u16 vendor; /* You can use PCI_ANY_ID here of course */
1674 u16 device; /* You can use PCI_ANY_ID here of course */
1675 u32 class; /* You can use PCI_ANY_ID here too */
1676 unsigned int class_shift; /* should be 0, 8, 16 */
1677 void (*hook)(struct pci_dev *dev);
1680 enum pci_fixup_pass {
1681 pci_fixup_early, /* Before probing BARs */
1682 pci_fixup_header, /* After reading configuration header */
1683 pci_fixup_final, /* Final phase of device fixups */
1684 pci_fixup_enable, /* pci_enable_device() time */
1685 pci_fixup_resume, /* pci_device_resume() */
1686 pci_fixup_suspend, /* pci_device_suspend() */
1687 pci_fixup_resume_early, /* pci_device_resume_early() */
1688 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1691 /* Anonymous variables would be nice... */
1692 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1693 class_shift, hook) \
1694 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1695 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1696 = { vendor, device, class, class_shift, hook };
1698 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1699 class_shift, hook) \
1700 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1701 hook, vendor, device, class, class_shift, hook)
1702 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1703 class_shift, hook) \
1704 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1705 hook, vendor, device, class, class_shift, hook)
1706 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1707 class_shift, hook) \
1708 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1709 hook, vendor, device, class, class_shift, hook)
1710 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1711 class_shift, hook) \
1712 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1713 hook, vendor, device, class, class_shift, hook)
1714 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1715 class_shift, hook) \
1716 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1717 resume##hook, vendor, device, class, \
1719 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1720 class_shift, hook) \
1721 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1722 resume_early##hook, vendor, device, \
1723 class, class_shift, hook)
1724 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1725 class_shift, hook) \
1726 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1727 suspend##hook, vendor, device, class, \
1729 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1730 class_shift, hook) \
1731 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1732 suspend_late##hook, vendor, device, \
1733 class, class_shift, hook)
1735 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1736 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1737 hook, vendor, device, PCI_ANY_ID, 0, hook)
1738 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1739 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1740 hook, vendor, device, PCI_ANY_ID, 0, hook)
1741 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1742 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1743 hook, vendor, device, PCI_ANY_ID, 0, hook)
1744 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1745 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1746 hook, vendor, device, PCI_ANY_ID, 0, hook)
1747 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1748 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1749 resume##hook, vendor, device, \
1750 PCI_ANY_ID, 0, hook)
1751 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1752 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1753 resume_early##hook, vendor, device, \
1754 PCI_ANY_ID, 0, hook)
1755 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1756 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1757 suspend##hook, vendor, device, \
1758 PCI_ANY_ID, 0, hook)
1759 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1760 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1761 suspend_late##hook, vendor, device, \
1762 PCI_ANY_ID, 0, hook)
1764 #ifdef CONFIG_PCI_QUIRKS
1765 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1766 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1767 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1769 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1770 struct pci_dev *dev) { }
1771 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1776 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1782 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1783 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1784 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1785 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1786 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1788 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1790 extern int pci_pci_problems;
1791 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1792 #define PCIPCI_TRITON 2
1793 #define PCIPCI_NATOMA 4
1794 #define PCIPCI_VIAETBF 8
1795 #define PCIPCI_VSFX 16
1796 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1797 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1799 extern unsigned long pci_cardbus_io_size;
1800 extern unsigned long pci_cardbus_mem_size;
1801 extern u8 pci_dfl_cache_line_size;
1802 extern u8 pci_cache_line_size;
1804 extern unsigned long pci_hotplug_io_size;
1805 extern unsigned long pci_hotplug_mem_size;
1806 extern unsigned long pci_hotplug_bus_size;
1808 /* Architecture-specific versions may override these (weak) */
1809 void pcibios_disable_device(struct pci_dev *dev);
1810 void pcibios_set_master(struct pci_dev *dev);
1811 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1812 enum pcie_reset_state state);
1813 int pcibios_add_device(struct pci_dev *dev);
1814 void pcibios_release_device(struct pci_dev *dev);
1815 void pcibios_penalize_isa_irq(int irq, int active);
1816 int pcibios_alloc_irq(struct pci_dev *dev);
1817 void pcibios_free_irq(struct pci_dev *dev);
1819 #ifdef CONFIG_HIBERNATE_CALLBACKS
1820 extern struct dev_pm_ops pcibios_pm_ops;
1823 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1824 void __init pci_mmcfg_early_init(void);
1825 void __init pci_mmcfg_late_init(void);
1827 static inline void pci_mmcfg_early_init(void) { }
1828 static inline void pci_mmcfg_late_init(void) { }
1831 int pci_ext_cfg_avail(void);
1833 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1834 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1836 #ifdef CONFIG_PCI_IOV
1837 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1838 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1840 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1841 void pci_disable_sriov(struct pci_dev *dev);
1842 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1843 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1844 int pci_num_vf(struct pci_dev *dev);
1845 int pci_vfs_assigned(struct pci_dev *dev);
1846 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1847 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1848 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1850 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1854 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1858 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1860 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1864 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1865 int id, int reset) { }
1866 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1867 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1868 static inline int pci_vfs_assigned(struct pci_dev *dev)
1870 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1872 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1874 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1878 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1879 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1880 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1884 * pci_pcie_cap - get the saved PCIe capability offset
1887 * PCIe capability offset is calculated at PCI device initialization
1888 * time and saved in the data structure. This function returns saved
1889 * PCIe capability offset. Using this instead of pci_find_capability()
1890 * reduces unnecessary search in the PCI configuration space. If you
1891 * need to calculate PCIe capability offset from raw device for some
1892 * reasons, please use pci_find_capability() instead.
1894 static inline int pci_pcie_cap(struct pci_dev *dev)
1896 return dev->pcie_cap;
1900 * pci_is_pcie - check if the PCI device is PCI Express capable
1903 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1905 static inline bool pci_is_pcie(struct pci_dev *dev)
1907 return pci_pcie_cap(dev);
1911 * pcie_caps_reg - get the PCIe Capabilities Register
1914 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1916 return dev->pcie_flags_reg;
1920 * pci_pcie_type - get the PCIe device/port type
1923 static inline int pci_pcie_type(const struct pci_dev *dev)
1925 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1928 void pci_request_acs(void);
1929 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1930 bool pci_acs_path_enabled(struct pci_dev *start,
1931 struct pci_dev *end, u16 acs_flags);
1933 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1934 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1936 /* Large Resource Data Type Tag Item Names */
1937 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1938 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1939 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1941 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1942 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1943 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1945 /* Small Resource Data Type Tag Item Names */
1946 #define PCI_VPD_STIN_END 0x0f /* End */
1948 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1950 #define PCI_VPD_SRDT_TIN_MASK 0x78
1951 #define PCI_VPD_SRDT_LEN_MASK 0x07
1952 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1954 #define PCI_VPD_LRDT_TAG_SIZE 3
1955 #define PCI_VPD_SRDT_TAG_SIZE 1
1957 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1959 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1960 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1961 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1962 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1965 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1966 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1968 * Returns the extracted Large Resource Data Type length.
1970 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1972 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1976 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1977 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1979 * Returns the extracted Large Resource Data Type Tag item.
1981 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1983 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1987 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1988 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1990 * Returns the extracted Small Resource Data Type length.
1992 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1994 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1998 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
1999 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2001 * Returns the extracted Small Resource Data Type Tag Item.
2003 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2005 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2009 * pci_vpd_info_field_size - Extracts the information field length
2010 * @lrdt: Pointer to the beginning of an information field header
2012 * Returns the extracted information field length.
2014 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2016 return info_field[2];
2020 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2021 * @buf: Pointer to buffered vpd data
2022 * @off: The offset into the buffer at which to begin the search
2023 * @len: The length of the vpd buffer
2024 * @rdt: The Resource Data Type to search for
2026 * Returns the index where the Resource Data Type was found or
2027 * -ENOENT otherwise.
2029 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2032 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2033 * @buf: Pointer to buffered vpd data
2034 * @off: The offset into the buffer at which to begin the search
2035 * @len: The length of the buffer area, relative to off, in which to search
2036 * @kw: The keyword to search for
2038 * Returns the index where the information field keyword was found or
2039 * -ENOENT otherwise.
2041 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2042 unsigned int len, const char *kw);
2044 /* PCI <-> OF binding helpers */
2048 void pci_set_of_node(struct pci_dev *dev);
2049 void pci_release_of_node(struct pci_dev *dev);
2050 void pci_set_bus_of_node(struct pci_bus *bus);
2051 void pci_release_bus_of_node(struct pci_bus *bus);
2052 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2054 /* Arch may override this (weak) */
2055 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2057 static inline struct device_node *
2058 pci_device_to_OF_node(const struct pci_dev *pdev)
2060 return pdev ? pdev->dev.of_node : NULL;
2063 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2065 return bus ? bus->dev.of_node : NULL;
2068 #else /* CONFIG_OF */
2069 static inline void pci_set_of_node(struct pci_dev *dev) { }
2070 static inline void pci_release_of_node(struct pci_dev *dev) { }
2071 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2072 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2073 static inline struct device_node *
2074 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2075 static inline struct irq_domain *
2076 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2077 #endif /* CONFIG_OF */
2080 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2083 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2085 static inline struct irq_domain *
2086 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2090 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2092 return pdev->dev.archdata.edev;
2096 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2097 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2098 int pci_for_each_dma_alias(struct pci_dev *pdev,
2099 int (*fn)(struct pci_dev *pdev,
2100 u16 alias, void *data), void *data);
2102 /* helper functions for operation of device flag */
2103 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2105 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2107 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2109 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2111 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2113 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2117 * pci_ari_enabled - query ARI forwarding status
2120 * Returns true if ARI forwarding is enabled.
2122 static inline bool pci_ari_enabled(struct pci_bus *bus)
2124 return bus->self && bus->self->ari_enabled;
2127 /* provide the legacy pci_dma_* API */
2128 #include <linux/pci-dma-compat.h>
2130 #endif /* LINUX_PCI_H */