1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
143 static inline const char *pci_power_name(pci_power_t state)
145 return pci_power_names[1 + (__force int) state];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t;
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t;
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
184 typedef unsigned short __bitwise pci_dev_flags_t;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
210 enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
215 typedef unsigned short __bitwise pci_bus_flags_t;
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
224 enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236 /* Based on the PCI Hotplug Spec, but some values are made up by us */
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
267 struct pci_cap_saved_data {
274 struct pci_cap_saved_state {
275 struct hlist_node next;
276 struct pci_cap_saved_data cap;
280 struct pcie_link_state;
286 /* The pci_dev structure describes PCI devices */
288 struct list_head bus_list; /* Node in per-bus list */
289 struct pci_bus *bus; /* Bus this device is on */
290 struct pci_bus *subordinate; /* Bus this device bridges to */
292 void *sysdata; /* Hook for sys-specific extension */
293 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
294 struct pci_slot *slot; /* Physical slot this device is in */
296 unsigned int devfn; /* Encoded device & function index */
297 unsigned short vendor;
298 unsigned short device;
299 unsigned short subsystem_vendor;
300 unsigned short subsystem_device;
301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
302 u8 revision; /* PCI revision, low byte of class word */
303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
304 #ifdef CONFIG_PCIEAER
305 u16 aer_cap; /* AER capability offset */
306 struct aer_stats *aer_stats; /* AER stats for this device */
308 u8 pcie_cap; /* PCIe capability offset */
309 u8 msi_cap; /* MSI capability offset */
310 u8 msix_cap; /* MSI-X capability offset */
311 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
312 u8 rom_base_reg; /* Config register controlling ROM */
313 u8 pin; /* Interrupt pin this device uses */
314 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
315 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
317 struct pci_driver *driver; /* Driver bound to this device */
318 u64 dma_mask; /* Mask of the bits of bus address this
319 device implements. Normally this is
320 0xffffffff. You only need to change
321 this if your device has broken DMA
322 or supports 64-bit transfers. */
324 struct device_dma_parameters dma_parms;
326 pci_power_t current_state; /* Current operating state. In ACPI,
327 this is D0-D3, D0 being fully
328 functional, and D3 being off. */
329 unsigned int imm_ready:1; /* Supports Immediate Readiness */
330 u8 pm_cap; /* PM capability offset */
331 unsigned int pme_support:5; /* Bitmask of states from which PME#
333 unsigned int pme_poll:1; /* Poll device's PME status bit */
334 unsigned int d1_support:1; /* Low power state D1 is supported */
335 unsigned int d2_support:1; /* Low power state D2 is supported */
336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
337 unsigned int no_d3cold:1; /* D3cold is forbidden */
338 unsigned int bridge_d3:1; /* Allow D3 for bridge */
339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
341 decoding during BAR sizing */
342 unsigned int wakeup_prepared:1;
343 unsigned int runtime_d3cold:1; /* Whether go through runtime
344 D3cold, not set for devices
345 powered on/off by the
346 corresponding bridge */
347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
349 controlled exclusively by
351 unsigned int d3_delay; /* D3->D0 transition time in ms */
352 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
354 #ifdef CONFIG_PCIEASPM
355 struct pcie_link_state *link_state; /* ASPM link state */
356 unsigned int ltr_path:1; /* Latency Tolerance Reporting
357 supported from root to here */
359 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
361 pci_channel_state_t error_state; /* Current connectivity state */
362 struct device dev; /* Generic device interface */
364 int cfg_size; /* Size of config space */
367 * Instead of touching interrupt line and base address registers
368 * directly, use the values stored here. They might be different!
371 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
373 bool match_driver; /* Skip attaching driver */
375 unsigned int transparent:1; /* Subtractive decode bridge */
376 unsigned int multifunction:1; /* Multi-function device */
378 unsigned int is_busmaster:1; /* Is busmaster */
379 unsigned int no_msi:1; /* May not use MSI */
380 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
381 unsigned int block_cfg_access:1; /* Config space access blocked */
382 unsigned int broken_parity_status:1; /* Generates false positive parity */
383 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
384 unsigned int msi_enabled:1;
385 unsigned int msix_enabled:1;
386 unsigned int ari_enabled:1; /* ARI forwarding */
387 unsigned int ats_enabled:1; /* Address Translation Svc */
388 unsigned int pasid_enabled:1; /* Process Address Space ID */
389 unsigned int pri_enabled:1; /* Page Request Interface */
390 unsigned int is_managed:1;
391 unsigned int needs_freset:1; /* Requires fundamental reset */
392 unsigned int state_saved:1;
393 unsigned int is_physfn:1;
394 unsigned int is_virtfn:1;
395 unsigned int reset_fn:1;
396 unsigned int is_hotplug_bridge:1;
397 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
398 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
399 unsigned int __aer_firmware_first_valid:1;
400 unsigned int __aer_firmware_first:1;
401 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
402 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
403 unsigned int irq_managed:1;
404 unsigned int has_secondary_link:1;
405 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
406 unsigned int is_probed:1; /* Device probing in progress */
407 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
408 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
409 pci_dev_flags_t dev_flags;
410 atomic_t enable_cnt; /* pci_enable_device has been called */
412 u32 saved_config_space[16]; /* Config space saved at suspend time */
413 struct hlist_head saved_cap_space;
414 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
415 int rom_attr_enabled; /* Display of ROM attribute enabled? */
416 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
417 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
419 #ifdef CONFIG_HOTPLUG_PCI_PCIE
420 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
422 #ifdef CONFIG_PCIE_PTM
423 unsigned int ptm_root:1;
424 unsigned int ptm_enabled:1;
427 #ifdef CONFIG_PCI_MSI
428 const struct attribute_group **msi_irq_groups;
431 #ifdef CONFIG_PCI_ATS
433 struct pci_sriov *sriov; /* PF: SR-IOV info */
434 struct pci_dev *physfn; /* VF: related PF */
436 u16 ats_cap; /* ATS Capability offset */
437 u8 ats_stu; /* ATS Smallest Translation Unit */
438 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
440 #ifdef CONFIG_PCI_PRI
441 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
443 #ifdef CONFIG_PCI_PASID
446 #ifdef CONFIG_PCI_P2PDMA
447 struct pci_p2pdma *p2pdma;
449 phys_addr_t rom; /* Physical address if not from BAR */
450 size_t romlen; /* Length if not from BAR */
451 char *driver_override; /* Driver name to force a match */
453 unsigned long priv_flags; /* Private flags for the PCI driver */
456 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
458 #ifdef CONFIG_PCI_IOV
465 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
467 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
468 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
470 static inline int pci_channel_offline(struct pci_dev *pdev)
472 return (pdev->error_state != pci_channel_io_normal);
475 struct pci_host_bridge {
477 struct pci_bus *bus; /* Root bus */
481 struct list_head windows; /* resource_entry */
482 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
483 int (*map_irq)(const struct pci_dev *, u8, u8);
484 void (*release_fn)(struct pci_host_bridge *);
486 struct msi_controller *msi;
487 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
488 unsigned int no_ext_tags:1; /* No Extended Tags */
489 unsigned int native_aer:1; /* OS may use PCIe AER */
490 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
491 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
492 unsigned int native_pme:1; /* OS may use PCIe PME */
493 unsigned int native_ltr:1; /* OS may use PCIe LTR */
494 /* Resource alignment requirements */
495 resource_size_t (*align_resource)(struct pci_dev *dev,
496 const struct resource *res,
497 resource_size_t start,
498 resource_size_t size,
499 resource_size_t align);
500 unsigned long private[0] ____cacheline_aligned;
503 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
505 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
507 return (void *)bridge->private;
510 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
512 return container_of(priv, struct pci_host_bridge, private);
515 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
516 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
518 void pci_free_host_bridge(struct pci_host_bridge *bridge);
519 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
521 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
522 void (*release_fn)(struct pci_host_bridge *),
525 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
528 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
529 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
530 * buses below host bridges or subtractive decode bridges) go in the list.
531 * Use pci_bus_for_each_resource() to iterate through all the resources.
535 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
536 * and there's no way to program the bridge with the details of the window.
537 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
538 * decode bit set, because they are explicit and can be programmed with _SRS.
540 #define PCI_SUBTRACTIVE_DECODE 0x1
542 struct pci_bus_resource {
543 struct list_head list;
544 struct resource *res;
548 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
551 struct list_head node; /* Node in list of buses */
552 struct pci_bus *parent; /* Parent bus this bridge is on */
553 struct list_head children; /* List of child buses */
554 struct list_head devices; /* List of devices on this bus */
555 struct pci_dev *self; /* Bridge device as seen by parent */
556 struct list_head slots; /* List of slots on this bus;
557 protected by pci_slot_mutex */
558 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
559 struct list_head resources; /* Address space routed to this bus */
560 struct resource busn_res; /* Bus numbers routed to this bus */
562 struct pci_ops *ops; /* Configuration access functions */
563 struct msi_controller *msi; /* MSI controller */
564 void *sysdata; /* Hook for sys-specific extension */
565 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
567 unsigned char number; /* Bus number */
568 unsigned char primary; /* Number of primary bridge */
569 unsigned char max_bus_speed; /* enum pci_bus_speed */
570 unsigned char cur_bus_speed; /* enum pci_bus_speed */
571 #ifdef CONFIG_PCI_DOMAINS_GENERIC
577 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
578 pci_bus_flags_t bus_flags; /* Inherited by child buses */
579 struct device *bridge;
581 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
582 struct bin_attribute *legacy_mem; /* Legacy mem */
583 unsigned int is_added:1;
586 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
589 * Returns true if the PCI bus is root (behind host-PCI bridge),
592 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
593 * This is incorrect because "virtual" buses added for SR-IOV (via
594 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
596 static inline bool pci_is_root_bus(struct pci_bus *pbus)
598 return !(pbus->parent);
602 * pci_is_bridge - check if the PCI device is a bridge
605 * Return true if the PCI device is bridge whether it has subordinate
608 static inline bool pci_is_bridge(struct pci_dev *dev)
610 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
611 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
614 #define for_each_pci_bridge(dev, bus) \
615 list_for_each_entry(dev, &bus->devices, bus_list) \
616 if (!pci_is_bridge(dev)) {} else
618 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
620 dev = pci_physfn(dev);
621 if (pci_is_root_bus(dev->bus))
624 return dev->bus->self;
627 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
628 void pci_put_host_bridge_device(struct device *dev);
630 #ifdef CONFIG_PCI_MSI
631 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
633 return pci_dev->msi_enabled || pci_dev->msix_enabled;
636 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
639 /* Error values that may be returned by PCI functions */
640 #define PCIBIOS_SUCCESSFUL 0x00
641 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
642 #define PCIBIOS_BAD_VENDOR_ID 0x83
643 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
644 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
645 #define PCIBIOS_SET_FAILED 0x88
646 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
648 /* Translate above to generic errno for passing back through non-PCI code */
649 static inline int pcibios_err_to_errno(int err)
651 if (err <= PCIBIOS_SUCCESSFUL)
652 return err; /* Assume already errno */
655 case PCIBIOS_FUNC_NOT_SUPPORTED:
657 case PCIBIOS_BAD_VENDOR_ID:
659 case PCIBIOS_DEVICE_NOT_FOUND:
661 case PCIBIOS_BAD_REGISTER_NUMBER:
663 case PCIBIOS_SET_FAILED:
665 case PCIBIOS_BUFFER_TOO_SMALL:
672 /* Low-level architecture-dependent routines */
675 int (*add_bus)(struct pci_bus *bus);
676 void (*remove_bus)(struct pci_bus *bus);
677 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
678 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
679 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
683 * ACPI needs to be able to access PCI config space before we've done a
684 * PCI bus scan and created pci_bus structures.
686 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
687 int reg, int len, u32 *val);
688 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
689 int reg, int len, u32 val);
691 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
692 typedef u64 pci_bus_addr_t;
694 typedef u32 pci_bus_addr_t;
697 struct pci_bus_region {
698 pci_bus_addr_t start;
703 spinlock_t lock; /* Protects list, index */
704 struct list_head list; /* For IDs added at runtime */
709 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
710 * a set of callbacks in struct pci_error_handlers, that device driver
711 * will be notified of PCI bus errors, and will be driven to recovery
712 * when an error occurs.
715 typedef unsigned int __bitwise pci_ers_result_t;
717 enum pci_ers_result {
718 /* No result/none/not supported in device driver */
719 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
721 /* Device driver can recover without slot reset */
722 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
724 /* Device driver wants slot to be reset */
725 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
727 /* Device has completely failed, is unrecoverable */
728 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
730 /* Device driver is fully recovered and operational */
731 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
733 /* No AER capabilities registered for the driver */
734 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
737 /* PCI bus error event callbacks */
738 struct pci_error_handlers {
739 /* PCI bus error detected on this device */
740 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
741 enum pci_channel_state error);
743 /* MMIO has been re-enabled, but not DMA */
744 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
746 /* PCI slot has been reset */
747 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
749 /* PCI function reset prepare or completed */
750 void (*reset_prepare)(struct pci_dev *dev);
751 void (*reset_done)(struct pci_dev *dev);
753 /* Device driver may resume normal operations */
754 void (*resume)(struct pci_dev *dev);
760 struct list_head node;
762 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
763 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
764 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
765 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
766 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
767 int (*resume_early)(struct pci_dev *dev);
768 int (*resume)(struct pci_dev *dev); /* Device woken up */
769 void (*shutdown)(struct pci_dev *dev);
770 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
771 const struct pci_error_handlers *err_handler;
772 const struct attribute_group **groups;
773 struct device_driver driver;
774 struct pci_dynids dynids;
777 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
780 * PCI_DEVICE - macro used to describe a specific PCI device
781 * @vend: the 16 bit PCI Vendor ID
782 * @dev: the 16 bit PCI Device ID
784 * This macro is used to create a struct pci_device_id that matches a
785 * specific device. The subvendor and subdevice fields will be set to
788 #define PCI_DEVICE(vend,dev) \
789 .vendor = (vend), .device = (dev), \
790 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
793 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
794 * @vend: the 16 bit PCI Vendor ID
795 * @dev: the 16 bit PCI Device ID
796 * @subvend: the 16 bit PCI Subvendor ID
797 * @subdev: the 16 bit PCI Subdevice ID
799 * This macro is used to create a struct pci_device_id that matches a
800 * specific device with subsystem information.
802 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
803 .vendor = (vend), .device = (dev), \
804 .subvendor = (subvend), .subdevice = (subdev)
807 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
808 * @dev_class: the class, subclass, prog-if triple for this device
809 * @dev_class_mask: the class mask for this device
811 * This macro is used to create a struct pci_device_id that matches a
812 * specific PCI class. The vendor, device, subvendor, and subdevice
813 * fields will be set to PCI_ANY_ID.
815 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
816 .class = (dev_class), .class_mask = (dev_class_mask), \
817 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
818 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
821 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
822 * @vend: the vendor name
823 * @dev: the 16 bit PCI Device ID
825 * This macro is used to create a struct pci_device_id that matches a
826 * specific PCI device. The subvendor, and subdevice fields will be set
827 * to PCI_ANY_ID. The macro allows the next field to follow as the device
830 #define PCI_VDEVICE(vend, dev) \
831 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
832 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
835 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
836 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
837 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
838 * @data: the driver data to be filled
840 * This macro is used to create a struct pci_device_id that matches a
841 * specific PCI device. The subvendor, and subdevice fields will be set
844 #define PCI_DEVICE_DATA(vend, dev, data) \
845 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
846 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
847 .driver_data = (kernel_ulong_t)(data)
850 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
851 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
852 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
853 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
854 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
855 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
856 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
859 /* These external functions are only available when PCI support is enabled */
862 extern unsigned int pci_flags;
864 static inline void pci_set_flags(int flags) { pci_flags = flags; }
865 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
866 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
867 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
869 void pcie_bus_configure_settings(struct pci_bus *bus);
871 enum pcie_bus_config_types {
872 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
873 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
874 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
875 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
876 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
879 extern enum pcie_bus_config_types pcie_bus_config;
881 extern struct bus_type pci_bus_type;
883 /* Do NOT directly access these two variables, unless you are arch-specific PCI
884 * code, or PCI core code. */
885 extern struct list_head pci_root_buses; /* List of all known PCI buses */
886 /* Some device drivers need know if PCI is initiated */
887 int no_pci_devices(void);
889 void pcibios_resource_survey_bus(struct pci_bus *bus);
890 void pcibios_bus_add_device(struct pci_dev *pdev);
891 void pcibios_add_bus(struct pci_bus *bus);
892 void pcibios_remove_bus(struct pci_bus *bus);
893 void pcibios_fixup_bus(struct pci_bus *);
894 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
895 /* Architecture-specific versions may override this (weak) */
896 char *pcibios_setup(char *str);
898 /* Used only when drivers/pci/setup.c is used */
899 resource_size_t pcibios_align_resource(void *, const struct resource *,
903 /* Weak but can be overriden by arch */
904 void pci_fixup_cardbus(struct pci_bus *);
906 /* Generic PCI functions used internally */
908 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
909 struct resource *res);
910 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
911 struct pci_bus_region *region);
912 void pcibios_scan_specific_bus(int busn);
913 struct pci_bus *pci_find_bus(int domain, int busnr);
914 void pci_bus_add_devices(const struct pci_bus *bus);
915 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
916 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
917 struct pci_ops *ops, void *sysdata,
918 struct list_head *resources);
919 int pci_host_probe(struct pci_host_bridge *bridge);
920 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
921 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
922 void pci_bus_release_busn_res(struct pci_bus *b);
923 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
924 struct pci_ops *ops, void *sysdata,
925 struct list_head *resources);
926 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
927 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
929 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
930 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
932 struct hotplug_slot *hotplug);
933 void pci_destroy_slot(struct pci_slot *slot);
935 void pci_dev_assign_slot(struct pci_dev *dev);
937 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
939 int pci_scan_slot(struct pci_bus *bus, int devfn);
940 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
941 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
942 unsigned int pci_scan_child_bus(struct pci_bus *bus);
943 void pci_bus_add_device(struct pci_dev *dev);
944 void pci_read_bridge_bases(struct pci_bus *child);
945 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
946 struct resource *res);
947 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
948 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
949 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
950 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
951 struct pci_dev *pci_dev_get(struct pci_dev *dev);
952 void pci_dev_put(struct pci_dev *dev);
953 void pci_remove_bus(struct pci_bus *b);
954 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
955 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
956 void pci_stop_root_bus(struct pci_bus *bus);
957 void pci_remove_root_bus(struct pci_bus *bus);
958 void pci_setup_cardbus(struct pci_bus *bus);
959 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
960 void pci_sort_breadthfirst(void);
961 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
962 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
964 /* Generic PCI functions exported to card drivers */
966 enum pci_lost_interrupt_reason {
967 PCI_LOST_IRQ_NO_INFORMATION = 0,
968 PCI_LOST_IRQ_DISABLE_MSI,
969 PCI_LOST_IRQ_DISABLE_MSIX,
970 PCI_LOST_IRQ_DISABLE_ACPI,
972 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
973 int pci_find_capability(struct pci_dev *dev, int cap);
974 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
975 int pci_find_ext_capability(struct pci_dev *dev, int cap);
976 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
977 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
978 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
979 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
981 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
982 struct pci_dev *from);
983 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
984 unsigned int ss_vendor, unsigned int ss_device,
985 struct pci_dev *from);
986 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
987 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
989 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
990 int pci_dev_present(const struct pci_device_id *ids);
992 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
994 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
995 int where, u16 *val);
996 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
997 int where, u32 *val);
998 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1000 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1001 int where, u16 val);
1002 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1003 int where, u32 val);
1005 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1006 int where, int size, u32 *val);
1007 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1008 int where, int size, u32 val);
1009 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1010 int where, int size, u32 *val);
1011 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1012 int where, int size, u32 val);
1014 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1016 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1017 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1018 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1019 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1020 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1021 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1023 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1024 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1025 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1026 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1027 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1028 u16 clear, u16 set);
1029 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1030 u32 clear, u32 set);
1032 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1035 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1038 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1041 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1044 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1047 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1050 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1053 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1056 /* User-space driven config access */
1057 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1058 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1059 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1060 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1061 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1062 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1064 int __must_check pci_enable_device(struct pci_dev *dev);
1065 int __must_check pci_enable_device_io(struct pci_dev *dev);
1066 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1067 int __must_check pci_reenable_device(struct pci_dev *);
1068 int __must_check pcim_enable_device(struct pci_dev *pdev);
1069 void pcim_pin_device(struct pci_dev *pdev);
1071 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1074 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1075 * writable and no quirk has marked the feature broken.
1077 return !pdev->broken_intx_masking;
1080 static inline int pci_is_enabled(struct pci_dev *pdev)
1082 return (atomic_read(&pdev->enable_cnt) > 0);
1085 static inline int pci_is_managed(struct pci_dev *pdev)
1087 return pdev->is_managed;
1090 void pci_disable_device(struct pci_dev *dev);
1092 extern unsigned int pcibios_max_latency;
1093 void pci_set_master(struct pci_dev *dev);
1094 void pci_clear_master(struct pci_dev *dev);
1096 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1097 int pci_set_cacheline_size(struct pci_dev *dev);
1098 #define HAVE_PCI_SET_MWI
1099 int __must_check pci_set_mwi(struct pci_dev *dev);
1100 int __must_check pcim_set_mwi(struct pci_dev *dev);
1101 int pci_try_set_mwi(struct pci_dev *dev);
1102 void pci_clear_mwi(struct pci_dev *dev);
1103 void pci_intx(struct pci_dev *dev, int enable);
1104 bool pci_check_and_mask_intx(struct pci_dev *dev);
1105 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1106 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1107 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1108 int pcix_get_max_mmrbc(struct pci_dev *dev);
1109 int pcix_get_mmrbc(struct pci_dev *dev);
1110 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1111 int pcie_get_readrq(struct pci_dev *dev);
1112 int pcie_set_readrq(struct pci_dev *dev, int rq);
1113 int pcie_get_mps(struct pci_dev *dev);
1114 int pcie_set_mps(struct pci_dev *dev, int mps);
1115 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1116 enum pci_bus_speed *speed,
1117 enum pcie_link_width *width);
1118 void pcie_print_link_status(struct pci_dev *dev);
1119 bool pcie_has_flr(struct pci_dev *dev);
1120 int pcie_flr(struct pci_dev *dev);
1121 int __pci_reset_function_locked(struct pci_dev *dev);
1122 int pci_reset_function(struct pci_dev *dev);
1123 int pci_reset_function_locked(struct pci_dev *dev);
1124 int pci_try_reset_function(struct pci_dev *dev);
1125 int pci_probe_reset_slot(struct pci_slot *slot);
1126 int pci_probe_reset_bus(struct pci_bus *bus);
1127 int pci_reset_bus(struct pci_dev *dev);
1128 void pci_reset_secondary_bus(struct pci_dev *dev);
1129 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1130 void pci_update_resource(struct pci_dev *dev, int resno);
1131 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1132 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1133 void pci_release_resource(struct pci_dev *dev, int resno);
1134 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1135 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1136 bool pci_device_is_present(struct pci_dev *pdev);
1137 void pci_ignore_hotplug(struct pci_dev *dev);
1139 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1140 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1141 const char *fmt, ...);
1142 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1144 /* ROM control related routines */
1145 int pci_enable_rom(struct pci_dev *pdev);
1146 void pci_disable_rom(struct pci_dev *pdev);
1147 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1148 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1149 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1151 /* Power management related routines */
1152 int pci_save_state(struct pci_dev *dev);
1153 void pci_restore_state(struct pci_dev *dev);
1154 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1155 int pci_load_saved_state(struct pci_dev *dev,
1156 struct pci_saved_state *state);
1157 int pci_load_and_free_saved_state(struct pci_dev *dev,
1158 struct pci_saved_state **state);
1159 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1160 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1162 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1163 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1164 u16 cap, unsigned int size);
1165 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1166 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1167 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1168 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1169 void pci_pme_active(struct pci_dev *dev, bool enable);
1170 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1171 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1172 int pci_prepare_to_sleep(struct pci_dev *dev);
1173 int pci_back_from_sleep(struct pci_dev *dev);
1174 bool pci_dev_run_wake(struct pci_dev *dev);
1175 bool pci_check_pme_status(struct pci_dev *dev);
1176 void pci_pme_wakeup_bus(struct pci_bus *bus);
1177 void pci_d3cold_enable(struct pci_dev *dev);
1178 void pci_d3cold_disable(struct pci_dev *dev);
1179 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1180 void pci_wakeup_bus(struct pci_bus *bus);
1181 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1183 /* PCI Virtual Channel */
1184 int pci_save_vc_state(struct pci_dev *dev);
1185 void pci_restore_vc_state(struct pci_dev *dev);
1186 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1188 /* For use by arch with custom probe code */
1189 void set_pcie_port_type(struct pci_dev *pdev);
1190 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1192 /* Functions for PCI Hotplug drivers to use */
1193 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1194 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1195 unsigned int pci_rescan_bus(struct pci_bus *bus);
1196 void pci_lock_rescan_remove(void);
1197 void pci_unlock_rescan_remove(void);
1199 /* Vital Product Data routines */
1200 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1201 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1202 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1204 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1205 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1206 void pci_bus_assign_resources(const struct pci_bus *bus);
1207 void pci_bus_claim_resources(struct pci_bus *bus);
1208 void pci_bus_size_bridges(struct pci_bus *bus);
1209 int pci_claim_resource(struct pci_dev *, int);
1210 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1211 void pci_assign_unassigned_resources(void);
1212 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1213 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1214 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1215 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1216 void pdev_enable_device(struct pci_dev *);
1217 int pci_enable_resources(struct pci_dev *, int mask);
1218 void pci_assign_irq(struct pci_dev *dev);
1219 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1220 #define HAVE_PCI_REQ_REGIONS 2
1221 int __must_check pci_request_regions(struct pci_dev *, const char *);
1222 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1223 void pci_release_regions(struct pci_dev *);
1224 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1225 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1226 void pci_release_region(struct pci_dev *, int);
1227 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1228 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1229 void pci_release_selected_regions(struct pci_dev *, int);
1231 /* drivers/pci/bus.c */
1232 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1233 void pci_bus_put(struct pci_bus *bus);
1234 void pci_add_resource(struct list_head *resources, struct resource *res);
1235 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1236 resource_size_t offset);
1237 void pci_free_resource_list(struct list_head *resources);
1238 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1239 unsigned int flags);
1240 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1241 void pci_bus_remove_resources(struct pci_bus *bus);
1242 int devm_request_pci_bus_resources(struct device *dev,
1243 struct list_head *resources);
1245 /* Temporary until new and working PCI SBR API in place */
1246 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1248 #define pci_bus_for_each_resource(bus, res, i) \
1250 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1253 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1254 struct resource *res, resource_size_t size,
1255 resource_size_t align, resource_size_t min,
1256 unsigned long type_mask,
1257 resource_size_t (*alignf)(void *,
1258 const struct resource *,
1264 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1265 resource_size_t size);
1266 unsigned long pci_address_to_pio(phys_addr_t addr);
1267 phys_addr_t pci_pio_to_address(unsigned long pio);
1268 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1269 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1270 phys_addr_t phys_addr);
1271 void pci_unmap_iospace(struct resource *res);
1272 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1273 resource_size_t offset,
1274 resource_size_t size);
1275 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1276 struct resource *res);
1278 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1280 struct pci_bus_region region;
1282 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1283 return region.start;
1286 /* Proper probing supporting hot-pluggable devices */
1287 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1288 const char *mod_name);
1290 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1291 #define pci_register_driver(driver) \
1292 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1294 void pci_unregister_driver(struct pci_driver *dev);
1297 * module_pci_driver() - Helper macro for registering a PCI driver
1298 * @__pci_driver: pci_driver struct
1300 * Helper macro for PCI drivers which do not do anything special in module
1301 * init/exit. This eliminates a lot of boilerplate. Each module may only
1302 * use this macro once, and calling it replaces module_init() and module_exit()
1304 #define module_pci_driver(__pci_driver) \
1305 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1308 * builtin_pci_driver() - Helper macro for registering a PCI driver
1309 * @__pci_driver: pci_driver struct
1311 * Helper macro for PCI drivers which do not do anything special in their
1312 * init code. This eliminates a lot of boilerplate. Each driver may only
1313 * use this macro once, and calling it replaces device_initcall(...)
1315 #define builtin_pci_driver(__pci_driver) \
1316 builtin_driver(__pci_driver, pci_register_driver)
1318 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1319 int pci_add_dynid(struct pci_driver *drv,
1320 unsigned int vendor, unsigned int device,
1321 unsigned int subvendor, unsigned int subdevice,
1322 unsigned int class, unsigned int class_mask,
1323 unsigned long driver_data);
1324 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1325 struct pci_dev *dev);
1326 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1329 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1331 int pci_cfg_space_size(struct pci_dev *dev);
1332 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1333 void pci_setup_bridge(struct pci_bus *bus);
1334 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1335 unsigned long type);
1337 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1338 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1340 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1341 unsigned int command_bits, u32 flags);
1343 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1344 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1345 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1346 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1347 #define PCI_IRQ_ALL_TYPES \
1348 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1350 /* kmem_cache style wrapper around pci_alloc_consistent() */
1352 #include <linux/dmapool.h>
1354 #define pci_pool dma_pool
1355 #define pci_pool_create(name, pdev, size, align, allocation) \
1356 dma_pool_create(name, &pdev->dev, size, align, allocation)
1357 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1358 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1359 #define pci_pool_zalloc(pool, flags, handle) \
1360 dma_pool_zalloc(pool, flags, handle)
1361 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1364 u32 vector; /* Kernel uses to write allocated vector */
1365 u16 entry; /* Driver uses to specify entry, OS writes */
1368 #ifdef CONFIG_PCI_MSI
1369 int pci_msi_vec_count(struct pci_dev *dev);
1370 void pci_disable_msi(struct pci_dev *dev);
1371 int pci_msix_vec_count(struct pci_dev *dev);
1372 void pci_disable_msix(struct pci_dev *dev);
1373 void pci_restore_msi_state(struct pci_dev *dev);
1374 int pci_msi_enabled(void);
1375 int pci_enable_msi(struct pci_dev *dev);
1376 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1377 int minvec, int maxvec);
1378 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1379 struct msix_entry *entries, int nvec)
1381 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1386 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1387 unsigned int max_vecs, unsigned int flags,
1388 const struct irq_affinity *affd);
1390 void pci_free_irq_vectors(struct pci_dev *dev);
1391 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1392 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1393 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1396 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1397 static inline void pci_disable_msi(struct pci_dev *dev) { }
1398 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1399 static inline void pci_disable_msix(struct pci_dev *dev) { }
1400 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1401 static inline int pci_msi_enabled(void) { return 0; }
1402 static inline int pci_enable_msi(struct pci_dev *dev)
1404 static inline int pci_enable_msix_range(struct pci_dev *dev,
1405 struct msix_entry *entries, int minvec, int maxvec)
1407 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1408 struct msix_entry *entries, int nvec)
1412 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1413 unsigned int max_vecs, unsigned int flags,
1414 const struct irq_affinity *aff_desc)
1416 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1421 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1425 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1427 if (WARN_ON_ONCE(nr > 0))
1431 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1434 return cpu_possible_mask;
1437 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1439 return first_online_node;
1444 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1445 unsigned int max_vecs, unsigned int flags)
1447 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1452 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1453 * @d: the INTx IRQ domain
1454 * @node: the DT node for the device whose interrupt we're translating
1455 * @intspec: the interrupt specifier data from the DT
1456 * @intsize: the number of entries in @intspec
1457 * @out_hwirq: pointer at which to write the hwirq number
1458 * @out_type: pointer at which to write the interrupt type
1460 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1461 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1462 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1463 * INTx value to obtain the hwirq number.
1465 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1467 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1468 struct device_node *node,
1470 unsigned int intsize,
1471 unsigned long *out_hwirq,
1472 unsigned int *out_type)
1474 const u32 intx = intspec[0];
1476 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1479 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1483 #ifdef CONFIG_PCIEPORTBUS
1484 extern bool pcie_ports_disabled;
1485 extern bool pcie_ports_native;
1487 #define pcie_ports_disabled true
1488 #define pcie_ports_native false
1491 #ifdef CONFIG_PCIEASPM
1492 bool pcie_aspm_support_enabled(void);
1494 static inline bool pcie_aspm_support_enabled(void) { return false; }
1497 #ifdef CONFIG_PCIEAER
1498 bool pci_aer_available(void);
1500 static inline bool pci_aer_available(void) { return false; }
1503 #ifdef CONFIG_PCIE_ECRC
1504 void pcie_set_ecrc_checking(struct pci_dev *dev);
1505 void pcie_ecrc_get_policy(char *str);
1507 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1508 static inline void pcie_ecrc_get_policy(char *str) { }
1511 bool pci_ats_disabled(void);
1513 #ifdef CONFIG_PCI_ATS
1514 /* Address Translation Service */
1515 void pci_ats_init(struct pci_dev *dev);
1516 int pci_enable_ats(struct pci_dev *dev, int ps);
1517 void pci_disable_ats(struct pci_dev *dev);
1518 int pci_ats_queue_depth(struct pci_dev *dev);
1520 static inline void pci_ats_init(struct pci_dev *d) { }
1521 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1522 static inline void pci_disable_ats(struct pci_dev *d) { }
1523 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1526 #ifdef CONFIG_PCIE_PTM
1527 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1529 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1533 void pci_cfg_access_lock(struct pci_dev *dev);
1534 bool pci_cfg_access_trylock(struct pci_dev *dev);
1535 void pci_cfg_access_unlock(struct pci_dev *dev);
1538 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1539 * a PCI domain is defined to be a set of PCI buses which share
1540 * configuration space.
1542 #ifdef CONFIG_PCI_DOMAINS
1543 extern int pci_domains_supported;
1545 enum { pci_domains_supported = 0 };
1546 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1547 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1548 #endif /* CONFIG_PCI_DOMAINS */
1551 * Generic implementation for PCI domain support. If your
1552 * architecture does not need custom management of PCI
1553 * domains then this implementation will be used
1555 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1556 static inline int pci_domain_nr(struct pci_bus *bus)
1558 return bus->domain_nr;
1561 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1563 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1566 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1569 /* Some architectures require additional setup to direct VGA traffic */
1570 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1571 unsigned int command_bits, u32 flags);
1572 void pci_register_set_vga_state(arch_set_vga_state_t func);
1575 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1577 return pci_request_selected_regions(pdev,
1578 pci_select_bars(pdev, IORESOURCE_IO), name);
1582 pci_release_io_regions(struct pci_dev *pdev)
1584 return pci_release_selected_regions(pdev,
1585 pci_select_bars(pdev, IORESOURCE_IO));
1589 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1591 return pci_request_selected_regions(pdev,
1592 pci_select_bars(pdev, IORESOURCE_MEM), name);
1596 pci_release_mem_regions(struct pci_dev *pdev)
1598 return pci_release_selected_regions(pdev,
1599 pci_select_bars(pdev, IORESOURCE_MEM));
1602 #else /* CONFIG_PCI is not enabled */
1604 static inline void pci_set_flags(int flags) { }
1605 static inline void pci_add_flags(int flags) { }
1606 static inline void pci_clear_flags(int flags) { }
1607 static inline int pci_has_flag(int flag) { return 0; }
1610 * If the system does not have PCI, clearly these return errors. Define
1611 * these as simple inline functions to avoid hair in drivers.
1613 #define _PCI_NOP(o, s, t) \
1614 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1616 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1618 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1619 _PCI_NOP(o, word, u16 x) \
1620 _PCI_NOP(o, dword, u32 x)
1621 _PCI_NOP_ALL(read, *)
1622 _PCI_NOP_ALL(write,)
1624 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1625 unsigned int device,
1626 struct pci_dev *from)
1629 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1630 unsigned int device,
1631 unsigned int ss_vendor,
1632 unsigned int ss_device,
1633 struct pci_dev *from)
1636 static inline struct pci_dev *pci_get_class(unsigned int class,
1637 struct pci_dev *from)
1640 #define pci_dev_present(ids) (0)
1641 #define no_pci_devices() (1)
1642 #define pci_dev_put(dev) do { } while (0)
1644 static inline void pci_set_master(struct pci_dev *dev) { }
1645 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1646 static inline void pci_disable_device(struct pci_dev *dev) { }
1647 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1649 static inline int __pci_register_driver(struct pci_driver *drv,
1650 struct module *owner)
1652 static inline int pci_register_driver(struct pci_driver *drv)
1654 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1655 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1657 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1660 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1663 /* Power management related routines */
1664 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1665 static inline void pci_restore_state(struct pci_dev *dev) { }
1666 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1668 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1670 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1673 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1677 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1678 struct resource *res)
1680 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1682 static inline void pci_release_regions(struct pci_dev *dev) { }
1684 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1686 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1687 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1689 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1691 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1693 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1696 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1697 unsigned int bus, unsigned int devfn)
1700 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1701 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1703 #define dev_is_pci(d) (false)
1704 #define dev_is_pf(d) (false)
1705 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1707 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1708 struct device_node *node,
1710 unsigned int intsize,
1711 unsigned long *out_hwirq,
1712 unsigned int *out_type)
1715 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1716 struct pci_dev *dev)
1718 #endif /* CONFIG_PCI */
1720 /* Include architecture-dependent settings and functions */
1722 #include <asm/pci.h>
1724 /* These two functions provide almost identical functionality. Depennding
1725 * on the architecture, one will be implemented as a wrapper around the
1726 * other (in drivers/pci/mmap.c).
1728 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1729 * is expected to be an offset within that region.
1731 * pci_mmap_page_range() is the legacy architecture-specific interface,
1732 * which accepts a "user visible" resource address converted by
1733 * pci_resource_to_user(), as used in the legacy mmap() interface in
1736 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1737 struct vm_area_struct *vma,
1738 enum pci_mmap_state mmap_state, int write_combine);
1739 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1740 struct vm_area_struct *vma,
1741 enum pci_mmap_state mmap_state, int write_combine);
1743 #ifndef arch_can_pci_mmap_wc
1744 #define arch_can_pci_mmap_wc() 0
1747 #ifndef arch_can_pci_mmap_io
1748 #define arch_can_pci_mmap_io() 0
1749 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1751 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1754 #ifndef pci_root_bus_fwnode
1755 #define pci_root_bus_fwnode(bus) NULL
1759 * These helpers provide future and backwards compatibility
1760 * for accessing popular PCI BAR info
1762 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1763 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1764 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1765 #define pci_resource_len(dev,bar) \
1766 ((pci_resource_start((dev), (bar)) == 0 && \
1767 pci_resource_end((dev), (bar)) == \
1768 pci_resource_start((dev), (bar))) ? 0 : \
1770 (pci_resource_end((dev), (bar)) - \
1771 pci_resource_start((dev), (bar)) + 1))
1774 * Similar to the helpers above, these manipulate per-pci_dev
1775 * driver-specific data. They are really just a wrapper around
1776 * the generic device structure functions of these calls.
1778 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1780 return dev_get_drvdata(&pdev->dev);
1783 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1785 dev_set_drvdata(&pdev->dev, data);
1788 static inline const char *pci_name(const struct pci_dev *pdev)
1790 return dev_name(&pdev->dev);
1795 * Some archs don't want to expose struct resource to userland as-is
1796 * in sysfs and /proc
1798 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1799 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1800 const struct resource *rsrc,
1801 resource_size_t *start, resource_size_t *end);
1803 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1804 const struct resource *rsrc, resource_size_t *start,
1805 resource_size_t *end)
1807 *start = rsrc->start;
1810 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1814 * The world is not perfect and supplies us with broken PCI devices.
1815 * For at least a part of these bugs we need a work-around, so both
1816 * generic (drivers/pci/quirks.c) and per-architecture code can define
1817 * fixup hooks to be called for particular buggy devices.
1821 u16 vendor; /* Or PCI_ANY_ID */
1822 u16 device; /* Or PCI_ANY_ID */
1823 u32 class; /* Or PCI_ANY_ID */
1824 unsigned int class_shift; /* should be 0, 8, 16 */
1825 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1828 void (*hook)(struct pci_dev *dev);
1832 enum pci_fixup_pass {
1833 pci_fixup_early, /* Before probing BARs */
1834 pci_fixup_header, /* After reading configuration header */
1835 pci_fixup_final, /* Final phase of device fixups */
1836 pci_fixup_enable, /* pci_enable_device() time */
1837 pci_fixup_resume, /* pci_device_resume() */
1838 pci_fixup_suspend, /* pci_device_suspend() */
1839 pci_fixup_resume_early, /* pci_device_resume_early() */
1840 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1843 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1844 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1845 class_shift, hook) \
1846 __ADDRESSABLE(hook) \
1847 asm(".section " #sec ", \"a\" \n" \
1849 ".short " #vendor ", " #device " \n" \
1850 ".long " #class ", " #class_shift " \n" \
1851 ".long " #hook " - . \n" \
1853 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1854 class_shift, hook) \
1855 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1858 /* Anonymous variables would be nice... */
1859 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1860 class_shift, hook) \
1861 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1862 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1863 = { vendor, device, class, class_shift, hook };
1866 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1867 class_shift, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1869 hook, vendor, device, class, class_shift, hook)
1870 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1871 class_shift, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1873 hook, vendor, device, class, class_shift, hook)
1874 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1875 class_shift, hook) \
1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1877 hook, vendor, device, class, class_shift, hook)
1878 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1879 class_shift, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1881 hook, vendor, device, class, class_shift, hook)
1882 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1883 class_shift, hook) \
1884 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1885 resume##hook, vendor, device, class, class_shift, hook)
1886 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1887 class_shift, hook) \
1888 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1889 resume_early##hook, vendor, device, class, class_shift, hook)
1890 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1891 class_shift, hook) \
1892 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1893 suspend##hook, vendor, device, class, class_shift, hook)
1894 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1895 class_shift, hook) \
1896 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1897 suspend_late##hook, vendor, device, class, class_shift, hook)
1899 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1900 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1901 hook, vendor, device, PCI_ANY_ID, 0, hook)
1902 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1903 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1904 hook, vendor, device, PCI_ANY_ID, 0, hook)
1905 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1906 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1907 hook, vendor, device, PCI_ANY_ID, 0, hook)
1908 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1909 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1910 hook, vendor, device, PCI_ANY_ID, 0, hook)
1911 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1912 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1913 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1914 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1915 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1916 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1917 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1918 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1919 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1920 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1921 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1922 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1924 #ifdef CONFIG_PCI_QUIRKS
1925 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1927 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1928 struct pci_dev *dev) { }
1931 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1932 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1933 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1934 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1935 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1937 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1939 extern int pci_pci_problems;
1940 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1941 #define PCIPCI_TRITON 2
1942 #define PCIPCI_NATOMA 4
1943 #define PCIPCI_VIAETBF 8
1944 #define PCIPCI_VSFX 16
1945 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1946 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1948 extern unsigned long pci_cardbus_io_size;
1949 extern unsigned long pci_cardbus_mem_size;
1950 extern u8 pci_dfl_cache_line_size;
1951 extern u8 pci_cache_line_size;
1953 extern unsigned long pci_hotplug_io_size;
1954 extern unsigned long pci_hotplug_mem_size;
1955 extern unsigned long pci_hotplug_bus_size;
1957 /* Architecture-specific versions may override these (weak) */
1958 void pcibios_disable_device(struct pci_dev *dev);
1959 void pcibios_set_master(struct pci_dev *dev);
1960 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1961 enum pcie_reset_state state);
1962 int pcibios_add_device(struct pci_dev *dev);
1963 void pcibios_release_device(struct pci_dev *dev);
1964 void pcibios_penalize_isa_irq(int irq, int active);
1965 int pcibios_alloc_irq(struct pci_dev *dev);
1966 void pcibios_free_irq(struct pci_dev *dev);
1967 resource_size_t pcibios_default_alignment(void);
1969 #ifdef CONFIG_HIBERNATE_CALLBACKS
1970 extern struct dev_pm_ops pcibios_pm_ops;
1973 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1974 void __init pci_mmcfg_early_init(void);
1975 void __init pci_mmcfg_late_init(void);
1977 static inline void pci_mmcfg_early_init(void) { }
1978 static inline void pci_mmcfg_late_init(void) { }
1981 int pci_ext_cfg_avail(void);
1983 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1984 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1986 #ifdef CONFIG_PCI_IOV
1987 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1988 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1990 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1991 void pci_disable_sriov(struct pci_dev *dev);
1992 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1993 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1994 int pci_num_vf(struct pci_dev *dev);
1995 int pci_vfs_assigned(struct pci_dev *dev);
1996 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1997 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1998 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1999 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2000 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2002 /* Arch may override these (weak) */
2003 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2004 int pcibios_sriov_disable(struct pci_dev *pdev);
2005 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2007 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2011 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2015 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2017 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2021 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2023 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2024 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2025 static inline int pci_vfs_assigned(struct pci_dev *dev)
2027 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2029 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2031 #define pci_sriov_configure_simple NULL
2032 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2034 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2037 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2038 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2039 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2043 * pci_pcie_cap - get the saved PCIe capability offset
2046 * PCIe capability offset is calculated at PCI device initialization
2047 * time and saved in the data structure. This function returns saved
2048 * PCIe capability offset. Using this instead of pci_find_capability()
2049 * reduces unnecessary search in the PCI configuration space. If you
2050 * need to calculate PCIe capability offset from raw device for some
2051 * reasons, please use pci_find_capability() instead.
2053 static inline int pci_pcie_cap(struct pci_dev *dev)
2055 return dev->pcie_cap;
2059 * pci_is_pcie - check if the PCI device is PCI Express capable
2062 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2064 static inline bool pci_is_pcie(struct pci_dev *dev)
2066 return pci_pcie_cap(dev);
2070 * pcie_caps_reg - get the PCIe Capabilities Register
2073 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2075 return dev->pcie_flags_reg;
2079 * pci_pcie_type - get the PCIe device/port type
2082 static inline int pci_pcie_type(const struct pci_dev *dev)
2084 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2087 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2090 if (!pci_is_pcie(dev))
2092 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2094 if (!dev->bus->self)
2096 dev = dev->bus->self;
2101 void pci_request_acs(void);
2102 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2103 bool pci_acs_path_enabled(struct pci_dev *start,
2104 struct pci_dev *end, u16 acs_flags);
2105 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2107 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2108 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2110 /* Large Resource Data Type Tag Item Names */
2111 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2112 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2113 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2115 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2116 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2117 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2119 /* Small Resource Data Type Tag Item Names */
2120 #define PCI_VPD_STIN_END 0x0f /* End */
2122 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2124 #define PCI_VPD_SRDT_TIN_MASK 0x78
2125 #define PCI_VPD_SRDT_LEN_MASK 0x07
2126 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2128 #define PCI_VPD_LRDT_TAG_SIZE 3
2129 #define PCI_VPD_SRDT_TAG_SIZE 1
2131 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2133 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2134 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2135 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2136 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2139 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2140 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2142 * Returns the extracted Large Resource Data Type length.
2144 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2146 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2150 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2151 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2153 * Returns the extracted Large Resource Data Type Tag item.
2155 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2157 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2161 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2162 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2164 * Returns the extracted Small Resource Data Type length.
2166 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2168 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2172 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2173 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2175 * Returns the extracted Small Resource Data Type Tag Item.
2177 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2179 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2183 * pci_vpd_info_field_size - Extracts the information field length
2184 * @lrdt: Pointer to the beginning of an information field header
2186 * Returns the extracted information field length.
2188 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2190 return info_field[2];
2194 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2195 * @buf: Pointer to buffered vpd data
2196 * @off: The offset into the buffer at which to begin the search
2197 * @len: The length of the vpd buffer
2198 * @rdt: The Resource Data Type to search for
2200 * Returns the index where the Resource Data Type was found or
2201 * -ENOENT otherwise.
2203 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2206 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2207 * @buf: Pointer to buffered vpd data
2208 * @off: The offset into the buffer at which to begin the search
2209 * @len: The length of the buffer area, relative to off, in which to search
2210 * @kw: The keyword to search for
2212 * Returns the index where the information field keyword was found or
2213 * -ENOENT otherwise.
2215 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2216 unsigned int len, const char *kw);
2218 /* PCI <-> OF binding helpers */
2222 void pci_set_of_node(struct pci_dev *dev);
2223 void pci_release_of_node(struct pci_dev *dev);
2224 void pci_set_bus_of_node(struct pci_bus *bus);
2225 void pci_release_bus_of_node(struct pci_bus *bus);
2226 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2227 int pci_parse_request_of_pci_ranges(struct device *dev,
2228 struct list_head *resources,
2229 struct resource **bus_range);
2231 /* Arch may override this (weak) */
2232 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2234 #else /* CONFIG_OF */
2235 static inline void pci_set_of_node(struct pci_dev *dev) { }
2236 static inline void pci_release_of_node(struct pci_dev *dev) { }
2237 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2238 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2239 static inline struct irq_domain *
2240 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2241 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2242 struct list_head *resources,
2243 struct resource **bus_range)
2247 #endif /* CONFIG_OF */
2249 static inline struct device_node *
2250 pci_device_to_OF_node(const struct pci_dev *pdev)
2252 return pdev ? pdev->dev.of_node : NULL;
2255 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2257 return bus ? bus->dev.of_node : NULL;
2261 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2264 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2266 static inline struct irq_domain *
2267 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2271 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2273 return pdev->dev.archdata.edev;
2277 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2278 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2279 int pci_for_each_dma_alias(struct pci_dev *pdev,
2280 int (*fn)(struct pci_dev *pdev,
2281 u16 alias, void *data), void *data);
2283 /* Helper functions for operation of device flag */
2284 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2286 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2288 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2290 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2292 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2294 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2298 * pci_ari_enabled - query ARI forwarding status
2301 * Returns true if ARI forwarding is enabled.
2303 static inline bool pci_ari_enabled(struct pci_bus *bus)
2305 return bus->self && bus->self->ari_enabled;
2309 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2310 * @pdev: PCI device to check
2312 * Walk upwards from @pdev and check for each encountered bridge if it's part
2313 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2314 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2316 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2318 struct pci_dev *parent = pdev;
2320 if (pdev->is_thunderbolt)
2323 while ((parent = pci_upstream_bridge(parent)))
2324 if (parent->is_thunderbolt)
2330 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2331 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2334 /* Provide the legacy pci_dma_* API */
2335 #include <linux/pci-dma-compat.h>
2337 #define pci_printk(level, pdev, fmt, arg...) \
2338 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2340 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2341 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2342 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2343 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2344 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2345 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2346 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2347 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2349 #endif /* LINUX_PCI_H */