include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _LINUX_NVME_H
  16 #define _LINUX_NVME_H
  17
  18 #include <linux/types.h>
  19 #include <linux/uuid.h>
  20
  21 /* NQN names in commands fields specified one size */
  22 #define NVMF_NQN_FIELD_LEN      256
  23
  24 /* However the max length of a qualified name is another size */
  25 #define NVMF_NQN_SIZE           223
  26
  27 #define NVMF_TRSVCID_SIZE       32
  28 #define NVMF_TRADDR_SIZE        256
  29 #define NVMF_TSAS_SIZE          256
  30
  31 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  32
  33 #define NVME_RDMA_IP_PORT       4420
  34
  35 #define NVME_NSID_ALL           0xffffffff
  36
  37 enum nvme_subsys_type {
  38         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  39         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  40 };
  41
  42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  43 enum {
  44         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  45         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  46         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  47         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  48         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  49 };
  50
  51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  52 enum {
  53         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  54         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  55         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  56         NVMF_TRTYPE_MAX,
  57 };
  58
  59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  60 enum {
  61         NVMF_TREQ_NOT_SPECIFIED = 0,    /* Not specified */
  62         NVMF_TREQ_REQUIRED      = 1,    /* Required */
  63         NVMF_TREQ_NOT_REQUIRED  = 2,    /* Not Required */
  64 };
  65
  66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  67  * RDMA_QPTYPE field
  68  */
  69 enum {
  70         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  71         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  72 };
  73
  74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  75  * RDMA_QPTYPE field
  76  */
  77 enum {
  78         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  79         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  80         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  81         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  82         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  83 };
  84
  85 /* RDMA Connection Management Service Type codes for Discovery Log Page
  86  * entry TSAS RDMA_CMS field
  87  */
  88 enum {
  89         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  90 };
  91
  92 #define NVME_AQ_DEPTH           32
  93
  94 enum {
  95         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
  96         NVME_REG_VS     = 0x0008,       /* Version */
  97         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
  98         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
  99         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 100         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 101         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 102         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 103         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 104         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 105         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 106         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 107         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 108 };
 109
 110 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 111 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 112 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 113 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 114 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 115 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 116
 117 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 118 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 119 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
 120 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
 121
 122 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
 123 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
 124 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
 125 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
 126 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
 127
 128 /*
 129  * Submission and Completion Queue Entry Sizes for the NVM command set.
 130  * (In bytes and specified as a power of two (2^n)).
 131  */
 132 #define NVME_NVM_IOSQES         6
 133 #define NVME_NVM_IOCQES         4
 134
 135 enum {
 136         NVME_CC_ENABLE          = 1 << 0,
 137         NVME_CC_CSS_NVM         = 0 << 4,
 138         NVME_CC_EN_SHIFT        = 0,
 139         NVME_CC_CSS_SHIFT       = 4,
 140         NVME_CC_MPS_SHIFT       = 7,
 141         NVME_CC_AMS_SHIFT       = 11,
 142         NVME_CC_SHN_SHIFT       = 14,
 143         NVME_CC_IOSQES_SHIFT    = 16,
 144         NVME_CC_IOCQES_SHIFT    = 20,
 145         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 146         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 147         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 148         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 149         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 150         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 151         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 152         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 153         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 154         NVME_CSTS_RDY           = 1 << 0,
 155         NVME_CSTS_CFS           = 1 << 1,
 156         NVME_CSTS_NSSRO         = 1 << 4,
 157         NVME_CSTS_PP            = 1 << 5,
 158         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 159         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 160         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 161         NVME_CSTS_SHST_MASK     = 3 << 2,
 162 };
 163
 164 struct nvme_id_power_state {
 165         __le16                  max_power;      /* centiwatts */
 166         __u8                    rsvd2;
 167         __u8                    flags;
 168         __le32                  entry_lat;      /* microseconds */
 169         __le32                  exit_lat;       /* microseconds */
 170         __u8                    read_tput;
 171         __u8                    read_lat;
 172         __u8                    write_tput;
 173         __u8                    write_lat;
 174         __le16                  idle_power;
 175         __u8                    idle_scale;
 176         __u8                    rsvd19;
 177         __le16                  active_power;
 178         __u8                    active_work_scale;
 179         __u8                    rsvd23[9];
 180 };
 181
 182 enum {
 183         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 184         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 185 };
 186
 187 struct nvme_id_ctrl {
 188         __le16                  vid;
 189         __le16                  ssvid;
 190         char                    sn[20];
 191         char                    mn[40];
 192         char                    fr[8];
 193         __u8                    rab;
 194         __u8                    ieee[3];
 195         __u8                    cmic;
 196         __u8                    mdts;
 197         __le16                  cntlid;
 198         __le32                  ver;
 199         __le32                  rtd3r;
 200         __le32                  rtd3e;
 201         __le32                  oaes;
 202         __le32                  ctratt;
 203         __u8                    rsvd100[156];
 204         __le16                  oacs;
 205         __u8                    acl;
 206         __u8                    aerl;
 207         __u8                    frmw;
 208         __u8                    lpa;
 209         __u8                    elpe;
 210         __u8                    npss;
 211         __u8                    avscc;
 212         __u8                    apsta;
 213         __le16                  wctemp;
 214         __le16                  cctemp;
 215         __le16                  mtfa;
 216         __le32                  hmpre;
 217         __le32                  hmmin;
 218         __u8                    tnvmcap[16];
 219         __u8                    unvmcap[16];
 220         __le32                  rpmbs;
 221         __le16                  edstt;
 222         __u8                    dsto;
 223         __u8                    fwug;
 224         __le16                  kas;
 225         __le16                  hctma;
 226         __le16                  mntmt;
 227         __le16                  mxtmt;
 228         __le32                  sanicap;
 229         __le32                  hmminds;
 230         __le16                  hmmaxd;
 231         __u8                    rsvd338[174];
 232         __u8                    sqes;
 233         __u8                    cqes;
 234         __le16                  maxcmd;
 235         __le32                  nn;
 236         __le16                  oncs;
 237         __le16                  fuses;
 238         __u8                    fna;
 239         __u8                    vwc;
 240         __le16                  awun;
 241         __le16                  awupf;
 242         __u8                    nvscc;
 243         __u8                    rsvd531;
 244         __le16                  acwu;
 245         __u8                    rsvd534[2];
 246         __le32                  sgls;
 247         __u8                    rsvd540[228];
 248         char                    subnqn[256];
 249         __u8                    rsvd1024[768];
 250         __le32                  ioccsz;
 251         __le32                  iorcsz;
 252         __le16                  icdoff;
 253         __u8                    ctrattr;
 254         __u8                    msdbd;
 255         __u8                    rsvd1804[244];
 256         struct nvme_id_power_state      psd[32];
 257         __u8                    vs[1024];
 258 };
 259
 260 enum {
 261         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 262         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 263         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 264         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 265         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 266         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 267         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 268         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 269         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 270 };
 271
 272 struct nvme_lbaf {
 273         __le16                  ms;
 274         __u8                    ds;
 275         __u8                    rp;
 276 };
 277
 278 struct nvme_id_ns {
 279         __le64                  nsze;
 280         __le64                  ncap;
 281         __le64                  nuse;
 282         __u8                    nsfeat;
 283         __u8                    nlbaf;
 284         __u8                    flbas;
 285         __u8                    mc;
 286         __u8                    dpc;
 287         __u8                    dps;
 288         __u8                    nmic;
 289         __u8                    rescap;
 290         __u8                    fpi;
 291         __u8                    rsvd33;
 292         __le16                  nawun;
 293         __le16                  nawupf;
 294         __le16                  nacwu;
 295         __le16                  nabsn;
 296         __le16                  nabo;
 297         __le16                  nabspf;
 298         __le16                  noiob;
 299         __u8                    nvmcap[16];
 300         __u8                    rsvd64[40];
 301         __u8                    nguid[16];
 302         __u8                    eui64[8];
 303         struct nvme_lbaf        lbaf[16];
 304         __u8                    rsvd192[192];
 305         __u8                    vs[3712];
 306 };
 307
 308 enum {
 309         NVME_ID_CNS_NS                  = 0x00,
 310         NVME_ID_CNS_CTRL                = 0x01,
 311         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 312         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 313         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 314         NVME_ID_CNS_NS_PRESENT          = 0x11,
 315         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 316         NVME_ID_CNS_CTRL_LIST           = 0x13,
 317 };
 318
 319 enum {
 320         NVME_DIR_IDENTIFY               = 0x00,
 321         NVME_DIR_STREAMS                = 0x01,
 322         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 323         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 324         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 325         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 326         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 327         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 328         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 329         NVME_DIR_ENDIR                  = 0x01,
 330 };
 331
 332 enum {
 333         NVME_NS_FEAT_THIN       = 1 << 0,
 334         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 335         NVME_NS_FLBAS_META_EXT  = 0x10,
 336         NVME_LBAF_RP_BEST       = 0,
 337         NVME_LBAF_RP_BETTER     = 1,
 338         NVME_LBAF_RP_GOOD       = 2,
 339         NVME_LBAF_RP_DEGRADED   = 3,
 340         NVME_NS_DPC_PI_LAST     = 1 << 4,
 341         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 342         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 343         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 344         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 345         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 346         NVME_NS_DPS_PI_MASK     = 0x7,
 347         NVME_NS_DPS_PI_TYPE1    = 1,
 348         NVME_NS_DPS_PI_TYPE2    = 2,
 349         NVME_NS_DPS_PI_TYPE3    = 3,
 350 };
 351
 352 struct nvme_ns_id_desc {
 353         __u8 nidt;
 354         __u8 nidl;
 355         __le16 reserved;
 356 };
 357
 358 #define NVME_NIDT_EUI64_LEN     8
 359 #define NVME_NIDT_NGUID_LEN     16
 360 #define NVME_NIDT_UUID_LEN      16
 361
 362 enum {
 363         NVME_NIDT_EUI64         = 0x01,
 364         NVME_NIDT_NGUID         = 0x02,
 365         NVME_NIDT_UUID          = 0x03,
 366 };
 367
 368 struct nvme_smart_log {
 369         __u8                    critical_warning;
 370         __u8                    temperature[2];
 371         __u8                    avail_spare;
 372         __u8                    spare_thresh;
 373         __u8                    percent_used;
 374         __u8                    rsvd6[26];
 375         __u8                    data_units_read[16];
 376         __u8                    data_units_written[16];
 377         __u8                    host_reads[16];
 378         __u8                    host_writes[16];
 379         __u8                    ctrl_busy_time[16];
 380         __u8                    power_cycles[16];
 381         __u8                    power_on_hours[16];
 382         __u8                    unsafe_shutdowns[16];
 383         __u8                    media_errors[16];
 384         __u8                    num_err_log_entries[16];
 385         __le32                  warning_temp_time;
 386         __le32                  critical_comp_time;
 387         __le16                  temp_sensor[8];
 388         __u8                    rsvd216[296];
 389 };
 390
 391 struct nvme_fw_slot_info_log {
 392         __u8                    afi;
 393         __u8                    rsvd1[7];
 394         __le64                  frs[7];
 395         __u8                    rsvd64[448];
 396 };
 397
 398 enum {
 399         NVME_SMART_CRIT_SPARE           = 1 << 0,
 400         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 401         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 402         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 403         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 404 };
 405
 406 enum {
 407         NVME_AER_NOTICE_NS_CHANGED      = 0x0002,
 408         NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
 409 };
 410
 411 struct nvme_lba_range_type {
 412         __u8                    type;
 413         __u8                    attributes;
 414         __u8                    rsvd2[14];
 415         __u64                   slba;
 416         __u64                   nlb;
 417         __u8                    guid[16];
 418         __u8                    rsvd48[16];
 419 };
 420
 421 enum {
 422         NVME_LBART_TYPE_FS      = 0x01,
 423         NVME_LBART_TYPE_RAID    = 0x02,
 424         NVME_LBART_TYPE_CACHE   = 0x03,
 425         NVME_LBART_TYPE_SWAP    = 0x04,
 426
 427         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 428         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 429 };
 430
 431 struct nvme_reservation_status {
 432         __le32  gen;
 433         __u8    rtype;
 434         __u8    regctl[2];
 435         __u8    resv5[2];
 436         __u8    ptpls;
 437         __u8    resv10[13];
 438         struct {
 439                 __le16  cntlid;
 440                 __u8    rcsts;
 441                 __u8    resv3[5];
 442                 __le64  hostid;
 443                 __le64  rkey;
 444         } regctl_ds[];
 445 };
 446
 447 enum nvme_async_event_type {
 448         NVME_AER_TYPE_ERROR     = 0,
 449         NVME_AER_TYPE_SMART     = 1,
 450         NVME_AER_TYPE_NOTICE    = 2,
 451 };
 452
 453 /* I/O commands */
 454
 455 enum nvme_opcode {
 456         nvme_cmd_flush          = 0x00,
 457         nvme_cmd_write          = 0x01,
 458         nvme_cmd_read           = 0x02,
 459         nvme_cmd_write_uncor    = 0x04,
 460         nvme_cmd_compare        = 0x05,
 461         nvme_cmd_write_zeroes   = 0x08,
 462         nvme_cmd_dsm            = 0x09,
 463         nvme_cmd_resv_register  = 0x0d,
 464         nvme_cmd_resv_report    = 0x0e,
 465         nvme_cmd_resv_acquire   = 0x11,
 466         nvme_cmd_resv_release   = 0x15,
 467 };
 468
 469 /*
 470  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 471  *
 472  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 473  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 474  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 475  *                            request subtype
 476  */
 477 enum {
 478         NVME_SGL_FMT_ADDRESS            = 0x00,
 479         NVME_SGL_FMT_OFFSET             = 0x01,
 480         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 481 };
 482
 483 /*
 484  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 485  *
 486  * For struct nvme_sgl_desc:
 487  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 488  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 489  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 490  *
 491  * For struct nvme_keyed_sgl_desc:
 492  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 493  */
 494 enum {
 495         NVME_SGL_FMT_DATA_DESC          = 0x00,
 496         NVME_SGL_FMT_SEG_DESC           = 0x02,
 497         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 498         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 499 };
 500
 501 struct nvme_sgl_desc {
 502         __le64  addr;
 503         __le32  length;
 504         __u8    rsvd[3];
 505         __u8    type;
 506 };
 507
 508 struct nvme_keyed_sgl_desc {
 509         __le64  addr;
 510         __u8    length[3];
 511         __u8    key[4];
 512         __u8    type;
 513 };
 514
 515 union nvme_data_ptr {
 516         struct {
 517                 __le64  prp1;
 518                 __le64  prp2;
 519         };
 520         struct nvme_sgl_desc    sgl;
 521         struct nvme_keyed_sgl_desc ksgl;
 522 };
 523
 524 /*
 525  * Lowest two bits of our flags field (FUSE field in the spec):
 526  *
 527  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 528  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 529  *
 530  * Highest two bits in our flags field (PSDT field in the spec):
 531  *
 532  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 533  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 534  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 535  *      If used, MPTR contains an address of an SGL segment containing
 536  *      exactly 1 SGL descriptor (qword aligned).
 537  */
 538 enum {
 539         NVME_CMD_FUSE_FIRST     = (1 << 0),
 540         NVME_CMD_FUSE_SECOND    = (1 << 1),
 541
 542         NVME_CMD_SGL_METABUF    = (1 << 6),
 543         NVME_CMD_SGL_METASEG    = (1 << 7),
 544         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 545 };
 546
 547 struct nvme_common_command {
 548         __u8                    opcode;
 549         __u8                    flags;
 550         __u16                   command_id;
 551         __le32                  nsid;
 552         __le32                  cdw2[2];
 553         __le64                  metadata;
 554         union nvme_data_ptr     dptr;
 555         __le32                  cdw10[6];
 556 };
 557
 558 struct nvme_rw_command {
 559         __u8                    opcode;
 560         __u8                    flags;
 561         __u16                   command_id;
 562         __le32                  nsid;
 563         __u64                   rsvd2;
 564         __le64                  metadata;
 565         union nvme_data_ptr     dptr;
 566         __le64                  slba;
 567         __le16                  length;
 568         __le16                  control;
 569         __le32                  dsmgmt;
 570         __le32                  reftag;
 571         __le16                  apptag;
 572         __le16                  appmask;
 573 };
 574
 575 enum {
 576         NVME_RW_LR                      = 1 << 15,
 577         NVME_RW_FUA                     = 1 << 14,
 578         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 579         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 580         NVME_RW_DSM_FREQ_RARE           = 2,
 581         NVME_RW_DSM_FREQ_READS          = 3,
 582         NVME_RW_DSM_FREQ_WRITES         = 4,
 583         NVME_RW_DSM_FREQ_RW             = 5,
 584         NVME_RW_DSM_FREQ_ONCE           = 6,
 585         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 586         NVME_RW_DSM_FREQ_TEMP           = 8,
 587         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 588         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 589         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 590         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 591         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 592         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 593         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 594         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 595         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 596         NVME_RW_PRINFO_PRACT            = 1 << 13,
 597         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 598 };
 599
 600 struct nvme_dsm_cmd {
 601         __u8                    opcode;
 602         __u8                    flags;
 603         __u16                   command_id;
 604         __le32                  nsid;
 605         __u64                   rsvd2[2];
 606         union nvme_data_ptr     dptr;
 607         __le32                  nr;
 608         __le32                  attributes;
 609         __u32                   rsvd12[4];
 610 };
 611
 612 enum {
 613         NVME_DSMGMT_IDR         = 1 << 0,
 614         NVME_DSMGMT_IDW         = 1 << 1,
 615         NVME_DSMGMT_AD          = 1 << 2,
 616 };
 617
 618 #define NVME_DSM_MAX_RANGES     256
 619
 620 struct nvme_dsm_range {
 621         __le32                  cattr;
 622         __le32                  nlb;
 623         __le64                  slba;
 624 };
 625
 626 struct nvme_write_zeroes_cmd {
 627         __u8                    opcode;
 628         __u8                    flags;
 629         __u16                   command_id;
 630         __le32                  nsid;
 631         __u64                   rsvd2;
 632         __le64                  metadata;
 633         union nvme_data_ptr     dptr;
 634         __le64                  slba;
 635         __le16                  length;
 636         __le16                  control;
 637         __le32                  dsmgmt;
 638         __le32                  reftag;
 639         __le16                  apptag;
 640         __le16                  appmask;
 641 };
 642
 643 /* Features */
 644
 645 struct nvme_feat_auto_pst {
 646         __le64 entries[32];
 647 };
 648
 649 enum {
 650         NVME_HOST_MEM_ENABLE    = (1 << 0),
 651         NVME_HOST_MEM_RETURN    = (1 << 1),
 652 };
 653
 654 /* Admin commands */
 655
 656 enum nvme_admin_opcode {
 657         nvme_admin_delete_sq            = 0x00,
 658         nvme_admin_create_sq            = 0x01,
 659         nvme_admin_get_log_page         = 0x02,
 660         nvme_admin_delete_cq            = 0x04,
 661         nvme_admin_create_cq            = 0x05,
 662         nvme_admin_identify             = 0x06,
 663         nvme_admin_abort_cmd            = 0x08,
 664         nvme_admin_set_features         = 0x09,
 665         nvme_admin_get_features         = 0x0a,
 666         nvme_admin_async_event          = 0x0c,
 667         nvme_admin_ns_mgmt              = 0x0d,
 668         nvme_admin_activate_fw          = 0x10,
 669         nvme_admin_download_fw          = 0x11,
 670         nvme_admin_ns_attach            = 0x15,
 671         nvme_admin_keep_alive           = 0x18,
 672         nvme_admin_directive_send       = 0x19,
 673         nvme_admin_directive_recv       = 0x1a,
 674         nvme_admin_dbbuf                = 0x7C,
 675         nvme_admin_format_nvm           = 0x80,
 676         nvme_admin_security_send        = 0x81,
 677         nvme_admin_security_recv        = 0x82,
 678 };
 679
 680 enum {
 681         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 682         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 683         NVME_SQ_PRIO_URGENT     = (0 << 1),
 684         NVME_SQ_PRIO_HIGH       = (1 << 1),
 685         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 686         NVME_SQ_PRIO_LOW        = (3 << 1),
 687         NVME_FEAT_ARBITRATION   = 0x01,
 688         NVME_FEAT_POWER_MGMT    = 0x02,
 689         NVME_FEAT_LBA_RANGE     = 0x03,
 690         NVME_FEAT_TEMP_THRESH   = 0x04,
 691         NVME_FEAT_ERR_RECOVERY  = 0x05,
 692         NVME_FEAT_VOLATILE_WC   = 0x06,
 693         NVME_FEAT_NUM_QUEUES    = 0x07,
 694         NVME_FEAT_IRQ_COALESCE  = 0x08,
 695         NVME_FEAT_IRQ_CONFIG    = 0x09,
 696         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 697         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 698         NVME_FEAT_AUTO_PST      = 0x0c,
 699         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 700         NVME_FEAT_TIMESTAMP     = 0x0e,
 701         NVME_FEAT_KATO          = 0x0f,
 702         NVME_FEAT_SW_PROGRESS   = 0x80,
 703         NVME_FEAT_HOST_ID       = 0x81,
 704         NVME_FEAT_RESV_MASK     = 0x82,
 705         NVME_FEAT_RESV_PERSIST  = 0x83,
 706         NVME_LOG_ERROR          = 0x01,
 707         NVME_LOG_SMART          = 0x02,
 708         NVME_LOG_FW_SLOT        = 0x03,
 709         NVME_LOG_DISC           = 0x70,
 710         NVME_LOG_RESERVATION    = 0x80,
 711         NVME_FWACT_REPL         = (0 << 3),
 712         NVME_FWACT_REPL_ACTV    = (1 << 3),
 713         NVME_FWACT_ACTV         = (2 << 3),
 714 };
 715
 716 struct nvme_identify {
 717         __u8                    opcode;
 718         __u8                    flags;
 719         __u16                   command_id;
 720         __le32                  nsid;
 721         __u64                   rsvd2[2];
 722         union nvme_data_ptr     dptr;
 723         __u8                    cns;
 724         __u8                    rsvd3;
 725         __le16                  ctrlid;
 726         __u32                   rsvd11[5];
 727 };
 728
 729 #define NVME_IDENTIFY_DATA_SIZE 4096
 730
 731 struct nvme_features {
 732         __u8                    opcode;
 733         __u8                    flags;
 734         __u16                   command_id;
 735         __le32                  nsid;
 736         __u64                   rsvd2[2];
 737         union nvme_data_ptr     dptr;
 738         __le32                  fid;
 739         __le32                  dword11;
 740         __le32                  dword12;
 741         __le32                  dword13;
 742         __le32                  dword14;
 743         __le32                  dword15;
 744 };
 745
 746 struct nvme_host_mem_buf_desc {
 747         __le64                  addr;
 748         __le32                  size;
 749         __u32                   rsvd;
 750 };
 751
 752 struct nvme_create_cq {
 753         __u8                    opcode;
 754         __u8                    flags;
 755         __u16                   command_id;
 756         __u32                   rsvd1[5];
 757         __le64                  prp1;
 758         __u64                   rsvd8;
 759         __le16                  cqid;
 760         __le16                  qsize;
 761         __le16                  cq_flags;
 762         __le16                  irq_vector;
 763         __u32                   rsvd12[4];
 764 };
 765
 766 struct nvme_create_sq {
 767         __u8                    opcode;
 768         __u8                    flags;
 769         __u16                   command_id;
 770         __u32                   rsvd1[5];
 771         __le64                  prp1;
 772         __u64                   rsvd8;
 773         __le16                  sqid;
 774         __le16                  qsize;
 775         __le16                  sq_flags;
 776         __le16                  cqid;
 777         __u32                   rsvd12[4];
 778 };
 779
 780 struct nvme_delete_queue {
 781         __u8                    opcode;
 782         __u8                    flags;
 783         __u16                   command_id;
 784         __u32                   rsvd1[9];
 785         __le16                  qid;
 786         __u16                   rsvd10;
 787         __u32                   rsvd11[5];
 788 };
 789
 790 struct nvme_abort_cmd {
 791         __u8                    opcode;
 792         __u8                    flags;
 793         __u16                   command_id;
 794         __u32                   rsvd1[9];
 795         __le16                  sqid;
 796         __u16                   cid;
 797         __u32                   rsvd11[5];
 798 };
 799
 800 struct nvme_download_firmware {
 801         __u8                    opcode;
 802         __u8                    flags;
 803         __u16                   command_id;
 804         __u32                   rsvd1[5];
 805         union nvme_data_ptr     dptr;
 806         __le32                  numd;
 807         __le32                  offset;
 808         __u32                   rsvd12[4];
 809 };
 810
 811 struct nvme_format_cmd {
 812         __u8                    opcode;
 813         __u8                    flags;
 814         __u16                   command_id;
 815         __le32                  nsid;
 816         __u64                   rsvd2[4];
 817         __le32                  cdw10;
 818         __u32                   rsvd11[5];
 819 };
 820
 821 struct nvme_get_log_page_command {
 822         __u8                    opcode;
 823         __u8                    flags;
 824         __u16                   command_id;
 825         __le32                  nsid;
 826         __u64                   rsvd2[2];
 827         union nvme_data_ptr     dptr;
 828         __u8                    lid;
 829         __u8                    rsvd10;
 830         __le16                  numdl;
 831         __le16                  numdu;
 832         __u16                   rsvd11;
 833         __le32                  lpol;
 834         __le32                  lpou;
 835         __u32                   rsvd14[2];
 836 };
 837
 838 struct nvme_directive_cmd {
 839         __u8                    opcode;
 840         __u8                    flags;
 841         __u16                   command_id;
 842         __le32                  nsid;
 843         __u64                   rsvd2[2];
 844         union nvme_data_ptr     dptr;
 845         __le32                  numd;
 846         __u8                    doper;
 847         __u8                    dtype;
 848         __le16                  dspec;
 849         __u8                    endir;
 850         __u8                    tdtype;
 851         __u16                   rsvd15;
 852
 853         __u32                   rsvd16[3];
 854 };
 855
 856 /*
 857  * Fabrics subcommands.
 858  */
 859 enum nvmf_fabrics_opcode {
 860         nvme_fabrics_command            = 0x7f,
 861 };
 862
 863 enum nvmf_capsule_command {
 864         nvme_fabrics_type_property_set  = 0x00,
 865         nvme_fabrics_type_connect       = 0x01,
 866         nvme_fabrics_type_property_get  = 0x04,
 867 };
 868
 869 struct nvmf_common_command {
 870         __u8    opcode;
 871         __u8    resv1;
 872         __u16   command_id;
 873         __u8    fctype;
 874         __u8    resv2[35];
 875         __u8    ts[24];
 876 };
 877
 878 /*
 879  * The legal cntlid range a NVMe Target will provide.
 880  * Note that cntlid of value 0 is considered illegal in the fabrics world.
 881  * Devices based on earlier specs did not have the subsystem concept;
 882  * therefore, those devices had their cntlid value set to 0 as a result.
 883  */
 884 #define NVME_CNTLID_MIN         1
 885 #define NVME_CNTLID_MAX         0xffef
 886 #define NVME_CNTLID_DYNAMIC     0xffff
 887
 888 #define MAX_DISC_LOGS   255
 889
 890 /* Discovery log page entry */
 891 struct nvmf_disc_rsp_page_entry {
 892         __u8            trtype;
 893         __u8            adrfam;
 894         __u8            subtype;
 895         __u8            treq;
 896         __le16          portid;
 897         __le16          cntlid;
 898         __le16          asqsz;
 899         __u8            resv8[22];
 900         char            trsvcid[NVMF_TRSVCID_SIZE];
 901         __u8            resv64[192];
 902         char            subnqn[NVMF_NQN_FIELD_LEN];
 903         char            traddr[NVMF_TRADDR_SIZE];
 904         union tsas {
 905                 char            common[NVMF_TSAS_SIZE];
 906                 struct rdma {
 907                         __u8    qptype;
 908                         __u8    prtype;
 909                         __u8    cms;
 910                         __u8    resv3[5];
 911                         __u16   pkey;
 912                         __u8    resv10[246];
 913                 } rdma;
 914         } tsas;
 915 };
 916
 917 /* Discovery log page header */
 918 struct nvmf_disc_rsp_page_hdr {
 919         __le64          genctr;
 920         __le64          numrec;
 921         __le16          recfmt;
 922         __u8            resv14[1006];
 923         struct nvmf_disc_rsp_page_entry entries[0];
 924 };
 925
 926 struct nvmf_connect_command {
 927         __u8            opcode;
 928         __u8            resv1;
 929         __u16           command_id;
 930         __u8            fctype;
 931         __u8            resv2[19];
 932         union nvme_data_ptr dptr;
 933         __le16          recfmt;
 934         __le16          qid;
 935         __le16          sqsize;
 936         __u8            cattr;
 937         __u8            resv3;
 938         __le32          kato;
 939         __u8            resv4[12];
 940 };
 941
 942 struct nvmf_connect_data {
 943         uuid_t          hostid;
 944         __le16          cntlid;
 945         char            resv4[238];
 946         char            subsysnqn[NVMF_NQN_FIELD_LEN];
 947         char            hostnqn[NVMF_NQN_FIELD_LEN];
 948         char            resv5[256];
 949 };
 950
 951 struct nvmf_property_set_command {
 952         __u8            opcode;
 953         __u8            resv1;
 954         __u16           command_id;
 955         __u8            fctype;
 956         __u8            resv2[35];
 957         __u8            attrib;
 958         __u8            resv3[3];
 959         __le32          offset;
 960         __le64          value;
 961         __u8            resv4[8];
 962 };
 963
 964 struct nvmf_property_get_command {
 965         __u8            opcode;
 966         __u8            resv1;
 967         __u16           command_id;
 968         __u8            fctype;
 969         __u8            resv2[35];
 970         __u8            attrib;
 971         __u8            resv3[3];
 972         __le32          offset;
 973         __u8            resv4[16];
 974 };
 975
 976 struct nvme_dbbuf {
 977         __u8                    opcode;
 978         __u8                    flags;
 979         __u16                   command_id;
 980         __u32                   rsvd1[5];
 981         __le64                  prp1;
 982         __le64                  prp2;
 983         __u32                   rsvd12[6];
 984 };
 985
 986 struct streams_directive_params {
 987         __le16  msl;
 988         __le16  nssa;
 989         __le16  nsso;
 990         __u8    rsvd[10];
 991         __le32  sws;
 992         __le16  sgs;
 993         __le16  nsa;
 994         __le16  nso;
 995         __u8    rsvd2[6];
 996 };
 997
 998 struct nvme_command {
 999         union {
1000                 struct nvme_common_command common;
1001                 struct nvme_rw_command rw;
1002                 struct nvme_identify identify;
1003                 struct nvme_features features;
1004                 struct nvme_create_cq create_cq;
1005                 struct nvme_create_sq create_sq;
1006                 struct nvme_delete_queue delete_queue;
1007                 struct nvme_download_firmware dlfw;
1008                 struct nvme_format_cmd format;
1009                 struct nvme_dsm_cmd dsm;
1010                 struct nvme_write_zeroes_cmd write_zeroes;
1011                 struct nvme_abort_cmd abort;
1012                 struct nvme_get_log_page_command get_log_page;
1013                 struct nvmf_common_command fabrics;
1014                 struct nvmf_connect_command connect;
1015                 struct nvmf_property_set_command prop_set;
1016                 struct nvmf_property_get_command prop_get;
1017                 struct nvme_dbbuf dbbuf;
1018                 struct nvme_directive_cmd directive;
1019         };
1020 };
1021
1022 static inline bool nvme_is_write(struct nvme_command *cmd)
1023 {
1024         /*
1025          * What a mess...
1026          *
1027          * Why can't we simply have a Fabrics In and Fabrics out command?
1028          */
1029         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1030                 return cmd->fabrics.fctype & 1;
1031         return cmd->common.opcode & 1;
1032 }
1033
1034 enum {
1035         /*
1036          * Generic Command Status:
1037          */
1038         NVME_SC_SUCCESS                 = 0x0,
1039         NVME_SC_INVALID_OPCODE          = 0x1,
1040         NVME_SC_INVALID_FIELD           = 0x2,
1041         NVME_SC_CMDID_CONFLICT          = 0x3,
1042         NVME_SC_DATA_XFER_ERROR         = 0x4,
1043         NVME_SC_POWER_LOSS              = 0x5,
1044         NVME_SC_INTERNAL                = 0x6,
1045         NVME_SC_ABORT_REQ               = 0x7,
1046         NVME_SC_ABORT_QUEUE             = 0x8,
1047         NVME_SC_FUSED_FAIL              = 0x9,
1048         NVME_SC_FUSED_MISSING           = 0xa,
1049         NVME_SC_INVALID_NS              = 0xb,
1050         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1051         NVME_SC_SGL_INVALID_LAST        = 0xd,
1052         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1053         NVME_SC_SGL_INVALID_DATA        = 0xf,
1054         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1055         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1056
1057         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1058         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1059
1060         NVME_SC_LBA_RANGE               = 0x80,
1061         NVME_SC_CAP_EXCEEDED            = 0x81,
1062         NVME_SC_NS_NOT_READY            = 0x82,
1063         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1064
1065         /*
1066          * Command Specific Status:
1067          */
1068         NVME_SC_CQ_INVALID              = 0x100,
1069         NVME_SC_QID_INVALID             = 0x101,
1070         NVME_SC_QUEUE_SIZE              = 0x102,
1071         NVME_SC_ABORT_LIMIT             = 0x103,
1072         NVME_SC_ABORT_MISSING           = 0x104,
1073         NVME_SC_ASYNC_LIMIT             = 0x105,
1074         NVME_SC_FIRMWARE_SLOT           = 0x106,
1075         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1076         NVME_SC_INVALID_VECTOR          = 0x108,
1077         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1078         NVME_SC_INVALID_FORMAT          = 0x10a,
1079         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1080         NVME_SC_INVALID_QUEUE           = 0x10c,
1081         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1082         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1083         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1084         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1085         NVME_SC_FW_NEEDS_RESET          = 0x111,
1086         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1087         NVME_SC_FW_ACIVATE_PROHIBITED   = 0x113,
1088         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1089         NVME_SC_NS_INSUFFICENT_CAP      = 0x115,
1090         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1091         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1092         NVME_SC_NS_IS_PRIVATE           = 0x119,
1093         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1094         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1095         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1096
1097         /*
1098          * I/O Command Set Specific - NVM commands:
1099          */
1100         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1101         NVME_SC_INVALID_PI              = 0x181,
1102         NVME_SC_READ_ONLY               = 0x182,
1103         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1104
1105         /*
1106          * I/O Command Set Specific - Fabrics commands:
1107          */
1108         NVME_SC_CONNECT_FORMAT          = 0x180,
1109         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1110         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1111         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1112         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1113
1114         NVME_SC_DISCOVERY_RESTART       = 0x190,
1115         NVME_SC_AUTH_REQUIRED           = 0x191,
1116
1117         /*
1118          * Media and Data Integrity Errors:
1119          */
1120         NVME_SC_WRITE_FAULT             = 0x280,
1121         NVME_SC_READ_ERROR              = 0x281,
1122         NVME_SC_GUARD_CHECK             = 0x282,
1123         NVME_SC_APPTAG_CHECK            = 0x283,
1124         NVME_SC_REFTAG_CHECK            = 0x284,
1125         NVME_SC_COMPARE_FAILED          = 0x285,
1126         NVME_SC_ACCESS_DENIED           = 0x286,
1127         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1128
1129         NVME_SC_DNR                     = 0x4000,
1130
1131
1132         /*
1133          * FC Transport-specific error status values for NVME commands
1134          *
1135          * Transport-specific status code values must be in the range 0xB0..0xBF
1136          */
1137
1138         /* Generic FC failure - catchall */
1139         NVME_SC_FC_TRANSPORT_ERROR      = 0x00B0,
1140
1141         /* I/O failure due to FC ABTS'd */
1142         NVME_SC_FC_TRANSPORT_ABORTED    = 0x00B1,
1143 };
1144
1145 struct nvme_completion {
1146         /*
1147          * Used by Admin and Fabrics commands to return data:
1148          */
1149         union nvme_result {
1150                 __le16  u16;
1151                 __le32  u32;
1152                 __le64  u64;
1153         } result;
1154         __le16  sq_head;        /* how much of this queue may be reclaimed */
1155         __le16  sq_id;          /* submission queue that generated this entry */
1156         __u16   command_id;     /* of the command which completed */
1157         __le16  status;         /* did the command fail, and if so, why? */
1158 };
1159
1160 #define NVME_VS(major, minor, tertiary) \
1161         (((major) << 16) | ((minor) << 8) | (tertiary))
1162
1163 #define NVME_MAJOR(ver)         ((ver) >> 16)
1164 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1165 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1166
1167 #endif /* _LINUX_NVME_H */