219c699c17b76ddd06caefde2181e5e220e6fd46
[sfrench/cifs-2.6.git] / include / linux / mlx5 / qp.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #ifndef MLX5_QP_H
34 #define MLX5_QP_H
35
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
38
39 #define MLX5_INVALID_LKEY       0x100
40 #define MLX5_SIG_WQE_SIZE       (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE           8
42 #define MLX5_STRIDE_BLOCK_OP    0x400
43 #define MLX5_CPY_GRD_MASK       0xc0
44 #define MLX5_CPY_APP_MASK       0x30
45 #define MLX5_CPY_REF_MASK       0x0f
46 #define MLX5_BSF_INC_REFTAG     (1 << 6)
47 #define MLX5_BSF_INL_VALID      (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF    (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK   (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE  0x1
51 #define MLX5_BSF_APPREF_ESCAPE  0x2
52
53 enum mlx5_qp_optpar {
54         MLX5_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
55         MLX5_QP_OPTPAR_RRE                      = 1 << 1,
56         MLX5_QP_OPTPAR_RAE                      = 1 << 2,
57         MLX5_QP_OPTPAR_RWE                      = 1 << 3,
58         MLX5_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
59         MLX5_QP_OPTPAR_Q_KEY                    = 1 << 5,
60         MLX5_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
61         MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
62         MLX5_QP_OPTPAR_SRA_MAX                  = 1 << 8,
63         MLX5_QP_OPTPAR_RRA_MAX                  = 1 << 9,
64         MLX5_QP_OPTPAR_PM_STATE                 = 1 << 10,
65         MLX5_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
66         MLX5_QP_OPTPAR_RNR_RETRY                = 1 << 13,
67         MLX5_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
68         MLX5_QP_OPTPAR_PRI_PORT                 = 1 << 16,
69         MLX5_QP_OPTPAR_SRQN                     = 1 << 18,
70         MLX5_QP_OPTPAR_CQN_RCV                  = 1 << 19,
71         MLX5_QP_OPTPAR_DC_HS                    = 1 << 20,
72         MLX5_QP_OPTPAR_DC_KEY                   = 1 << 21,
73 };
74
75 enum mlx5_qp_state {
76         MLX5_QP_STATE_RST                       = 0,
77         MLX5_QP_STATE_INIT                      = 1,
78         MLX5_QP_STATE_RTR                       = 2,
79         MLX5_QP_STATE_RTS                       = 3,
80         MLX5_QP_STATE_SQER                      = 4,
81         MLX5_QP_STATE_SQD                       = 5,
82         MLX5_QP_STATE_ERR                       = 6,
83         MLX5_QP_STATE_SQ_DRAINING               = 7,
84         MLX5_QP_STATE_SUSPENDED                 = 9,
85         MLX5_QP_NUM_STATE,
86         MLX5_QP_STATE,
87         MLX5_QP_STATE_BAD,
88 };
89
90 enum {
91         MLX5_SQ_STATE_NA        = MLX5_SQC_STATE_ERR + 1,
92         MLX5_SQ_NUM_STATE       = MLX5_SQ_STATE_NA + 1,
93         MLX5_RQ_STATE_NA        = MLX5_RQC_STATE_ERR + 1,
94         MLX5_RQ_NUM_STATE       = MLX5_RQ_STATE_NA + 1,
95 };
96
97 enum {
98         MLX5_QP_ST_RC                           = 0x0,
99         MLX5_QP_ST_UC                           = 0x1,
100         MLX5_QP_ST_UD                           = 0x2,
101         MLX5_QP_ST_XRC                          = 0x3,
102         MLX5_QP_ST_MLX                          = 0x4,
103         MLX5_QP_ST_DCI                          = 0x5,
104         MLX5_QP_ST_DCT                          = 0x6,
105         MLX5_QP_ST_QP0                          = 0x7,
106         MLX5_QP_ST_QP1                          = 0x8,
107         MLX5_QP_ST_RAW_ETHERTYPE                = 0x9,
108         MLX5_QP_ST_RAW_IPV6                     = 0xa,
109         MLX5_QP_ST_SNIFFER                      = 0xb,
110         MLX5_QP_ST_SYNC_UMR                     = 0xe,
111         MLX5_QP_ST_PTP_1588                     = 0xd,
112         MLX5_QP_ST_REG_UMR                      = 0xc,
113         MLX5_QP_ST_MAX
114 };
115
116 enum {
117         MLX5_QP_PM_MIGRATED                     = 0x3,
118         MLX5_QP_PM_ARMED                        = 0x0,
119         MLX5_QP_PM_REARM                        = 0x1
120 };
121
122 enum {
123         MLX5_NON_ZERO_RQ        = 0x0,
124         MLX5_SRQ_RQ             = 0x1,
125         MLX5_CRQ_RQ             = 0x2,
126         MLX5_ZERO_LEN_RQ        = 0x3
127 };
128
129 /* TODO REM */
130 enum {
131         /* params1 */
132         MLX5_QP_BIT_SRE                         = 1 << 15,
133         MLX5_QP_BIT_SWE                         = 1 << 14,
134         MLX5_QP_BIT_SAE                         = 1 << 13,
135         /* params2 */
136         MLX5_QP_BIT_RRE                         = 1 << 15,
137         MLX5_QP_BIT_RWE                         = 1 << 14,
138         MLX5_QP_BIT_RAE                         = 1 << 13,
139         MLX5_QP_BIT_RIC                         = 1 <<  4,
140         MLX5_QP_BIT_CC_SLAVE_RECV               = 1 <<  2,
141         MLX5_QP_BIT_CC_SLAVE_SEND               = 1 <<  1,
142         MLX5_QP_BIT_CC_MASTER                   = 1 <<  0
143 };
144
145 enum {
146         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
147         MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
148         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
149 };
150
151 enum {
152         MLX5_SEND_WQE_DS        = 16,
153         MLX5_SEND_WQE_BB        = 64,
154 };
155
156 #define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
157
158 enum {
159         MLX5_SEND_WQE_MAX_WQEBBS        = 16,
160 };
161
162 enum {
163         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
164         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
165         MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
166         MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
167         MLX5_WQE_FMR_PERM_ATOMIC        = 1 << 31
168 };
169
170 enum {
171         MLX5_FENCE_MODE_NONE                    = 0 << 5,
172         MLX5_FENCE_MODE_INITIATOR_SMALL         = 1 << 5,
173         MLX5_FENCE_MODE_FENCE                   = 2 << 5,
174         MLX5_FENCE_MODE_STRONG_ORDERING         = 3 << 5,
175         MLX5_FENCE_MODE_SMALL_AND_FENCE         = 4 << 5,
176 };
177
178 enum {
179         MLX5_RCV_DBR    = 0,
180         MLX5_SND_DBR    = 1,
181 };
182
183 enum {
184         MLX5_FLAGS_INLINE       = 1<<7,
185         MLX5_FLAGS_CHECK_FREE   = 1<<5,
186 };
187
188 struct mlx5_wqe_fmr_seg {
189         __be32                  flags;
190         __be32                  mem_key;
191         __be64                  buf_list;
192         __be64                  start_addr;
193         __be64                  reg_len;
194         __be32                  offset;
195         __be32                  page_size;
196         u32                     reserved[2];
197 };
198
199 struct mlx5_wqe_ctrl_seg {
200         __be32                  opmod_idx_opcode;
201         __be32                  qpn_ds;
202         u8                      signature;
203         u8                      rsvd[2];
204         u8                      fm_ce_se;
205         __be32                  imm;
206 };
207
208 #define MLX5_WQE_CTRL_DS_MASK 0x3f
209 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
210 #define MLX5_WQE_CTRL_QPN_SHIFT 8
211 #define MLX5_WQE_DS_UNITS 16
212 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
213 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
214 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
215 #define MLX5_WQE_AV_EXT 0x80000000
216
217 enum {
218         MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
219         MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
220         MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
221         MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
222 };
223
224 struct mlx5_wqe_eth_seg {
225         u8              rsvd0[4];
226         u8              cs_flags;
227         u8              rsvd1;
228         __be16          mss;
229         __be32          rsvd2;
230         __be16          inline_hdr_sz;
231         u8              inline_hdr_start[2];
232 };
233
234 struct mlx5_wqe_xrc_seg {
235         __be32                  xrc_srqn;
236         u8                      rsvd[12];
237 };
238
239 struct mlx5_wqe_masked_atomic_seg {
240         __be64                  swap_add;
241         __be64                  compare;
242         __be64                  swap_add_mask;
243         __be64                  compare_mask;
244 };
245
246 struct mlx5_base_av {
247         union {
248                 struct {
249                         __be32  qkey;
250                         __be32  reserved;
251                 } qkey;
252                 __be64  dc_key;
253         } key;
254         __be32  dqp_dct;
255         u8      stat_rate_sl;
256         u8      fl_mlid;
257         union {
258                 __be16  rlid;
259                 __be16  udp_sport;
260         };
261 };
262
263 struct mlx5_av {
264         union {
265                 struct {
266                         __be32  qkey;
267                         __be32  reserved;
268                 } qkey;
269                 __be64  dc_key;
270         } key;
271         __be32  dqp_dct;
272         u8      stat_rate_sl;
273         u8      fl_mlid;
274         union {
275                 __be16  rlid;
276                 __be16  udp_sport;
277         };
278         u8      reserved0[4];
279         u8      rmac[6];
280         u8      tclass;
281         u8      hop_limit;
282         __be32  grh_gid_fl;
283         u8      rgid[16];
284 };
285
286 struct mlx5_wqe_datagram_seg {
287         struct mlx5_av  av;
288 };
289
290 struct mlx5_wqe_raddr_seg {
291         __be64                  raddr;
292         __be32                  rkey;
293         u32                     reserved;
294 };
295
296 struct mlx5_wqe_atomic_seg {
297         __be64                  swap_add;
298         __be64                  compare;
299 };
300
301 struct mlx5_wqe_data_seg {
302         __be32                  byte_count;
303         __be32                  lkey;
304         __be64                  addr;
305 };
306
307 struct mlx5_wqe_umr_ctrl_seg {
308         u8              flags;
309         u8              rsvd0[3];
310         __be16          xlt_octowords;
311         union {
312                 __be16  xlt_offset;
313                 __be16  bsf_octowords;
314         };
315         __be64          mkey_mask;
316         __be32          xlt_offset_47_16;
317         u8              rsvd1[28];
318 };
319
320 struct mlx5_seg_set_psv {
321         __be32          psv_num;
322         __be16          syndrome;
323         __be16          status;
324         __be32          transient_sig;
325         __be32          ref_tag;
326 };
327
328 struct mlx5_seg_get_psv {
329         u8              rsvd[19];
330         u8              num_psv;
331         __be32          l_key;
332         __be64          va;
333         __be32          psv_index[4];
334 };
335
336 struct mlx5_seg_check_psv {
337         u8              rsvd0[2];
338         __be16          err_coalescing_op;
339         u8              rsvd1[2];
340         __be16          xport_err_op;
341         u8              rsvd2[2];
342         __be16          xport_err_mask;
343         u8              rsvd3[7];
344         u8              num_psv;
345         __be32          l_key;
346         __be64          va;
347         __be32          psv_index[4];
348 };
349
350 struct mlx5_rwqe_sig {
351         u8      rsvd0[4];
352         u8      signature;
353         u8      rsvd1[11];
354 };
355
356 struct mlx5_wqe_signature_seg {
357         u8      rsvd0[4];
358         u8      signature;
359         u8      rsvd1[11];
360 };
361
362 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
363
364 struct mlx5_wqe_inline_seg {
365         __be32  byte_count;
366 };
367
368 enum mlx5_sig_type {
369         MLX5_DIF_CRC = 0x1,
370         MLX5_DIF_IPCS = 0x2,
371 };
372
373 struct mlx5_bsf_inl {
374         __be16          vld_refresh;
375         __be16          dif_apptag;
376         __be32          dif_reftag;
377         u8              sig_type;
378         u8              rp_inv_seed;
379         u8              rsvd[3];
380         u8              dif_inc_ref_guard_check;
381         __be16          dif_app_bitmask_check;
382 };
383
384 struct mlx5_bsf {
385         struct mlx5_bsf_basic {
386                 u8              bsf_size_sbs;
387                 u8              check_byte_mask;
388                 union {
389                         u8      copy_byte_mask;
390                         u8      bs_selector;
391                         u8      rsvd_wflags;
392                 } wire;
393                 union {
394                         u8      bs_selector;
395                         u8      rsvd_mflags;
396                 } mem;
397                 __be32          raw_data_size;
398                 __be32          w_bfs_psv;
399                 __be32          m_bfs_psv;
400         } basic;
401         struct mlx5_bsf_ext {
402                 __be32          t_init_gen_pro_size;
403                 __be32          rsvd_epi_size;
404                 __be32          w_tfs_psv;
405                 __be32          m_tfs_psv;
406         } ext;
407         struct mlx5_bsf_inl     w_inl;
408         struct mlx5_bsf_inl     m_inl;
409 };
410
411 struct mlx5_mtt {
412         __be64          ptag;
413 };
414
415 struct mlx5_klm {
416         __be32          bcount;
417         __be32          key;
418         __be64          va;
419 };
420
421 struct mlx5_stride_block_entry {
422         __be16          stride;
423         __be16          bcount;
424         __be32          key;
425         __be64          va;
426 };
427
428 struct mlx5_stride_block_ctrl_seg {
429         __be32          bcount_per_cycle;
430         __be32          op;
431         __be32          repeat_count;
432         u16             rsvd;
433         __be16          num_entries;
434 };
435
436 struct mlx5_core_qp {
437         struct mlx5_core_rsc_common     common; /* must be first */
438         void (*event)           (struct mlx5_core_qp *, int);
439         int                     qpn;
440         struct mlx5_rsc_debug   *dbg;
441         int                     pid;
442 };
443
444 struct mlx5_qp_path {
445         u8                      fl_free_ar;
446         u8                      rsvd3;
447         __be16                  pkey_index;
448         u8                      rsvd0;
449         u8                      grh_mlid;
450         __be16                  rlid;
451         u8                      ackto_lt;
452         u8                      mgid_index;
453         u8                      static_rate;
454         u8                      hop_limit;
455         __be32                  tclass_flowlabel;
456         union {
457                 u8              rgid[16];
458                 u8              rip[16];
459         };
460         u8                      f_dscp_ecn_prio;
461         u8                      ecn_dscp;
462         __be16                  udp_sport;
463         u8                      dci_cfi_prio_sl;
464         u8                      port;
465         u8                      rmac[6];
466 };
467
468 /* FIXME: use mlx5_ifc.h qpc */
469 struct mlx5_qp_context {
470         __be32                  flags;
471         __be32                  flags_pd;
472         u8                      mtu_msgmax;
473         u8                      rq_size_stride;
474         __be16                  sq_crq_size;
475         __be32                  qp_counter_set_usr_page;
476         __be32                  wire_qpn;
477         __be32                  log_pg_sz_remote_qpn;
478         struct                  mlx5_qp_path pri_path;
479         struct                  mlx5_qp_path alt_path;
480         __be32                  params1;
481         u8                      reserved2[4];
482         __be32                  next_send_psn;
483         __be32                  cqn_send;
484         __be32                  deth_sqpn;
485         u8                      reserved3[4];
486         __be32                  last_acked_psn;
487         __be32                  ssn;
488         __be32                  params2;
489         __be32                  rnr_nextrecvpsn;
490         __be32                  xrcd;
491         __be32                  cqn_recv;
492         __be64                  db_rec_addr;
493         __be32                  qkey;
494         __be32                  rq_type_srqn;
495         __be32                  rmsn;
496         __be16                  hw_sq_wqe_counter;
497         __be16                  sw_sq_wqe_counter;
498         __be16                  hw_rcyclic_byte_counter;
499         __be16                  hw_rq_counter;
500         __be16                  sw_rcyclic_byte_counter;
501         __be16                  sw_rq_counter;
502         u8                      rsvd0[5];
503         u8                      cgs;
504         u8                      cs_req;
505         u8                      cs_res;
506         __be64                  dc_access_key;
507         u8                      rsvd1[24];
508 };
509
510 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
511 {
512         return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
513 }
514
515 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
516 {
517         return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
518 }
519
520 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
521                         struct mlx5_core_qp *qp,
522                         u32 *in,
523                         int inlen);
524 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
525                         u32 opt_param_mask, void *qpc,
526                         struct mlx5_core_qp *qp);
527 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
528                          struct mlx5_core_qp *qp);
529 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
530                        u32 *out, int outlen);
531
532 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
533 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
534 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
535 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
536 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
537 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
538 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
539                                 struct mlx5_core_qp *rq);
540 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
541                                   struct mlx5_core_qp *rq);
542 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
543                                 struct mlx5_core_qp *sq);
544 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
545                                   struct mlx5_core_qp *sq);
546 int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id);
547 int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id);
548 int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id,
549                               int reset, void *out, int out_size);
550 int mlx5_core_query_out_of_buffer(struct mlx5_core_dev *dev, u16 counter_id,
551                                   u32 *out_of_buffer);
552
553 static inline const char *mlx5_qp_type_str(int type)
554 {
555         switch (type) {
556         case MLX5_QP_ST_RC: return "RC";
557         case MLX5_QP_ST_UC: return "C";
558         case MLX5_QP_ST_UD: return "UD";
559         case MLX5_QP_ST_XRC: return "XRC";
560         case MLX5_QP_ST_MLX: return "MLX";
561         case MLX5_QP_ST_QP0: return "QP0";
562         case MLX5_QP_ST_QP1: return "QP1";
563         case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
564         case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
565         case MLX5_QP_ST_SNIFFER: return "SNIFFER";
566         case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
567         case MLX5_QP_ST_PTP_1588: return "PTP_1588";
568         case MLX5_QP_ST_REG_UMR: return "REG_UMR";
569         default: return "Invalid transport type";
570         }
571 }
572
573 static inline const char *mlx5_qp_state_str(int state)
574 {
575         switch (state) {
576         case MLX5_QP_STATE_RST:
577         return "RST";
578         case MLX5_QP_STATE_INIT:
579         return "INIT";
580         case MLX5_QP_STATE_RTR:
581         return "RTR";
582         case MLX5_QP_STATE_RTS:
583         return "RTS";
584         case MLX5_QP_STATE_SQER:
585         return "SQER";
586         case MLX5_QP_STATE_SQD:
587         return "SQD";
588         case MLX5_QP_STATE_ERR:
589         return "ERR";
590         case MLX5_QP_STATE_SQ_DRAINING:
591         return "SQ_DRAINING";
592         case MLX5_QP_STATE_SUSPENDED:
593         return "SUSPENDED";
594         default: return "Invalid QP state";
595         }
596 }
597
598 #endif /* MLX5_QP_H */