2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
84 MLX5_OBJ_TYPE_UCTX = 0x0004,
85 MLX5_OBJ_TYPE_UMEM = 0x0005,
89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
91 MLX5_CMD_OP_INIT_HCA = 0x102,
92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
93 MLX5_CMD_OP_ENABLE_HCA = 0x104,
94 MLX5_CMD_OP_DISABLE_HCA = 0x105,
95 MLX5_CMD_OP_QUERY_PAGES = 0x107,
96 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
97 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
98 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
99 MLX5_CMD_OP_SET_ISSI = 0x10b,
100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
101 MLX5_CMD_OP_CREATE_MKEY = 0x200,
102 MLX5_CMD_OP_QUERY_MKEY = 0x201,
103 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
108 MLX5_CMD_OP_CREATE_EQ = 0x301,
109 MLX5_CMD_OP_DESTROY_EQ = 0x302,
110 MLX5_CMD_OP_QUERY_EQ = 0x303,
111 MLX5_CMD_OP_GEN_EQE = 0x304,
112 MLX5_CMD_OP_CREATE_CQ = 0x400,
113 MLX5_CMD_OP_DESTROY_CQ = 0x401,
114 MLX5_CMD_OP_QUERY_CQ = 0x402,
115 MLX5_CMD_OP_MODIFY_CQ = 0x403,
116 MLX5_CMD_OP_CREATE_QP = 0x500,
117 MLX5_CMD_OP_DESTROY_QP = 0x501,
118 MLX5_CMD_OP_RST2INIT_QP = 0x502,
119 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
120 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
121 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
123 MLX5_CMD_OP_2ERR_QP = 0x507,
124 MLX5_CMD_OP_2RST_QP = 0x50a,
125 MLX5_CMD_OP_QUERY_QP = 0x50b,
126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
128 MLX5_CMD_OP_CREATE_PSV = 0x600,
129 MLX5_CMD_OP_DESTROY_PSV = 0x601,
130 MLX5_CMD_OP_CREATE_SRQ = 0x700,
131 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
132 MLX5_CMD_OP_QUERY_SRQ = 0x702,
133 MLX5_CMD_OP_ARM_RQ = 0x703,
134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
138 MLX5_CMD_OP_CREATE_DCT = 0x710,
139 MLX5_CMD_OP_DESTROY_DCT = 0x711,
140 MLX5_CMD_OP_DRAIN_DCT = 0x712,
141 MLX5_CMD_OP_QUERY_DCT = 0x713,
142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
143 MLX5_CMD_OP_CREATE_XRQ = 0x717,
144 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
145 MLX5_CMD_OP_QUERY_XRQ = 0x719,
146 MLX5_CMD_OP_ARM_XRQ = 0x71a,
147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
172 MLX5_CMD_OP_ALLOC_PD = 0x800,
173 MLX5_CMD_OP_DEALLOC_PD = 0x801,
174 MLX5_CMD_OP_ALLOC_UAR = 0x802,
175 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
177 MLX5_CMD_OP_ACCESS_REG = 0x805,
178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
181 MLX5_CMD_OP_MAD_IFC = 0x50d,
182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
184 MLX5_CMD_OP_NOP = 0x80d,
185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
199 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
201 MLX5_CMD_OP_CREATE_LAG = 0x840,
202 MLX5_CMD_OP_MODIFY_LAG = 0x841,
203 MLX5_CMD_OP_QUERY_LAG = 0x842,
204 MLX5_CMD_OP_DESTROY_LAG = 0x843,
205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
207 MLX5_CMD_OP_CREATE_TIR = 0x900,
208 MLX5_CMD_OP_MODIFY_TIR = 0x901,
209 MLX5_CMD_OP_DESTROY_TIR = 0x902,
210 MLX5_CMD_OP_QUERY_TIR = 0x903,
211 MLX5_CMD_OP_CREATE_SQ = 0x904,
212 MLX5_CMD_OP_MODIFY_SQ = 0x905,
213 MLX5_CMD_OP_DESTROY_SQ = 0x906,
214 MLX5_CMD_OP_QUERY_SQ = 0x907,
215 MLX5_CMD_OP_CREATE_RQ = 0x908,
216 MLX5_CMD_OP_MODIFY_RQ = 0x909,
217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
218 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
219 MLX5_CMD_OP_QUERY_RQ = 0x90b,
220 MLX5_CMD_OP_CREATE_RMP = 0x90c,
221 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
222 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
223 MLX5_CMD_OP_QUERY_RMP = 0x90f,
224 MLX5_CMD_OP_CREATE_TIS = 0x912,
225 MLX5_CMD_OP_MODIFY_TIS = 0x913,
226 MLX5_CMD_OP_DESTROY_TIS = 0x914,
227 MLX5_CMD_OP_QUERY_TIS = 0x915,
228 MLX5_CMD_OP_CREATE_RQT = 0x916,
229 MLX5_CMD_OP_MODIFY_RQT = 0x917,
230 MLX5_CMD_OP_DESTROY_RQT = 0x918,
231 MLX5_CMD_OP_QUERY_RQT = 0x919,
232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
246 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
247 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
263 struct mlx5_ifc_flow_table_fields_supported_bits {
266 u8 outer_ether_type[0x1];
267 u8 outer_ip_version[0x1];
268 u8 outer_first_prio[0x1];
269 u8 outer_first_cfi[0x1];
270 u8 outer_first_vid[0x1];
271 u8 outer_ipv4_ttl[0x1];
272 u8 outer_second_prio[0x1];
273 u8 outer_second_cfi[0x1];
274 u8 outer_second_vid[0x1];
275 u8 reserved_at_b[0x1];
279 u8 outer_ip_protocol[0x1];
280 u8 outer_ip_ecn[0x1];
281 u8 outer_ip_dscp[0x1];
282 u8 outer_udp_sport[0x1];
283 u8 outer_udp_dport[0x1];
284 u8 outer_tcp_sport[0x1];
285 u8 outer_tcp_dport[0x1];
286 u8 outer_tcp_flags[0x1];
287 u8 outer_gre_protocol[0x1];
288 u8 outer_gre_key[0x1];
289 u8 outer_vxlan_vni[0x1];
290 u8 reserved_at_1a[0x5];
291 u8 source_eswitch_port[0x1];
295 u8 inner_ether_type[0x1];
296 u8 inner_ip_version[0x1];
297 u8 inner_first_prio[0x1];
298 u8 inner_first_cfi[0x1];
299 u8 inner_first_vid[0x1];
300 u8 reserved_at_27[0x1];
301 u8 inner_second_prio[0x1];
302 u8 inner_second_cfi[0x1];
303 u8 inner_second_vid[0x1];
304 u8 reserved_at_2b[0x1];
308 u8 inner_ip_protocol[0x1];
309 u8 inner_ip_ecn[0x1];
310 u8 inner_ip_dscp[0x1];
311 u8 inner_udp_sport[0x1];
312 u8 inner_udp_dport[0x1];
313 u8 inner_tcp_sport[0x1];
314 u8 inner_tcp_dport[0x1];
315 u8 inner_tcp_flags[0x1];
316 u8 reserved_at_37[0x9];
318 u8 reserved_at_40[0x5];
319 u8 outer_first_mpls_over_udp[0x4];
320 u8 outer_first_mpls_over_gre[0x4];
321 u8 inner_first_mpls[0x4];
322 u8 outer_first_mpls[0x4];
323 u8 reserved_at_55[0x2];
324 u8 outer_esp_spi[0x1];
325 u8 reserved_at_58[0x2];
328 u8 reserved_at_5b[0x25];
331 struct mlx5_ifc_flow_table_prop_layout_bits {
333 u8 reserved_at_1[0x1];
334 u8 flow_counter[0x1];
335 u8 flow_modify_en[0x1];
337 u8 identified_miss_table_mode[0x1];
338 u8 flow_table_modify[0x1];
341 u8 reserved_at_9[0x1];
344 u8 reserved_at_c[0x1];
347 u8 reserved_at_f[0x11];
349 u8 reserved_at_20[0x2];
350 u8 log_max_ft_size[0x6];
351 u8 log_max_modify_header_context[0x8];
352 u8 max_modify_header_actions[0x8];
353 u8 max_ft_level[0x8];
355 u8 reserved_at_40[0x20];
357 u8 reserved_at_60[0x18];
358 u8 log_max_ft_num[0x8];
360 u8 reserved_at_80[0x18];
361 u8 log_max_destination[0x8];
363 u8 log_max_flow_counter[0x8];
364 u8 reserved_at_a8[0x10];
365 u8 log_max_flow[0x8];
367 u8 reserved_at_c0[0x40];
369 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
371 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
374 struct mlx5_ifc_odp_per_transport_service_cap_bits {
381 u8 reserved_at_6[0x1a];
384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
409 u8 reserved_at_c0[0x18];
410 u8 ttl_hoplimit[0x8];
415 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
417 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
420 struct mlx5_ifc_fte_match_set_misc_bits {
421 u8 reserved_at_0[0x8];
424 u8 source_eswitch_owner_vhca_id[0x10];
425 u8 source_port[0x10];
427 u8 outer_second_prio[0x3];
428 u8 outer_second_cfi[0x1];
429 u8 outer_second_vid[0xc];
430 u8 inner_second_prio[0x3];
431 u8 inner_second_cfi[0x1];
432 u8 inner_second_vid[0xc];
434 u8 outer_second_cvlan_tag[0x1];
435 u8 inner_second_cvlan_tag[0x1];
436 u8 outer_second_svlan_tag[0x1];
437 u8 inner_second_svlan_tag[0x1];
438 u8 reserved_at_64[0xc];
439 u8 gre_protocol[0x10];
445 u8 reserved_at_b8[0x8];
447 u8 reserved_at_c0[0x20];
449 u8 reserved_at_e0[0xc];
450 u8 outer_ipv6_flow_label[0x14];
452 u8 reserved_at_100[0xc];
453 u8 inner_ipv6_flow_label[0x14];
455 u8 reserved_at_120[0x28];
457 u8 reserved_at_160[0x20];
458 u8 outer_esp_spi[0x20];
459 u8 reserved_at_1a0[0x60];
462 struct mlx5_ifc_fte_match_mpls_bits {
469 struct mlx5_ifc_fte_match_set_misc2_bits {
470 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
472 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
476 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
478 u8 reserved_at_80[0x100];
480 u8 metadata_reg_a[0x20];
482 u8 reserved_at_1a0[0x60];
485 struct mlx5_ifc_cmd_pas_bits {
489 u8 reserved_at_34[0xc];
492 struct mlx5_ifc_uint64_bits {
499 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
500 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
501 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
502 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
503 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
504 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
505 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
506 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
507 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
508 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
511 struct mlx5_ifc_ads_bits {
514 u8 reserved_at_2[0xe];
517 u8 reserved_at_20[0x8];
523 u8 reserved_at_45[0x3];
524 u8 src_addr_index[0x8];
525 u8 reserved_at_50[0x4];
529 u8 reserved_at_60[0x4];
533 u8 rgid_rip[16][0x8];
535 u8 reserved_at_100[0x4];
538 u8 reserved_at_106[0x1];
547 u8 vhca_port_num[0x8];
553 struct mlx5_ifc_flow_table_nic_cap_bits {
554 u8 nic_rx_multi_path_tirs[0x1];
555 u8 nic_rx_multi_path_tirs_fts[0x1];
556 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
557 u8 reserved_at_3[0x1fd];
559 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
561 u8 reserved_at_400[0x200];
563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
567 u8 reserved_at_a00[0x200];
569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
571 u8 reserved_at_e00[0x7200];
574 struct mlx5_ifc_flow_table_eswitch_cap_bits {
575 u8 reserved_at_0[0x1c];
576 u8 fdb_multi_path_to_table[0x1];
577 u8 reserved_at_1d[0x1e3];
579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
581 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
583 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
585 u8 reserved_at_800[0x7800];
588 struct mlx5_ifc_e_switch_cap_bits {
589 u8 vport_svlan_strip[0x1];
590 u8 vport_cvlan_strip[0x1];
591 u8 vport_svlan_insert[0x1];
592 u8 vport_cvlan_insert_if_not_exist[0x1];
593 u8 vport_cvlan_insert_overwrite[0x1];
594 u8 reserved_at_5[0x18];
595 u8 merged_eswitch[0x1];
596 u8 nic_vport_node_guid_modify[0x1];
597 u8 nic_vport_port_guid_modify[0x1];
599 u8 vxlan_encap_decap[0x1];
600 u8 nvgre_encap_decap[0x1];
601 u8 reserved_at_22[0x9];
602 u8 log_max_encap_headers[0x5];
604 u8 max_encap_header_size[0xa];
606 u8 reserved_40[0x7c0];
610 struct mlx5_ifc_qos_cap_bits {
611 u8 packet_pacing[0x1];
612 u8 esw_scheduling[0x1];
613 u8 esw_bw_share[0x1];
614 u8 esw_rate_limit[0x1];
615 u8 reserved_at_4[0x1];
616 u8 packet_pacing_burst_bound[0x1];
617 u8 packet_pacing_typical_size[0x1];
618 u8 reserved_at_7[0x19];
620 u8 reserved_at_20[0x20];
622 u8 packet_pacing_max_rate[0x20];
624 u8 packet_pacing_min_rate[0x20];
626 u8 reserved_at_80[0x10];
627 u8 packet_pacing_rate_table_size[0x10];
629 u8 esw_element_type[0x10];
630 u8 esw_tsar_type[0x10];
632 u8 reserved_at_c0[0x10];
633 u8 max_qos_para_vport[0x10];
635 u8 max_tsar_bw_share[0x20];
637 u8 reserved_at_100[0x700];
640 struct mlx5_ifc_debug_cap_bits {
641 u8 reserved_at_0[0x20];
643 u8 reserved_at_20[0x2];
644 u8 stall_detect[0x1];
645 u8 reserved_at_23[0x1d];
647 u8 reserved_at_40[0x7c0];
650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
654 u8 lro_psh_flag[0x1];
655 u8 lro_time_stamp[0x1];
656 u8 reserved_at_5[0x2];
657 u8 wqe_vlan_insert[0x1];
658 u8 self_lb_en_modifiable[0x1];
659 u8 reserved_at_9[0x2];
661 u8 multi_pkt_send_wqe[0x2];
662 u8 wqe_inline_mode[0x2];
663 u8 rss_ind_tbl_cap[0x4];
666 u8 enhanced_multi_pkt_send_wqe[0x1];
667 u8 tunnel_lso_const_out_ip_id[0x1];
668 u8 reserved_at_1c[0x2];
669 u8 tunnel_stateless_gre[0x1];
670 u8 tunnel_stateless_vxlan[0x1];
675 u8 reserved_at_23[0xd];
676 u8 max_vxlan_udp_ports[0x8];
677 u8 reserved_at_38[0x6];
678 u8 max_geneve_opt_len[0x1];
679 u8 tunnel_stateless_geneve_rx[0x1];
681 u8 reserved_at_40[0x10];
682 u8 lro_min_mss_size[0x10];
684 u8 reserved_at_60[0x120];
686 u8 lro_timer_supported_periods[4][0x20];
688 u8 reserved_at_200[0x600];
691 struct mlx5_ifc_roce_cap_bits {
693 u8 reserved_at_1[0x1f];
695 u8 reserved_at_20[0x60];
697 u8 reserved_at_80[0xc];
699 u8 reserved_at_90[0x8];
700 u8 roce_version[0x8];
702 u8 reserved_at_a0[0x10];
703 u8 r_roce_dest_udp_port[0x10];
705 u8 r_roce_max_src_udp_port[0x10];
706 u8 r_roce_min_src_udp_port[0x10];
708 u8 reserved_at_e0[0x10];
709 u8 roce_address_table_size[0x10];
711 u8 reserved_at_100[0x700];
714 struct mlx5_ifc_device_mem_cap_bits {
716 u8 reserved_at_1[0x1f];
718 u8 reserved_at_20[0xb];
719 u8 log_min_memic_alloc_size[0x5];
720 u8 reserved_at_30[0x8];
721 u8 log_max_memic_addr_alignment[0x8];
723 u8 memic_bar_start_addr[0x40];
725 u8 memic_bar_size[0x20];
727 u8 max_memic_size[0x20];
729 u8 reserved_at_c0[0x740];
733 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
734 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
735 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
736 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
737 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
738 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
739 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
740 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
741 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
756 struct mlx5_ifc_atomic_caps_bits {
757 u8 reserved_at_0[0x40];
759 u8 atomic_req_8B_endianness_mode[0x2];
760 u8 reserved_at_42[0x4];
761 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
763 u8 reserved_at_47[0x19];
765 u8 reserved_at_60[0x20];
767 u8 reserved_at_80[0x10];
768 u8 atomic_operations[0x10];
770 u8 reserved_at_a0[0x10];
771 u8 atomic_size_qp[0x10];
773 u8 reserved_at_c0[0x10];
774 u8 atomic_size_dc[0x10];
776 u8 reserved_at_e0[0x720];
779 struct mlx5_ifc_odp_cap_bits {
780 u8 reserved_at_0[0x40];
783 u8 reserved_at_41[0x1f];
785 u8 reserved_at_60[0x20];
787 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
789 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
791 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
793 u8 reserved_at_e0[0x720];
796 struct mlx5_ifc_calc_op {
797 u8 reserved_at_0[0x10];
798 u8 reserved_at_10[0x9];
799 u8 op_swap_endianness[0x1];
808 struct mlx5_ifc_vector_calc_cap_bits {
810 u8 reserved_at_1[0x1f];
811 u8 reserved_at_20[0x8];
812 u8 max_vec_count[0x8];
813 u8 reserved_at_30[0xd];
814 u8 max_chunk_size[0x3];
815 struct mlx5_ifc_calc_op calc0;
816 struct mlx5_ifc_calc_op calc1;
817 struct mlx5_ifc_calc_op calc2;
818 struct mlx5_ifc_calc_op calc3;
820 u8 reserved_at_e0[0x720];
824 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
825 MLX5_WQ_TYPE_CYCLIC = 0x1,
826 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
827 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
831 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
832 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
836 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
837 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
838 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
839 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
840 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
844 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
845 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
846 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
847 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
848 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
849 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
853 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
854 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
858 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
859 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
860 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
864 MLX5_CAP_PORT_TYPE_IB = 0x0,
865 MLX5_CAP_PORT_TYPE_ETH = 0x1,
869 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
870 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
871 MLX5_CAP_UMR_FENCE_NONE = 0x2,
874 struct mlx5_ifc_cmd_hca_cap_bits {
875 u8 reserved_at_0[0x30];
878 u8 reserved_at_40[0x40];
880 u8 log_max_srq_sz[0x8];
881 u8 log_max_qp_sz[0x8];
882 u8 reserved_at_90[0xb];
885 u8 reserved_at_a0[0xb];
887 u8 reserved_at_b0[0x10];
889 u8 reserved_at_c0[0x8];
890 u8 log_max_cq_sz[0x8];
891 u8 reserved_at_d0[0xb];
894 u8 log_max_eq_sz[0x8];
895 u8 reserved_at_e8[0x2];
896 u8 log_max_mkey[0x6];
897 u8 reserved_at_f0[0x8];
898 u8 dump_fill_mkey[0x1];
899 u8 reserved_at_f9[0x3];
902 u8 max_indirection[0x8];
903 u8 fixed_buffer_size[0x1];
904 u8 log_max_mrw_sz[0x7];
905 u8 force_teardown[0x1];
906 u8 reserved_at_111[0x1];
907 u8 log_max_bsf_list_size[0x6];
908 u8 umr_extended_translation_offset[0x1];
910 u8 log_max_klm_list_size[0x6];
912 u8 reserved_at_120[0xa];
913 u8 log_max_ra_req_dc[0x6];
914 u8 reserved_at_130[0xa];
915 u8 log_max_ra_res_dc[0x6];
917 u8 reserved_at_140[0xa];
918 u8 log_max_ra_req_qp[0x6];
919 u8 reserved_at_150[0xa];
920 u8 log_max_ra_res_qp[0x6];
923 u8 cc_query_allowed[0x1];
924 u8 cc_modify_allowed[0x1];
926 u8 cache_line_128byte[0x1];
927 u8 reserved_at_165[0xa];
929 u8 gid_table_size[0x10];
931 u8 out_of_seq_cnt[0x1];
932 u8 vport_counters[0x1];
933 u8 retransmission_q_counters[0x1];
935 u8 modify_rq_counter_set_id[0x1];
936 u8 rq_delay_drop[0x1];
938 u8 pkey_table_size[0x10];
940 u8 vport_group_manager[0x1];
941 u8 vhca_group_manager[0x1];
944 u8 vnic_env_queue_counters[0x1];
946 u8 nic_flow_table[0x1];
947 u8 eswitch_manager[0x1];
948 u8 device_memory[0x1];
951 u8 local_ca_ack_delay[0x5];
952 u8 port_module_event[0x1];
953 u8 enhanced_error_q_counters[0x1];
955 u8 reserved_at_1b3[0x1];
956 u8 disable_link_up[0x1];
961 u8 reserved_at_1c0[0x1];
965 u8 reserved_at_1c8[0x4];
967 u8 temp_warn_event[0x1];
969 u8 general_notification_event[0x1];
970 u8 reserved_at_1d3[0x2];
974 u8 reserved_at_1d8[0x1];
983 u8 stat_rate_support[0x10];
984 u8 reserved_at_1f0[0xc];
987 u8 compact_address_vector[0x1];
989 u8 reserved_at_202[0x1];
990 u8 ipoib_enhanced_offloads[0x1];
991 u8 ipoib_basic_offloads[0x1];
992 u8 reserved_at_205[0x1];
993 u8 repeated_block_disabled[0x1];
994 u8 umr_modify_entity_size_disabled[0x1];
995 u8 umr_modify_atomic_disabled[0x1];
996 u8 umr_indirect_mkey_disabled[0x1];
998 u8 reserved_at_20c[0x3];
999 u8 drain_sigerr[0x1];
1000 u8 cmdif_checksum[0x2];
1002 u8 reserved_at_213[0x1];
1003 u8 wq_signature[0x1];
1004 u8 sctr_data_cqe[0x1];
1005 u8 reserved_at_216[0x1];
1011 u8 eth_net_offloads[0x1];
1014 u8 reserved_at_21f[0x1];
1018 u8 cq_moderation[0x1];
1019 u8 reserved_at_223[0x3];
1020 u8 cq_eq_remap[0x1];
1022 u8 block_lb_mc[0x1];
1023 u8 reserved_at_229[0x1];
1024 u8 scqe_break_moderation[0x1];
1025 u8 cq_period_start_from_cqe[0x1];
1027 u8 reserved_at_22d[0x1];
1029 u8 vector_calc[0x1];
1030 u8 umr_ptr_rlky[0x1];
1032 u8 reserved_at_232[0x4];
1035 u8 set_deth_sqpn[0x1];
1036 u8 reserved_at_239[0x3];
1043 u8 reserved_at_241[0x9];
1045 u8 reserved_at_250[0x8];
1049 u8 driver_version[0x1];
1050 u8 pad_tx_eth_packet[0x1];
1051 u8 reserved_at_263[0x8];
1052 u8 log_bf_reg_size[0x5];
1054 u8 reserved_at_270[0xb];
1056 u8 num_lag_ports[0x4];
1058 u8 reserved_at_280[0x10];
1059 u8 max_wqe_sz_sq[0x10];
1061 u8 reserved_at_2a0[0x10];
1062 u8 max_wqe_sz_rq[0x10];
1064 u8 max_flow_counter_31_16[0x10];
1065 u8 max_wqe_sz_sq_dc[0x10];
1067 u8 reserved_at_2e0[0x7];
1068 u8 max_qp_mcg[0x19];
1070 u8 reserved_at_300[0x18];
1071 u8 log_max_mcg[0x8];
1073 u8 reserved_at_320[0x3];
1074 u8 log_max_transport_domain[0x5];
1075 u8 reserved_at_328[0x3];
1077 u8 reserved_at_330[0xb];
1078 u8 log_max_xrcd[0x5];
1080 u8 nic_receive_steering_discard[0x1];
1081 u8 receive_discard_vport_down[0x1];
1082 u8 transmit_discard_vport_down[0x1];
1083 u8 reserved_at_343[0x5];
1084 u8 log_max_flow_counter_bulk[0x8];
1085 u8 max_flow_counter_15_0[0x10];
1088 u8 reserved_at_360[0x3];
1090 u8 reserved_at_368[0x3];
1092 u8 reserved_at_370[0x3];
1093 u8 log_max_tir[0x5];
1094 u8 reserved_at_378[0x3];
1095 u8 log_max_tis[0x5];
1097 u8 basic_cyclic_rcv_wqe[0x1];
1098 u8 reserved_at_381[0x2];
1099 u8 log_max_rmp[0x5];
1100 u8 reserved_at_388[0x3];
1101 u8 log_max_rqt[0x5];
1102 u8 reserved_at_390[0x3];
1103 u8 log_max_rqt_size[0x5];
1104 u8 reserved_at_398[0x3];
1105 u8 log_max_tis_per_sq[0x5];
1107 u8 ext_stride_num_range[0x1];
1108 u8 reserved_at_3a1[0x2];
1109 u8 log_max_stride_sz_rq[0x5];
1110 u8 reserved_at_3a8[0x3];
1111 u8 log_min_stride_sz_rq[0x5];
1112 u8 reserved_at_3b0[0x3];
1113 u8 log_max_stride_sz_sq[0x5];
1114 u8 reserved_at_3b8[0x3];
1115 u8 log_min_stride_sz_sq[0x5];
1118 u8 reserved_at_3c1[0x2];
1119 u8 log_max_hairpin_queues[0x5];
1120 u8 reserved_at_3c8[0x3];
1121 u8 log_max_hairpin_wq_data_sz[0x5];
1122 u8 reserved_at_3d0[0x3];
1123 u8 log_max_hairpin_num_packets[0x5];
1124 u8 reserved_at_3d8[0x3];
1125 u8 log_max_wq_sz[0x5];
1127 u8 nic_vport_change_event[0x1];
1128 u8 disable_local_lb_uc[0x1];
1129 u8 disable_local_lb_mc[0x1];
1130 u8 log_min_hairpin_wq_data_sz[0x5];
1131 u8 reserved_at_3e8[0x3];
1132 u8 log_max_vlan_list[0x5];
1133 u8 reserved_at_3f0[0x3];
1134 u8 log_max_current_mc_list[0x5];
1135 u8 reserved_at_3f8[0x3];
1136 u8 log_max_current_uc_list[0x5];
1138 u8 general_obj_types[0x40];
1140 u8 reserved_at_440[0x20];
1142 u8 reserved_at_460[0x10];
1143 u8 max_num_eqs[0x10];
1145 u8 reserved_at_480[0x3];
1146 u8 log_max_l2_table[0x5];
1147 u8 reserved_at_488[0x8];
1148 u8 log_uar_page_sz[0x10];
1150 u8 reserved_at_4a0[0x20];
1151 u8 device_frequency_mhz[0x20];
1152 u8 device_frequency_khz[0x20];
1154 u8 reserved_at_500[0x20];
1155 u8 num_of_uars_per_page[0x20];
1157 u8 flex_parser_protocols[0x20];
1158 u8 reserved_at_560[0x20];
1160 u8 reserved_at_580[0x3c];
1161 u8 mini_cqe_resp_stride_index[0x1];
1162 u8 cqe_128_always[0x1];
1163 u8 cqe_compression_128[0x1];
1164 u8 cqe_compression[0x1];
1166 u8 cqe_compression_timeout[0x10];
1167 u8 cqe_compression_max_num[0x10];
1169 u8 reserved_at_5e0[0x10];
1170 u8 tag_matching[0x1];
1171 u8 rndv_offload_rc[0x1];
1172 u8 rndv_offload_dc[0x1];
1173 u8 log_tag_matching_list_sz[0x5];
1174 u8 reserved_at_5f8[0x3];
1175 u8 log_max_xrq[0x5];
1177 u8 affiliate_nic_vport_criteria[0x8];
1178 u8 native_port_num[0x8];
1179 u8 num_vhca_ports[0x8];
1180 u8 reserved_at_618[0x6];
1181 u8 sw_owner_id[0x1];
1182 u8 reserved_at_61f[0x1e1];
1185 enum mlx5_flow_destination_type {
1186 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1187 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1188 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1190 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1191 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1192 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1195 struct mlx5_ifc_dest_format_struct_bits {
1196 u8 destination_type[0x8];
1197 u8 destination_id[0x18];
1198 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1199 u8 reserved_at_21[0xf];
1200 u8 destination_eswitch_owner_vhca_id[0x10];
1203 struct mlx5_ifc_flow_counter_list_bits {
1204 u8 flow_counter_id[0x20];
1206 u8 reserved_at_20[0x20];
1209 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1210 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1211 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1212 u8 reserved_at_0[0x40];
1215 struct mlx5_ifc_fte_match_param_bits {
1216 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1218 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1220 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1222 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1224 u8 reserved_at_800[0x800];
1228 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1229 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1230 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1231 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1232 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1235 struct mlx5_ifc_rx_hash_field_select_bits {
1236 u8 l3_prot_type[0x1];
1237 u8 l4_prot_type[0x1];
1238 u8 selected_fields[0x1e];
1242 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1243 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1247 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1248 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1251 struct mlx5_ifc_wq_bits {
1253 u8 wq_signature[0x1];
1254 u8 end_padding_mode[0x2];
1256 u8 reserved_at_8[0x18];
1258 u8 hds_skip_first_sge[0x1];
1259 u8 log2_hds_buf_size[0x3];
1260 u8 reserved_at_24[0x7];
1261 u8 page_offset[0x5];
1264 u8 reserved_at_40[0x8];
1267 u8 reserved_at_60[0x8];
1272 u8 hw_counter[0x20];
1274 u8 sw_counter[0x20];
1276 u8 reserved_at_100[0xc];
1277 u8 log_wq_stride[0x4];
1278 u8 reserved_at_110[0x3];
1279 u8 log_wq_pg_sz[0x5];
1280 u8 reserved_at_118[0x3];
1283 u8 reserved_at_120[0x3];
1284 u8 log_hairpin_num_packets[0x5];
1285 u8 reserved_at_128[0x3];
1286 u8 log_hairpin_data_sz[0x5];
1288 u8 reserved_at_130[0x4];
1289 u8 log_wqe_num_of_strides[0x4];
1290 u8 two_byte_shift_en[0x1];
1291 u8 reserved_at_139[0x4];
1292 u8 log_wqe_stride_size[0x3];
1294 u8 reserved_at_140[0x4c0];
1296 struct mlx5_ifc_cmd_pas_bits pas[0];
1299 struct mlx5_ifc_rq_num_bits {
1300 u8 reserved_at_0[0x8];
1304 struct mlx5_ifc_mac_address_layout_bits {
1305 u8 reserved_at_0[0x10];
1306 u8 mac_addr_47_32[0x10];
1308 u8 mac_addr_31_0[0x20];
1311 struct mlx5_ifc_vlan_layout_bits {
1312 u8 reserved_at_0[0x14];
1315 u8 reserved_at_20[0x20];
1318 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1319 u8 reserved_at_0[0xa0];
1321 u8 min_time_between_cnps[0x20];
1323 u8 reserved_at_c0[0x12];
1325 u8 reserved_at_d8[0x4];
1326 u8 cnp_prio_mode[0x1];
1327 u8 cnp_802p_prio[0x3];
1329 u8 reserved_at_e0[0x720];
1332 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1333 u8 reserved_at_0[0x60];
1335 u8 reserved_at_60[0x4];
1336 u8 clamp_tgt_rate[0x1];
1337 u8 reserved_at_65[0x3];
1338 u8 clamp_tgt_rate_after_time_inc[0x1];
1339 u8 reserved_at_69[0x17];
1341 u8 reserved_at_80[0x20];
1343 u8 rpg_time_reset[0x20];
1345 u8 rpg_byte_reset[0x20];
1347 u8 rpg_threshold[0x20];
1349 u8 rpg_max_rate[0x20];
1351 u8 rpg_ai_rate[0x20];
1353 u8 rpg_hai_rate[0x20];
1357 u8 rpg_min_dec_fac[0x20];
1359 u8 rpg_min_rate[0x20];
1361 u8 reserved_at_1c0[0xe0];
1363 u8 rate_to_set_on_first_cnp[0x20];
1367 u8 dce_tcp_rtt[0x20];
1369 u8 rate_reduce_monitor_period[0x20];
1371 u8 reserved_at_320[0x20];
1373 u8 initial_alpha_value[0x20];
1375 u8 reserved_at_360[0x4a0];
1378 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1379 u8 reserved_at_0[0x80];
1381 u8 rppp_max_rps[0x20];
1383 u8 rpg_time_reset[0x20];
1385 u8 rpg_byte_reset[0x20];
1387 u8 rpg_threshold[0x20];
1389 u8 rpg_max_rate[0x20];
1391 u8 rpg_ai_rate[0x20];
1393 u8 rpg_hai_rate[0x20];
1397 u8 rpg_min_dec_fac[0x20];
1399 u8 rpg_min_rate[0x20];
1401 u8 reserved_at_1c0[0x640];
1405 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1406 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1407 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1410 struct mlx5_ifc_resize_field_select_bits {
1411 u8 resize_field_select[0x20];
1415 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1416 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1417 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1418 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1421 struct mlx5_ifc_modify_field_select_bits {
1422 u8 modify_field_select[0x20];
1425 struct mlx5_ifc_field_select_r_roce_np_bits {
1426 u8 field_select_r_roce_np[0x20];
1429 struct mlx5_ifc_field_select_r_roce_rp_bits {
1430 u8 field_select_r_roce_rp[0x20];
1434 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1435 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1436 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1437 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1438 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1439 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1440 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1446 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1447 u8 field_select_8021qaurp[0x20];
1450 struct mlx5_ifc_phys_layer_cntrs_bits {
1451 u8 time_since_last_clear_high[0x20];
1453 u8 time_since_last_clear_low[0x20];
1455 u8 symbol_errors_high[0x20];
1457 u8 symbol_errors_low[0x20];
1459 u8 sync_headers_errors_high[0x20];
1461 u8 sync_headers_errors_low[0x20];
1463 u8 edpl_bip_errors_lane0_high[0x20];
1465 u8 edpl_bip_errors_lane0_low[0x20];
1467 u8 edpl_bip_errors_lane1_high[0x20];
1469 u8 edpl_bip_errors_lane1_low[0x20];
1471 u8 edpl_bip_errors_lane2_high[0x20];
1473 u8 edpl_bip_errors_lane2_low[0x20];
1475 u8 edpl_bip_errors_lane3_high[0x20];
1477 u8 edpl_bip_errors_lane3_low[0x20];
1479 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1481 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1483 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1485 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1487 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1489 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1491 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1493 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1495 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1497 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1499 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1501 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1503 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1505 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1507 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1509 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1511 u8 rs_fec_corrected_blocks_high[0x20];
1513 u8 rs_fec_corrected_blocks_low[0x20];
1515 u8 rs_fec_uncorrectable_blocks_high[0x20];
1517 u8 rs_fec_uncorrectable_blocks_low[0x20];
1519 u8 rs_fec_no_errors_blocks_high[0x20];
1521 u8 rs_fec_no_errors_blocks_low[0x20];
1523 u8 rs_fec_single_error_blocks_high[0x20];
1525 u8 rs_fec_single_error_blocks_low[0x20];
1527 u8 rs_fec_corrected_symbols_total_high[0x20];
1529 u8 rs_fec_corrected_symbols_total_low[0x20];
1531 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1533 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1535 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1537 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1539 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1541 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1543 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1545 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1547 u8 link_down_events[0x20];
1549 u8 successful_recovery_events[0x20];
1551 u8 reserved_at_640[0x180];
1554 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1555 u8 time_since_last_clear_high[0x20];
1557 u8 time_since_last_clear_low[0x20];
1559 u8 phy_received_bits_high[0x20];
1561 u8 phy_received_bits_low[0x20];
1563 u8 phy_symbol_errors_high[0x20];
1565 u8 phy_symbol_errors_low[0x20];
1567 u8 phy_corrected_bits_high[0x20];
1569 u8 phy_corrected_bits_low[0x20];
1571 u8 phy_corrected_bits_lane0_high[0x20];
1573 u8 phy_corrected_bits_lane0_low[0x20];
1575 u8 phy_corrected_bits_lane1_high[0x20];
1577 u8 phy_corrected_bits_lane1_low[0x20];
1579 u8 phy_corrected_bits_lane2_high[0x20];
1581 u8 phy_corrected_bits_lane2_low[0x20];
1583 u8 phy_corrected_bits_lane3_high[0x20];
1585 u8 phy_corrected_bits_lane3_low[0x20];
1587 u8 reserved_at_200[0x5c0];
1590 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1591 u8 symbol_error_counter[0x10];
1593 u8 link_error_recovery_counter[0x8];
1595 u8 link_downed_counter[0x8];
1597 u8 port_rcv_errors[0x10];
1599 u8 port_rcv_remote_physical_errors[0x10];
1601 u8 port_rcv_switch_relay_errors[0x10];
1603 u8 port_xmit_discards[0x10];
1605 u8 port_xmit_constraint_errors[0x8];
1607 u8 port_rcv_constraint_errors[0x8];
1609 u8 reserved_at_70[0x8];
1611 u8 link_overrun_errors[0x8];
1613 u8 reserved_at_80[0x10];
1615 u8 vl_15_dropped[0x10];
1617 u8 reserved_at_a0[0x80];
1619 u8 port_xmit_wait[0x20];
1622 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1623 u8 transmit_queue_high[0x20];
1625 u8 transmit_queue_low[0x20];
1627 u8 reserved_at_40[0x780];
1630 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1631 u8 rx_octets_high[0x20];
1633 u8 rx_octets_low[0x20];
1635 u8 reserved_at_40[0xc0];
1637 u8 rx_frames_high[0x20];
1639 u8 rx_frames_low[0x20];
1641 u8 tx_octets_high[0x20];
1643 u8 tx_octets_low[0x20];
1645 u8 reserved_at_180[0xc0];
1647 u8 tx_frames_high[0x20];
1649 u8 tx_frames_low[0x20];
1651 u8 rx_pause_high[0x20];
1653 u8 rx_pause_low[0x20];
1655 u8 rx_pause_duration_high[0x20];
1657 u8 rx_pause_duration_low[0x20];
1659 u8 tx_pause_high[0x20];
1661 u8 tx_pause_low[0x20];
1663 u8 tx_pause_duration_high[0x20];
1665 u8 tx_pause_duration_low[0x20];
1667 u8 rx_pause_transition_high[0x20];
1669 u8 rx_pause_transition_low[0x20];
1671 u8 reserved_at_3c0[0x40];
1673 u8 device_stall_minor_watermark_cnt_high[0x20];
1675 u8 device_stall_minor_watermark_cnt_low[0x20];
1677 u8 device_stall_critical_watermark_cnt_high[0x20];
1679 u8 device_stall_critical_watermark_cnt_low[0x20];
1681 u8 reserved_at_480[0x340];
1684 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1685 u8 port_transmit_wait_high[0x20];
1687 u8 port_transmit_wait_low[0x20];
1689 u8 reserved_at_40[0x100];
1691 u8 rx_buffer_almost_full_high[0x20];
1693 u8 rx_buffer_almost_full_low[0x20];
1695 u8 rx_buffer_full_high[0x20];
1697 u8 rx_buffer_full_low[0x20];
1699 u8 rx_icrc_encapsulated_high[0x20];
1701 u8 rx_icrc_encapsulated_low[0x20];
1703 u8 reserved_at_200[0x5c0];
1706 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1707 u8 dot3stats_alignment_errors_high[0x20];
1709 u8 dot3stats_alignment_errors_low[0x20];
1711 u8 dot3stats_fcs_errors_high[0x20];
1713 u8 dot3stats_fcs_errors_low[0x20];
1715 u8 dot3stats_single_collision_frames_high[0x20];
1717 u8 dot3stats_single_collision_frames_low[0x20];
1719 u8 dot3stats_multiple_collision_frames_high[0x20];
1721 u8 dot3stats_multiple_collision_frames_low[0x20];
1723 u8 dot3stats_sqe_test_errors_high[0x20];
1725 u8 dot3stats_sqe_test_errors_low[0x20];
1727 u8 dot3stats_deferred_transmissions_high[0x20];
1729 u8 dot3stats_deferred_transmissions_low[0x20];
1731 u8 dot3stats_late_collisions_high[0x20];
1733 u8 dot3stats_late_collisions_low[0x20];
1735 u8 dot3stats_excessive_collisions_high[0x20];
1737 u8 dot3stats_excessive_collisions_low[0x20];
1739 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1741 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1743 u8 dot3stats_carrier_sense_errors_high[0x20];
1745 u8 dot3stats_carrier_sense_errors_low[0x20];
1747 u8 dot3stats_frame_too_longs_high[0x20];
1749 u8 dot3stats_frame_too_longs_low[0x20];
1751 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1753 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1755 u8 dot3stats_symbol_errors_high[0x20];
1757 u8 dot3stats_symbol_errors_low[0x20];
1759 u8 dot3control_in_unknown_opcodes_high[0x20];
1761 u8 dot3control_in_unknown_opcodes_low[0x20];
1763 u8 dot3in_pause_frames_high[0x20];
1765 u8 dot3in_pause_frames_low[0x20];
1767 u8 dot3out_pause_frames_high[0x20];
1769 u8 dot3out_pause_frames_low[0x20];
1771 u8 reserved_at_400[0x3c0];
1774 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1775 u8 ether_stats_drop_events_high[0x20];
1777 u8 ether_stats_drop_events_low[0x20];
1779 u8 ether_stats_octets_high[0x20];
1781 u8 ether_stats_octets_low[0x20];
1783 u8 ether_stats_pkts_high[0x20];
1785 u8 ether_stats_pkts_low[0x20];
1787 u8 ether_stats_broadcast_pkts_high[0x20];
1789 u8 ether_stats_broadcast_pkts_low[0x20];
1791 u8 ether_stats_multicast_pkts_high[0x20];
1793 u8 ether_stats_multicast_pkts_low[0x20];
1795 u8 ether_stats_crc_align_errors_high[0x20];
1797 u8 ether_stats_crc_align_errors_low[0x20];
1799 u8 ether_stats_undersize_pkts_high[0x20];
1801 u8 ether_stats_undersize_pkts_low[0x20];
1803 u8 ether_stats_oversize_pkts_high[0x20];
1805 u8 ether_stats_oversize_pkts_low[0x20];
1807 u8 ether_stats_fragments_high[0x20];
1809 u8 ether_stats_fragments_low[0x20];
1811 u8 ether_stats_jabbers_high[0x20];
1813 u8 ether_stats_jabbers_low[0x20];
1815 u8 ether_stats_collisions_high[0x20];
1817 u8 ether_stats_collisions_low[0x20];
1819 u8 ether_stats_pkts64octets_high[0x20];
1821 u8 ether_stats_pkts64octets_low[0x20];
1823 u8 ether_stats_pkts65to127octets_high[0x20];
1825 u8 ether_stats_pkts65to127octets_low[0x20];
1827 u8 ether_stats_pkts128to255octets_high[0x20];
1829 u8 ether_stats_pkts128to255octets_low[0x20];
1831 u8 ether_stats_pkts256to511octets_high[0x20];
1833 u8 ether_stats_pkts256to511octets_low[0x20];
1835 u8 ether_stats_pkts512to1023octets_high[0x20];
1837 u8 ether_stats_pkts512to1023octets_low[0x20];
1839 u8 ether_stats_pkts1024to1518octets_high[0x20];
1841 u8 ether_stats_pkts1024to1518octets_low[0x20];
1843 u8 ether_stats_pkts1519to2047octets_high[0x20];
1845 u8 ether_stats_pkts1519to2047octets_low[0x20];
1847 u8 ether_stats_pkts2048to4095octets_high[0x20];
1849 u8 ether_stats_pkts2048to4095octets_low[0x20];
1851 u8 ether_stats_pkts4096to8191octets_high[0x20];
1853 u8 ether_stats_pkts4096to8191octets_low[0x20];
1855 u8 ether_stats_pkts8192to10239octets_high[0x20];
1857 u8 ether_stats_pkts8192to10239octets_low[0x20];
1859 u8 reserved_at_540[0x280];
1862 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1863 u8 if_in_octets_high[0x20];
1865 u8 if_in_octets_low[0x20];
1867 u8 if_in_ucast_pkts_high[0x20];
1869 u8 if_in_ucast_pkts_low[0x20];
1871 u8 if_in_discards_high[0x20];
1873 u8 if_in_discards_low[0x20];
1875 u8 if_in_errors_high[0x20];
1877 u8 if_in_errors_low[0x20];
1879 u8 if_in_unknown_protos_high[0x20];
1881 u8 if_in_unknown_protos_low[0x20];
1883 u8 if_out_octets_high[0x20];
1885 u8 if_out_octets_low[0x20];
1887 u8 if_out_ucast_pkts_high[0x20];
1889 u8 if_out_ucast_pkts_low[0x20];
1891 u8 if_out_discards_high[0x20];
1893 u8 if_out_discards_low[0x20];
1895 u8 if_out_errors_high[0x20];
1897 u8 if_out_errors_low[0x20];
1899 u8 if_in_multicast_pkts_high[0x20];
1901 u8 if_in_multicast_pkts_low[0x20];
1903 u8 if_in_broadcast_pkts_high[0x20];
1905 u8 if_in_broadcast_pkts_low[0x20];
1907 u8 if_out_multicast_pkts_high[0x20];
1909 u8 if_out_multicast_pkts_low[0x20];
1911 u8 if_out_broadcast_pkts_high[0x20];
1913 u8 if_out_broadcast_pkts_low[0x20];
1915 u8 reserved_at_340[0x480];
1918 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1919 u8 a_frames_transmitted_ok_high[0x20];
1921 u8 a_frames_transmitted_ok_low[0x20];
1923 u8 a_frames_received_ok_high[0x20];
1925 u8 a_frames_received_ok_low[0x20];
1927 u8 a_frame_check_sequence_errors_high[0x20];
1929 u8 a_frame_check_sequence_errors_low[0x20];
1931 u8 a_alignment_errors_high[0x20];
1933 u8 a_alignment_errors_low[0x20];
1935 u8 a_octets_transmitted_ok_high[0x20];
1937 u8 a_octets_transmitted_ok_low[0x20];
1939 u8 a_octets_received_ok_high[0x20];
1941 u8 a_octets_received_ok_low[0x20];
1943 u8 a_multicast_frames_xmitted_ok_high[0x20];
1945 u8 a_multicast_frames_xmitted_ok_low[0x20];
1947 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1949 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1951 u8 a_multicast_frames_received_ok_high[0x20];
1953 u8 a_multicast_frames_received_ok_low[0x20];
1955 u8 a_broadcast_frames_received_ok_high[0x20];
1957 u8 a_broadcast_frames_received_ok_low[0x20];
1959 u8 a_in_range_length_errors_high[0x20];
1961 u8 a_in_range_length_errors_low[0x20];
1963 u8 a_out_of_range_length_field_high[0x20];
1965 u8 a_out_of_range_length_field_low[0x20];
1967 u8 a_frame_too_long_errors_high[0x20];
1969 u8 a_frame_too_long_errors_low[0x20];
1971 u8 a_symbol_error_during_carrier_high[0x20];
1973 u8 a_symbol_error_during_carrier_low[0x20];
1975 u8 a_mac_control_frames_transmitted_high[0x20];
1977 u8 a_mac_control_frames_transmitted_low[0x20];
1979 u8 a_mac_control_frames_received_high[0x20];
1981 u8 a_mac_control_frames_received_low[0x20];
1983 u8 a_unsupported_opcodes_received_high[0x20];
1985 u8 a_unsupported_opcodes_received_low[0x20];
1987 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1989 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1991 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1993 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1995 u8 reserved_at_4c0[0x300];
1998 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1999 u8 life_time_counter_high[0x20];
2001 u8 life_time_counter_low[0x20];
2007 u8 l0_to_recovery_eieos[0x20];
2009 u8 l0_to_recovery_ts[0x20];
2011 u8 l0_to_recovery_framing[0x20];
2013 u8 l0_to_recovery_retrain[0x20];
2015 u8 crc_error_dllp[0x20];
2017 u8 crc_error_tlp[0x20];
2019 u8 tx_overflow_buffer_pkt_high[0x20];
2021 u8 tx_overflow_buffer_pkt_low[0x20];
2023 u8 outbound_stalled_reads[0x20];
2025 u8 outbound_stalled_writes[0x20];
2027 u8 outbound_stalled_reads_events[0x20];
2029 u8 outbound_stalled_writes_events[0x20];
2031 u8 reserved_at_200[0x5c0];
2034 struct mlx5_ifc_cmd_inter_comp_event_bits {
2035 u8 command_completion_vector[0x20];
2037 u8 reserved_at_20[0xc0];
2040 struct mlx5_ifc_stall_vl_event_bits {
2041 u8 reserved_at_0[0x18];
2043 u8 reserved_at_19[0x3];
2046 u8 reserved_at_20[0xa0];
2049 struct mlx5_ifc_db_bf_congestion_event_bits {
2050 u8 event_subtype[0x8];
2051 u8 reserved_at_8[0x8];
2052 u8 congestion_level[0x8];
2053 u8 reserved_at_18[0x8];
2055 u8 reserved_at_20[0xa0];
2058 struct mlx5_ifc_gpio_event_bits {
2059 u8 reserved_at_0[0x60];
2061 u8 gpio_event_hi[0x20];
2063 u8 gpio_event_lo[0x20];
2065 u8 reserved_at_a0[0x40];
2068 struct mlx5_ifc_port_state_change_event_bits {
2069 u8 reserved_at_0[0x40];
2072 u8 reserved_at_44[0x1c];
2074 u8 reserved_at_60[0x80];
2077 struct mlx5_ifc_dropped_packet_logged_bits {
2078 u8 reserved_at_0[0xe0];
2082 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2083 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2086 struct mlx5_ifc_cq_error_bits {
2087 u8 reserved_at_0[0x8];
2090 u8 reserved_at_20[0x20];
2092 u8 reserved_at_40[0x18];
2095 u8 reserved_at_60[0x80];
2098 struct mlx5_ifc_rdma_page_fault_event_bits {
2099 u8 bytes_committed[0x20];
2103 u8 reserved_at_40[0x10];
2104 u8 packet_len[0x10];
2106 u8 rdma_op_len[0x20];
2110 u8 reserved_at_c0[0x5];
2117 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2118 u8 bytes_committed[0x20];
2120 u8 reserved_at_20[0x10];
2123 u8 reserved_at_40[0x10];
2126 u8 reserved_at_60[0x60];
2128 u8 reserved_at_c0[0x5];
2135 struct mlx5_ifc_qp_events_bits {
2136 u8 reserved_at_0[0xa0];
2139 u8 reserved_at_a8[0x18];
2141 u8 reserved_at_c0[0x8];
2142 u8 qpn_rqn_sqn[0x18];
2145 struct mlx5_ifc_dct_events_bits {
2146 u8 reserved_at_0[0xc0];
2148 u8 reserved_at_c0[0x8];
2149 u8 dct_number[0x18];
2152 struct mlx5_ifc_comp_event_bits {
2153 u8 reserved_at_0[0xc0];
2155 u8 reserved_at_c0[0x8];
2160 MLX5_QPC_STATE_RST = 0x0,
2161 MLX5_QPC_STATE_INIT = 0x1,
2162 MLX5_QPC_STATE_RTR = 0x2,
2163 MLX5_QPC_STATE_RTS = 0x3,
2164 MLX5_QPC_STATE_SQER = 0x4,
2165 MLX5_QPC_STATE_ERR = 0x6,
2166 MLX5_QPC_STATE_SQD = 0x7,
2167 MLX5_QPC_STATE_SUSPENDED = 0x9,
2171 MLX5_QPC_ST_RC = 0x0,
2172 MLX5_QPC_ST_UC = 0x1,
2173 MLX5_QPC_ST_UD = 0x2,
2174 MLX5_QPC_ST_XRC = 0x3,
2175 MLX5_QPC_ST_DCI = 0x5,
2176 MLX5_QPC_ST_QP0 = 0x7,
2177 MLX5_QPC_ST_QP1 = 0x8,
2178 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2179 MLX5_QPC_ST_REG_UMR = 0xc,
2183 MLX5_QPC_PM_STATE_ARMED = 0x0,
2184 MLX5_QPC_PM_STATE_REARM = 0x1,
2185 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2186 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2190 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2194 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2195 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2199 MLX5_QPC_MTU_256_BYTES = 0x1,
2200 MLX5_QPC_MTU_512_BYTES = 0x2,
2201 MLX5_QPC_MTU_1K_BYTES = 0x3,
2202 MLX5_QPC_MTU_2K_BYTES = 0x4,
2203 MLX5_QPC_MTU_4K_BYTES = 0x5,
2204 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2208 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2209 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2210 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2211 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2212 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2213 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2214 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2215 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2219 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2220 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2221 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2225 MLX5_QPC_CS_RES_DISABLE = 0x0,
2226 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2227 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2230 struct mlx5_ifc_qpc_bits {
2232 u8 lag_tx_port_affinity[0x4];
2234 u8 reserved_at_10[0x3];
2236 u8 reserved_at_15[0x3];
2237 u8 offload_type[0x4];
2238 u8 end_padding_mode[0x2];
2239 u8 reserved_at_1e[0x2];
2241 u8 wq_signature[0x1];
2242 u8 block_lb_mc[0x1];
2243 u8 atomic_like_write_en[0x1];
2244 u8 latency_sensitive[0x1];
2245 u8 reserved_at_24[0x1];
2246 u8 drain_sigerr[0x1];
2247 u8 reserved_at_26[0x2];
2251 u8 log_msg_max[0x5];
2252 u8 reserved_at_48[0x1];
2253 u8 log_rq_size[0x4];
2254 u8 log_rq_stride[0x3];
2256 u8 log_sq_size[0x4];
2257 u8 reserved_at_55[0x6];
2259 u8 ulp_stateless_offload_mode[0x4];
2261 u8 counter_set_id[0x8];
2264 u8 reserved_at_80[0x8];
2265 u8 user_index[0x18];
2267 u8 reserved_at_a0[0x3];
2268 u8 log_page_size[0x5];
2269 u8 remote_qpn[0x18];
2271 struct mlx5_ifc_ads_bits primary_address_path;
2273 struct mlx5_ifc_ads_bits secondary_address_path;
2275 u8 log_ack_req_freq[0x4];
2276 u8 reserved_at_384[0x4];
2277 u8 log_sra_max[0x3];
2278 u8 reserved_at_38b[0x2];
2279 u8 retry_count[0x3];
2281 u8 reserved_at_393[0x1];
2283 u8 cur_rnr_retry[0x3];
2284 u8 cur_retry_count[0x3];
2285 u8 reserved_at_39b[0x5];
2287 u8 reserved_at_3a0[0x20];
2289 u8 reserved_at_3c0[0x8];
2290 u8 next_send_psn[0x18];
2292 u8 reserved_at_3e0[0x8];
2295 u8 reserved_at_400[0x8];
2298 u8 reserved_at_420[0x20];
2300 u8 reserved_at_440[0x8];
2301 u8 last_acked_psn[0x18];
2303 u8 reserved_at_460[0x8];
2306 u8 reserved_at_480[0x8];
2307 u8 log_rra_max[0x3];
2308 u8 reserved_at_48b[0x1];
2309 u8 atomic_mode[0x4];
2313 u8 reserved_at_493[0x1];
2314 u8 page_offset[0x6];
2315 u8 reserved_at_49a[0x3];
2316 u8 cd_slave_receive[0x1];
2317 u8 cd_slave_send[0x1];
2320 u8 reserved_at_4a0[0x3];
2321 u8 min_rnr_nak[0x5];
2322 u8 next_rcv_psn[0x18];
2324 u8 reserved_at_4c0[0x8];
2327 u8 reserved_at_4e0[0x8];
2334 u8 reserved_at_560[0x5];
2336 u8 srqn_rmpn_xrqn[0x18];
2338 u8 reserved_at_580[0x8];
2341 u8 hw_sq_wqebb_counter[0x10];
2342 u8 sw_sq_wqebb_counter[0x10];
2344 u8 hw_rq_counter[0x20];
2346 u8 sw_rq_counter[0x20];
2348 u8 reserved_at_600[0x20];
2350 u8 reserved_at_620[0xf];
2355 u8 dc_access_key[0x40];
2357 u8 reserved_at_680[0xc0];
2360 struct mlx5_ifc_roce_addr_layout_bits {
2361 u8 source_l3_address[16][0x8];
2363 u8 reserved_at_80[0x3];
2366 u8 source_mac_47_32[0x10];
2368 u8 source_mac_31_0[0x20];
2370 u8 reserved_at_c0[0x14];
2371 u8 roce_l3_type[0x4];
2372 u8 roce_version[0x8];
2374 u8 reserved_at_e0[0x20];
2377 union mlx5_ifc_hca_cap_union_bits {
2378 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2379 struct mlx5_ifc_odp_cap_bits odp_cap;
2380 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2381 struct mlx5_ifc_roce_cap_bits roce_cap;
2382 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2383 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2384 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2385 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2386 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2387 struct mlx5_ifc_qos_cap_bits qos_cap;
2388 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2389 u8 reserved_at_0[0x8000];
2393 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2394 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2395 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2396 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2397 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2398 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2399 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2400 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2401 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2402 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2403 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2406 struct mlx5_ifc_vlan_bits {
2413 struct mlx5_ifc_flow_context_bits {
2414 struct mlx5_ifc_vlan_bits push_vlan;
2418 u8 reserved_at_40[0x8];
2421 u8 reserved_at_60[0x10];
2424 u8 reserved_at_80[0x8];
2425 u8 destination_list_size[0x18];
2427 u8 reserved_at_a0[0x8];
2428 u8 flow_counter_list_size[0x18];
2432 u8 modify_header_id[0x20];
2434 struct mlx5_ifc_vlan_bits push_vlan_2;
2436 u8 reserved_at_120[0xe0];
2438 struct mlx5_ifc_fte_match_param_bits match_value;
2440 u8 reserved_at_1200[0x600];
2442 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2446 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2447 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2450 struct mlx5_ifc_xrc_srqc_bits {
2452 u8 log_xrc_srq_size[0x4];
2453 u8 reserved_at_8[0x18];
2455 u8 wq_signature[0x1];
2457 u8 reserved_at_22[0x1];
2459 u8 basic_cyclic_rcv_wqe[0x1];
2460 u8 log_rq_stride[0x3];
2463 u8 page_offset[0x6];
2464 u8 reserved_at_46[0x2];
2467 u8 reserved_at_60[0x20];
2469 u8 user_index_equal_xrc_srqn[0x1];
2470 u8 reserved_at_81[0x1];
2471 u8 log_page_size[0x6];
2472 u8 user_index[0x18];
2474 u8 reserved_at_a0[0x20];
2476 u8 reserved_at_c0[0x8];
2482 u8 reserved_at_100[0x40];
2484 u8 db_record_addr_h[0x20];
2486 u8 db_record_addr_l[0x1e];
2487 u8 reserved_at_17e[0x2];
2489 u8 reserved_at_180[0x80];
2492 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2493 u8 counter_error_queues[0x20];
2495 u8 total_error_queues[0x20];
2497 u8 send_queue_priority_update_flow[0x20];
2499 u8 reserved_at_60[0x20];
2501 u8 nic_receive_steering_discard[0x40];
2503 u8 receive_discard_vport_down[0x40];
2505 u8 transmit_discard_vport_down[0x40];
2507 u8 reserved_at_140[0xec0];
2510 struct mlx5_ifc_traffic_counter_bits {
2516 struct mlx5_ifc_tisc_bits {
2517 u8 strict_lag_tx_port_affinity[0x1];
2518 u8 reserved_at_1[0x3];
2519 u8 lag_tx_port_affinity[0x04];
2521 u8 reserved_at_8[0x4];
2523 u8 reserved_at_10[0x10];
2525 u8 reserved_at_20[0x100];
2527 u8 reserved_at_120[0x8];
2528 u8 transport_domain[0x18];
2530 u8 reserved_at_140[0x8];
2531 u8 underlay_qpn[0x18];
2532 u8 reserved_at_160[0x3a0];
2536 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2537 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2541 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2542 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2546 MLX5_RX_HASH_FN_NONE = 0x0,
2547 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2548 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2552 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2553 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2556 struct mlx5_ifc_tirc_bits {
2557 u8 reserved_at_0[0x20];
2560 u8 reserved_at_24[0x1c];
2562 u8 reserved_at_40[0x40];
2564 u8 reserved_at_80[0x4];
2565 u8 lro_timeout_period_usecs[0x10];
2566 u8 lro_enable_mask[0x4];
2567 u8 lro_max_ip_payload_size[0x8];
2569 u8 reserved_at_a0[0x40];
2571 u8 reserved_at_e0[0x8];
2572 u8 inline_rqn[0x18];
2574 u8 rx_hash_symmetric[0x1];
2575 u8 reserved_at_101[0x1];
2576 u8 tunneled_offload_en[0x1];
2577 u8 reserved_at_103[0x5];
2578 u8 indirect_table[0x18];
2581 u8 reserved_at_124[0x2];
2582 u8 self_lb_block[0x2];
2583 u8 transport_domain[0x18];
2585 u8 rx_hash_toeplitz_key[10][0x20];
2587 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2589 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2591 u8 reserved_at_2c0[0x4c0];
2595 MLX5_SRQC_STATE_GOOD = 0x0,
2596 MLX5_SRQC_STATE_ERROR = 0x1,
2599 struct mlx5_ifc_srqc_bits {
2601 u8 log_srq_size[0x4];
2602 u8 reserved_at_8[0x18];
2604 u8 wq_signature[0x1];
2606 u8 reserved_at_22[0x1];
2608 u8 reserved_at_24[0x1];
2609 u8 log_rq_stride[0x3];
2612 u8 page_offset[0x6];
2613 u8 reserved_at_46[0x2];
2616 u8 reserved_at_60[0x20];
2618 u8 reserved_at_80[0x2];
2619 u8 log_page_size[0x6];
2620 u8 reserved_at_88[0x18];
2622 u8 reserved_at_a0[0x20];
2624 u8 reserved_at_c0[0x8];
2630 u8 reserved_at_100[0x40];
2634 u8 reserved_at_180[0x80];
2638 MLX5_SQC_STATE_RST = 0x0,
2639 MLX5_SQC_STATE_RDY = 0x1,
2640 MLX5_SQC_STATE_ERR = 0x3,
2643 struct mlx5_ifc_sqc_bits {
2647 u8 flush_in_error_en[0x1];
2648 u8 allow_multi_pkt_send_wqe[0x1];
2649 u8 min_wqe_inline_mode[0x3];
2654 u8 reserved_at_f[0x11];
2656 u8 reserved_at_20[0x8];
2657 u8 user_index[0x18];
2659 u8 reserved_at_40[0x8];
2662 u8 reserved_at_60[0x8];
2663 u8 hairpin_peer_rq[0x18];
2665 u8 reserved_at_80[0x10];
2666 u8 hairpin_peer_vhca[0x10];
2668 u8 reserved_at_a0[0x50];
2670 u8 packet_pacing_rate_limit_index[0x10];
2671 u8 tis_lst_sz[0x10];
2672 u8 reserved_at_110[0x10];
2674 u8 reserved_at_120[0x40];
2676 u8 reserved_at_160[0x8];
2679 struct mlx5_ifc_wq_bits wq;
2683 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2684 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2685 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2686 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2689 struct mlx5_ifc_scheduling_context_bits {
2690 u8 element_type[0x8];
2691 u8 reserved_at_8[0x18];
2693 u8 element_attributes[0x20];
2695 u8 parent_element_id[0x20];
2697 u8 reserved_at_60[0x40];
2701 u8 max_average_bw[0x20];
2703 u8 reserved_at_e0[0x120];
2706 struct mlx5_ifc_rqtc_bits {
2707 u8 reserved_at_0[0xa0];
2709 u8 reserved_at_a0[0x10];
2710 u8 rqt_max_size[0x10];
2712 u8 reserved_at_c0[0x10];
2713 u8 rqt_actual_size[0x10];
2715 u8 reserved_at_e0[0x6a0];
2717 struct mlx5_ifc_rq_num_bits rq_num[0];
2721 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2722 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2726 MLX5_RQC_STATE_RST = 0x0,
2727 MLX5_RQC_STATE_RDY = 0x1,
2728 MLX5_RQC_STATE_ERR = 0x3,
2731 struct mlx5_ifc_rqc_bits {
2733 u8 delay_drop_en[0x1];
2734 u8 scatter_fcs[0x1];
2736 u8 mem_rq_type[0x4];
2738 u8 reserved_at_c[0x1];
2739 u8 flush_in_error_en[0x1];
2741 u8 reserved_at_f[0x11];
2743 u8 reserved_at_20[0x8];
2744 u8 user_index[0x18];
2746 u8 reserved_at_40[0x8];
2749 u8 counter_set_id[0x8];
2750 u8 reserved_at_68[0x18];
2752 u8 reserved_at_80[0x8];
2755 u8 reserved_at_a0[0x8];
2756 u8 hairpin_peer_sq[0x18];
2758 u8 reserved_at_c0[0x10];
2759 u8 hairpin_peer_vhca[0x10];
2761 u8 reserved_at_e0[0xa0];
2763 struct mlx5_ifc_wq_bits wq;
2767 MLX5_RMPC_STATE_RDY = 0x1,
2768 MLX5_RMPC_STATE_ERR = 0x3,
2771 struct mlx5_ifc_rmpc_bits {
2772 u8 reserved_at_0[0x8];
2774 u8 reserved_at_c[0x14];
2776 u8 basic_cyclic_rcv_wqe[0x1];
2777 u8 reserved_at_21[0x1f];
2779 u8 reserved_at_40[0x140];
2781 struct mlx5_ifc_wq_bits wq;
2784 struct mlx5_ifc_nic_vport_context_bits {
2785 u8 reserved_at_0[0x5];
2786 u8 min_wqe_inline_mode[0x3];
2787 u8 reserved_at_8[0x15];
2788 u8 disable_mc_local_lb[0x1];
2789 u8 disable_uc_local_lb[0x1];
2792 u8 arm_change_event[0x1];
2793 u8 reserved_at_21[0x1a];
2794 u8 event_on_mtu[0x1];
2795 u8 event_on_promisc_change[0x1];
2796 u8 event_on_vlan_change[0x1];
2797 u8 event_on_mc_address_change[0x1];
2798 u8 event_on_uc_address_change[0x1];
2800 u8 reserved_at_40[0xc];
2802 u8 affiliation_criteria[0x4];
2803 u8 affiliated_vhca_id[0x10];
2805 u8 reserved_at_60[0xd0];
2809 u8 system_image_guid[0x40];
2813 u8 reserved_at_200[0x140];
2814 u8 qkey_violation_counter[0x10];
2815 u8 reserved_at_350[0x430];
2819 u8 promisc_all[0x1];
2820 u8 reserved_at_783[0x2];
2821 u8 allowed_list_type[0x3];
2822 u8 reserved_at_788[0xc];
2823 u8 allowed_list_size[0xc];
2825 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2827 u8 reserved_at_7e0[0x20];
2829 u8 current_uc_mac_address[0][0x40];
2833 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2834 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2835 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2836 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2837 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2840 struct mlx5_ifc_mkc_bits {
2841 u8 reserved_at_0[0x1];
2843 u8 reserved_at_2[0x1];
2844 u8 access_mode_4_2[0x3];
2845 u8 reserved_at_6[0x7];
2846 u8 relaxed_ordering_write[0x1];
2847 u8 reserved_at_e[0x1];
2848 u8 small_fence_on_rdma_read_response[0x1];
2855 u8 access_mode_1_0[0x2];
2856 u8 reserved_at_18[0x8];
2861 u8 reserved_at_40[0x20];
2866 u8 reserved_at_63[0x2];
2867 u8 expected_sigerr_count[0x1];
2868 u8 reserved_at_66[0x1];
2872 u8 start_addr[0x40];
2876 u8 bsf_octword_size[0x20];
2878 u8 reserved_at_120[0x80];
2880 u8 translations_octword_size[0x20];
2882 u8 reserved_at_1c0[0x1b];
2883 u8 log_page_size[0x5];
2885 u8 reserved_at_1e0[0x20];
2888 struct mlx5_ifc_pkey_bits {
2889 u8 reserved_at_0[0x10];
2893 struct mlx5_ifc_array128_auto_bits {
2894 u8 array128_auto[16][0x8];
2897 struct mlx5_ifc_hca_vport_context_bits {
2898 u8 field_select[0x20];
2900 u8 reserved_at_20[0xe0];
2902 u8 sm_virt_aware[0x1];
2905 u8 grh_required[0x1];
2906 u8 reserved_at_104[0xc];
2907 u8 port_physical_state[0x4];
2908 u8 vport_state_policy[0x4];
2910 u8 vport_state[0x4];
2912 u8 reserved_at_120[0x20];
2914 u8 system_image_guid[0x40];
2922 u8 cap_mask1_field_select[0x20];
2926 u8 cap_mask2_field_select[0x20];
2928 u8 reserved_at_280[0x80];
2931 u8 reserved_at_310[0x4];
2932 u8 init_type_reply[0x4];
2934 u8 subnet_timeout[0x5];
2938 u8 reserved_at_334[0xc];
2940 u8 qkey_violation_counter[0x10];
2941 u8 pkey_violation_counter[0x10];
2943 u8 reserved_at_360[0xca0];
2946 struct mlx5_ifc_esw_vport_context_bits {
2947 u8 reserved_at_0[0x3];
2948 u8 vport_svlan_strip[0x1];
2949 u8 vport_cvlan_strip[0x1];
2950 u8 vport_svlan_insert[0x1];
2951 u8 vport_cvlan_insert[0x2];
2952 u8 reserved_at_8[0x18];
2954 u8 reserved_at_20[0x20];
2963 u8 reserved_at_60[0x7a0];
2967 MLX5_EQC_STATUS_OK = 0x0,
2968 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2972 MLX5_EQC_ST_ARMED = 0x9,
2973 MLX5_EQC_ST_FIRED = 0xa,
2976 struct mlx5_ifc_eqc_bits {
2978 u8 reserved_at_4[0x9];
2981 u8 reserved_at_f[0x5];
2983 u8 reserved_at_18[0x8];
2985 u8 reserved_at_20[0x20];
2987 u8 reserved_at_40[0x14];
2988 u8 page_offset[0x6];
2989 u8 reserved_at_5a[0x6];
2991 u8 reserved_at_60[0x3];
2992 u8 log_eq_size[0x5];
2995 u8 reserved_at_80[0x20];
2997 u8 reserved_at_a0[0x18];
3000 u8 reserved_at_c0[0x3];
3001 u8 log_page_size[0x5];
3002 u8 reserved_at_c8[0x18];
3004 u8 reserved_at_e0[0x60];
3006 u8 reserved_at_140[0x8];
3007 u8 consumer_counter[0x18];
3009 u8 reserved_at_160[0x8];
3010 u8 producer_counter[0x18];
3012 u8 reserved_at_180[0x80];
3016 MLX5_DCTC_STATE_ACTIVE = 0x0,
3017 MLX5_DCTC_STATE_DRAINING = 0x1,
3018 MLX5_DCTC_STATE_DRAINED = 0x2,
3022 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3023 MLX5_DCTC_CS_RES_NA = 0x1,
3024 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3028 MLX5_DCTC_MTU_256_BYTES = 0x1,
3029 MLX5_DCTC_MTU_512_BYTES = 0x2,
3030 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3031 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3032 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3035 struct mlx5_ifc_dctc_bits {
3036 u8 reserved_at_0[0x4];
3038 u8 reserved_at_8[0x18];
3040 u8 reserved_at_20[0x8];
3041 u8 user_index[0x18];
3043 u8 reserved_at_40[0x8];
3046 u8 counter_set_id[0x8];
3047 u8 atomic_mode[0x4];
3051 u8 atomic_like_write_en[0x1];
3052 u8 latency_sensitive[0x1];
3055 u8 reserved_at_73[0xd];
3057 u8 reserved_at_80[0x8];
3059 u8 reserved_at_90[0x3];
3060 u8 min_rnr_nak[0x5];
3061 u8 reserved_at_98[0x8];
3063 u8 reserved_at_a0[0x8];
3066 u8 reserved_at_c0[0x8];
3070 u8 reserved_at_e8[0x4];
3071 u8 flow_label[0x14];
3073 u8 dc_access_key[0x40];
3075 u8 reserved_at_140[0x5];
3078 u8 pkey_index[0x10];
3080 u8 reserved_at_160[0x8];
3081 u8 my_addr_index[0x8];
3082 u8 reserved_at_170[0x8];
3085 u8 dc_access_key_violation_count[0x20];
3087 u8 reserved_at_1a0[0x14];
3093 u8 reserved_at_1c0[0x40];
3097 MLX5_CQC_STATUS_OK = 0x0,
3098 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3099 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3103 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3104 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3108 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3109 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3110 MLX5_CQC_ST_FIRED = 0xa,
3114 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3115 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3116 MLX5_CQ_PERIOD_NUM_MODES
3119 struct mlx5_ifc_cqc_bits {
3121 u8 reserved_at_4[0x4];
3124 u8 reserved_at_c[0x1];
3125 u8 scqe_break_moderation_en[0x1];
3127 u8 cq_period_mode[0x2];
3128 u8 cqe_comp_en[0x1];
3129 u8 mini_cqe_res_format[0x2];
3131 u8 reserved_at_18[0x8];
3133 u8 reserved_at_20[0x20];
3135 u8 reserved_at_40[0x14];
3136 u8 page_offset[0x6];
3137 u8 reserved_at_5a[0x6];
3139 u8 reserved_at_60[0x3];
3140 u8 log_cq_size[0x5];
3143 u8 reserved_at_80[0x4];
3145 u8 cq_max_count[0x10];
3147 u8 reserved_at_a0[0x18];
3150 u8 reserved_at_c0[0x3];
3151 u8 log_page_size[0x5];
3152 u8 reserved_at_c8[0x18];
3154 u8 reserved_at_e0[0x20];
3156 u8 reserved_at_100[0x8];
3157 u8 last_notified_index[0x18];
3159 u8 reserved_at_120[0x8];
3160 u8 last_solicit_index[0x18];
3162 u8 reserved_at_140[0x8];
3163 u8 consumer_counter[0x18];
3165 u8 reserved_at_160[0x8];
3166 u8 producer_counter[0x18];
3168 u8 reserved_at_180[0x40];
3173 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3174 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3175 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3176 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3177 u8 reserved_at_0[0x800];
3180 struct mlx5_ifc_query_adapter_param_block_bits {
3181 u8 reserved_at_0[0xc0];
3183 u8 reserved_at_c0[0x8];
3184 u8 ieee_vendor_id[0x18];
3186 u8 reserved_at_e0[0x10];
3187 u8 vsd_vendor_id[0x10];
3191 u8 vsd_contd_psid[16][0x8];
3195 MLX5_XRQC_STATE_GOOD = 0x0,
3196 MLX5_XRQC_STATE_ERROR = 0x1,
3200 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3201 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3205 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3208 struct mlx5_ifc_tag_matching_topology_context_bits {
3209 u8 log_matching_list_sz[0x4];
3210 u8 reserved_at_4[0xc];
3211 u8 append_next_index[0x10];
3213 u8 sw_phase_cnt[0x10];
3214 u8 hw_phase_cnt[0x10];
3216 u8 reserved_at_40[0x40];
3219 struct mlx5_ifc_xrqc_bits {
3222 u8 reserved_at_5[0xf];
3224 u8 reserved_at_18[0x4];
3227 u8 reserved_at_20[0x8];
3228 u8 user_index[0x18];
3230 u8 reserved_at_40[0x8];
3233 u8 reserved_at_60[0xa0];
3235 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3237 u8 reserved_at_180[0x280];
3239 struct mlx5_ifc_wq_bits wq;
3242 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3243 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3244 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3245 u8 reserved_at_0[0x20];
3248 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3249 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3250 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3251 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3252 u8 reserved_at_0[0x20];
3255 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3256 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3257 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3258 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3259 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3260 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3261 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3262 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3263 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3264 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3265 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3266 u8 reserved_at_0[0x7c0];
3269 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3270 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3271 u8 reserved_at_0[0x7c0];
3274 union mlx5_ifc_event_auto_bits {
3275 struct mlx5_ifc_comp_event_bits comp_event;
3276 struct mlx5_ifc_dct_events_bits dct_events;
3277 struct mlx5_ifc_qp_events_bits qp_events;
3278 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3279 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3280 struct mlx5_ifc_cq_error_bits cq_error;
3281 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3282 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3283 struct mlx5_ifc_gpio_event_bits gpio_event;
3284 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3285 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3286 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3287 u8 reserved_at_0[0xe0];
3290 struct mlx5_ifc_health_buffer_bits {
3291 u8 reserved_at_0[0x100];
3293 u8 assert_existptr[0x20];
3295 u8 assert_callra[0x20];
3297 u8 reserved_at_140[0x40];
3299 u8 fw_version[0x20];
3303 u8 reserved_at_1c0[0x20];
3305 u8 irisc_index[0x8];
3310 struct mlx5_ifc_register_loopback_control_bits {
3312 u8 reserved_at_1[0x7];
3314 u8 reserved_at_10[0x10];
3316 u8 reserved_at_20[0x60];
3319 struct mlx5_ifc_vport_tc_element_bits {
3320 u8 traffic_class[0x4];
3321 u8 reserved_at_4[0xc];
3322 u8 vport_number[0x10];
3325 struct mlx5_ifc_vport_element_bits {
3326 u8 reserved_at_0[0x10];
3327 u8 vport_number[0x10];
3331 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3332 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3333 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3336 struct mlx5_ifc_tsar_element_bits {
3337 u8 reserved_at_0[0x8];
3339 u8 reserved_at_10[0x10];
3343 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3344 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3347 struct mlx5_ifc_teardown_hca_out_bits {
3349 u8 reserved_at_8[0x18];
3353 u8 reserved_at_40[0x3f];
3355 u8 force_state[0x1];
3359 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3360 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3363 struct mlx5_ifc_teardown_hca_in_bits {
3365 u8 reserved_at_10[0x10];
3367 u8 reserved_at_20[0x10];
3370 u8 reserved_at_40[0x10];
3373 u8 reserved_at_60[0x20];
3376 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3378 u8 reserved_at_8[0x18];
3382 u8 reserved_at_40[0x40];
3385 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3387 u8 reserved_at_10[0x10];
3389 u8 reserved_at_20[0x10];
3392 u8 reserved_at_40[0x8];
3395 u8 reserved_at_60[0x20];
3397 u8 opt_param_mask[0x20];
3399 u8 reserved_at_a0[0x20];
3401 struct mlx5_ifc_qpc_bits qpc;
3403 u8 reserved_at_800[0x80];
3406 struct mlx5_ifc_sqd2rts_qp_out_bits {
3408 u8 reserved_at_8[0x18];
3412 u8 reserved_at_40[0x40];
3415 struct mlx5_ifc_sqd2rts_qp_in_bits {
3417 u8 reserved_at_10[0x10];
3419 u8 reserved_at_20[0x10];
3422 u8 reserved_at_40[0x8];
3425 u8 reserved_at_60[0x20];
3427 u8 opt_param_mask[0x20];
3429 u8 reserved_at_a0[0x20];
3431 struct mlx5_ifc_qpc_bits qpc;
3433 u8 reserved_at_800[0x80];
3436 struct mlx5_ifc_set_roce_address_out_bits {
3438 u8 reserved_at_8[0x18];
3442 u8 reserved_at_40[0x40];
3445 struct mlx5_ifc_set_roce_address_in_bits {
3447 u8 reserved_at_10[0x10];
3449 u8 reserved_at_20[0x10];
3452 u8 roce_address_index[0x10];
3453 u8 reserved_at_50[0xc];
3454 u8 vhca_port_num[0x4];
3456 u8 reserved_at_60[0x20];
3458 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3461 struct mlx5_ifc_set_mad_demux_out_bits {
3463 u8 reserved_at_8[0x18];
3467 u8 reserved_at_40[0x40];
3471 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3472 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3475 struct mlx5_ifc_set_mad_demux_in_bits {
3477 u8 reserved_at_10[0x10];
3479 u8 reserved_at_20[0x10];
3482 u8 reserved_at_40[0x20];
3484 u8 reserved_at_60[0x6];
3486 u8 reserved_at_68[0x18];
3489 struct mlx5_ifc_set_l2_table_entry_out_bits {
3491 u8 reserved_at_8[0x18];
3495 u8 reserved_at_40[0x40];
3498 struct mlx5_ifc_set_l2_table_entry_in_bits {
3500 u8 reserved_at_10[0x10];
3502 u8 reserved_at_20[0x10];
3505 u8 reserved_at_40[0x60];
3507 u8 reserved_at_a0[0x8];
3508 u8 table_index[0x18];
3510 u8 reserved_at_c0[0x20];
3512 u8 reserved_at_e0[0x13];
3516 struct mlx5_ifc_mac_address_layout_bits mac_address;
3518 u8 reserved_at_140[0xc0];
3521 struct mlx5_ifc_set_issi_out_bits {
3523 u8 reserved_at_8[0x18];
3527 u8 reserved_at_40[0x40];
3530 struct mlx5_ifc_set_issi_in_bits {
3532 u8 reserved_at_10[0x10];
3534 u8 reserved_at_20[0x10];
3537 u8 reserved_at_40[0x10];
3538 u8 current_issi[0x10];
3540 u8 reserved_at_60[0x20];
3543 struct mlx5_ifc_set_hca_cap_out_bits {
3545 u8 reserved_at_8[0x18];
3549 u8 reserved_at_40[0x40];
3552 struct mlx5_ifc_set_hca_cap_in_bits {
3554 u8 reserved_at_10[0x10];
3556 u8 reserved_at_20[0x10];
3559 u8 reserved_at_40[0x40];
3561 union mlx5_ifc_hca_cap_union_bits capability;
3565 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3566 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3567 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3568 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3571 struct mlx5_ifc_set_fte_out_bits {
3573 u8 reserved_at_8[0x18];
3577 u8 reserved_at_40[0x40];
3580 struct mlx5_ifc_set_fte_in_bits {
3582 u8 reserved_at_10[0x10];
3584 u8 reserved_at_20[0x10];
3587 u8 other_vport[0x1];
3588 u8 reserved_at_41[0xf];
3589 u8 vport_number[0x10];
3591 u8 reserved_at_60[0x20];
3594 u8 reserved_at_88[0x18];
3596 u8 reserved_at_a0[0x8];
3599 u8 reserved_at_c0[0x18];
3600 u8 modify_enable_mask[0x8];
3602 u8 reserved_at_e0[0x20];
3604 u8 flow_index[0x20];
3606 u8 reserved_at_120[0xe0];
3608 struct mlx5_ifc_flow_context_bits flow_context;
3611 struct mlx5_ifc_rts2rts_qp_out_bits {
3613 u8 reserved_at_8[0x18];
3617 u8 reserved_at_40[0x40];
3620 struct mlx5_ifc_rts2rts_qp_in_bits {
3622 u8 reserved_at_10[0x10];
3624 u8 reserved_at_20[0x10];
3627 u8 reserved_at_40[0x8];
3630 u8 reserved_at_60[0x20];
3632 u8 opt_param_mask[0x20];
3634 u8 reserved_at_a0[0x20];
3636 struct mlx5_ifc_qpc_bits qpc;
3638 u8 reserved_at_800[0x80];
3641 struct mlx5_ifc_rtr2rts_qp_out_bits {
3643 u8 reserved_at_8[0x18];
3647 u8 reserved_at_40[0x40];
3650 struct mlx5_ifc_rtr2rts_qp_in_bits {
3652 u8 reserved_at_10[0x10];
3654 u8 reserved_at_20[0x10];
3657 u8 reserved_at_40[0x8];
3660 u8 reserved_at_60[0x20];
3662 u8 opt_param_mask[0x20];
3664 u8 reserved_at_a0[0x20];
3666 struct mlx5_ifc_qpc_bits qpc;
3668 u8 reserved_at_800[0x80];
3671 struct mlx5_ifc_rst2init_qp_out_bits {
3673 u8 reserved_at_8[0x18];
3677 u8 reserved_at_40[0x40];
3680 struct mlx5_ifc_rst2init_qp_in_bits {
3682 u8 reserved_at_10[0x10];
3684 u8 reserved_at_20[0x10];
3687 u8 reserved_at_40[0x8];
3690 u8 reserved_at_60[0x20];
3692 u8 opt_param_mask[0x20];
3694 u8 reserved_at_a0[0x20];
3696 struct mlx5_ifc_qpc_bits qpc;
3698 u8 reserved_at_800[0x80];
3701 struct mlx5_ifc_query_xrq_out_bits {
3703 u8 reserved_at_8[0x18];
3707 u8 reserved_at_40[0x40];
3709 struct mlx5_ifc_xrqc_bits xrq_context;
3712 struct mlx5_ifc_query_xrq_in_bits {
3714 u8 reserved_at_10[0x10];
3716 u8 reserved_at_20[0x10];
3719 u8 reserved_at_40[0x8];
3722 u8 reserved_at_60[0x20];
3725 struct mlx5_ifc_query_xrc_srq_out_bits {
3727 u8 reserved_at_8[0x18];
3731 u8 reserved_at_40[0x40];
3733 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3735 u8 reserved_at_280[0x600];
3740 struct mlx5_ifc_query_xrc_srq_in_bits {
3742 u8 reserved_at_10[0x10];
3744 u8 reserved_at_20[0x10];
3747 u8 reserved_at_40[0x8];
3750 u8 reserved_at_60[0x20];
3754 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3755 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3758 struct mlx5_ifc_query_vport_state_out_bits {
3760 u8 reserved_at_8[0x18];
3764 u8 reserved_at_40[0x20];
3766 u8 reserved_at_60[0x18];
3767 u8 admin_state[0x4];
3772 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3773 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
3776 struct mlx5_ifc_query_vport_state_in_bits {
3778 u8 reserved_at_10[0x10];
3780 u8 reserved_at_20[0x10];
3783 u8 other_vport[0x1];
3784 u8 reserved_at_41[0xf];
3785 u8 vport_number[0x10];
3787 u8 reserved_at_60[0x20];
3790 struct mlx5_ifc_query_vnic_env_out_bits {
3792 u8 reserved_at_8[0x18];
3796 u8 reserved_at_40[0x40];
3798 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3802 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3805 struct mlx5_ifc_query_vnic_env_in_bits {
3807 u8 reserved_at_10[0x10];
3809 u8 reserved_at_20[0x10];
3812 u8 other_vport[0x1];
3813 u8 reserved_at_41[0xf];
3814 u8 vport_number[0x10];
3816 u8 reserved_at_60[0x20];
3819 struct mlx5_ifc_query_vport_counter_out_bits {
3821 u8 reserved_at_8[0x18];
3825 u8 reserved_at_40[0x40];
3827 struct mlx5_ifc_traffic_counter_bits received_errors;
3829 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3831 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3833 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3835 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3837 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3839 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3841 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3843 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3845 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3847 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3849 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3851 u8 reserved_at_680[0xa00];
3855 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3858 struct mlx5_ifc_query_vport_counter_in_bits {
3860 u8 reserved_at_10[0x10];
3862 u8 reserved_at_20[0x10];
3865 u8 other_vport[0x1];
3866 u8 reserved_at_41[0xb];
3868 u8 vport_number[0x10];
3870 u8 reserved_at_60[0x60];
3873 u8 reserved_at_c1[0x1f];
3875 u8 reserved_at_e0[0x20];
3878 struct mlx5_ifc_query_tis_out_bits {
3880 u8 reserved_at_8[0x18];
3884 u8 reserved_at_40[0x40];
3886 struct mlx5_ifc_tisc_bits tis_context;
3889 struct mlx5_ifc_query_tis_in_bits {
3891 u8 reserved_at_10[0x10];
3893 u8 reserved_at_20[0x10];
3896 u8 reserved_at_40[0x8];
3899 u8 reserved_at_60[0x20];
3902 struct mlx5_ifc_query_tir_out_bits {
3904 u8 reserved_at_8[0x18];
3908 u8 reserved_at_40[0xc0];
3910 struct mlx5_ifc_tirc_bits tir_context;
3913 struct mlx5_ifc_query_tir_in_bits {
3915 u8 reserved_at_10[0x10];
3917 u8 reserved_at_20[0x10];
3920 u8 reserved_at_40[0x8];
3923 u8 reserved_at_60[0x20];
3926 struct mlx5_ifc_query_srq_out_bits {
3928 u8 reserved_at_8[0x18];
3932 u8 reserved_at_40[0x40];
3934 struct mlx5_ifc_srqc_bits srq_context_entry;
3936 u8 reserved_at_280[0x600];
3941 struct mlx5_ifc_query_srq_in_bits {
3943 u8 reserved_at_10[0x10];
3945 u8 reserved_at_20[0x10];
3948 u8 reserved_at_40[0x8];
3951 u8 reserved_at_60[0x20];
3954 struct mlx5_ifc_query_sq_out_bits {
3956 u8 reserved_at_8[0x18];
3960 u8 reserved_at_40[0xc0];
3962 struct mlx5_ifc_sqc_bits sq_context;
3965 struct mlx5_ifc_query_sq_in_bits {
3967 u8 reserved_at_10[0x10];
3969 u8 reserved_at_20[0x10];
3972 u8 reserved_at_40[0x8];
3975 u8 reserved_at_60[0x20];
3978 struct mlx5_ifc_query_special_contexts_out_bits {
3980 u8 reserved_at_8[0x18];
3984 u8 dump_fill_mkey[0x20];
3990 u8 reserved_at_a0[0x60];
3993 struct mlx5_ifc_query_special_contexts_in_bits {
3995 u8 reserved_at_10[0x10];
3997 u8 reserved_at_20[0x10];
4000 u8 reserved_at_40[0x40];
4003 struct mlx5_ifc_query_scheduling_element_out_bits {
4005 u8 reserved_at_10[0x10];
4007 u8 reserved_at_20[0x10];
4010 u8 reserved_at_40[0xc0];
4012 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4014 u8 reserved_at_300[0x100];
4018 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4021 struct mlx5_ifc_query_scheduling_element_in_bits {
4023 u8 reserved_at_10[0x10];
4025 u8 reserved_at_20[0x10];
4028 u8 scheduling_hierarchy[0x8];
4029 u8 reserved_at_48[0x18];
4031 u8 scheduling_element_id[0x20];
4033 u8 reserved_at_80[0x180];
4036 struct mlx5_ifc_query_rqt_out_bits {
4038 u8 reserved_at_8[0x18];
4042 u8 reserved_at_40[0xc0];
4044 struct mlx5_ifc_rqtc_bits rqt_context;
4047 struct mlx5_ifc_query_rqt_in_bits {
4049 u8 reserved_at_10[0x10];
4051 u8 reserved_at_20[0x10];
4054 u8 reserved_at_40[0x8];
4057 u8 reserved_at_60[0x20];
4060 struct mlx5_ifc_query_rq_out_bits {
4062 u8 reserved_at_8[0x18];
4066 u8 reserved_at_40[0xc0];
4068 struct mlx5_ifc_rqc_bits rq_context;
4071 struct mlx5_ifc_query_rq_in_bits {
4073 u8 reserved_at_10[0x10];
4075 u8 reserved_at_20[0x10];
4078 u8 reserved_at_40[0x8];
4081 u8 reserved_at_60[0x20];
4084 struct mlx5_ifc_query_roce_address_out_bits {
4086 u8 reserved_at_8[0x18];
4090 u8 reserved_at_40[0x40];
4092 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4095 struct mlx5_ifc_query_roce_address_in_bits {
4097 u8 reserved_at_10[0x10];
4099 u8 reserved_at_20[0x10];
4102 u8 roce_address_index[0x10];
4103 u8 reserved_at_50[0xc];
4104 u8 vhca_port_num[0x4];
4106 u8 reserved_at_60[0x20];
4109 struct mlx5_ifc_query_rmp_out_bits {
4111 u8 reserved_at_8[0x18];
4115 u8 reserved_at_40[0xc0];
4117 struct mlx5_ifc_rmpc_bits rmp_context;
4120 struct mlx5_ifc_query_rmp_in_bits {
4122 u8 reserved_at_10[0x10];
4124 u8 reserved_at_20[0x10];
4127 u8 reserved_at_40[0x8];
4130 u8 reserved_at_60[0x20];
4133 struct mlx5_ifc_query_qp_out_bits {
4135 u8 reserved_at_8[0x18];
4139 u8 reserved_at_40[0x40];
4141 u8 opt_param_mask[0x20];
4143 u8 reserved_at_a0[0x20];
4145 struct mlx5_ifc_qpc_bits qpc;
4147 u8 reserved_at_800[0x80];
4152 struct mlx5_ifc_query_qp_in_bits {
4154 u8 reserved_at_10[0x10];
4156 u8 reserved_at_20[0x10];
4159 u8 reserved_at_40[0x8];
4162 u8 reserved_at_60[0x20];
4165 struct mlx5_ifc_query_q_counter_out_bits {
4167 u8 reserved_at_8[0x18];
4171 u8 reserved_at_40[0x40];
4173 u8 rx_write_requests[0x20];
4175 u8 reserved_at_a0[0x20];
4177 u8 rx_read_requests[0x20];
4179 u8 reserved_at_e0[0x20];
4181 u8 rx_atomic_requests[0x20];
4183 u8 reserved_at_120[0x20];
4185 u8 rx_dct_connect[0x20];
4187 u8 reserved_at_160[0x20];
4189 u8 out_of_buffer[0x20];
4191 u8 reserved_at_1a0[0x20];
4193 u8 out_of_sequence[0x20];
4195 u8 reserved_at_1e0[0x20];
4197 u8 duplicate_request[0x20];
4199 u8 reserved_at_220[0x20];
4201 u8 rnr_nak_retry_err[0x20];
4203 u8 reserved_at_260[0x20];
4205 u8 packet_seq_err[0x20];
4207 u8 reserved_at_2a0[0x20];
4209 u8 implied_nak_seq_err[0x20];
4211 u8 reserved_at_2e0[0x20];
4213 u8 local_ack_timeout_err[0x20];
4215 u8 reserved_at_320[0xa0];
4217 u8 resp_local_length_error[0x20];
4219 u8 req_local_length_error[0x20];
4221 u8 resp_local_qp_error[0x20];
4223 u8 local_operation_error[0x20];
4225 u8 resp_local_protection[0x20];
4227 u8 req_local_protection[0x20];
4229 u8 resp_cqe_error[0x20];
4231 u8 req_cqe_error[0x20];
4233 u8 req_mw_binding[0x20];
4235 u8 req_bad_response[0x20];
4237 u8 req_remote_invalid_request[0x20];
4239 u8 resp_remote_invalid_request[0x20];
4241 u8 req_remote_access_errors[0x20];
4243 u8 resp_remote_access_errors[0x20];
4245 u8 req_remote_operation_errors[0x20];
4247 u8 req_transport_retries_exceeded[0x20];
4249 u8 cq_overflow[0x20];
4251 u8 resp_cqe_flush_error[0x20];
4253 u8 req_cqe_flush_error[0x20];
4255 u8 reserved_at_620[0x1e0];
4258 struct mlx5_ifc_query_q_counter_in_bits {
4260 u8 reserved_at_10[0x10];
4262 u8 reserved_at_20[0x10];
4265 u8 reserved_at_40[0x80];
4268 u8 reserved_at_c1[0x1f];
4270 u8 reserved_at_e0[0x18];
4271 u8 counter_set_id[0x8];
4274 struct mlx5_ifc_query_pages_out_bits {
4276 u8 reserved_at_8[0x18];
4280 u8 reserved_at_40[0x10];
4281 u8 function_id[0x10];
4287 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4288 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4289 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4292 struct mlx5_ifc_query_pages_in_bits {
4294 u8 reserved_at_10[0x10];
4296 u8 reserved_at_20[0x10];
4299 u8 reserved_at_40[0x10];
4300 u8 function_id[0x10];
4302 u8 reserved_at_60[0x20];
4305 struct mlx5_ifc_query_nic_vport_context_out_bits {
4307 u8 reserved_at_8[0x18];
4311 u8 reserved_at_40[0x40];
4313 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4316 struct mlx5_ifc_query_nic_vport_context_in_bits {
4318 u8 reserved_at_10[0x10];
4320 u8 reserved_at_20[0x10];
4323 u8 other_vport[0x1];
4324 u8 reserved_at_41[0xf];
4325 u8 vport_number[0x10];
4327 u8 reserved_at_60[0x5];
4328 u8 allowed_list_type[0x3];
4329 u8 reserved_at_68[0x18];
4332 struct mlx5_ifc_query_mkey_out_bits {
4334 u8 reserved_at_8[0x18];
4338 u8 reserved_at_40[0x40];
4340 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4342 u8 reserved_at_280[0x600];
4344 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4346 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4349 struct mlx5_ifc_query_mkey_in_bits {
4351 u8 reserved_at_10[0x10];
4353 u8 reserved_at_20[0x10];
4356 u8 reserved_at_40[0x8];
4357 u8 mkey_index[0x18];
4360 u8 reserved_at_61[0x1f];
4363 struct mlx5_ifc_query_mad_demux_out_bits {
4365 u8 reserved_at_8[0x18];
4369 u8 reserved_at_40[0x40];
4371 u8 mad_dumux_parameters_block[0x20];
4374 struct mlx5_ifc_query_mad_demux_in_bits {
4376 u8 reserved_at_10[0x10];
4378 u8 reserved_at_20[0x10];
4381 u8 reserved_at_40[0x40];
4384 struct mlx5_ifc_query_l2_table_entry_out_bits {
4386 u8 reserved_at_8[0x18];
4390 u8 reserved_at_40[0xa0];
4392 u8 reserved_at_e0[0x13];
4396 struct mlx5_ifc_mac_address_layout_bits mac_address;
4398 u8 reserved_at_140[0xc0];
4401 struct mlx5_ifc_query_l2_table_entry_in_bits {
4403 u8 reserved_at_10[0x10];
4405 u8 reserved_at_20[0x10];
4408 u8 reserved_at_40[0x60];
4410 u8 reserved_at_a0[0x8];
4411 u8 table_index[0x18];
4413 u8 reserved_at_c0[0x140];
4416 struct mlx5_ifc_query_issi_out_bits {
4418 u8 reserved_at_8[0x18];
4422 u8 reserved_at_40[0x10];
4423 u8 current_issi[0x10];
4425 u8 reserved_at_60[0xa0];
4427 u8 reserved_at_100[76][0x8];
4428 u8 supported_issi_dw0[0x20];
4431 struct mlx5_ifc_query_issi_in_bits {
4433 u8 reserved_at_10[0x10];
4435 u8 reserved_at_20[0x10];
4438 u8 reserved_at_40[0x40];
4441 struct mlx5_ifc_set_driver_version_out_bits {
4443 u8 reserved_0[0x18];
4446 u8 reserved_1[0x40];
4449 struct mlx5_ifc_set_driver_version_in_bits {
4451 u8 reserved_0[0x10];
4453 u8 reserved_1[0x10];
4456 u8 reserved_2[0x40];
4457 u8 driver_version[64][0x8];
4460 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4462 u8 reserved_at_8[0x18];
4466 u8 reserved_at_40[0x40];
4468 struct mlx5_ifc_pkey_bits pkey[0];
4471 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4473 u8 reserved_at_10[0x10];
4475 u8 reserved_at_20[0x10];
4478 u8 other_vport[0x1];
4479 u8 reserved_at_41[0xb];
4481 u8 vport_number[0x10];
4483 u8 reserved_at_60[0x10];
4484 u8 pkey_index[0x10];
4488 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4489 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4490 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4493 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4495 u8 reserved_at_8[0x18];
4499 u8 reserved_at_40[0x20];
4502 u8 reserved_at_70[0x10];
4504 struct mlx5_ifc_array128_auto_bits gid[0];
4507 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4509 u8 reserved_at_10[0x10];
4511 u8 reserved_at_20[0x10];
4514 u8 other_vport[0x1];
4515 u8 reserved_at_41[0xb];
4517 u8 vport_number[0x10];
4519 u8 reserved_at_60[0x10];
4523 struct mlx5_ifc_query_hca_vport_context_out_bits {
4525 u8 reserved_at_8[0x18];
4529 u8 reserved_at_40[0x40];
4531 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4534 struct mlx5_ifc_query_hca_vport_context_in_bits {
4536 u8 reserved_at_10[0x10];
4538 u8 reserved_at_20[0x10];
4541 u8 other_vport[0x1];
4542 u8 reserved_at_41[0xb];
4544 u8 vport_number[0x10];
4546 u8 reserved_at_60[0x20];
4549 struct mlx5_ifc_query_hca_cap_out_bits {
4551 u8 reserved_at_8[0x18];
4555 u8 reserved_at_40[0x40];
4557 union mlx5_ifc_hca_cap_union_bits capability;
4560 struct mlx5_ifc_query_hca_cap_in_bits {
4562 u8 reserved_at_10[0x10];
4564 u8 reserved_at_20[0x10];
4567 u8 reserved_at_40[0x40];
4570 struct mlx5_ifc_query_flow_table_out_bits {
4572 u8 reserved_at_8[0x18];
4576 u8 reserved_at_40[0x80];
4578 u8 reserved_at_c0[0x8];
4580 u8 reserved_at_d0[0x8];
4583 u8 reserved_at_e0[0x120];
4586 struct mlx5_ifc_query_flow_table_in_bits {
4588 u8 reserved_at_10[0x10];
4590 u8 reserved_at_20[0x10];
4593 u8 reserved_at_40[0x40];
4596 u8 reserved_at_88[0x18];
4598 u8 reserved_at_a0[0x8];
4601 u8 reserved_at_c0[0x140];
4604 struct mlx5_ifc_query_fte_out_bits {
4606 u8 reserved_at_8[0x18];
4610 u8 reserved_at_40[0x1c0];
4612 struct mlx5_ifc_flow_context_bits flow_context;
4615 struct mlx5_ifc_query_fte_in_bits {
4617 u8 reserved_at_10[0x10];
4619 u8 reserved_at_20[0x10];
4622 u8 reserved_at_40[0x40];
4625 u8 reserved_at_88[0x18];
4627 u8 reserved_at_a0[0x8];
4630 u8 reserved_at_c0[0x40];
4632 u8 flow_index[0x20];
4634 u8 reserved_at_120[0xe0];
4638 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4639 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4640 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4641 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4644 struct mlx5_ifc_query_flow_group_out_bits {
4646 u8 reserved_at_8[0x18];
4650 u8 reserved_at_40[0xa0];
4652 u8 start_flow_index[0x20];
4654 u8 reserved_at_100[0x20];
4656 u8 end_flow_index[0x20];
4658 u8 reserved_at_140[0xa0];
4660 u8 reserved_at_1e0[0x18];
4661 u8 match_criteria_enable[0x8];
4663 struct mlx5_ifc_fte_match_param_bits match_criteria;
4665 u8 reserved_at_1200[0xe00];
4668 struct mlx5_ifc_query_flow_group_in_bits {
4670 u8 reserved_at_10[0x10];
4672 u8 reserved_at_20[0x10];
4675 u8 reserved_at_40[0x40];
4678 u8 reserved_at_88[0x18];
4680 u8 reserved_at_a0[0x8];
4685 u8 reserved_at_e0[0x120];
4688 struct mlx5_ifc_query_flow_counter_out_bits {
4690 u8 reserved_at_8[0x18];
4694 u8 reserved_at_40[0x40];
4696 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4699 struct mlx5_ifc_query_flow_counter_in_bits {
4701 u8 reserved_at_10[0x10];
4703 u8 reserved_at_20[0x10];
4706 u8 reserved_at_40[0x80];
4709 u8 reserved_at_c1[0xf];
4710 u8 num_of_counters[0x10];
4712 u8 flow_counter_id[0x20];
4715 struct mlx5_ifc_query_esw_vport_context_out_bits {
4717 u8 reserved_at_8[0x18];
4721 u8 reserved_at_40[0x40];
4723 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4726 struct mlx5_ifc_query_esw_vport_context_in_bits {
4728 u8 reserved_at_10[0x10];
4730 u8 reserved_at_20[0x10];
4733 u8 other_vport[0x1];
4734 u8 reserved_at_41[0xf];
4735 u8 vport_number[0x10];
4737 u8 reserved_at_60[0x20];
4740 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4742 u8 reserved_at_8[0x18];
4746 u8 reserved_at_40[0x40];
4749 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4750 u8 reserved_at_0[0x1c];
4751 u8 vport_cvlan_insert[0x1];
4752 u8 vport_svlan_insert[0x1];
4753 u8 vport_cvlan_strip[0x1];
4754 u8 vport_svlan_strip[0x1];
4757 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4759 u8 reserved_at_10[0x10];
4761 u8 reserved_at_20[0x10];
4764 u8 other_vport[0x1];
4765 u8 reserved_at_41[0xf];
4766 u8 vport_number[0x10];
4768 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4770 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4773 struct mlx5_ifc_query_eq_out_bits {
4775 u8 reserved_at_8[0x18];
4779 u8 reserved_at_40[0x40];
4781 struct mlx5_ifc_eqc_bits eq_context_entry;
4783 u8 reserved_at_280[0x40];
4785 u8 event_bitmask[0x40];
4787 u8 reserved_at_300[0x580];
4792 struct mlx5_ifc_query_eq_in_bits {
4794 u8 reserved_at_10[0x10];
4796 u8 reserved_at_20[0x10];
4799 u8 reserved_at_40[0x18];
4802 u8 reserved_at_60[0x20];
4805 struct mlx5_ifc_encap_header_in_bits {
4806 u8 reserved_at_0[0x5];
4807 u8 header_type[0x3];
4808 u8 reserved_at_8[0xe];
4809 u8 encap_header_size[0xa];
4811 u8 reserved_at_20[0x10];
4812 u8 encap_header[2][0x8];
4814 u8 more_encap_header[0][0x8];
4817 struct mlx5_ifc_query_encap_header_out_bits {
4819 u8 reserved_at_8[0x18];
4823 u8 reserved_at_40[0xa0];
4825 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4828 struct mlx5_ifc_query_encap_header_in_bits {
4830 u8 reserved_at_10[0x10];
4832 u8 reserved_at_20[0x10];
4837 u8 reserved_at_60[0xa0];
4840 struct mlx5_ifc_alloc_encap_header_out_bits {
4842 u8 reserved_at_8[0x18];
4848 u8 reserved_at_60[0x20];
4852 MLX5_HEADER_TYPE_VXLAN = 0x0,
4853 MLX5_HEADER_TYPE_NVGRE = 0x1,
4856 struct mlx5_ifc_alloc_encap_header_in_bits {
4858 u8 reserved_at_10[0x10];
4860 u8 reserved_at_20[0x10];
4863 u8 reserved_at_40[0xa0];
4865 struct mlx5_ifc_encap_header_in_bits encap_header;
4868 struct mlx5_ifc_dealloc_encap_header_out_bits {
4870 u8 reserved_at_8[0x18];
4874 u8 reserved_at_40[0x40];
4877 struct mlx5_ifc_dealloc_encap_header_in_bits {
4879 u8 reserved_at_10[0x10];
4881 u8 reserved_20[0x10];
4886 u8 reserved_60[0x20];
4889 struct mlx5_ifc_set_action_in_bits {
4890 u8 action_type[0x4];
4892 u8 reserved_at_10[0x3];
4894 u8 reserved_at_18[0x3];
4900 struct mlx5_ifc_add_action_in_bits {
4901 u8 action_type[0x4];
4903 u8 reserved_at_10[0x10];
4908 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4909 struct mlx5_ifc_set_action_in_bits set_action_in;
4910 struct mlx5_ifc_add_action_in_bits add_action_in;
4911 u8 reserved_at_0[0x40];
4915 MLX5_ACTION_TYPE_SET = 0x1,
4916 MLX5_ACTION_TYPE_ADD = 0x2,
4920 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4921 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4922 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4923 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4924 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4925 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4926 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4927 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4928 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4929 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4930 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4931 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4932 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4933 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4934 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4935 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4936 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4937 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4938 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4939 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4940 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4941 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4942 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4945 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4947 u8 reserved_at_8[0x18];
4951 u8 modify_header_id[0x20];
4953 u8 reserved_at_60[0x20];
4956 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4958 u8 reserved_at_10[0x10];
4960 u8 reserved_at_20[0x10];
4963 u8 reserved_at_40[0x20];
4966 u8 reserved_at_68[0x10];
4967 u8 num_of_actions[0x8];
4969 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4972 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4974 u8 reserved_at_8[0x18];
4978 u8 reserved_at_40[0x40];
4981 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4983 u8 reserved_at_10[0x10];
4985 u8 reserved_at_20[0x10];
4988 u8 modify_header_id[0x20];
4990 u8 reserved_at_60[0x20];
4993 struct mlx5_ifc_query_dct_out_bits {
4995 u8 reserved_at_8[0x18];
4999 u8 reserved_at_40[0x40];
5001 struct mlx5_ifc_dctc_bits dct_context_entry;
5003 u8 reserved_at_280[0x180];
5006 struct mlx5_ifc_query_dct_in_bits {
5008 u8 reserved_at_10[0x10];
5010 u8 reserved_at_20[0x10];
5013 u8 reserved_at_40[0x8];
5016 u8 reserved_at_60[0x20];
5019 struct mlx5_ifc_query_cq_out_bits {
5021 u8 reserved_at_8[0x18];
5025 u8 reserved_at_40[0x40];
5027 struct mlx5_ifc_cqc_bits cq_context;
5029 u8 reserved_at_280[0x600];
5034 struct mlx5_ifc_query_cq_in_bits {
5036 u8 reserved_at_10[0x10];
5038 u8 reserved_at_20[0x10];
5041 u8 reserved_at_40[0x8];
5044 u8 reserved_at_60[0x20];
5047 struct mlx5_ifc_query_cong_status_out_bits {
5049 u8 reserved_at_8[0x18];
5053 u8 reserved_at_40[0x20];
5057 u8 reserved_at_62[0x1e];
5060 struct mlx5_ifc_query_cong_status_in_bits {
5062 u8 reserved_at_10[0x10];
5064 u8 reserved_at_20[0x10];
5067 u8 reserved_at_40[0x18];
5069 u8 cong_protocol[0x4];
5071 u8 reserved_at_60[0x20];
5074 struct mlx5_ifc_query_cong_statistics_out_bits {
5076 u8 reserved_at_8[0x18];
5080 u8 reserved_at_40[0x40];
5082 u8 rp_cur_flows[0x20];
5086 u8 rp_cnp_ignored_high[0x20];
5088 u8 rp_cnp_ignored_low[0x20];
5090 u8 rp_cnp_handled_high[0x20];
5092 u8 rp_cnp_handled_low[0x20];
5094 u8 reserved_at_140[0x100];
5096 u8 time_stamp_high[0x20];
5098 u8 time_stamp_low[0x20];
5100 u8 accumulators_period[0x20];
5102 u8 np_ecn_marked_roce_packets_high[0x20];
5104 u8 np_ecn_marked_roce_packets_low[0x20];
5106 u8 np_cnp_sent_high[0x20];
5108 u8 np_cnp_sent_low[0x20];
5110 u8 reserved_at_320[0x560];
5113 struct mlx5_ifc_query_cong_statistics_in_bits {
5115 u8 reserved_at_10[0x10];
5117 u8 reserved_at_20[0x10];
5121 u8 reserved_at_41[0x1f];
5123 u8 reserved_at_60[0x20];
5126 struct mlx5_ifc_query_cong_params_out_bits {
5128 u8 reserved_at_8[0x18];
5132 u8 reserved_at_40[0x40];
5134 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5137 struct mlx5_ifc_query_cong_params_in_bits {
5139 u8 reserved_at_10[0x10];
5141 u8 reserved_at_20[0x10];
5144 u8 reserved_at_40[0x1c];
5145 u8 cong_protocol[0x4];
5147 u8 reserved_at_60[0x20];
5150 struct mlx5_ifc_query_adapter_out_bits {
5152 u8 reserved_at_8[0x18];
5156 u8 reserved_at_40[0x40];
5158 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5161 struct mlx5_ifc_query_adapter_in_bits {
5163 u8 reserved_at_10[0x10];
5165 u8 reserved_at_20[0x10];
5168 u8 reserved_at_40[0x40];
5171 struct mlx5_ifc_qp_2rst_out_bits {
5173 u8 reserved_at_8[0x18];
5177 u8 reserved_at_40[0x40];
5180 struct mlx5_ifc_qp_2rst_in_bits {
5182 u8 reserved_at_10[0x10];
5184 u8 reserved_at_20[0x10];
5187 u8 reserved_at_40[0x8];
5190 u8 reserved_at_60[0x20];
5193 struct mlx5_ifc_qp_2err_out_bits {
5195 u8 reserved_at_8[0x18];
5199 u8 reserved_at_40[0x40];
5202 struct mlx5_ifc_qp_2err_in_bits {
5204 u8 reserved_at_10[0x10];
5206 u8 reserved_at_20[0x10];
5209 u8 reserved_at_40[0x8];
5212 u8 reserved_at_60[0x20];
5215 struct mlx5_ifc_page_fault_resume_out_bits {
5217 u8 reserved_at_8[0x18];
5221 u8 reserved_at_40[0x40];
5224 struct mlx5_ifc_page_fault_resume_in_bits {
5226 u8 reserved_at_10[0x10];
5228 u8 reserved_at_20[0x10];
5232 u8 reserved_at_41[0x4];
5233 u8 page_fault_type[0x3];
5236 u8 reserved_at_60[0x8];
5240 struct mlx5_ifc_nop_out_bits {
5242 u8 reserved_at_8[0x18];
5246 u8 reserved_at_40[0x40];
5249 struct mlx5_ifc_nop_in_bits {
5251 u8 reserved_at_10[0x10];
5253 u8 reserved_at_20[0x10];
5256 u8 reserved_at_40[0x40];
5259 struct mlx5_ifc_modify_vport_state_out_bits {
5261 u8 reserved_at_8[0x18];
5265 u8 reserved_at_40[0x40];
5268 struct mlx5_ifc_modify_vport_state_in_bits {
5270 u8 reserved_at_10[0x10];
5272 u8 reserved_at_20[0x10];
5275 u8 other_vport[0x1];
5276 u8 reserved_at_41[0xf];
5277 u8 vport_number[0x10];
5279 u8 reserved_at_60[0x18];
5280 u8 admin_state[0x4];
5281 u8 reserved_at_7c[0x4];
5284 struct mlx5_ifc_modify_tis_out_bits {
5286 u8 reserved_at_8[0x18];
5290 u8 reserved_at_40[0x40];
5293 struct mlx5_ifc_modify_tis_bitmask_bits {
5294 u8 reserved_at_0[0x20];
5296 u8 reserved_at_20[0x1d];
5297 u8 lag_tx_port_affinity[0x1];
5298 u8 strict_lag_tx_port_affinity[0x1];
5302 struct mlx5_ifc_modify_tis_in_bits {
5304 u8 reserved_at_10[0x10];
5306 u8 reserved_at_20[0x10];
5309 u8 reserved_at_40[0x8];
5312 u8 reserved_at_60[0x20];
5314 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5316 u8 reserved_at_c0[0x40];
5318 struct mlx5_ifc_tisc_bits ctx;
5321 struct mlx5_ifc_modify_tir_bitmask_bits {
5322 u8 reserved_at_0[0x20];
5324 u8 reserved_at_20[0x1b];
5326 u8 reserved_at_3c[0x1];
5328 u8 reserved_at_3e[0x1];
5332 struct mlx5_ifc_modify_tir_out_bits {
5334 u8 reserved_at_8[0x18];
5338 u8 reserved_at_40[0x40];
5341 struct mlx5_ifc_modify_tir_in_bits {
5343 u8 reserved_at_10[0x10];
5345 u8 reserved_at_20[0x10];
5348 u8 reserved_at_40[0x8];
5351 u8 reserved_at_60[0x20];
5353 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5355 u8 reserved_at_c0[0x40];
5357 struct mlx5_ifc_tirc_bits ctx;
5360 struct mlx5_ifc_modify_sq_out_bits {
5362 u8 reserved_at_8[0x18];
5366 u8 reserved_at_40[0x40];
5369 struct mlx5_ifc_modify_sq_in_bits {
5371 u8 reserved_at_10[0x10];
5373 u8 reserved_at_20[0x10];
5377 u8 reserved_at_44[0x4];
5380 u8 reserved_at_60[0x20];
5382 u8 modify_bitmask[0x40];
5384 u8 reserved_at_c0[0x40];
5386 struct mlx5_ifc_sqc_bits ctx;
5389 struct mlx5_ifc_modify_scheduling_element_out_bits {
5391 u8 reserved_at_8[0x18];
5395 u8 reserved_at_40[0x1c0];
5399 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5400 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5403 struct mlx5_ifc_modify_scheduling_element_in_bits {
5405 u8 reserved_at_10[0x10];
5407 u8 reserved_at_20[0x10];
5410 u8 scheduling_hierarchy[0x8];
5411 u8 reserved_at_48[0x18];
5413 u8 scheduling_element_id[0x20];
5415 u8 reserved_at_80[0x20];
5417 u8 modify_bitmask[0x20];
5419 u8 reserved_at_c0[0x40];
5421 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5423 u8 reserved_at_300[0x100];
5426 struct mlx5_ifc_modify_rqt_out_bits {
5428 u8 reserved_at_8[0x18];
5432 u8 reserved_at_40[0x40];
5435 struct mlx5_ifc_rqt_bitmask_bits {
5436 u8 reserved_at_0[0x20];
5438 u8 reserved_at_20[0x1f];
5442 struct mlx5_ifc_modify_rqt_in_bits {
5444 u8 reserved_at_10[0x10];
5446 u8 reserved_at_20[0x10];
5449 u8 reserved_at_40[0x8];
5452 u8 reserved_at_60[0x20];
5454 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5456 u8 reserved_at_c0[0x40];
5458 struct mlx5_ifc_rqtc_bits ctx;
5461 struct mlx5_ifc_modify_rq_out_bits {
5463 u8 reserved_at_8[0x18];
5467 u8 reserved_at_40[0x40];
5471 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5472 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5473 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5476 struct mlx5_ifc_modify_rq_in_bits {
5478 u8 reserved_at_10[0x10];
5480 u8 reserved_at_20[0x10];
5484 u8 reserved_at_44[0x4];
5487 u8 reserved_at_60[0x20];
5489 u8 modify_bitmask[0x40];
5491 u8 reserved_at_c0[0x40];
5493 struct mlx5_ifc_rqc_bits ctx;
5496 struct mlx5_ifc_modify_rmp_out_bits {
5498 u8 reserved_at_8[0x18];
5502 u8 reserved_at_40[0x40];
5505 struct mlx5_ifc_rmp_bitmask_bits {
5506 u8 reserved_at_0[0x20];
5508 u8 reserved_at_20[0x1f];
5512 struct mlx5_ifc_modify_rmp_in_bits {
5514 u8 reserved_at_10[0x10];
5516 u8 reserved_at_20[0x10];
5520 u8 reserved_at_44[0x4];
5523 u8 reserved_at_60[0x20];
5525 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5527 u8 reserved_at_c0[0x40];
5529 struct mlx5_ifc_rmpc_bits ctx;
5532 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5534 u8 reserved_at_8[0x18];
5538 u8 reserved_at_40[0x40];
5541 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5542 u8 reserved_at_0[0x12];
5543 u8 affiliation[0x1];
5544 u8 reserved_at_e[0x1];
5545 u8 disable_uc_local_lb[0x1];
5546 u8 disable_mc_local_lb[0x1];
5551 u8 change_event[0x1];
5553 u8 permanent_address[0x1];
5554 u8 addresses_list[0x1];
5556 u8 reserved_at_1f[0x1];
5559 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5561 u8 reserved_at_10[0x10];
5563 u8 reserved_at_20[0x10];
5566 u8 other_vport[0x1];
5567 u8 reserved_at_41[0xf];
5568 u8 vport_number[0x10];
5570 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5572 u8 reserved_at_80[0x780];
5574 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5577 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5579 u8 reserved_at_8[0x18];
5583 u8 reserved_at_40[0x40];
5586 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5588 u8 reserved_at_10[0x10];
5590 u8 reserved_at_20[0x10];
5593 u8 other_vport[0x1];
5594 u8 reserved_at_41[0xb];
5596 u8 vport_number[0x10];
5598 u8 reserved_at_60[0x20];
5600 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5603 struct mlx5_ifc_modify_cq_out_bits {
5605 u8 reserved_at_8[0x18];
5609 u8 reserved_at_40[0x40];
5613 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5614 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5617 struct mlx5_ifc_modify_cq_in_bits {
5619 u8 reserved_at_10[0x10];
5621 u8 reserved_at_20[0x10];
5624 u8 reserved_at_40[0x8];
5627 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5629 struct mlx5_ifc_cqc_bits cq_context;
5631 u8 reserved_at_280[0x600];
5636 struct mlx5_ifc_modify_cong_status_out_bits {
5638 u8 reserved_at_8[0x18];
5642 u8 reserved_at_40[0x40];
5645 struct mlx5_ifc_modify_cong_status_in_bits {
5647 u8 reserved_at_10[0x10];
5649 u8 reserved_at_20[0x10];
5652 u8 reserved_at_40[0x18];
5654 u8 cong_protocol[0x4];
5658 u8 reserved_at_62[0x1e];
5661 struct mlx5_ifc_modify_cong_params_out_bits {
5663 u8 reserved_at_8[0x18];
5667 u8 reserved_at_40[0x40];
5670 struct mlx5_ifc_modify_cong_params_in_bits {
5672 u8 reserved_at_10[0x10];
5674 u8 reserved_at_20[0x10];
5677 u8 reserved_at_40[0x1c];
5678 u8 cong_protocol[0x4];
5680 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5682 u8 reserved_at_80[0x80];
5684 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5687 struct mlx5_ifc_manage_pages_out_bits {
5689 u8 reserved_at_8[0x18];
5693 u8 output_num_entries[0x20];
5695 u8 reserved_at_60[0x20];
5701 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5702 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5703 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5706 struct mlx5_ifc_manage_pages_in_bits {
5708 u8 reserved_at_10[0x10];
5710 u8 reserved_at_20[0x10];
5713 u8 reserved_at_40[0x10];
5714 u8 function_id[0x10];
5716 u8 input_num_entries[0x20];
5721 struct mlx5_ifc_mad_ifc_out_bits {
5723 u8 reserved_at_8[0x18];
5727 u8 reserved_at_40[0x40];
5729 u8 response_mad_packet[256][0x8];
5732 struct mlx5_ifc_mad_ifc_in_bits {
5734 u8 reserved_at_10[0x10];
5736 u8 reserved_at_20[0x10];
5739 u8 remote_lid[0x10];
5740 u8 reserved_at_50[0x8];
5743 u8 reserved_at_60[0x20];
5748 struct mlx5_ifc_init_hca_out_bits {
5750 u8 reserved_at_8[0x18];
5754 u8 reserved_at_40[0x40];
5757 struct mlx5_ifc_init_hca_in_bits {
5759 u8 reserved_at_10[0x10];
5761 u8 reserved_at_20[0x10];
5764 u8 reserved_at_40[0x40];
5765 u8 sw_owner_id[4][0x20];
5768 struct mlx5_ifc_init2rtr_qp_out_bits {
5770 u8 reserved_at_8[0x18];
5774 u8 reserved_at_40[0x40];
5777 struct mlx5_ifc_init2rtr_qp_in_bits {
5779 u8 reserved_at_10[0x10];
5781 u8 reserved_at_20[0x10];
5784 u8 reserved_at_40[0x8];
5787 u8 reserved_at_60[0x20];
5789 u8 opt_param_mask[0x20];
5791 u8 reserved_at_a0[0x20];
5793 struct mlx5_ifc_qpc_bits qpc;
5795 u8 reserved_at_800[0x80];
5798 struct mlx5_ifc_init2init_qp_out_bits {
5800 u8 reserved_at_8[0x18];
5804 u8 reserved_at_40[0x40];
5807 struct mlx5_ifc_init2init_qp_in_bits {
5809 u8 reserved_at_10[0x10];
5811 u8 reserved_at_20[0x10];
5814 u8 reserved_at_40[0x8];
5817 u8 reserved_at_60[0x20];
5819 u8 opt_param_mask[0x20];
5821 u8 reserved_at_a0[0x20];
5823 struct mlx5_ifc_qpc_bits qpc;
5825 u8 reserved_at_800[0x80];
5828 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5830 u8 reserved_at_8[0x18];
5834 u8 reserved_at_40[0x40];
5836 u8 packet_headers_log[128][0x8];
5838 u8 packet_syndrome[64][0x8];
5841 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5843 u8 reserved_at_10[0x10];
5845 u8 reserved_at_20[0x10];
5848 u8 reserved_at_40[0x40];
5851 struct mlx5_ifc_gen_eqe_in_bits {
5853 u8 reserved_at_10[0x10];
5855 u8 reserved_at_20[0x10];
5858 u8 reserved_at_40[0x18];
5861 u8 reserved_at_60[0x20];
5866 struct mlx5_ifc_gen_eq_out_bits {
5868 u8 reserved_at_8[0x18];
5872 u8 reserved_at_40[0x40];
5875 struct mlx5_ifc_enable_hca_out_bits {
5877 u8 reserved_at_8[0x18];
5881 u8 reserved_at_40[0x20];
5884 struct mlx5_ifc_enable_hca_in_bits {
5886 u8 reserved_at_10[0x10];
5888 u8 reserved_at_20[0x10];
5891 u8 reserved_at_40[0x10];
5892 u8 function_id[0x10];
5894 u8 reserved_at_60[0x20];
5897 struct mlx5_ifc_drain_dct_out_bits {
5899 u8 reserved_at_8[0x18];
5903 u8 reserved_at_40[0x40];
5906 struct mlx5_ifc_drain_dct_in_bits {
5908 u8 reserved_at_10[0x10];
5910 u8 reserved_at_20[0x10];
5913 u8 reserved_at_40[0x8];
5916 u8 reserved_at_60[0x20];
5919 struct mlx5_ifc_disable_hca_out_bits {
5921 u8 reserved_at_8[0x18];
5925 u8 reserved_at_40[0x20];
5928 struct mlx5_ifc_disable_hca_in_bits {
5930 u8 reserved_at_10[0x10];
5932 u8 reserved_at_20[0x10];
5935 u8 reserved_at_40[0x10];
5936 u8 function_id[0x10];
5938 u8 reserved_at_60[0x20];
5941 struct mlx5_ifc_detach_from_mcg_out_bits {
5943 u8 reserved_at_8[0x18];
5947 u8 reserved_at_40[0x40];
5950 struct mlx5_ifc_detach_from_mcg_in_bits {
5952 u8 reserved_at_10[0x10];
5954 u8 reserved_at_20[0x10];
5957 u8 reserved_at_40[0x8];
5960 u8 reserved_at_60[0x20];
5962 u8 multicast_gid[16][0x8];
5965 struct mlx5_ifc_destroy_xrq_out_bits {
5967 u8 reserved_at_8[0x18];
5971 u8 reserved_at_40[0x40];
5974 struct mlx5_ifc_destroy_xrq_in_bits {
5976 u8 reserved_at_10[0x10];
5978 u8 reserved_at_20[0x10];
5981 u8 reserved_at_40[0x8];
5984 u8 reserved_at_60[0x20];
5987 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5989 u8 reserved_at_8[0x18];
5993 u8 reserved_at_40[0x40];
5996 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5998 u8 reserved_at_10[0x10];
6000 u8 reserved_at_20[0x10];
6003 u8 reserved_at_40[0x8];
6006 u8 reserved_at_60[0x20];
6009 struct mlx5_ifc_destroy_tis_out_bits {
6011 u8 reserved_at_8[0x18];
6015 u8 reserved_at_40[0x40];
6018 struct mlx5_ifc_destroy_tis_in_bits {
6020 u8 reserved_at_10[0x10];
6022 u8 reserved_at_20[0x10];
6025 u8 reserved_at_40[0x8];
6028 u8 reserved_at_60[0x20];
6031 struct mlx5_ifc_destroy_tir_out_bits {
6033 u8 reserved_at_8[0x18];
6037 u8 reserved_at_40[0x40];
6040 struct mlx5_ifc_destroy_tir_in_bits {
6042 u8 reserved_at_10[0x10];
6044 u8 reserved_at_20[0x10];
6047 u8 reserved_at_40[0x8];
6050 u8 reserved_at_60[0x20];
6053 struct mlx5_ifc_destroy_srq_out_bits {
6055 u8 reserved_at_8[0x18];
6059 u8 reserved_at_40[0x40];
6062 struct mlx5_ifc_destroy_srq_in_bits {
6064 u8 reserved_at_10[0x10];
6066 u8 reserved_at_20[0x10];
6069 u8 reserved_at_40[0x8];
6072 u8 reserved_at_60[0x20];
6075 struct mlx5_ifc_destroy_sq_out_bits {
6077 u8 reserved_at_8[0x18];
6081 u8 reserved_at_40[0x40];
6084 struct mlx5_ifc_destroy_sq_in_bits {
6086 u8 reserved_at_10[0x10];
6088 u8 reserved_at_20[0x10];
6091 u8 reserved_at_40[0x8];
6094 u8 reserved_at_60[0x20];
6097 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6099 u8 reserved_at_8[0x18];
6103 u8 reserved_at_40[0x1c0];
6106 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6108 u8 reserved_at_10[0x10];
6110 u8 reserved_at_20[0x10];
6113 u8 scheduling_hierarchy[0x8];
6114 u8 reserved_at_48[0x18];
6116 u8 scheduling_element_id[0x20];
6118 u8 reserved_at_80[0x180];
6121 struct mlx5_ifc_destroy_rqt_out_bits {
6123 u8 reserved_at_8[0x18];
6127 u8 reserved_at_40[0x40];
6130 struct mlx5_ifc_destroy_rqt_in_bits {
6132 u8 reserved_at_10[0x10];
6134 u8 reserved_at_20[0x10];
6137 u8 reserved_at_40[0x8];
6140 u8 reserved_at_60[0x20];
6143 struct mlx5_ifc_destroy_rq_out_bits {
6145 u8 reserved_at_8[0x18];
6149 u8 reserved_at_40[0x40];
6152 struct mlx5_ifc_destroy_rq_in_bits {
6154 u8 reserved_at_10[0x10];
6156 u8 reserved_at_20[0x10];
6159 u8 reserved_at_40[0x8];
6162 u8 reserved_at_60[0x20];
6165 struct mlx5_ifc_set_delay_drop_params_in_bits {
6167 u8 reserved_at_10[0x10];
6169 u8 reserved_at_20[0x10];
6172 u8 reserved_at_40[0x20];
6174 u8 reserved_at_60[0x10];
6175 u8 delay_drop_timeout[0x10];
6178 struct mlx5_ifc_set_delay_drop_params_out_bits {
6180 u8 reserved_at_8[0x18];
6184 u8 reserved_at_40[0x40];
6187 struct mlx5_ifc_destroy_rmp_out_bits {
6189 u8 reserved_at_8[0x18];
6193 u8 reserved_at_40[0x40];
6196 struct mlx5_ifc_destroy_rmp_in_bits {
6198 u8 reserved_at_10[0x10];
6200 u8 reserved_at_20[0x10];
6203 u8 reserved_at_40[0x8];
6206 u8 reserved_at_60[0x20];
6209 struct mlx5_ifc_destroy_qp_out_bits {
6211 u8 reserved_at_8[0x18];
6215 u8 reserved_at_40[0x40];
6218 struct mlx5_ifc_destroy_qp_in_bits {
6220 u8 reserved_at_10[0x10];
6222 u8 reserved_at_20[0x10];
6225 u8 reserved_at_40[0x8];
6228 u8 reserved_at_60[0x20];
6231 struct mlx5_ifc_destroy_psv_out_bits {
6233 u8 reserved_at_8[0x18];
6237 u8 reserved_at_40[0x40];
6240 struct mlx5_ifc_destroy_psv_in_bits {
6242 u8 reserved_at_10[0x10];
6244 u8 reserved_at_20[0x10];
6247 u8 reserved_at_40[0x8];
6250 u8 reserved_at_60[0x20];
6253 struct mlx5_ifc_destroy_mkey_out_bits {
6255 u8 reserved_at_8[0x18];
6259 u8 reserved_at_40[0x40];
6262 struct mlx5_ifc_destroy_mkey_in_bits {
6264 u8 reserved_at_10[0x10];
6266 u8 reserved_at_20[0x10];
6269 u8 reserved_at_40[0x8];
6270 u8 mkey_index[0x18];
6272 u8 reserved_at_60[0x20];
6275 struct mlx5_ifc_destroy_flow_table_out_bits {
6277 u8 reserved_at_8[0x18];
6281 u8 reserved_at_40[0x40];
6284 struct mlx5_ifc_destroy_flow_table_in_bits {
6286 u8 reserved_at_10[0x10];
6288 u8 reserved_at_20[0x10];
6291 u8 other_vport[0x1];
6292 u8 reserved_at_41[0xf];
6293 u8 vport_number[0x10];
6295 u8 reserved_at_60[0x20];
6298 u8 reserved_at_88[0x18];
6300 u8 reserved_at_a0[0x8];
6303 u8 reserved_at_c0[0x140];
6306 struct mlx5_ifc_destroy_flow_group_out_bits {
6308 u8 reserved_at_8[0x18];
6312 u8 reserved_at_40[0x40];
6315 struct mlx5_ifc_destroy_flow_group_in_bits {
6317 u8 reserved_at_10[0x10];
6319 u8 reserved_at_20[0x10];
6322 u8 other_vport[0x1];
6323 u8 reserved_at_41[0xf];
6324 u8 vport_number[0x10];
6326 u8 reserved_at_60[0x20];
6329 u8 reserved_at_88[0x18];
6331 u8 reserved_at_a0[0x8];
6336 u8 reserved_at_e0[0x120];
6339 struct mlx5_ifc_destroy_eq_out_bits {
6341 u8 reserved_at_8[0x18];
6345 u8 reserved_at_40[0x40];
6348 struct mlx5_ifc_destroy_eq_in_bits {
6350 u8 reserved_at_10[0x10];
6352 u8 reserved_at_20[0x10];
6355 u8 reserved_at_40[0x18];
6358 u8 reserved_at_60[0x20];
6361 struct mlx5_ifc_destroy_dct_out_bits {
6363 u8 reserved_at_8[0x18];
6367 u8 reserved_at_40[0x40];
6370 struct mlx5_ifc_destroy_dct_in_bits {
6372 u8 reserved_at_10[0x10];
6374 u8 reserved_at_20[0x10];
6377 u8 reserved_at_40[0x8];
6380 u8 reserved_at_60[0x20];
6383 struct mlx5_ifc_destroy_cq_out_bits {
6385 u8 reserved_at_8[0x18];
6389 u8 reserved_at_40[0x40];
6392 struct mlx5_ifc_destroy_cq_in_bits {
6394 u8 reserved_at_10[0x10];
6396 u8 reserved_at_20[0x10];
6399 u8 reserved_at_40[0x8];
6402 u8 reserved_at_60[0x20];
6405 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6407 u8 reserved_at_8[0x18];
6411 u8 reserved_at_40[0x40];
6414 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6416 u8 reserved_at_10[0x10];
6418 u8 reserved_at_20[0x10];
6421 u8 reserved_at_40[0x20];
6423 u8 reserved_at_60[0x10];
6424 u8 vxlan_udp_port[0x10];
6427 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6429 u8 reserved_at_8[0x18];
6433 u8 reserved_at_40[0x40];
6436 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6438 u8 reserved_at_10[0x10];
6440 u8 reserved_at_20[0x10];
6443 u8 reserved_at_40[0x60];
6445 u8 reserved_at_a0[0x8];
6446 u8 table_index[0x18];
6448 u8 reserved_at_c0[0x140];
6451 struct mlx5_ifc_delete_fte_out_bits {
6453 u8 reserved_at_8[0x18];
6457 u8 reserved_at_40[0x40];
6460 struct mlx5_ifc_delete_fte_in_bits {
6462 u8 reserved_at_10[0x10];
6464 u8 reserved_at_20[0x10];
6467 u8 other_vport[0x1];
6468 u8 reserved_at_41[0xf];
6469 u8 vport_number[0x10];
6471 u8 reserved_at_60[0x20];
6474 u8 reserved_at_88[0x18];
6476 u8 reserved_at_a0[0x8];
6479 u8 reserved_at_c0[0x40];
6481 u8 flow_index[0x20];
6483 u8 reserved_at_120[0xe0];
6486 struct mlx5_ifc_dealloc_xrcd_out_bits {
6488 u8 reserved_at_8[0x18];
6492 u8 reserved_at_40[0x40];
6495 struct mlx5_ifc_dealloc_xrcd_in_bits {
6497 u8 reserved_at_10[0x10];
6499 u8 reserved_at_20[0x10];
6502 u8 reserved_at_40[0x8];
6505 u8 reserved_at_60[0x20];
6508 struct mlx5_ifc_dealloc_uar_out_bits {
6510 u8 reserved_at_8[0x18];
6514 u8 reserved_at_40[0x40];
6517 struct mlx5_ifc_dealloc_uar_in_bits {
6519 u8 reserved_at_10[0x10];
6521 u8 reserved_at_20[0x10];
6524 u8 reserved_at_40[0x8];
6527 u8 reserved_at_60[0x20];
6530 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6532 u8 reserved_at_8[0x18];
6536 u8 reserved_at_40[0x40];
6539 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6541 u8 reserved_at_10[0x10];
6543 u8 reserved_at_20[0x10];
6546 u8 reserved_at_40[0x8];
6547 u8 transport_domain[0x18];
6549 u8 reserved_at_60[0x20];
6552 struct mlx5_ifc_dealloc_q_counter_out_bits {
6554 u8 reserved_at_8[0x18];
6558 u8 reserved_at_40[0x40];
6561 struct mlx5_ifc_dealloc_q_counter_in_bits {
6563 u8 reserved_at_10[0x10];
6565 u8 reserved_at_20[0x10];
6568 u8 reserved_at_40[0x18];
6569 u8 counter_set_id[0x8];
6571 u8 reserved_at_60[0x20];
6574 struct mlx5_ifc_dealloc_pd_out_bits {
6576 u8 reserved_at_8[0x18];
6580 u8 reserved_at_40[0x40];
6583 struct mlx5_ifc_dealloc_pd_in_bits {
6585 u8 reserved_at_10[0x10];
6587 u8 reserved_at_20[0x10];
6590 u8 reserved_at_40[0x8];
6593 u8 reserved_at_60[0x20];
6596 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6598 u8 reserved_at_8[0x18];
6602 u8 reserved_at_40[0x40];
6605 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6607 u8 reserved_at_10[0x10];
6609 u8 reserved_at_20[0x10];
6612 u8 flow_counter_id[0x20];
6614 u8 reserved_at_60[0x20];
6617 struct mlx5_ifc_create_xrq_out_bits {
6619 u8 reserved_at_8[0x18];
6623 u8 reserved_at_40[0x8];
6626 u8 reserved_at_60[0x20];
6629 struct mlx5_ifc_create_xrq_in_bits {
6631 u8 reserved_at_10[0x10];
6633 u8 reserved_at_20[0x10];
6636 u8 reserved_at_40[0x40];
6638 struct mlx5_ifc_xrqc_bits xrq_context;
6641 struct mlx5_ifc_create_xrc_srq_out_bits {
6643 u8 reserved_at_8[0x18];
6647 u8 reserved_at_40[0x8];
6650 u8 reserved_at_60[0x20];
6653 struct mlx5_ifc_create_xrc_srq_in_bits {
6655 u8 reserved_at_10[0x10];
6657 u8 reserved_at_20[0x10];
6660 u8 reserved_at_40[0x40];
6662 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6664 u8 reserved_at_280[0x600];
6669 struct mlx5_ifc_create_tis_out_bits {
6671 u8 reserved_at_8[0x18];
6675 u8 reserved_at_40[0x8];
6678 u8 reserved_at_60[0x20];
6681 struct mlx5_ifc_create_tis_in_bits {
6683 u8 reserved_at_10[0x10];
6685 u8 reserved_at_20[0x10];
6688 u8 reserved_at_40[0xc0];
6690 struct mlx5_ifc_tisc_bits ctx;
6693 struct mlx5_ifc_create_tir_out_bits {
6695 u8 reserved_at_8[0x18];
6699 u8 reserved_at_40[0x8];
6702 u8 reserved_at_60[0x20];
6705 struct mlx5_ifc_create_tir_in_bits {
6707 u8 reserved_at_10[0x10];
6709 u8 reserved_at_20[0x10];
6712 u8 reserved_at_40[0xc0];
6714 struct mlx5_ifc_tirc_bits ctx;
6717 struct mlx5_ifc_create_srq_out_bits {
6719 u8 reserved_at_8[0x18];
6723 u8 reserved_at_40[0x8];
6726 u8 reserved_at_60[0x20];
6729 struct mlx5_ifc_create_srq_in_bits {
6731 u8 reserved_at_10[0x10];
6733 u8 reserved_at_20[0x10];
6736 u8 reserved_at_40[0x40];
6738 struct mlx5_ifc_srqc_bits srq_context_entry;
6740 u8 reserved_at_280[0x600];
6745 struct mlx5_ifc_create_sq_out_bits {
6747 u8 reserved_at_8[0x18];
6751 u8 reserved_at_40[0x8];
6754 u8 reserved_at_60[0x20];
6757 struct mlx5_ifc_create_sq_in_bits {
6759 u8 reserved_at_10[0x10];
6761 u8 reserved_at_20[0x10];
6764 u8 reserved_at_40[0xc0];
6766 struct mlx5_ifc_sqc_bits ctx;
6769 struct mlx5_ifc_create_scheduling_element_out_bits {
6771 u8 reserved_at_8[0x18];
6775 u8 reserved_at_40[0x40];
6777 u8 scheduling_element_id[0x20];
6779 u8 reserved_at_a0[0x160];
6782 struct mlx5_ifc_create_scheduling_element_in_bits {
6784 u8 reserved_at_10[0x10];
6786 u8 reserved_at_20[0x10];
6789 u8 scheduling_hierarchy[0x8];
6790 u8 reserved_at_48[0x18];
6792 u8 reserved_at_60[0xa0];
6794 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6796 u8 reserved_at_300[0x100];
6799 struct mlx5_ifc_create_rqt_out_bits {
6801 u8 reserved_at_8[0x18];
6805 u8 reserved_at_40[0x8];
6808 u8 reserved_at_60[0x20];
6811 struct mlx5_ifc_create_rqt_in_bits {
6813 u8 reserved_at_10[0x10];
6815 u8 reserved_at_20[0x10];
6818 u8 reserved_at_40[0xc0];
6820 struct mlx5_ifc_rqtc_bits rqt_context;
6823 struct mlx5_ifc_create_rq_out_bits {
6825 u8 reserved_at_8[0x18];
6829 u8 reserved_at_40[0x8];
6832 u8 reserved_at_60[0x20];
6835 struct mlx5_ifc_create_rq_in_bits {
6837 u8 reserved_at_10[0x10];
6839 u8 reserved_at_20[0x10];
6842 u8 reserved_at_40[0xc0];
6844 struct mlx5_ifc_rqc_bits ctx;
6847 struct mlx5_ifc_create_rmp_out_bits {
6849 u8 reserved_at_8[0x18];
6853 u8 reserved_at_40[0x8];
6856 u8 reserved_at_60[0x20];
6859 struct mlx5_ifc_create_rmp_in_bits {
6861 u8 reserved_at_10[0x10];
6863 u8 reserved_at_20[0x10];
6866 u8 reserved_at_40[0xc0];
6868 struct mlx5_ifc_rmpc_bits ctx;
6871 struct mlx5_ifc_create_qp_out_bits {
6873 u8 reserved_at_8[0x18];
6877 u8 reserved_at_40[0x8];
6880 u8 reserved_at_60[0x20];
6883 struct mlx5_ifc_create_qp_in_bits {
6885 u8 reserved_at_10[0x10];
6887 u8 reserved_at_20[0x10];
6890 u8 reserved_at_40[0x40];
6892 u8 opt_param_mask[0x20];
6894 u8 reserved_at_a0[0x20];
6896 struct mlx5_ifc_qpc_bits qpc;
6898 u8 reserved_at_800[0x80];
6903 struct mlx5_ifc_create_psv_out_bits {
6905 u8 reserved_at_8[0x18];
6909 u8 reserved_at_40[0x40];
6911 u8 reserved_at_80[0x8];
6912 u8 psv0_index[0x18];
6914 u8 reserved_at_a0[0x8];
6915 u8 psv1_index[0x18];
6917 u8 reserved_at_c0[0x8];
6918 u8 psv2_index[0x18];
6920 u8 reserved_at_e0[0x8];
6921 u8 psv3_index[0x18];
6924 struct mlx5_ifc_create_psv_in_bits {
6926 u8 reserved_at_10[0x10];
6928 u8 reserved_at_20[0x10];
6932 u8 reserved_at_44[0x4];
6935 u8 reserved_at_60[0x20];
6938 struct mlx5_ifc_create_mkey_out_bits {
6940 u8 reserved_at_8[0x18];
6944 u8 reserved_at_40[0x8];
6945 u8 mkey_index[0x18];
6947 u8 reserved_at_60[0x20];
6950 struct mlx5_ifc_create_mkey_in_bits {
6952 u8 reserved_at_10[0x10];
6954 u8 reserved_at_20[0x10];
6957 u8 reserved_at_40[0x20];
6960 u8 reserved_at_61[0x1f];
6962 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6964 u8 reserved_at_280[0x80];
6966 u8 translations_octword_actual_size[0x20];
6968 u8 reserved_at_320[0x560];
6970 u8 klm_pas_mtt[0][0x20];
6973 struct mlx5_ifc_create_flow_table_out_bits {
6975 u8 reserved_at_8[0x18];
6979 u8 reserved_at_40[0x8];
6982 u8 reserved_at_60[0x20];
6985 struct mlx5_ifc_flow_table_context_bits {
6988 u8 reserved_at_2[0x2];
6989 u8 table_miss_action[0x4];
6991 u8 reserved_at_10[0x8];
6994 u8 reserved_at_20[0x8];
6995 u8 table_miss_id[0x18];
6997 u8 reserved_at_40[0x8];
6998 u8 lag_master_next_table_id[0x18];
7000 u8 reserved_at_60[0xe0];
7003 struct mlx5_ifc_create_flow_table_in_bits {
7005 u8 reserved_at_10[0x10];
7007 u8 reserved_at_20[0x10];
7010 u8 other_vport[0x1];
7011 u8 reserved_at_41[0xf];
7012 u8 vport_number[0x10];
7014 u8 reserved_at_60[0x20];
7017 u8 reserved_at_88[0x18];
7019 u8 reserved_at_a0[0x20];
7021 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7024 struct mlx5_ifc_create_flow_group_out_bits {
7026 u8 reserved_at_8[0x18];
7030 u8 reserved_at_40[0x8];
7033 u8 reserved_at_60[0x20];
7037 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7038 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7039 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7040 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7043 struct mlx5_ifc_create_flow_group_in_bits {
7045 u8 reserved_at_10[0x10];
7047 u8 reserved_at_20[0x10];
7050 u8 other_vport[0x1];
7051 u8 reserved_at_41[0xf];
7052 u8 vport_number[0x10];
7054 u8 reserved_at_60[0x20];
7057 u8 reserved_at_88[0x18];
7059 u8 reserved_at_a0[0x8];
7062 u8 source_eswitch_owner_vhca_id_valid[0x1];
7064 u8 reserved_at_c1[0x1f];
7066 u8 start_flow_index[0x20];
7068 u8 reserved_at_100[0x20];
7070 u8 end_flow_index[0x20];
7072 u8 reserved_at_140[0xa0];
7074 u8 reserved_at_1e0[0x18];
7075 u8 match_criteria_enable[0x8];
7077 struct mlx5_ifc_fte_match_param_bits match_criteria;
7079 u8 reserved_at_1200[0xe00];
7082 struct mlx5_ifc_create_eq_out_bits {
7084 u8 reserved_at_8[0x18];
7088 u8 reserved_at_40[0x18];
7091 u8 reserved_at_60[0x20];
7094 struct mlx5_ifc_create_eq_in_bits {
7096 u8 reserved_at_10[0x10];
7098 u8 reserved_at_20[0x10];
7101 u8 reserved_at_40[0x40];
7103 struct mlx5_ifc_eqc_bits eq_context_entry;
7105 u8 reserved_at_280[0x40];
7107 u8 event_bitmask[0x40];
7109 u8 reserved_at_300[0x580];
7114 struct mlx5_ifc_create_dct_out_bits {
7116 u8 reserved_at_8[0x18];
7120 u8 reserved_at_40[0x8];
7123 u8 reserved_at_60[0x20];
7126 struct mlx5_ifc_create_dct_in_bits {
7128 u8 reserved_at_10[0x10];
7130 u8 reserved_at_20[0x10];
7133 u8 reserved_at_40[0x40];
7135 struct mlx5_ifc_dctc_bits dct_context_entry;
7137 u8 reserved_at_280[0x180];
7140 struct mlx5_ifc_create_cq_out_bits {
7142 u8 reserved_at_8[0x18];
7146 u8 reserved_at_40[0x8];
7149 u8 reserved_at_60[0x20];
7152 struct mlx5_ifc_create_cq_in_bits {
7154 u8 reserved_at_10[0x10];
7156 u8 reserved_at_20[0x10];
7159 u8 reserved_at_40[0x40];
7161 struct mlx5_ifc_cqc_bits cq_context;
7163 u8 reserved_at_280[0x600];
7168 struct mlx5_ifc_config_int_moderation_out_bits {
7170 u8 reserved_at_8[0x18];
7174 u8 reserved_at_40[0x4];
7176 u8 int_vector[0x10];
7178 u8 reserved_at_60[0x20];
7182 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7183 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7186 struct mlx5_ifc_config_int_moderation_in_bits {
7188 u8 reserved_at_10[0x10];
7190 u8 reserved_at_20[0x10];
7193 u8 reserved_at_40[0x4];
7195 u8 int_vector[0x10];
7197 u8 reserved_at_60[0x20];
7200 struct mlx5_ifc_attach_to_mcg_out_bits {
7202 u8 reserved_at_8[0x18];
7206 u8 reserved_at_40[0x40];
7209 struct mlx5_ifc_attach_to_mcg_in_bits {
7211 u8 reserved_at_10[0x10];
7213 u8 reserved_at_20[0x10];
7216 u8 reserved_at_40[0x8];
7219 u8 reserved_at_60[0x20];
7221 u8 multicast_gid[16][0x8];
7224 struct mlx5_ifc_arm_xrq_out_bits {
7226 u8 reserved_at_8[0x18];
7230 u8 reserved_at_40[0x40];
7233 struct mlx5_ifc_arm_xrq_in_bits {
7235 u8 reserved_at_10[0x10];
7237 u8 reserved_at_20[0x10];
7240 u8 reserved_at_40[0x8];
7243 u8 reserved_at_60[0x10];
7247 struct mlx5_ifc_arm_xrc_srq_out_bits {
7249 u8 reserved_at_8[0x18];
7253 u8 reserved_at_40[0x40];
7257 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7260 struct mlx5_ifc_arm_xrc_srq_in_bits {
7262 u8 reserved_at_10[0x10];
7264 u8 reserved_at_20[0x10];
7267 u8 reserved_at_40[0x8];
7270 u8 reserved_at_60[0x10];
7274 struct mlx5_ifc_arm_rq_out_bits {
7276 u8 reserved_at_8[0x18];
7280 u8 reserved_at_40[0x40];
7284 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7285 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7288 struct mlx5_ifc_arm_rq_in_bits {
7290 u8 reserved_at_10[0x10];
7292 u8 reserved_at_20[0x10];
7295 u8 reserved_at_40[0x8];
7296 u8 srq_number[0x18];
7298 u8 reserved_at_60[0x10];
7302 struct mlx5_ifc_arm_dct_out_bits {
7304 u8 reserved_at_8[0x18];
7308 u8 reserved_at_40[0x40];
7311 struct mlx5_ifc_arm_dct_in_bits {
7313 u8 reserved_at_10[0x10];
7315 u8 reserved_at_20[0x10];
7318 u8 reserved_at_40[0x8];
7319 u8 dct_number[0x18];
7321 u8 reserved_at_60[0x20];
7324 struct mlx5_ifc_alloc_xrcd_out_bits {
7326 u8 reserved_at_8[0x18];
7330 u8 reserved_at_40[0x8];
7333 u8 reserved_at_60[0x20];
7336 struct mlx5_ifc_alloc_xrcd_in_bits {
7338 u8 reserved_at_10[0x10];
7340 u8 reserved_at_20[0x10];
7343 u8 reserved_at_40[0x40];
7346 struct mlx5_ifc_alloc_uar_out_bits {
7348 u8 reserved_at_8[0x18];
7352 u8 reserved_at_40[0x8];
7355 u8 reserved_at_60[0x20];
7358 struct mlx5_ifc_alloc_uar_in_bits {
7360 u8 reserved_at_10[0x10];
7362 u8 reserved_at_20[0x10];
7365 u8 reserved_at_40[0x40];
7368 struct mlx5_ifc_alloc_transport_domain_out_bits {
7370 u8 reserved_at_8[0x18];
7374 u8 reserved_at_40[0x8];
7375 u8 transport_domain[0x18];
7377 u8 reserved_at_60[0x20];
7380 struct mlx5_ifc_alloc_transport_domain_in_bits {
7382 u8 reserved_at_10[0x10];
7384 u8 reserved_at_20[0x10];
7387 u8 reserved_at_40[0x40];
7390 struct mlx5_ifc_alloc_q_counter_out_bits {
7392 u8 reserved_at_8[0x18];
7396 u8 reserved_at_40[0x18];
7397 u8 counter_set_id[0x8];
7399 u8 reserved_at_60[0x20];
7402 struct mlx5_ifc_alloc_q_counter_in_bits {
7404 u8 reserved_at_10[0x10];
7406 u8 reserved_at_20[0x10];
7409 u8 reserved_at_40[0x40];
7412 struct mlx5_ifc_alloc_pd_out_bits {
7414 u8 reserved_at_8[0x18];
7418 u8 reserved_at_40[0x8];
7421 u8 reserved_at_60[0x20];
7424 struct mlx5_ifc_alloc_pd_in_bits {
7426 u8 reserved_at_10[0x10];
7428 u8 reserved_at_20[0x10];
7431 u8 reserved_at_40[0x40];
7434 struct mlx5_ifc_alloc_flow_counter_out_bits {
7436 u8 reserved_at_8[0x18];
7440 u8 flow_counter_id[0x20];
7442 u8 reserved_at_60[0x20];
7445 struct mlx5_ifc_alloc_flow_counter_in_bits {
7447 u8 reserved_at_10[0x10];
7449 u8 reserved_at_20[0x10];
7452 u8 reserved_at_40[0x40];
7455 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7457 u8 reserved_at_8[0x18];
7461 u8 reserved_at_40[0x40];
7464 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7466 u8 reserved_at_10[0x10];
7468 u8 reserved_at_20[0x10];
7471 u8 reserved_at_40[0x20];
7473 u8 reserved_at_60[0x10];
7474 u8 vxlan_udp_port[0x10];
7477 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7479 u8 reserved_at_8[0x18];
7483 u8 reserved_at_40[0x40];
7486 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7488 u8 reserved_at_10[0x10];
7490 u8 reserved_at_20[0x10];
7493 u8 reserved_at_40[0x10];
7494 u8 rate_limit_index[0x10];
7496 u8 reserved_at_60[0x20];
7498 u8 rate_limit[0x20];
7500 u8 burst_upper_bound[0x20];
7502 u8 reserved_at_c0[0x10];
7503 u8 typical_packet_size[0x10];
7505 u8 reserved_at_e0[0x120];
7508 struct mlx5_ifc_access_register_out_bits {
7510 u8 reserved_at_8[0x18];
7514 u8 reserved_at_40[0x40];
7516 u8 register_data[0][0x20];
7520 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7521 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7524 struct mlx5_ifc_access_register_in_bits {
7526 u8 reserved_at_10[0x10];
7528 u8 reserved_at_20[0x10];
7531 u8 reserved_at_40[0x10];
7532 u8 register_id[0x10];
7536 u8 register_data[0][0x20];
7539 struct mlx5_ifc_sltp_reg_bits {
7544 u8 reserved_at_12[0x2];
7546 u8 reserved_at_18[0x8];
7548 u8 reserved_at_20[0x20];
7550 u8 reserved_at_40[0x7];
7556 u8 reserved_at_60[0xc];
7557 u8 ob_preemp_mode[0x4];
7561 u8 reserved_at_80[0x20];
7564 struct mlx5_ifc_slrg_reg_bits {
7569 u8 reserved_at_12[0x2];
7571 u8 reserved_at_18[0x8];
7573 u8 time_to_link_up[0x10];
7574 u8 reserved_at_30[0xc];
7575 u8 grade_lane_speed[0x4];
7577 u8 grade_version[0x8];
7580 u8 reserved_at_60[0x4];
7581 u8 height_grade_type[0x4];
7582 u8 height_grade[0x18];
7587 u8 reserved_at_a0[0x10];
7588 u8 height_sigma[0x10];
7590 u8 reserved_at_c0[0x20];
7592 u8 reserved_at_e0[0x4];
7593 u8 phase_grade_type[0x4];
7594 u8 phase_grade[0x18];
7596 u8 reserved_at_100[0x8];
7597 u8 phase_eo_pos[0x8];
7598 u8 reserved_at_110[0x8];
7599 u8 phase_eo_neg[0x8];
7601 u8 ffe_set_tested[0x10];
7602 u8 test_errors_per_lane[0x10];
7605 struct mlx5_ifc_pvlc_reg_bits {
7606 u8 reserved_at_0[0x8];
7608 u8 reserved_at_10[0x10];
7610 u8 reserved_at_20[0x1c];
7613 u8 reserved_at_40[0x1c];
7616 u8 reserved_at_60[0x1c];
7617 u8 vl_operational[0x4];
7620 struct mlx5_ifc_pude_reg_bits {
7623 u8 reserved_at_10[0x4];
7624 u8 admin_status[0x4];
7625 u8 reserved_at_18[0x4];
7626 u8 oper_status[0x4];
7628 u8 reserved_at_20[0x60];
7631 struct mlx5_ifc_ptys_reg_bits {
7632 u8 reserved_at_0[0x1];
7633 u8 an_disable_admin[0x1];
7634 u8 an_disable_cap[0x1];
7635 u8 reserved_at_3[0x5];
7637 u8 reserved_at_10[0xd];
7641 u8 reserved_at_24[0x3c];
7643 u8 eth_proto_capability[0x20];
7645 u8 ib_link_width_capability[0x10];
7646 u8 ib_proto_capability[0x10];
7648 u8 reserved_at_a0[0x20];
7650 u8 eth_proto_admin[0x20];
7652 u8 ib_link_width_admin[0x10];
7653 u8 ib_proto_admin[0x10];
7655 u8 reserved_at_100[0x20];
7657 u8 eth_proto_oper[0x20];
7659 u8 ib_link_width_oper[0x10];
7660 u8 ib_proto_oper[0x10];
7662 u8 reserved_at_160[0x1c];
7663 u8 connector_type[0x4];
7665 u8 eth_proto_lp_advertise[0x20];
7667 u8 reserved_at_1a0[0x60];
7670 struct mlx5_ifc_mlcr_reg_bits {
7671 u8 reserved_at_0[0x8];
7673 u8 reserved_at_10[0x20];
7675 u8 beacon_duration[0x10];
7676 u8 reserved_at_40[0x10];
7678 u8 beacon_remain[0x10];
7681 struct mlx5_ifc_ptas_reg_bits {
7682 u8 reserved_at_0[0x20];
7684 u8 algorithm_options[0x10];
7685 u8 reserved_at_30[0x4];
7686 u8 repetitions_mode[0x4];
7687 u8 num_of_repetitions[0x8];
7689 u8 grade_version[0x8];
7690 u8 height_grade_type[0x4];
7691 u8 phase_grade_type[0x4];
7692 u8 height_grade_weight[0x8];
7693 u8 phase_grade_weight[0x8];
7695 u8 gisim_measure_bits[0x10];
7696 u8 adaptive_tap_measure_bits[0x10];
7698 u8 ber_bath_high_error_threshold[0x10];
7699 u8 ber_bath_mid_error_threshold[0x10];
7701 u8 ber_bath_low_error_threshold[0x10];
7702 u8 one_ratio_high_threshold[0x10];
7704 u8 one_ratio_high_mid_threshold[0x10];
7705 u8 one_ratio_low_mid_threshold[0x10];
7707 u8 one_ratio_low_threshold[0x10];
7708 u8 ndeo_error_threshold[0x10];
7710 u8 mixer_offset_step_size[0x10];
7711 u8 reserved_at_110[0x8];
7712 u8 mix90_phase_for_voltage_bath[0x8];
7714 u8 mixer_offset_start[0x10];
7715 u8 mixer_offset_end[0x10];
7717 u8 reserved_at_140[0x15];
7718 u8 ber_test_time[0xb];
7721 struct mlx5_ifc_pspa_reg_bits {
7725 u8 reserved_at_18[0x8];
7727 u8 reserved_at_20[0x20];
7730 struct mlx5_ifc_pqdr_reg_bits {
7731 u8 reserved_at_0[0x8];
7733 u8 reserved_at_10[0x5];
7735 u8 reserved_at_18[0x6];
7738 u8 reserved_at_20[0x20];
7740 u8 reserved_at_40[0x10];
7741 u8 min_threshold[0x10];
7743 u8 reserved_at_60[0x10];
7744 u8 max_threshold[0x10];
7746 u8 reserved_at_80[0x10];
7747 u8 mark_probability_denominator[0x10];
7749 u8 reserved_at_a0[0x60];
7752 struct mlx5_ifc_ppsc_reg_bits {
7753 u8 reserved_at_0[0x8];
7755 u8 reserved_at_10[0x10];
7757 u8 reserved_at_20[0x60];
7759 u8 reserved_at_80[0x1c];
7762 u8 reserved_at_a0[0x1c];
7763 u8 wrps_status[0x4];
7765 u8 reserved_at_c0[0x8];
7766 u8 up_threshold[0x8];
7767 u8 reserved_at_d0[0x8];
7768 u8 down_threshold[0x8];
7770 u8 reserved_at_e0[0x20];
7772 u8 reserved_at_100[0x1c];
7775 u8 reserved_at_120[0x1c];
7776 u8 srps_status[0x4];
7778 u8 reserved_at_140[0x40];
7781 struct mlx5_ifc_pplr_reg_bits {
7782 u8 reserved_at_0[0x8];
7784 u8 reserved_at_10[0x10];
7786 u8 reserved_at_20[0x8];
7788 u8 reserved_at_30[0x8];
7792 struct mlx5_ifc_pplm_reg_bits {
7793 u8 reserved_at_0[0x8];
7795 u8 reserved_at_10[0x10];
7797 u8 reserved_at_20[0x20];
7799 u8 port_profile_mode[0x8];
7800 u8 static_port_profile[0x8];
7801 u8 active_port_profile[0x8];
7802 u8 reserved_at_58[0x8];
7804 u8 retransmission_active[0x8];
7805 u8 fec_mode_active[0x18];
7807 u8 reserved_at_80[0x20];
7810 struct mlx5_ifc_ppcnt_reg_bits {
7814 u8 reserved_at_12[0x8];
7818 u8 reserved_at_21[0x1c];
7821 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7824 struct mlx5_ifc_mpcnt_reg_bits {
7825 u8 reserved_at_0[0x8];
7827 u8 reserved_at_10[0xa];
7831 u8 reserved_at_21[0x1f];
7833 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7836 struct mlx5_ifc_ppad_reg_bits {
7837 u8 reserved_at_0[0x3];
7839 u8 reserved_at_4[0x4];
7845 u8 reserved_at_40[0x40];
7848 struct mlx5_ifc_pmtu_reg_bits {
7849 u8 reserved_at_0[0x8];
7851 u8 reserved_at_10[0x10];
7854 u8 reserved_at_30[0x10];
7857 u8 reserved_at_50[0x10];
7860 u8 reserved_at_70[0x10];
7863 struct mlx5_ifc_pmpr_reg_bits {
7864 u8 reserved_at_0[0x8];
7866 u8 reserved_at_10[0x10];
7868 u8 reserved_at_20[0x18];
7869 u8 attenuation_5g[0x8];
7871 u8 reserved_at_40[0x18];
7872 u8 attenuation_7g[0x8];
7874 u8 reserved_at_60[0x18];
7875 u8 attenuation_12g[0x8];
7878 struct mlx5_ifc_pmpe_reg_bits {
7879 u8 reserved_at_0[0x8];
7881 u8 reserved_at_10[0xc];
7882 u8 module_status[0x4];
7884 u8 reserved_at_20[0x60];
7887 struct mlx5_ifc_pmpc_reg_bits {
7888 u8 module_state_updated[32][0x8];
7891 struct mlx5_ifc_pmlpn_reg_bits {
7892 u8 reserved_at_0[0x4];
7893 u8 mlpn_status[0x4];
7895 u8 reserved_at_10[0x10];
7898 u8 reserved_at_21[0x1f];
7901 struct mlx5_ifc_pmlp_reg_bits {
7903 u8 reserved_at_1[0x7];
7905 u8 reserved_at_10[0x8];
7908 u8 lane0_module_mapping[0x20];
7910 u8 lane1_module_mapping[0x20];
7912 u8 lane2_module_mapping[0x20];
7914 u8 lane3_module_mapping[0x20];
7916 u8 reserved_at_a0[0x160];
7919 struct mlx5_ifc_pmaos_reg_bits {
7920 u8 reserved_at_0[0x8];
7922 u8 reserved_at_10[0x4];
7923 u8 admin_status[0x4];
7924 u8 reserved_at_18[0x4];
7925 u8 oper_status[0x4];
7929 u8 reserved_at_22[0x1c];
7932 u8 reserved_at_40[0x40];
7935 struct mlx5_ifc_plpc_reg_bits {
7936 u8 reserved_at_0[0x4];
7938 u8 reserved_at_10[0x4];
7940 u8 reserved_at_18[0x8];
7942 u8 reserved_at_20[0x10];
7943 u8 lane_speed[0x10];
7945 u8 reserved_at_40[0x17];
7947 u8 fec_mode_policy[0x8];
7949 u8 retransmission_capability[0x8];
7950 u8 fec_mode_capability[0x18];
7952 u8 retransmission_support_admin[0x8];
7953 u8 fec_mode_support_admin[0x18];
7955 u8 retransmission_request_admin[0x8];
7956 u8 fec_mode_request_admin[0x18];
7958 u8 reserved_at_c0[0x80];
7961 struct mlx5_ifc_plib_reg_bits {
7962 u8 reserved_at_0[0x8];
7964 u8 reserved_at_10[0x8];
7967 u8 reserved_at_20[0x60];
7970 struct mlx5_ifc_plbf_reg_bits {
7971 u8 reserved_at_0[0x8];
7973 u8 reserved_at_10[0xd];
7976 u8 reserved_at_20[0x20];
7979 struct mlx5_ifc_pipg_reg_bits {
7980 u8 reserved_at_0[0x8];
7982 u8 reserved_at_10[0x10];
7985 u8 reserved_at_21[0x19];
7987 u8 reserved_at_3e[0x2];
7990 struct mlx5_ifc_pifr_reg_bits {
7991 u8 reserved_at_0[0x8];
7993 u8 reserved_at_10[0x10];
7995 u8 reserved_at_20[0xe0];
7997 u8 port_filter[8][0x20];
7999 u8 port_filter_update_en[8][0x20];
8002 struct mlx5_ifc_pfcc_reg_bits {
8003 u8 reserved_at_0[0x8];
8005 u8 reserved_at_10[0xb];
8006 u8 ppan_mask_n[0x1];
8007 u8 minor_stall_mask[0x1];
8008 u8 critical_stall_mask[0x1];
8009 u8 reserved_at_1e[0x2];
8012 u8 reserved_at_24[0x4];
8013 u8 prio_mask_tx[0x8];
8014 u8 reserved_at_30[0x8];
8015 u8 prio_mask_rx[0x8];
8019 u8 pptx_mask_n[0x1];
8020 u8 reserved_at_43[0x5];
8022 u8 reserved_at_50[0x10];
8026 u8 pprx_mask_n[0x1];
8027 u8 reserved_at_63[0x5];
8029 u8 reserved_at_70[0x10];
8031 u8 device_stall_minor_watermark[0x10];
8032 u8 device_stall_critical_watermark[0x10];
8034 u8 reserved_at_a0[0x60];
8037 struct mlx5_ifc_pelc_reg_bits {
8039 u8 reserved_at_4[0x4];
8041 u8 reserved_at_10[0x10];
8044 u8 op_capability[0x8];
8050 u8 capability[0x40];
8056 u8 reserved_at_140[0x80];
8059 struct mlx5_ifc_peir_reg_bits {
8060 u8 reserved_at_0[0x8];
8062 u8 reserved_at_10[0x10];
8064 u8 reserved_at_20[0xc];
8065 u8 error_count[0x4];
8066 u8 reserved_at_30[0x10];
8068 u8 reserved_at_40[0xc];
8070 u8 reserved_at_50[0x8];
8074 struct mlx5_ifc_mpegc_reg_bits {
8075 u8 reserved_at_0[0x30];
8076 u8 field_select[0x10];
8078 u8 tx_overflow_sense[0x1];
8081 u8 reserved_at_43[0x1b];
8082 u8 tx_lossy_overflow_oper[0x2];
8084 u8 reserved_at_60[0x100];
8087 struct mlx5_ifc_pcam_enhanced_features_bits {
8088 u8 reserved_at_0[0x6d];
8089 u8 rx_icrc_encapsulated_counter[0x1];
8090 u8 reserved_at_6e[0x8];
8092 u8 reserved_at_77[0x4];
8093 u8 rx_buffer_fullness_counters[0x1];
8094 u8 ptys_connector_type[0x1];
8095 u8 reserved_at_7d[0x1];
8096 u8 ppcnt_discard_group[0x1];
8097 u8 ppcnt_statistical_group[0x1];
8100 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8101 u8 port_access_reg_cap_mask_127_to_96[0x20];
8102 u8 port_access_reg_cap_mask_95_to_64[0x20];
8103 u8 port_access_reg_cap_mask_63_to_32[0x20];
8105 u8 port_access_reg_cap_mask_31_to_13[0x13];
8108 u8 port_access_reg_cap_mask_10_to_0[0xb];
8111 struct mlx5_ifc_pcam_reg_bits {
8112 u8 reserved_at_0[0x8];
8113 u8 feature_group[0x8];
8114 u8 reserved_at_10[0x8];
8115 u8 access_reg_group[0x8];
8117 u8 reserved_at_20[0x20];
8120 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8121 u8 reserved_at_0[0x80];
8122 } port_access_reg_cap_mask;
8124 u8 reserved_at_c0[0x80];
8127 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8128 u8 reserved_at_0[0x80];
8131 u8 reserved_at_1c0[0xc0];
8134 struct mlx5_ifc_mcam_enhanced_features_bits {
8135 u8 reserved_at_0[0x74];
8136 u8 mark_tx_action_cnp[0x1];
8137 u8 mark_tx_action_cqe[0x1];
8138 u8 dynamic_tx_overflow[0x1];
8139 u8 reserved_at_77[0x4];
8140 u8 pcie_outbound_stalled[0x1];
8141 u8 tx_overflow_buffer_pkt[0x1];
8142 u8 mtpps_enh_out_per_adj[0x1];
8144 u8 pcie_performance_group[0x1];
8147 struct mlx5_ifc_mcam_access_reg_bits {
8148 u8 reserved_at_0[0x1c];
8152 u8 reserved_at_1f[0x1];
8154 u8 regs_95_to_87[0x9];
8156 u8 regs_85_to_68[0x12];
8157 u8 tracer_registers[0x4];
8159 u8 regs_63_to_32[0x20];
8160 u8 regs_31_to_0[0x20];
8163 struct mlx5_ifc_mcam_reg_bits {
8164 u8 reserved_at_0[0x8];
8165 u8 feature_group[0x8];
8166 u8 reserved_at_10[0x8];
8167 u8 access_reg_group[0x8];
8169 u8 reserved_at_20[0x20];
8172 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8173 u8 reserved_at_0[0x80];
8174 } mng_access_reg_cap_mask;
8176 u8 reserved_at_c0[0x80];
8179 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8180 u8 reserved_at_0[0x80];
8181 } mng_feature_cap_mask;
8183 u8 reserved_at_1c0[0x80];
8186 struct mlx5_ifc_qcam_access_reg_cap_mask {
8187 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8189 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8193 u8 qcam_access_reg_cap_mask_0[0x1];
8196 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8197 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8198 u8 qpts_trust_both[0x1];
8201 struct mlx5_ifc_qcam_reg_bits {
8202 u8 reserved_at_0[0x8];
8203 u8 feature_group[0x8];
8204 u8 reserved_at_10[0x8];
8205 u8 access_reg_group[0x8];
8206 u8 reserved_at_20[0x20];
8209 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8210 u8 reserved_at_0[0x80];
8211 } qos_access_reg_cap_mask;
8213 u8 reserved_at_c0[0x80];
8216 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8217 u8 reserved_at_0[0x80];
8218 } qos_feature_cap_mask;
8220 u8 reserved_at_1c0[0x80];
8223 struct mlx5_ifc_pcap_reg_bits {
8224 u8 reserved_at_0[0x8];
8226 u8 reserved_at_10[0x10];
8228 u8 port_capability_mask[4][0x20];
8231 struct mlx5_ifc_paos_reg_bits {
8234 u8 reserved_at_10[0x4];
8235 u8 admin_status[0x4];
8236 u8 reserved_at_18[0x4];
8237 u8 oper_status[0x4];
8241 u8 reserved_at_22[0x1c];
8244 u8 reserved_at_40[0x40];
8247 struct mlx5_ifc_pamp_reg_bits {
8248 u8 reserved_at_0[0x8];
8249 u8 opamp_group[0x8];
8250 u8 reserved_at_10[0xc];
8251 u8 opamp_group_type[0x4];
8253 u8 start_index[0x10];
8254 u8 reserved_at_30[0x4];
8255 u8 num_of_indices[0xc];
8257 u8 index_data[18][0x10];
8260 struct mlx5_ifc_pcmr_reg_bits {
8261 u8 reserved_at_0[0x8];
8263 u8 reserved_at_10[0x2e];
8265 u8 reserved_at_3f[0x1f];
8267 u8 reserved_at_5f[0x1];
8270 struct mlx5_ifc_lane_2_module_mapping_bits {
8271 u8 reserved_at_0[0x6];
8273 u8 reserved_at_8[0x6];
8275 u8 reserved_at_10[0x8];
8279 struct mlx5_ifc_bufferx_reg_bits {
8280 u8 reserved_at_0[0x6];
8283 u8 reserved_at_8[0xc];
8286 u8 xoff_threshold[0x10];
8287 u8 xon_threshold[0x10];
8290 struct mlx5_ifc_set_node_in_bits {
8291 u8 node_description[64][0x8];
8294 struct mlx5_ifc_register_power_settings_bits {
8295 u8 reserved_at_0[0x18];
8296 u8 power_settings_level[0x8];
8298 u8 reserved_at_20[0x60];
8301 struct mlx5_ifc_register_host_endianness_bits {
8303 u8 reserved_at_1[0x1f];
8305 u8 reserved_at_20[0x60];
8308 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8309 u8 reserved_at_0[0x20];
8313 u8 addressh_63_32[0x20];
8315 u8 addressl_31_0[0x20];
8318 struct mlx5_ifc_ud_adrs_vector_bits {
8322 u8 reserved_at_41[0x7];
8323 u8 destination_qp_dct[0x18];
8325 u8 static_rate[0x4];
8326 u8 sl_eth_prio[0x4];
8329 u8 rlid_udp_sport[0x10];
8331 u8 reserved_at_80[0x20];
8333 u8 rmac_47_16[0x20];
8339 u8 reserved_at_e0[0x1];
8341 u8 reserved_at_e2[0x2];
8342 u8 src_addr_index[0x8];
8343 u8 flow_label[0x14];
8345 u8 rgid_rip[16][0x8];
8348 struct mlx5_ifc_pages_req_event_bits {
8349 u8 reserved_at_0[0x10];
8350 u8 function_id[0x10];
8354 u8 reserved_at_40[0xa0];
8357 struct mlx5_ifc_eqe_bits {
8358 u8 reserved_at_0[0x8];
8360 u8 reserved_at_10[0x8];
8361 u8 event_sub_type[0x8];
8363 u8 reserved_at_20[0xe0];
8365 union mlx5_ifc_event_auto_bits event_data;
8367 u8 reserved_at_1e0[0x10];
8369 u8 reserved_at_1f8[0x7];
8374 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8377 struct mlx5_ifc_cmd_queue_entry_bits {
8379 u8 reserved_at_8[0x18];
8381 u8 input_length[0x20];
8383 u8 input_mailbox_pointer_63_32[0x20];
8385 u8 input_mailbox_pointer_31_9[0x17];
8386 u8 reserved_at_77[0x9];
8388 u8 command_input_inline_data[16][0x8];
8390 u8 command_output_inline_data[16][0x8];
8392 u8 output_mailbox_pointer_63_32[0x20];
8394 u8 output_mailbox_pointer_31_9[0x17];
8395 u8 reserved_at_1b7[0x9];
8397 u8 output_length[0x20];
8401 u8 reserved_at_1f0[0x8];
8406 struct mlx5_ifc_cmd_out_bits {
8408 u8 reserved_at_8[0x18];
8412 u8 command_output[0x20];
8415 struct mlx5_ifc_cmd_in_bits {
8417 u8 reserved_at_10[0x10];
8419 u8 reserved_at_20[0x10];
8422 u8 command[0][0x20];
8425 struct mlx5_ifc_cmd_if_box_bits {
8426 u8 mailbox_data[512][0x8];
8428 u8 reserved_at_1000[0x180];
8430 u8 next_pointer_63_32[0x20];
8432 u8 next_pointer_31_10[0x16];
8433 u8 reserved_at_11b6[0xa];
8435 u8 block_number[0x20];
8437 u8 reserved_at_11e0[0x8];
8439 u8 ctrl_signature[0x8];
8443 struct mlx5_ifc_mtt_bits {
8444 u8 ptag_63_32[0x20];
8447 u8 reserved_at_38[0x6];
8452 struct mlx5_ifc_query_wol_rol_out_bits {
8454 u8 reserved_at_8[0x18];
8458 u8 reserved_at_40[0x10];
8462 u8 reserved_at_60[0x20];
8465 struct mlx5_ifc_query_wol_rol_in_bits {
8467 u8 reserved_at_10[0x10];
8469 u8 reserved_at_20[0x10];
8472 u8 reserved_at_40[0x40];
8475 struct mlx5_ifc_set_wol_rol_out_bits {
8477 u8 reserved_at_8[0x18];
8481 u8 reserved_at_40[0x40];
8484 struct mlx5_ifc_set_wol_rol_in_bits {
8486 u8 reserved_at_10[0x10];
8488 u8 reserved_at_20[0x10];
8491 u8 rol_mode_valid[0x1];
8492 u8 wol_mode_valid[0x1];
8493 u8 reserved_at_42[0xe];
8497 u8 reserved_at_60[0x20];
8501 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8502 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8503 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8507 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8508 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8509 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8513 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8514 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8515 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8516 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8517 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8518 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8519 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8520 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8521 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8526 struct mlx5_ifc_initial_seg_bits {
8527 u8 fw_rev_minor[0x10];
8528 u8 fw_rev_major[0x10];
8530 u8 cmd_interface_rev[0x10];
8531 u8 fw_rev_subminor[0x10];
8533 u8 reserved_at_40[0x40];
8535 u8 cmdq_phy_addr_63_32[0x20];
8537 u8 cmdq_phy_addr_31_12[0x14];
8538 u8 reserved_at_b4[0x2];
8539 u8 nic_interface[0x2];
8540 u8 log_cmdq_size[0x4];
8541 u8 log_cmdq_stride[0x4];
8543 u8 command_doorbell_vector[0x20];
8545 u8 reserved_at_e0[0xf00];
8547 u8 initializing[0x1];
8548 u8 reserved_at_fe1[0x4];
8549 u8 nic_interface_supported[0x3];
8550 u8 reserved_at_fe8[0x18];
8552 struct mlx5_ifc_health_buffer_bits health_buffer;
8554 u8 no_dram_nic_offset[0x20];
8556 u8 reserved_at_1220[0x6e40];
8558 u8 reserved_at_8060[0x1f];
8561 u8 health_syndrome[0x8];
8562 u8 health_counter[0x18];
8564 u8 reserved_at_80a0[0x17fc0];
8567 struct mlx5_ifc_mtpps_reg_bits {
8568 u8 reserved_at_0[0xc];
8569 u8 cap_number_of_pps_pins[0x4];
8570 u8 reserved_at_10[0x4];
8571 u8 cap_max_num_of_pps_in_pins[0x4];
8572 u8 reserved_at_18[0x4];
8573 u8 cap_max_num_of_pps_out_pins[0x4];
8575 u8 reserved_at_20[0x24];
8576 u8 cap_pin_3_mode[0x4];
8577 u8 reserved_at_48[0x4];
8578 u8 cap_pin_2_mode[0x4];
8579 u8 reserved_at_50[0x4];
8580 u8 cap_pin_1_mode[0x4];
8581 u8 reserved_at_58[0x4];
8582 u8 cap_pin_0_mode[0x4];
8584 u8 reserved_at_60[0x4];
8585 u8 cap_pin_7_mode[0x4];
8586 u8 reserved_at_68[0x4];
8587 u8 cap_pin_6_mode[0x4];
8588 u8 reserved_at_70[0x4];
8589 u8 cap_pin_5_mode[0x4];
8590 u8 reserved_at_78[0x4];
8591 u8 cap_pin_4_mode[0x4];
8593 u8 field_select[0x20];
8594 u8 reserved_at_a0[0x60];
8597 u8 reserved_at_101[0xb];
8599 u8 reserved_at_110[0x4];
8603 u8 reserved_at_120[0x20];
8605 u8 time_stamp[0x40];
8607 u8 out_pulse_duration[0x10];
8608 u8 out_periodic_adjustment[0x10];
8609 u8 enhanced_out_periodic_adjustment[0x20];
8611 u8 reserved_at_1c0[0x20];
8614 struct mlx5_ifc_mtppse_reg_bits {
8615 u8 reserved_at_0[0x18];
8618 u8 reserved_at_21[0x1b];
8619 u8 event_generation_mode[0x4];
8620 u8 reserved_at_40[0x40];
8623 struct mlx5_ifc_mcqi_cap_bits {
8624 u8 supported_info_bitmask[0x20];
8626 u8 component_size[0x20];
8628 u8 max_component_size[0x20];
8630 u8 log_mcda_word_size[0x4];
8631 u8 reserved_at_64[0xc];
8632 u8 mcda_max_write_size[0x10];
8635 u8 reserved_at_81[0x1];
8636 u8 match_chip_id[0x1];
8638 u8 check_user_timestamp[0x1];
8639 u8 match_base_guid_mac[0x1];
8640 u8 reserved_at_86[0x1a];
8643 struct mlx5_ifc_mcqi_reg_bits {
8644 u8 read_pending_component[0x1];
8645 u8 reserved_at_1[0xf];
8646 u8 component_index[0x10];
8648 u8 reserved_at_20[0x20];
8650 u8 reserved_at_40[0x1b];
8657 u8 reserved_at_a0[0x10];
8663 struct mlx5_ifc_mcc_reg_bits {
8664 u8 reserved_at_0[0x4];
8665 u8 time_elapsed_since_last_cmd[0xc];
8666 u8 reserved_at_10[0x8];
8667 u8 instruction[0x8];
8669 u8 reserved_at_20[0x10];
8670 u8 component_index[0x10];
8672 u8 reserved_at_40[0x8];
8673 u8 update_handle[0x18];
8675 u8 handle_owner_type[0x4];
8676 u8 handle_owner_host_id[0x4];
8677 u8 reserved_at_68[0x1];
8678 u8 control_progress[0x7];
8680 u8 reserved_at_78[0x4];
8681 u8 control_state[0x4];
8683 u8 component_size[0x20];
8685 u8 reserved_at_a0[0x60];
8688 struct mlx5_ifc_mcda_reg_bits {
8689 u8 reserved_at_0[0x8];
8690 u8 update_handle[0x18];
8694 u8 reserved_at_40[0x10];
8697 u8 reserved_at_60[0x20];
8702 union mlx5_ifc_ports_control_registers_document_bits {
8703 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8704 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8705 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8706 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8707 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8708 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8709 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8710 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8711 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8712 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8713 struct mlx5_ifc_paos_reg_bits paos_reg;
8714 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8715 struct mlx5_ifc_peir_reg_bits peir_reg;
8716 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8717 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8718 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8719 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8720 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8721 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8722 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8723 struct mlx5_ifc_plib_reg_bits plib_reg;
8724 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8725 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8726 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8727 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8728 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8729 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8730 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8731 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8732 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8733 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8734 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8735 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8736 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8737 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8738 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8739 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8740 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8741 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8742 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8743 struct mlx5_ifc_pude_reg_bits pude_reg;
8744 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8745 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8746 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8747 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8748 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8749 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8750 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8751 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8752 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8753 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8754 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8755 u8 reserved_at_0[0x60e0];
8758 union mlx5_ifc_debug_enhancements_document_bits {
8759 struct mlx5_ifc_health_buffer_bits health_buffer;
8760 u8 reserved_at_0[0x200];
8763 union mlx5_ifc_uplink_pci_interface_document_bits {
8764 struct mlx5_ifc_initial_seg_bits initial_seg;
8765 u8 reserved_at_0[0x20060];
8768 struct mlx5_ifc_set_flow_table_root_out_bits {
8770 u8 reserved_at_8[0x18];
8774 u8 reserved_at_40[0x40];
8777 struct mlx5_ifc_set_flow_table_root_in_bits {
8779 u8 reserved_at_10[0x10];
8781 u8 reserved_at_20[0x10];
8784 u8 other_vport[0x1];
8785 u8 reserved_at_41[0xf];
8786 u8 vport_number[0x10];
8788 u8 reserved_at_60[0x20];
8791 u8 reserved_at_88[0x18];
8793 u8 reserved_at_a0[0x8];
8796 u8 reserved_at_c0[0x8];
8797 u8 underlay_qpn[0x18];
8798 u8 reserved_at_e0[0x120];
8802 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8803 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8806 struct mlx5_ifc_modify_flow_table_out_bits {
8808 u8 reserved_at_8[0x18];
8812 u8 reserved_at_40[0x40];
8815 struct mlx5_ifc_modify_flow_table_in_bits {
8817 u8 reserved_at_10[0x10];
8819 u8 reserved_at_20[0x10];
8822 u8 other_vport[0x1];
8823 u8 reserved_at_41[0xf];
8824 u8 vport_number[0x10];
8826 u8 reserved_at_60[0x10];
8827 u8 modify_field_select[0x10];
8830 u8 reserved_at_88[0x18];
8832 u8 reserved_at_a0[0x8];
8835 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8838 struct mlx5_ifc_ets_tcn_config_reg_bits {
8842 u8 reserved_at_3[0x9];
8844 u8 reserved_at_10[0x9];
8845 u8 bw_allocation[0x7];
8847 u8 reserved_at_20[0xc];
8848 u8 max_bw_units[0x4];
8849 u8 reserved_at_30[0x8];
8850 u8 max_bw_value[0x8];
8853 struct mlx5_ifc_ets_global_config_reg_bits {
8854 u8 reserved_at_0[0x2];
8856 u8 reserved_at_3[0x1d];
8858 u8 reserved_at_20[0xc];
8859 u8 max_bw_units[0x4];
8860 u8 reserved_at_30[0x8];
8861 u8 max_bw_value[0x8];
8864 struct mlx5_ifc_qetc_reg_bits {
8865 u8 reserved_at_0[0x8];
8866 u8 port_number[0x8];
8867 u8 reserved_at_10[0x30];
8869 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8870 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8873 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8875 u8 reserved_at_01[0x0b];
8879 struct mlx5_ifc_qpdpm_reg_bits {
8880 u8 reserved_at_0[0x8];
8882 u8 reserved_at_10[0x10];
8883 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8886 struct mlx5_ifc_qpts_reg_bits {
8887 u8 reserved_at_0[0x8];
8889 u8 reserved_at_10[0x2d];
8890 u8 trust_state[0x3];
8893 struct mlx5_ifc_pptb_reg_bits {
8894 u8 reserved_at_0[0x2];
8896 u8 reserved_at_4[0x4];
8898 u8 reserved_at_10[0x6];
8903 u8 prio_x_buff[0x20];
8906 u8 reserved_at_48[0x10];
8908 u8 untagged_buff[0x4];
8911 struct mlx5_ifc_pbmc_reg_bits {
8912 u8 reserved_at_0[0x8];
8914 u8 reserved_at_10[0x10];
8916 u8 xoff_timer_value[0x10];
8917 u8 xoff_refresh[0x10];
8919 u8 reserved_at_40[0x9];
8920 u8 fullness_threshold[0x7];
8921 u8 port_buffer_size[0x10];
8923 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8925 u8 reserved_at_2e0[0x40];
8928 struct mlx5_ifc_qtct_reg_bits {
8929 u8 reserved_at_0[0x8];
8930 u8 port_number[0x8];
8931 u8 reserved_at_10[0xd];
8934 u8 reserved_at_20[0x1d];
8938 struct mlx5_ifc_mcia_reg_bits {
8940 u8 reserved_at_1[0x7];
8942 u8 reserved_at_10[0x8];
8945 u8 i2c_device_address[0x8];
8946 u8 page_number[0x8];
8947 u8 device_address[0x10];
8949 u8 reserved_at_40[0x10];
8952 u8 reserved_at_60[0x20];
8968 struct mlx5_ifc_dcbx_param_bits {
8969 u8 dcbx_cee_cap[0x1];
8970 u8 dcbx_ieee_cap[0x1];
8971 u8 dcbx_standby_cap[0x1];
8972 u8 reserved_at_0[0x5];
8973 u8 port_number[0x8];
8974 u8 reserved_at_10[0xa];
8975 u8 max_application_table_size[6];
8976 u8 reserved_at_20[0x15];
8977 u8 version_oper[0x3];
8978 u8 reserved_at_38[5];
8979 u8 version_admin[0x3];
8980 u8 willing_admin[0x1];
8981 u8 reserved_at_41[0x3];
8982 u8 pfc_cap_oper[0x4];
8983 u8 reserved_at_48[0x4];
8984 u8 pfc_cap_admin[0x4];
8985 u8 reserved_at_50[0x4];
8986 u8 num_of_tc_oper[0x4];
8987 u8 reserved_at_58[0x4];
8988 u8 num_of_tc_admin[0x4];
8989 u8 remote_willing[0x1];
8990 u8 reserved_at_61[3];
8991 u8 remote_pfc_cap[4];
8992 u8 reserved_at_68[0x14];
8993 u8 remote_num_of_tc[0x4];
8994 u8 reserved_at_80[0x18];
8996 u8 reserved_at_a0[0x160];
8999 struct mlx5_ifc_lagc_bits {
9000 u8 reserved_at_0[0x1d];
9003 u8 reserved_at_20[0x14];
9004 u8 tx_remap_affinity_2[0x4];
9005 u8 reserved_at_38[0x4];
9006 u8 tx_remap_affinity_1[0x4];
9009 struct mlx5_ifc_create_lag_out_bits {
9011 u8 reserved_at_8[0x18];
9015 u8 reserved_at_40[0x40];
9018 struct mlx5_ifc_create_lag_in_bits {
9020 u8 reserved_at_10[0x10];
9022 u8 reserved_at_20[0x10];
9025 struct mlx5_ifc_lagc_bits ctx;
9028 struct mlx5_ifc_modify_lag_out_bits {
9030 u8 reserved_at_8[0x18];
9034 u8 reserved_at_40[0x40];
9037 struct mlx5_ifc_modify_lag_in_bits {
9039 u8 reserved_at_10[0x10];
9041 u8 reserved_at_20[0x10];
9044 u8 reserved_at_40[0x20];
9045 u8 field_select[0x20];
9047 struct mlx5_ifc_lagc_bits ctx;
9050 struct mlx5_ifc_query_lag_out_bits {
9052 u8 reserved_at_8[0x18];
9056 u8 reserved_at_40[0x40];
9058 struct mlx5_ifc_lagc_bits ctx;
9061 struct mlx5_ifc_query_lag_in_bits {
9063 u8 reserved_at_10[0x10];
9065 u8 reserved_at_20[0x10];
9068 u8 reserved_at_40[0x40];
9071 struct mlx5_ifc_destroy_lag_out_bits {
9073 u8 reserved_at_8[0x18];
9077 u8 reserved_at_40[0x40];
9080 struct mlx5_ifc_destroy_lag_in_bits {
9082 u8 reserved_at_10[0x10];
9084 u8 reserved_at_20[0x10];
9087 u8 reserved_at_40[0x40];
9090 struct mlx5_ifc_create_vport_lag_out_bits {
9092 u8 reserved_at_8[0x18];
9096 u8 reserved_at_40[0x40];
9099 struct mlx5_ifc_create_vport_lag_in_bits {
9101 u8 reserved_at_10[0x10];
9103 u8 reserved_at_20[0x10];
9106 u8 reserved_at_40[0x40];
9109 struct mlx5_ifc_destroy_vport_lag_out_bits {
9111 u8 reserved_at_8[0x18];
9115 u8 reserved_at_40[0x40];
9118 struct mlx5_ifc_destroy_vport_lag_in_bits {
9120 u8 reserved_at_10[0x10];
9122 u8 reserved_at_20[0x10];
9125 u8 reserved_at_40[0x40];
9128 struct mlx5_ifc_alloc_memic_in_bits {
9130 u8 reserved_at_10[0x10];
9132 u8 reserved_at_20[0x10];
9135 u8 reserved_at_30[0x20];
9137 u8 reserved_at_40[0x18];
9138 u8 log_memic_addr_alignment[0x8];
9140 u8 range_start_addr[0x40];
9142 u8 range_size[0x20];
9144 u8 memic_size[0x20];
9147 struct mlx5_ifc_alloc_memic_out_bits {
9149 u8 reserved_at_8[0x18];
9153 u8 memic_start_addr[0x40];
9156 struct mlx5_ifc_dealloc_memic_in_bits {
9158 u8 reserved_at_10[0x10];
9160 u8 reserved_at_20[0x10];
9163 u8 reserved_at_40[0x40];
9165 u8 memic_start_addr[0x40];
9167 u8 memic_size[0x20];
9169 u8 reserved_at_e0[0x20];
9172 struct mlx5_ifc_dealloc_memic_out_bits {
9174 u8 reserved_at_8[0x18];
9178 u8 reserved_at_40[0x40];
9181 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9185 u8 reserved_at_20[0x10];
9190 u8 reserved_at_60[0x20];
9193 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9195 u8 reserved_at_8[0x18];
9201 u8 reserved_at_60[0x20];
9204 struct mlx5_ifc_umem_bits {
9205 u8 modify_field_select[0x40];
9207 u8 reserved_at_40[0x5b];
9208 u8 log_page_size[0x5];
9210 u8 page_offset[0x20];
9212 u8 num_of_mtt[0x40];
9214 struct mlx5_ifc_mtt_bits mtt[0];
9217 struct mlx5_ifc_uctx_bits {
9218 u8 modify_field_select[0x40];
9220 u8 reserved_at_40[0x1c0];
9223 struct mlx5_ifc_create_umem_in_bits {
9224 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9225 struct mlx5_ifc_umem_bits umem;
9228 struct mlx5_ifc_create_uctx_in_bits {
9229 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9230 struct mlx5_ifc_uctx_bits uctx;
9233 struct mlx5_ifc_mtrc_string_db_param_bits {
9234 u8 string_db_base_address[0x20];
9236 u8 reserved_at_20[0x8];
9237 u8 string_db_size[0x18];
9240 struct mlx5_ifc_mtrc_cap_bits {
9241 u8 trace_owner[0x1];
9242 u8 trace_to_memory[0x1];
9243 u8 reserved_at_2[0x4];
9245 u8 reserved_at_8[0x14];
9246 u8 num_string_db[0x4];
9248 u8 first_string_trace[0x8];
9249 u8 num_string_trace[0x8];
9250 u8 reserved_at_30[0x28];
9252 u8 log_max_trace_buffer_size[0x8];
9254 u8 reserved_at_60[0x20];
9256 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9258 u8 reserved_at_280[0x180];
9261 struct mlx5_ifc_mtrc_conf_bits {
9262 u8 reserved_at_0[0x1c];
9264 u8 reserved_at_20[0x18];
9265 u8 log_trace_buffer_size[0x8];
9266 u8 trace_mkey[0x20];
9267 u8 reserved_at_60[0x3a0];
9270 struct mlx5_ifc_mtrc_stdb_bits {
9271 u8 string_db_index[0x4];
9272 u8 reserved_at_4[0x4];
9274 u8 start_offset[0x20];
9275 u8 string_db_data[0];
9278 struct mlx5_ifc_mtrc_ctrl_bits {
9279 u8 trace_status[0x2];
9280 u8 reserved_at_2[0x2];
9282 u8 reserved_at_5[0xb];
9283 u8 modify_field_select[0x10];
9284 u8 reserved_at_20[0x2b];
9285 u8 current_timestamp52_32[0x15];
9286 u8 current_timestamp31_0[0x20];
9287 u8 reserved_at_80[0x180];
9290 #endif /* MLX5_IFC_H */