include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85         MLX5_OBJ_TYPE_UMEM = 0x0005,
  86 };
  87
  88 enum {
  89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 184         MLX5_CMD_OP_NOP                           = 0x80d,
 185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 246         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 247         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 260         MLX5_CMD_OP_MAX
 261 };
 262
 263 struct mlx5_ifc_flow_table_fields_supported_bits {
 264         u8         outer_dmac[0x1];
 265         u8         outer_smac[0x1];
 266         u8         outer_ether_type[0x1];
 267         u8         outer_ip_version[0x1];
 268         u8         outer_first_prio[0x1];
 269         u8         outer_first_cfi[0x1];
 270         u8         outer_first_vid[0x1];
 271         u8         outer_ipv4_ttl[0x1];
 272         u8         outer_second_prio[0x1];
 273         u8         outer_second_cfi[0x1];
 274         u8         outer_second_vid[0x1];
 275         u8         reserved_at_b[0x1];
 276         u8         outer_sip[0x1];
 277         u8         outer_dip[0x1];
 278         u8         outer_frag[0x1];
 279         u8         outer_ip_protocol[0x1];
 280         u8         outer_ip_ecn[0x1];
 281         u8         outer_ip_dscp[0x1];
 282         u8         outer_udp_sport[0x1];
 283         u8         outer_udp_dport[0x1];
 284         u8         outer_tcp_sport[0x1];
 285         u8         outer_tcp_dport[0x1];
 286         u8         outer_tcp_flags[0x1];
 287         u8         outer_gre_protocol[0x1];
 288         u8         outer_gre_key[0x1];
 289         u8         outer_vxlan_vni[0x1];
 290         u8         reserved_at_1a[0x5];
 291         u8         source_eswitch_port[0x1];
 292
 293         u8         inner_dmac[0x1];
 294         u8         inner_smac[0x1];
 295         u8         inner_ether_type[0x1];
 296         u8         inner_ip_version[0x1];
 297         u8         inner_first_prio[0x1];
 298         u8         inner_first_cfi[0x1];
 299         u8         inner_first_vid[0x1];
 300         u8         reserved_at_27[0x1];
 301         u8         inner_second_prio[0x1];
 302         u8         inner_second_cfi[0x1];
 303         u8         inner_second_vid[0x1];
 304         u8         reserved_at_2b[0x1];
 305         u8         inner_sip[0x1];
 306         u8         inner_dip[0x1];
 307         u8         inner_frag[0x1];
 308         u8         inner_ip_protocol[0x1];
 309         u8         inner_ip_ecn[0x1];
 310         u8         inner_ip_dscp[0x1];
 311         u8         inner_udp_sport[0x1];
 312         u8         inner_udp_dport[0x1];
 313         u8         inner_tcp_sport[0x1];
 314         u8         inner_tcp_dport[0x1];
 315         u8         inner_tcp_flags[0x1];
 316         u8         reserved_at_37[0x9];
 317
 318         u8         reserved_at_40[0x5];
 319         u8         outer_first_mpls_over_udp[0x4];
 320         u8         outer_first_mpls_over_gre[0x4];
 321         u8         inner_first_mpls[0x4];
 322         u8         outer_first_mpls[0x4];
 323         u8         reserved_at_55[0x2];
 324         u8         outer_esp_spi[0x1];
 325         u8         reserved_at_58[0x2];
 326         u8         bth_dst_qp[0x1];
 327
 328         u8         reserved_at_5b[0x25];
 329 };
 330
 331 struct mlx5_ifc_flow_table_prop_layout_bits {
 332         u8         ft_support[0x1];
 333         u8         reserved_at_1[0x1];
 334         u8         flow_counter[0x1];
 335         u8         flow_modify_en[0x1];
 336         u8         modify_root[0x1];
 337         u8         identified_miss_table_mode[0x1];
 338         u8         flow_table_modify[0x1];
 339         u8         encap[0x1];
 340         u8         decap[0x1];
 341         u8         reserved_at_9[0x1];
 342         u8         pop_vlan[0x1];
 343         u8         push_vlan[0x1];
 344         u8         reserved_at_c[0x1];
 345         u8         pop_vlan_2[0x1];
 346         u8         push_vlan_2[0x1];
 347         u8         reserved_at_f[0x11];
 348
 349         u8         reserved_at_20[0x2];
 350         u8         log_max_ft_size[0x6];
 351         u8         log_max_modify_header_context[0x8];
 352         u8         max_modify_header_actions[0x8];
 353         u8         max_ft_level[0x8];
 354
 355         u8         reserved_at_40[0x20];
 356
 357         u8         reserved_at_60[0x18];
 358         u8         log_max_ft_num[0x8];
 359
 360         u8         reserved_at_80[0x18];
 361         u8         log_max_destination[0x8];
 362
 363         u8         log_max_flow_counter[0x8];
 364         u8         reserved_at_a8[0x10];
 365         u8         log_max_flow[0x8];
 366
 367         u8         reserved_at_c0[0x40];
 368
 369         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 370
 371         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 372 };
 373
 374 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 375         u8         send[0x1];
 376         u8         receive[0x1];
 377         u8         write[0x1];
 378         u8         read[0x1];
 379         u8         atomic[0x1];
 380         u8         srq_receive[0x1];
 381         u8         reserved_at_6[0x1a];
 382 };
 383
 384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 385         u8         smac_47_16[0x20];
 386
 387         u8         smac_15_0[0x10];
 388         u8         ethertype[0x10];
 389
 390         u8         dmac_47_16[0x20];
 391
 392         u8         dmac_15_0[0x10];
 393         u8         first_prio[0x3];
 394         u8         first_cfi[0x1];
 395         u8         first_vid[0xc];
 396
 397         u8         ip_protocol[0x8];
 398         u8         ip_dscp[0x6];
 399         u8         ip_ecn[0x2];
 400         u8         cvlan_tag[0x1];
 401         u8         svlan_tag[0x1];
 402         u8         frag[0x1];
 403         u8         ip_version[0x4];
 404         u8         tcp_flags[0x9];
 405
 406         u8         tcp_sport[0x10];
 407         u8         tcp_dport[0x10];
 408
 409         u8         reserved_at_c0[0x18];
 410         u8         ttl_hoplimit[0x8];
 411
 412         u8         udp_sport[0x10];
 413         u8         udp_dport[0x10];
 414
 415         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 416
 417         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 418 };
 419
 420 struct mlx5_ifc_fte_match_set_misc_bits {
 421         u8         reserved_at_0[0x8];
 422         u8         source_sqn[0x18];
 423
 424         u8         source_eswitch_owner_vhca_id[0x10];
 425         u8         source_port[0x10];
 426
 427         u8         outer_second_prio[0x3];
 428         u8         outer_second_cfi[0x1];
 429         u8         outer_second_vid[0xc];
 430         u8         inner_second_prio[0x3];
 431         u8         inner_second_cfi[0x1];
 432         u8         inner_second_vid[0xc];
 433
 434         u8         outer_second_cvlan_tag[0x1];
 435         u8         inner_second_cvlan_tag[0x1];
 436         u8         outer_second_svlan_tag[0x1];
 437         u8         inner_second_svlan_tag[0x1];
 438         u8         reserved_at_64[0xc];
 439         u8         gre_protocol[0x10];
 440
 441         u8         gre_key_h[0x18];
 442         u8         gre_key_l[0x8];
 443
 444         u8         vxlan_vni[0x18];
 445         u8         reserved_at_b8[0x8];
 446
 447         u8         reserved_at_c0[0x20];
 448
 449         u8         reserved_at_e0[0xc];
 450         u8         outer_ipv6_flow_label[0x14];
 451
 452         u8         reserved_at_100[0xc];
 453         u8         inner_ipv6_flow_label[0x14];
 454
 455         u8         reserved_at_120[0x28];
 456         u8         bth_dst_qp[0x18];
 457         u8         reserved_at_160[0x20];
 458         u8         outer_esp_spi[0x20];
 459         u8         reserved_at_1a0[0x60];
 460 };
 461
 462 struct mlx5_ifc_fte_match_mpls_bits {
 463         u8         mpls_label[0x14];
 464         u8         mpls_exp[0x3];
 465         u8         mpls_s_bos[0x1];
 466         u8         mpls_ttl[0x8];
 467 };
 468
 469 struct mlx5_ifc_fte_match_set_misc2_bits {
 470         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 471
 472         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 473
 474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 475
 476         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 477
 478         u8         reserved_at_80[0x100];
 479
 480         u8         metadata_reg_a[0x20];
 481
 482         u8         reserved_at_1a0[0x60];
 483 };
 484
 485 struct mlx5_ifc_cmd_pas_bits {
 486         u8         pa_h[0x20];
 487
 488         u8         pa_l[0x14];
 489         u8         reserved_at_34[0xc];
 490 };
 491
 492 struct mlx5_ifc_uint64_bits {
 493         u8         hi[0x20];
 494
 495         u8         lo[0x20];
 496 };
 497
 498 enum {
 499         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 500         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 501         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 502         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 503         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 504         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 505         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 506         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 507         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 508         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 509 };
 510
 511 struct mlx5_ifc_ads_bits {
 512         u8         fl[0x1];
 513         u8         free_ar[0x1];
 514         u8         reserved_at_2[0xe];
 515         u8         pkey_index[0x10];
 516
 517         u8         reserved_at_20[0x8];
 518         u8         grh[0x1];
 519         u8         mlid[0x7];
 520         u8         rlid[0x10];
 521
 522         u8         ack_timeout[0x5];
 523         u8         reserved_at_45[0x3];
 524         u8         src_addr_index[0x8];
 525         u8         reserved_at_50[0x4];
 526         u8         stat_rate[0x4];
 527         u8         hop_limit[0x8];
 528
 529         u8         reserved_at_60[0x4];
 530         u8         tclass[0x8];
 531         u8         flow_label[0x14];
 532
 533         u8         rgid_rip[16][0x8];
 534
 535         u8         reserved_at_100[0x4];
 536         u8         f_dscp[0x1];
 537         u8         f_ecn[0x1];
 538         u8         reserved_at_106[0x1];
 539         u8         f_eth_prio[0x1];
 540         u8         ecn[0x2];
 541         u8         dscp[0x6];
 542         u8         udp_sport[0x10];
 543
 544         u8         dei_cfi[0x1];
 545         u8         eth_prio[0x3];
 546         u8         sl[0x4];
 547         u8         vhca_port_num[0x8];
 548         u8         rmac_47_32[0x10];
 549
 550         u8         rmac_31_0[0x20];
 551 };
 552
 553 struct mlx5_ifc_flow_table_nic_cap_bits {
 554         u8         nic_rx_multi_path_tirs[0x1];
 555         u8         nic_rx_multi_path_tirs_fts[0x1];
 556         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 557         u8         reserved_at_3[0x1fd];
 558
 559         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 560
 561         u8         reserved_at_400[0x200];
 562
 563         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 564
 565         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 566
 567         u8         reserved_at_a00[0x200];
 568
 569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 570
 571         u8         reserved_at_e00[0x7200];
 572 };
 573
 574 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 575         u8      reserved_at_0[0x1c];
 576         u8      fdb_multi_path_to_table[0x1];
 577         u8      reserved_at_1d[0x1e3];
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 580
 581         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 582
 583         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 584
 585         u8      reserved_at_800[0x7800];
 586 };
 587
 588 struct mlx5_ifc_e_switch_cap_bits {
 589         u8         vport_svlan_strip[0x1];
 590         u8         vport_cvlan_strip[0x1];
 591         u8         vport_svlan_insert[0x1];
 592         u8         vport_cvlan_insert_if_not_exist[0x1];
 593         u8         vport_cvlan_insert_overwrite[0x1];
 594         u8         reserved_at_5[0x18];
 595         u8         merged_eswitch[0x1];
 596         u8         nic_vport_node_guid_modify[0x1];
 597         u8         nic_vport_port_guid_modify[0x1];
 598
 599         u8         vxlan_encap_decap[0x1];
 600         u8         nvgre_encap_decap[0x1];
 601         u8         reserved_at_22[0x9];
 602         u8         log_max_encap_headers[0x5];
 603         u8         reserved_2b[0x6];
 604         u8         max_encap_header_size[0xa];
 605
 606         u8         reserved_40[0x7c0];
 607
 608 };
 609
 610 struct mlx5_ifc_qos_cap_bits {
 611         u8         packet_pacing[0x1];
 612         u8         esw_scheduling[0x1];
 613         u8         esw_bw_share[0x1];
 614         u8         esw_rate_limit[0x1];
 615         u8         reserved_at_4[0x1];
 616         u8         packet_pacing_burst_bound[0x1];
 617         u8         packet_pacing_typical_size[0x1];
 618         u8         reserved_at_7[0x19];
 619
 620         u8         reserved_at_20[0x20];
 621
 622         u8         packet_pacing_max_rate[0x20];
 623
 624         u8         packet_pacing_min_rate[0x20];
 625
 626         u8         reserved_at_80[0x10];
 627         u8         packet_pacing_rate_table_size[0x10];
 628
 629         u8         esw_element_type[0x10];
 630         u8         esw_tsar_type[0x10];
 631
 632         u8         reserved_at_c0[0x10];
 633         u8         max_qos_para_vport[0x10];
 634
 635         u8         max_tsar_bw_share[0x20];
 636
 637         u8         reserved_at_100[0x700];
 638 };
 639
 640 struct mlx5_ifc_debug_cap_bits {
 641         u8         reserved_at_0[0x20];
 642
 643         u8         reserved_at_20[0x2];
 644         u8         stall_detect[0x1];
 645         u8         reserved_at_23[0x1d];
 646
 647         u8         reserved_at_40[0x7c0];
 648 };
 649
 650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 651         u8         csum_cap[0x1];
 652         u8         vlan_cap[0x1];
 653         u8         lro_cap[0x1];
 654         u8         lro_psh_flag[0x1];
 655         u8         lro_time_stamp[0x1];
 656         u8         reserved_at_5[0x2];
 657         u8         wqe_vlan_insert[0x1];
 658         u8         self_lb_en_modifiable[0x1];
 659         u8         reserved_at_9[0x2];
 660         u8         max_lso_cap[0x5];
 661         u8         multi_pkt_send_wqe[0x2];
 662         u8         wqe_inline_mode[0x2];
 663         u8         rss_ind_tbl_cap[0x4];
 664         u8         reg_umr_sq[0x1];
 665         u8         scatter_fcs[0x1];
 666         u8         enhanced_multi_pkt_send_wqe[0x1];
 667         u8         tunnel_lso_const_out_ip_id[0x1];
 668         u8         reserved_at_1c[0x2];
 669         u8         tunnel_stateless_gre[0x1];
 670         u8         tunnel_stateless_vxlan[0x1];
 671
 672         u8         swp[0x1];
 673         u8         swp_csum[0x1];
 674         u8         swp_lso[0x1];
 675         u8         reserved_at_23[0xd];
 676         u8         max_vxlan_udp_ports[0x8];
 677         u8         reserved_at_38[0x6];
 678         u8         max_geneve_opt_len[0x1];
 679         u8         tunnel_stateless_geneve_rx[0x1];
 680
 681         u8         reserved_at_40[0x10];
 682         u8         lro_min_mss_size[0x10];
 683
 684         u8         reserved_at_60[0x120];
 685
 686         u8         lro_timer_supported_periods[4][0x20];
 687
 688         u8         reserved_at_200[0x600];
 689 };
 690
 691 struct mlx5_ifc_roce_cap_bits {
 692         u8         roce_apm[0x1];
 693         u8         reserved_at_1[0x1f];
 694
 695         u8         reserved_at_20[0x60];
 696
 697         u8         reserved_at_80[0xc];
 698         u8         l3_type[0x4];
 699         u8         reserved_at_90[0x8];
 700         u8         roce_version[0x8];
 701
 702         u8         reserved_at_a0[0x10];
 703         u8         r_roce_dest_udp_port[0x10];
 704
 705         u8         r_roce_max_src_udp_port[0x10];
 706         u8         r_roce_min_src_udp_port[0x10];
 707
 708         u8         reserved_at_e0[0x10];
 709         u8         roce_address_table_size[0x10];
 710
 711         u8         reserved_at_100[0x700];
 712 };
 713
 714 struct mlx5_ifc_device_mem_cap_bits {
 715         u8         memic[0x1];
 716         u8         reserved_at_1[0x1f];
 717
 718         u8         reserved_at_20[0xb];
 719         u8         log_min_memic_alloc_size[0x5];
 720         u8         reserved_at_30[0x8];
 721         u8         log_max_memic_addr_alignment[0x8];
 722
 723         u8         memic_bar_start_addr[0x40];
 724
 725         u8         memic_bar_size[0x20];
 726
 727         u8         max_memic_size[0x20];
 728
 729         u8         reserved_at_c0[0x740];
 730 };
 731
 732 enum {
 733         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 734         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 735         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 736         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 737         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 738         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 739         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 740         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 741         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 742 };
 743
 744 enum {
 745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 752         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 753         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 754 };
 755
 756 struct mlx5_ifc_atomic_caps_bits {
 757         u8         reserved_at_0[0x40];
 758
 759         u8         atomic_req_8B_endianness_mode[0x2];
 760         u8         reserved_at_42[0x4];
 761         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 762
 763         u8         reserved_at_47[0x19];
 764
 765         u8         reserved_at_60[0x20];
 766
 767         u8         reserved_at_80[0x10];
 768         u8         atomic_operations[0x10];
 769
 770         u8         reserved_at_a0[0x10];
 771         u8         atomic_size_qp[0x10];
 772
 773         u8         reserved_at_c0[0x10];
 774         u8         atomic_size_dc[0x10];
 775
 776         u8         reserved_at_e0[0x720];
 777 };
 778
 779 struct mlx5_ifc_odp_cap_bits {
 780         u8         reserved_at_0[0x40];
 781
 782         u8         sig[0x1];
 783         u8         reserved_at_41[0x1f];
 784
 785         u8         reserved_at_60[0x20];
 786
 787         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 788
 789         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 790
 791         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 792
 793         u8         reserved_at_e0[0x720];
 794 };
 795
 796 struct mlx5_ifc_calc_op {
 797         u8        reserved_at_0[0x10];
 798         u8        reserved_at_10[0x9];
 799         u8        op_swap_endianness[0x1];
 800         u8        op_min[0x1];
 801         u8        op_xor[0x1];
 802         u8        op_or[0x1];
 803         u8        op_and[0x1];
 804         u8        op_max[0x1];
 805         u8        op_add[0x1];
 806 };
 807
 808 struct mlx5_ifc_vector_calc_cap_bits {
 809         u8         calc_matrix[0x1];
 810         u8         reserved_at_1[0x1f];
 811         u8         reserved_at_20[0x8];
 812         u8         max_vec_count[0x8];
 813         u8         reserved_at_30[0xd];
 814         u8         max_chunk_size[0x3];
 815         struct mlx5_ifc_calc_op calc0;
 816         struct mlx5_ifc_calc_op calc1;
 817         struct mlx5_ifc_calc_op calc2;
 818         struct mlx5_ifc_calc_op calc3;
 819
 820         u8         reserved_at_e0[0x720];
 821 };
 822
 823 enum {
 824         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 825         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 826         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 827         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 828 };
 829
 830 enum {
 831         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 832         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 833 };
 834
 835 enum {
 836         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 837         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 838         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 839         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 840         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 841 };
 842
 843 enum {
 844         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 845         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 846         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 847         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 848         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 849         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 850 };
 851
 852 enum {
 853         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 854         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 855 };
 856
 857 enum {
 858         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 859         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 860         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 861 };
 862
 863 enum {
 864         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 865         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 866 };
 867
 868 enum {
 869         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 870         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 871         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 872 };
 873
 874 struct mlx5_ifc_cmd_hca_cap_bits {
 875         u8         reserved_at_0[0x30];
 876         u8         vhca_id[0x10];
 877
 878         u8         reserved_at_40[0x40];
 879
 880         u8         log_max_srq_sz[0x8];
 881         u8         log_max_qp_sz[0x8];
 882         u8         reserved_at_90[0xb];
 883         u8         log_max_qp[0x5];
 884
 885         u8         reserved_at_a0[0xb];
 886         u8         log_max_srq[0x5];
 887         u8         reserved_at_b0[0x10];
 888
 889         u8         reserved_at_c0[0x8];
 890         u8         log_max_cq_sz[0x8];
 891         u8         reserved_at_d0[0xb];
 892         u8         log_max_cq[0x5];
 893
 894         u8         log_max_eq_sz[0x8];
 895         u8         reserved_at_e8[0x2];
 896         u8         log_max_mkey[0x6];
 897         u8         reserved_at_f0[0x8];
 898         u8         dump_fill_mkey[0x1];
 899         u8         reserved_at_f9[0x3];
 900         u8         log_max_eq[0x4];
 901
 902         u8         max_indirection[0x8];
 903         u8         fixed_buffer_size[0x1];
 904         u8         log_max_mrw_sz[0x7];
 905         u8         force_teardown[0x1];
 906         u8         reserved_at_111[0x1];
 907         u8         log_max_bsf_list_size[0x6];
 908         u8         umr_extended_translation_offset[0x1];
 909         u8         null_mkey[0x1];
 910         u8         log_max_klm_list_size[0x6];
 911
 912         u8         reserved_at_120[0xa];
 913         u8         log_max_ra_req_dc[0x6];
 914         u8         reserved_at_130[0xa];
 915         u8         log_max_ra_res_dc[0x6];
 916
 917         u8         reserved_at_140[0xa];
 918         u8         log_max_ra_req_qp[0x6];
 919         u8         reserved_at_150[0xa];
 920         u8         log_max_ra_res_qp[0x6];
 921
 922         u8         end_pad[0x1];
 923         u8         cc_query_allowed[0x1];
 924         u8         cc_modify_allowed[0x1];
 925         u8         start_pad[0x1];
 926         u8         cache_line_128byte[0x1];
 927         u8         reserved_at_165[0xa];
 928         u8         qcam_reg[0x1];
 929         u8         gid_table_size[0x10];
 930
 931         u8         out_of_seq_cnt[0x1];
 932         u8         vport_counters[0x1];
 933         u8         retransmission_q_counters[0x1];
 934         u8         debug[0x1];
 935         u8         modify_rq_counter_set_id[0x1];
 936         u8         rq_delay_drop[0x1];
 937         u8         max_qp_cnt[0xa];
 938         u8         pkey_table_size[0x10];
 939
 940         u8         vport_group_manager[0x1];
 941         u8         vhca_group_manager[0x1];
 942         u8         ib_virt[0x1];
 943         u8         eth_virt[0x1];
 944         u8         vnic_env_queue_counters[0x1];
 945         u8         ets[0x1];
 946         u8         nic_flow_table[0x1];
 947         u8         eswitch_manager[0x1];
 948         u8         device_memory[0x1];
 949         u8         mcam_reg[0x1];
 950         u8         pcam_reg[0x1];
 951         u8         local_ca_ack_delay[0x5];
 952         u8         port_module_event[0x1];
 953         u8         enhanced_error_q_counters[0x1];
 954         u8         ports_check[0x1];
 955         u8         reserved_at_1b3[0x1];
 956         u8         disable_link_up[0x1];
 957         u8         beacon_led[0x1];
 958         u8         port_type[0x2];
 959         u8         num_ports[0x8];
 960
 961         u8         reserved_at_1c0[0x1];
 962         u8         pps[0x1];
 963         u8         pps_modify[0x1];
 964         u8         log_max_msg[0x5];
 965         u8         reserved_at_1c8[0x4];
 966         u8         max_tc[0x4];
 967         u8         temp_warn_event[0x1];
 968         u8         dcbx[0x1];
 969         u8         general_notification_event[0x1];
 970         u8         reserved_at_1d3[0x2];
 971         u8         fpga[0x1];
 972         u8         rol_s[0x1];
 973         u8         rol_g[0x1];
 974         u8         reserved_at_1d8[0x1];
 975         u8         wol_s[0x1];
 976         u8         wol_g[0x1];
 977         u8         wol_a[0x1];
 978         u8         wol_b[0x1];
 979         u8         wol_m[0x1];
 980         u8         wol_u[0x1];
 981         u8         wol_p[0x1];
 982
 983         u8         stat_rate_support[0x10];
 984         u8         reserved_at_1f0[0xc];
 985         u8         cqe_version[0x4];
 986
 987         u8         compact_address_vector[0x1];
 988         u8         striding_rq[0x1];
 989         u8         reserved_at_202[0x1];
 990         u8         ipoib_enhanced_offloads[0x1];
 991         u8         ipoib_basic_offloads[0x1];
 992         u8         reserved_at_205[0x1];
 993         u8         repeated_block_disabled[0x1];
 994         u8         umr_modify_entity_size_disabled[0x1];
 995         u8         umr_modify_atomic_disabled[0x1];
 996         u8         umr_indirect_mkey_disabled[0x1];
 997         u8         umr_fence[0x2];
 998         u8         reserved_at_20c[0x3];
 999         u8         drain_sigerr[0x1];
1000         u8         cmdif_checksum[0x2];
1001         u8         sigerr_cqe[0x1];
1002         u8         reserved_at_213[0x1];
1003         u8         wq_signature[0x1];
1004         u8         sctr_data_cqe[0x1];
1005         u8         reserved_at_216[0x1];
1006         u8         sho[0x1];
1007         u8         tph[0x1];
1008         u8         rf[0x1];
1009         u8         dct[0x1];
1010         u8         qos[0x1];
1011         u8         eth_net_offloads[0x1];
1012         u8         roce[0x1];
1013         u8         atomic[0x1];
1014         u8         reserved_at_21f[0x1];
1015
1016         u8         cq_oi[0x1];
1017         u8         cq_resize[0x1];
1018         u8         cq_moderation[0x1];
1019         u8         reserved_at_223[0x3];
1020         u8         cq_eq_remap[0x1];
1021         u8         pg[0x1];
1022         u8         block_lb_mc[0x1];
1023         u8         reserved_at_229[0x1];
1024         u8         scqe_break_moderation[0x1];
1025         u8         cq_period_start_from_cqe[0x1];
1026         u8         cd[0x1];
1027         u8         reserved_at_22d[0x1];
1028         u8         apm[0x1];
1029         u8         vector_calc[0x1];
1030         u8         umr_ptr_rlky[0x1];
1031         u8         imaicl[0x1];
1032         u8         reserved_at_232[0x4];
1033         u8         qkv[0x1];
1034         u8         pkv[0x1];
1035         u8         set_deth_sqpn[0x1];
1036         u8         reserved_at_239[0x3];
1037         u8         xrc[0x1];
1038         u8         ud[0x1];
1039         u8         uc[0x1];
1040         u8         rc[0x1];
1041
1042         u8         uar_4k[0x1];
1043         u8         reserved_at_241[0x9];
1044         u8         uar_sz[0x6];
1045         u8         reserved_at_250[0x8];
1046         u8         log_pg_sz[0x8];
1047
1048         u8         bf[0x1];
1049         u8         driver_version[0x1];
1050         u8         pad_tx_eth_packet[0x1];
1051         u8         reserved_at_263[0x8];
1052         u8         log_bf_reg_size[0x5];
1053
1054         u8         reserved_at_270[0xb];
1055         u8         lag_master[0x1];
1056         u8         num_lag_ports[0x4];
1057
1058         u8         reserved_at_280[0x10];
1059         u8         max_wqe_sz_sq[0x10];
1060
1061         u8         reserved_at_2a0[0x10];
1062         u8         max_wqe_sz_rq[0x10];
1063
1064         u8         max_flow_counter_31_16[0x10];
1065         u8         max_wqe_sz_sq_dc[0x10];
1066
1067         u8         reserved_at_2e0[0x7];
1068         u8         max_qp_mcg[0x19];
1069
1070         u8         reserved_at_300[0x18];
1071         u8         log_max_mcg[0x8];
1072
1073         u8         reserved_at_320[0x3];
1074         u8         log_max_transport_domain[0x5];
1075         u8         reserved_at_328[0x3];
1076         u8         log_max_pd[0x5];
1077         u8         reserved_at_330[0xb];
1078         u8         log_max_xrcd[0x5];
1079
1080         u8         nic_receive_steering_discard[0x1];
1081         u8         receive_discard_vport_down[0x1];
1082         u8         transmit_discard_vport_down[0x1];
1083         u8         reserved_at_343[0x5];
1084         u8         log_max_flow_counter_bulk[0x8];
1085         u8         max_flow_counter_15_0[0x10];
1086
1087
1088         u8         reserved_at_360[0x3];
1089         u8         log_max_rq[0x5];
1090         u8         reserved_at_368[0x3];
1091         u8         log_max_sq[0x5];
1092         u8         reserved_at_370[0x3];
1093         u8         log_max_tir[0x5];
1094         u8         reserved_at_378[0x3];
1095         u8         log_max_tis[0x5];
1096
1097         u8         basic_cyclic_rcv_wqe[0x1];
1098         u8         reserved_at_381[0x2];
1099         u8         log_max_rmp[0x5];
1100         u8         reserved_at_388[0x3];
1101         u8         log_max_rqt[0x5];
1102         u8         reserved_at_390[0x3];
1103         u8         log_max_rqt_size[0x5];
1104         u8         reserved_at_398[0x3];
1105         u8         log_max_tis_per_sq[0x5];
1106
1107         u8         ext_stride_num_range[0x1];
1108         u8         reserved_at_3a1[0x2];
1109         u8         log_max_stride_sz_rq[0x5];
1110         u8         reserved_at_3a8[0x3];
1111         u8         log_min_stride_sz_rq[0x5];
1112         u8         reserved_at_3b0[0x3];
1113         u8         log_max_stride_sz_sq[0x5];
1114         u8         reserved_at_3b8[0x3];
1115         u8         log_min_stride_sz_sq[0x5];
1116
1117         u8         hairpin[0x1];
1118         u8         reserved_at_3c1[0x2];
1119         u8         log_max_hairpin_queues[0x5];
1120         u8         reserved_at_3c8[0x3];
1121         u8         log_max_hairpin_wq_data_sz[0x5];
1122         u8         reserved_at_3d0[0x3];
1123         u8         log_max_hairpin_num_packets[0x5];
1124         u8         reserved_at_3d8[0x3];
1125         u8         log_max_wq_sz[0x5];
1126
1127         u8         nic_vport_change_event[0x1];
1128         u8         disable_local_lb_uc[0x1];
1129         u8         disable_local_lb_mc[0x1];
1130         u8         log_min_hairpin_wq_data_sz[0x5];
1131         u8         reserved_at_3e8[0x3];
1132         u8         log_max_vlan_list[0x5];
1133         u8         reserved_at_3f0[0x3];
1134         u8         log_max_current_mc_list[0x5];
1135         u8         reserved_at_3f8[0x3];
1136         u8         log_max_current_uc_list[0x5];
1137
1138         u8         general_obj_types[0x40];
1139
1140         u8         reserved_at_440[0x20];
1141
1142         u8         reserved_at_460[0x10];
1143         u8         max_num_eqs[0x10];
1144
1145         u8         reserved_at_480[0x3];
1146         u8         log_max_l2_table[0x5];
1147         u8         reserved_at_488[0x8];
1148         u8         log_uar_page_sz[0x10];
1149
1150         u8         reserved_at_4a0[0x20];
1151         u8         device_frequency_mhz[0x20];
1152         u8         device_frequency_khz[0x20];
1153
1154         u8         reserved_at_500[0x20];
1155         u8         num_of_uars_per_page[0x20];
1156
1157         u8         flex_parser_protocols[0x20];
1158         u8         reserved_at_560[0x20];
1159
1160         u8         reserved_at_580[0x3c];
1161         u8         mini_cqe_resp_stride_index[0x1];
1162         u8         cqe_128_always[0x1];
1163         u8         cqe_compression_128[0x1];
1164         u8         cqe_compression[0x1];
1165
1166         u8         cqe_compression_timeout[0x10];
1167         u8         cqe_compression_max_num[0x10];
1168
1169         u8         reserved_at_5e0[0x10];
1170         u8         tag_matching[0x1];
1171         u8         rndv_offload_rc[0x1];
1172         u8         rndv_offload_dc[0x1];
1173         u8         log_tag_matching_list_sz[0x5];
1174         u8         reserved_at_5f8[0x3];
1175         u8         log_max_xrq[0x5];
1176
1177         u8         affiliate_nic_vport_criteria[0x8];
1178         u8         native_port_num[0x8];
1179         u8         num_vhca_ports[0x8];
1180         u8         reserved_at_618[0x6];
1181         u8         sw_owner_id[0x1];
1182         u8         reserved_at_61f[0x1e1];
1183 };
1184
1185 enum mlx5_flow_destination_type {
1186         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1187         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1188         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1189
1190         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1191         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1192         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1193 };
1194
1195 struct mlx5_ifc_dest_format_struct_bits {
1196         u8         destination_type[0x8];
1197         u8         destination_id[0x18];
1198         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1199         u8         reserved_at_21[0xf];
1200         u8         destination_eswitch_owner_vhca_id[0x10];
1201 };
1202
1203 struct mlx5_ifc_flow_counter_list_bits {
1204         u8         flow_counter_id[0x20];
1205
1206         u8         reserved_at_20[0x20];
1207 };
1208
1209 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1210         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1211         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1212         u8         reserved_at_0[0x40];
1213 };
1214
1215 struct mlx5_ifc_fte_match_param_bits {
1216         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1217
1218         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1219
1220         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1221
1222         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1223
1224         u8         reserved_at_800[0x800];
1225 };
1226
1227 enum {
1228         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1229         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1230         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1231         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1232         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1233 };
1234
1235 struct mlx5_ifc_rx_hash_field_select_bits {
1236         u8         l3_prot_type[0x1];
1237         u8         l4_prot_type[0x1];
1238         u8         selected_fields[0x1e];
1239 };
1240
1241 enum {
1242         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1243         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1244 };
1245
1246 enum {
1247         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1248         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1249 };
1250
1251 struct mlx5_ifc_wq_bits {
1252         u8         wq_type[0x4];
1253         u8         wq_signature[0x1];
1254         u8         end_padding_mode[0x2];
1255         u8         cd_slave[0x1];
1256         u8         reserved_at_8[0x18];
1257
1258         u8         hds_skip_first_sge[0x1];
1259         u8         log2_hds_buf_size[0x3];
1260         u8         reserved_at_24[0x7];
1261         u8         page_offset[0x5];
1262         u8         lwm[0x10];
1263
1264         u8         reserved_at_40[0x8];
1265         u8         pd[0x18];
1266
1267         u8         reserved_at_60[0x8];
1268         u8         uar_page[0x18];
1269
1270         u8         dbr_addr[0x40];
1271
1272         u8         hw_counter[0x20];
1273
1274         u8         sw_counter[0x20];
1275
1276         u8         reserved_at_100[0xc];
1277         u8         log_wq_stride[0x4];
1278         u8         reserved_at_110[0x3];
1279         u8         log_wq_pg_sz[0x5];
1280         u8         reserved_at_118[0x3];
1281         u8         log_wq_sz[0x5];
1282
1283         u8         reserved_at_120[0x3];
1284         u8         log_hairpin_num_packets[0x5];
1285         u8         reserved_at_128[0x3];
1286         u8         log_hairpin_data_sz[0x5];
1287
1288         u8         reserved_at_130[0x4];
1289         u8         log_wqe_num_of_strides[0x4];
1290         u8         two_byte_shift_en[0x1];
1291         u8         reserved_at_139[0x4];
1292         u8         log_wqe_stride_size[0x3];
1293
1294         u8         reserved_at_140[0x4c0];
1295
1296         struct mlx5_ifc_cmd_pas_bits pas[0];
1297 };
1298
1299 struct mlx5_ifc_rq_num_bits {
1300         u8         reserved_at_0[0x8];
1301         u8         rq_num[0x18];
1302 };
1303
1304 struct mlx5_ifc_mac_address_layout_bits {
1305         u8         reserved_at_0[0x10];
1306         u8         mac_addr_47_32[0x10];
1307
1308         u8         mac_addr_31_0[0x20];
1309 };
1310
1311 struct mlx5_ifc_vlan_layout_bits {
1312         u8         reserved_at_0[0x14];
1313         u8         vlan[0x0c];
1314
1315         u8         reserved_at_20[0x20];
1316 };
1317
1318 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1319         u8         reserved_at_0[0xa0];
1320
1321         u8         min_time_between_cnps[0x20];
1322
1323         u8         reserved_at_c0[0x12];
1324         u8         cnp_dscp[0x6];
1325         u8         reserved_at_d8[0x4];
1326         u8         cnp_prio_mode[0x1];
1327         u8         cnp_802p_prio[0x3];
1328
1329         u8         reserved_at_e0[0x720];
1330 };
1331
1332 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1333         u8         reserved_at_0[0x60];
1334
1335         u8         reserved_at_60[0x4];
1336         u8         clamp_tgt_rate[0x1];
1337         u8         reserved_at_65[0x3];
1338         u8         clamp_tgt_rate_after_time_inc[0x1];
1339         u8         reserved_at_69[0x17];
1340
1341         u8         reserved_at_80[0x20];
1342
1343         u8         rpg_time_reset[0x20];
1344
1345         u8         rpg_byte_reset[0x20];
1346
1347         u8         rpg_threshold[0x20];
1348
1349         u8         rpg_max_rate[0x20];
1350
1351         u8         rpg_ai_rate[0x20];
1352
1353         u8         rpg_hai_rate[0x20];
1354
1355         u8         rpg_gd[0x20];
1356
1357         u8         rpg_min_dec_fac[0x20];
1358
1359         u8         rpg_min_rate[0x20];
1360
1361         u8         reserved_at_1c0[0xe0];
1362
1363         u8         rate_to_set_on_first_cnp[0x20];
1364
1365         u8         dce_tcp_g[0x20];
1366
1367         u8         dce_tcp_rtt[0x20];
1368
1369         u8         rate_reduce_monitor_period[0x20];
1370
1371         u8         reserved_at_320[0x20];
1372
1373         u8         initial_alpha_value[0x20];
1374
1375         u8         reserved_at_360[0x4a0];
1376 };
1377
1378 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1379         u8         reserved_at_0[0x80];
1380
1381         u8         rppp_max_rps[0x20];
1382
1383         u8         rpg_time_reset[0x20];
1384
1385         u8         rpg_byte_reset[0x20];
1386
1387         u8         rpg_threshold[0x20];
1388
1389         u8         rpg_max_rate[0x20];
1390
1391         u8         rpg_ai_rate[0x20];
1392
1393         u8         rpg_hai_rate[0x20];
1394
1395         u8         rpg_gd[0x20];
1396
1397         u8         rpg_min_dec_fac[0x20];
1398
1399         u8         rpg_min_rate[0x20];
1400
1401         u8         reserved_at_1c0[0x640];
1402 };
1403
1404 enum {
1405         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1406         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1407         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1408 };
1409
1410 struct mlx5_ifc_resize_field_select_bits {
1411         u8         resize_field_select[0x20];
1412 };
1413
1414 enum {
1415         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1416         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1417         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1418         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1419 };
1420
1421 struct mlx5_ifc_modify_field_select_bits {
1422         u8         modify_field_select[0x20];
1423 };
1424
1425 struct mlx5_ifc_field_select_r_roce_np_bits {
1426         u8         field_select_r_roce_np[0x20];
1427 };
1428
1429 struct mlx5_ifc_field_select_r_roce_rp_bits {
1430         u8         field_select_r_roce_rp[0x20];
1431 };
1432
1433 enum {
1434         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1435         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1436         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1437         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1438         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1439         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1440         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1441         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1442         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1443         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1444 };
1445
1446 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1447         u8         field_select_8021qaurp[0x20];
1448 };
1449
1450 struct mlx5_ifc_phys_layer_cntrs_bits {
1451         u8         time_since_last_clear_high[0x20];
1452
1453         u8         time_since_last_clear_low[0x20];
1454
1455         u8         symbol_errors_high[0x20];
1456
1457         u8         symbol_errors_low[0x20];
1458
1459         u8         sync_headers_errors_high[0x20];
1460
1461         u8         sync_headers_errors_low[0x20];
1462
1463         u8         edpl_bip_errors_lane0_high[0x20];
1464
1465         u8         edpl_bip_errors_lane0_low[0x20];
1466
1467         u8         edpl_bip_errors_lane1_high[0x20];
1468
1469         u8         edpl_bip_errors_lane1_low[0x20];
1470
1471         u8         edpl_bip_errors_lane2_high[0x20];
1472
1473         u8         edpl_bip_errors_lane2_low[0x20];
1474
1475         u8         edpl_bip_errors_lane3_high[0x20];
1476
1477         u8         edpl_bip_errors_lane3_low[0x20];
1478
1479         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1480
1481         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1482
1483         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1484
1485         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1486
1487         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1488
1489         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1490
1491         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1492
1493         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1494
1495         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1496
1497         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1498
1499         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1500
1501         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1502
1503         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1504
1505         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1506
1507         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1508
1509         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1510
1511         u8         rs_fec_corrected_blocks_high[0x20];
1512
1513         u8         rs_fec_corrected_blocks_low[0x20];
1514
1515         u8         rs_fec_uncorrectable_blocks_high[0x20];
1516
1517         u8         rs_fec_uncorrectable_blocks_low[0x20];
1518
1519         u8         rs_fec_no_errors_blocks_high[0x20];
1520
1521         u8         rs_fec_no_errors_blocks_low[0x20];
1522
1523         u8         rs_fec_single_error_blocks_high[0x20];
1524
1525         u8         rs_fec_single_error_blocks_low[0x20];
1526
1527         u8         rs_fec_corrected_symbols_total_high[0x20];
1528
1529         u8         rs_fec_corrected_symbols_total_low[0x20];
1530
1531         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1532
1533         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1534
1535         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1536
1537         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1538
1539         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1540
1541         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1542
1543         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1544
1545         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1546
1547         u8         link_down_events[0x20];
1548
1549         u8         successful_recovery_events[0x20];
1550
1551         u8         reserved_at_640[0x180];
1552 };
1553
1554 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1555         u8         time_since_last_clear_high[0x20];
1556
1557         u8         time_since_last_clear_low[0x20];
1558
1559         u8         phy_received_bits_high[0x20];
1560
1561         u8         phy_received_bits_low[0x20];
1562
1563         u8         phy_symbol_errors_high[0x20];
1564
1565         u8         phy_symbol_errors_low[0x20];
1566
1567         u8         phy_corrected_bits_high[0x20];
1568
1569         u8         phy_corrected_bits_low[0x20];
1570
1571         u8         phy_corrected_bits_lane0_high[0x20];
1572
1573         u8         phy_corrected_bits_lane0_low[0x20];
1574
1575         u8         phy_corrected_bits_lane1_high[0x20];
1576
1577         u8         phy_corrected_bits_lane1_low[0x20];
1578
1579         u8         phy_corrected_bits_lane2_high[0x20];
1580
1581         u8         phy_corrected_bits_lane2_low[0x20];
1582
1583         u8         phy_corrected_bits_lane3_high[0x20];
1584
1585         u8         phy_corrected_bits_lane3_low[0x20];
1586
1587         u8         reserved_at_200[0x5c0];
1588 };
1589
1590 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1591         u8         symbol_error_counter[0x10];
1592
1593         u8         link_error_recovery_counter[0x8];
1594
1595         u8         link_downed_counter[0x8];
1596
1597         u8         port_rcv_errors[0x10];
1598
1599         u8         port_rcv_remote_physical_errors[0x10];
1600
1601         u8         port_rcv_switch_relay_errors[0x10];
1602
1603         u8         port_xmit_discards[0x10];
1604
1605         u8         port_xmit_constraint_errors[0x8];
1606
1607         u8         port_rcv_constraint_errors[0x8];
1608
1609         u8         reserved_at_70[0x8];
1610
1611         u8         link_overrun_errors[0x8];
1612
1613         u8         reserved_at_80[0x10];
1614
1615         u8         vl_15_dropped[0x10];
1616
1617         u8         reserved_at_a0[0x80];
1618
1619         u8         port_xmit_wait[0x20];
1620 };
1621
1622 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1623         u8         transmit_queue_high[0x20];
1624
1625         u8         transmit_queue_low[0x20];
1626
1627         u8         reserved_at_40[0x780];
1628 };
1629
1630 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1631         u8         rx_octets_high[0x20];
1632
1633         u8         rx_octets_low[0x20];
1634
1635         u8         reserved_at_40[0xc0];
1636
1637         u8         rx_frames_high[0x20];
1638
1639         u8         rx_frames_low[0x20];
1640
1641         u8         tx_octets_high[0x20];
1642
1643         u8         tx_octets_low[0x20];
1644
1645         u8         reserved_at_180[0xc0];
1646
1647         u8         tx_frames_high[0x20];
1648
1649         u8         tx_frames_low[0x20];
1650
1651         u8         rx_pause_high[0x20];
1652
1653         u8         rx_pause_low[0x20];
1654
1655         u8         rx_pause_duration_high[0x20];
1656
1657         u8         rx_pause_duration_low[0x20];
1658
1659         u8         tx_pause_high[0x20];
1660
1661         u8         tx_pause_low[0x20];
1662
1663         u8         tx_pause_duration_high[0x20];
1664
1665         u8         tx_pause_duration_low[0x20];
1666
1667         u8         rx_pause_transition_high[0x20];
1668
1669         u8         rx_pause_transition_low[0x20];
1670
1671         u8         reserved_at_3c0[0x40];
1672
1673         u8         device_stall_minor_watermark_cnt_high[0x20];
1674
1675         u8         device_stall_minor_watermark_cnt_low[0x20];
1676
1677         u8         device_stall_critical_watermark_cnt_high[0x20];
1678
1679         u8         device_stall_critical_watermark_cnt_low[0x20];
1680
1681         u8         reserved_at_480[0x340];
1682 };
1683
1684 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1685         u8         port_transmit_wait_high[0x20];
1686
1687         u8         port_transmit_wait_low[0x20];
1688
1689         u8         reserved_at_40[0x100];
1690
1691         u8         rx_buffer_almost_full_high[0x20];
1692
1693         u8         rx_buffer_almost_full_low[0x20];
1694
1695         u8         rx_buffer_full_high[0x20];
1696
1697         u8         rx_buffer_full_low[0x20];
1698
1699         u8         rx_icrc_encapsulated_high[0x20];
1700
1701         u8         rx_icrc_encapsulated_low[0x20];
1702
1703         u8         reserved_at_200[0x5c0];
1704 };
1705
1706 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1707         u8         dot3stats_alignment_errors_high[0x20];
1708
1709         u8         dot3stats_alignment_errors_low[0x20];
1710
1711         u8         dot3stats_fcs_errors_high[0x20];
1712
1713         u8         dot3stats_fcs_errors_low[0x20];
1714
1715         u8         dot3stats_single_collision_frames_high[0x20];
1716
1717         u8         dot3stats_single_collision_frames_low[0x20];
1718
1719         u8         dot3stats_multiple_collision_frames_high[0x20];
1720
1721         u8         dot3stats_multiple_collision_frames_low[0x20];
1722
1723         u8         dot3stats_sqe_test_errors_high[0x20];
1724
1725         u8         dot3stats_sqe_test_errors_low[0x20];
1726
1727         u8         dot3stats_deferred_transmissions_high[0x20];
1728
1729         u8         dot3stats_deferred_transmissions_low[0x20];
1730
1731         u8         dot3stats_late_collisions_high[0x20];
1732
1733         u8         dot3stats_late_collisions_low[0x20];
1734
1735         u8         dot3stats_excessive_collisions_high[0x20];
1736
1737         u8         dot3stats_excessive_collisions_low[0x20];
1738
1739         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1740
1741         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1742
1743         u8         dot3stats_carrier_sense_errors_high[0x20];
1744
1745         u8         dot3stats_carrier_sense_errors_low[0x20];
1746
1747         u8         dot3stats_frame_too_longs_high[0x20];
1748
1749         u8         dot3stats_frame_too_longs_low[0x20];
1750
1751         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1752
1753         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1754
1755         u8         dot3stats_symbol_errors_high[0x20];
1756
1757         u8         dot3stats_symbol_errors_low[0x20];
1758
1759         u8         dot3control_in_unknown_opcodes_high[0x20];
1760
1761         u8         dot3control_in_unknown_opcodes_low[0x20];
1762
1763         u8         dot3in_pause_frames_high[0x20];
1764
1765         u8         dot3in_pause_frames_low[0x20];
1766
1767         u8         dot3out_pause_frames_high[0x20];
1768
1769         u8         dot3out_pause_frames_low[0x20];
1770
1771         u8         reserved_at_400[0x3c0];
1772 };
1773
1774 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1775         u8         ether_stats_drop_events_high[0x20];
1776
1777         u8         ether_stats_drop_events_low[0x20];
1778
1779         u8         ether_stats_octets_high[0x20];
1780
1781         u8         ether_stats_octets_low[0x20];
1782
1783         u8         ether_stats_pkts_high[0x20];
1784
1785         u8         ether_stats_pkts_low[0x20];
1786
1787         u8         ether_stats_broadcast_pkts_high[0x20];
1788
1789         u8         ether_stats_broadcast_pkts_low[0x20];
1790
1791         u8         ether_stats_multicast_pkts_high[0x20];
1792
1793         u8         ether_stats_multicast_pkts_low[0x20];
1794
1795         u8         ether_stats_crc_align_errors_high[0x20];
1796
1797         u8         ether_stats_crc_align_errors_low[0x20];
1798
1799         u8         ether_stats_undersize_pkts_high[0x20];
1800
1801         u8         ether_stats_undersize_pkts_low[0x20];
1802
1803         u8         ether_stats_oversize_pkts_high[0x20];
1804
1805         u8         ether_stats_oversize_pkts_low[0x20];
1806
1807         u8         ether_stats_fragments_high[0x20];
1808
1809         u8         ether_stats_fragments_low[0x20];
1810
1811         u8         ether_stats_jabbers_high[0x20];
1812
1813         u8         ether_stats_jabbers_low[0x20];
1814
1815         u8         ether_stats_collisions_high[0x20];
1816
1817         u8         ether_stats_collisions_low[0x20];
1818
1819         u8         ether_stats_pkts64octets_high[0x20];
1820
1821         u8         ether_stats_pkts64octets_low[0x20];
1822
1823         u8         ether_stats_pkts65to127octets_high[0x20];
1824
1825         u8         ether_stats_pkts65to127octets_low[0x20];
1826
1827         u8         ether_stats_pkts128to255octets_high[0x20];
1828
1829         u8         ether_stats_pkts128to255octets_low[0x20];
1830
1831         u8         ether_stats_pkts256to511octets_high[0x20];
1832
1833         u8         ether_stats_pkts256to511octets_low[0x20];
1834
1835         u8         ether_stats_pkts512to1023octets_high[0x20];
1836
1837         u8         ether_stats_pkts512to1023octets_low[0x20];
1838
1839         u8         ether_stats_pkts1024to1518octets_high[0x20];
1840
1841         u8         ether_stats_pkts1024to1518octets_low[0x20];
1842
1843         u8         ether_stats_pkts1519to2047octets_high[0x20];
1844
1845         u8         ether_stats_pkts1519to2047octets_low[0x20];
1846
1847         u8         ether_stats_pkts2048to4095octets_high[0x20];
1848
1849         u8         ether_stats_pkts2048to4095octets_low[0x20];
1850
1851         u8         ether_stats_pkts4096to8191octets_high[0x20];
1852
1853         u8         ether_stats_pkts4096to8191octets_low[0x20];
1854
1855         u8         ether_stats_pkts8192to10239octets_high[0x20];
1856
1857         u8         ether_stats_pkts8192to10239octets_low[0x20];
1858
1859         u8         reserved_at_540[0x280];
1860 };
1861
1862 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1863         u8         if_in_octets_high[0x20];
1864
1865         u8         if_in_octets_low[0x20];
1866
1867         u8         if_in_ucast_pkts_high[0x20];
1868
1869         u8         if_in_ucast_pkts_low[0x20];
1870
1871         u8         if_in_discards_high[0x20];
1872
1873         u8         if_in_discards_low[0x20];
1874
1875         u8         if_in_errors_high[0x20];
1876
1877         u8         if_in_errors_low[0x20];
1878
1879         u8         if_in_unknown_protos_high[0x20];
1880
1881         u8         if_in_unknown_protos_low[0x20];
1882
1883         u8         if_out_octets_high[0x20];
1884
1885         u8         if_out_octets_low[0x20];
1886
1887         u8         if_out_ucast_pkts_high[0x20];
1888
1889         u8         if_out_ucast_pkts_low[0x20];
1890
1891         u8         if_out_discards_high[0x20];
1892
1893         u8         if_out_discards_low[0x20];
1894
1895         u8         if_out_errors_high[0x20];
1896
1897         u8         if_out_errors_low[0x20];
1898
1899         u8         if_in_multicast_pkts_high[0x20];
1900
1901         u8         if_in_multicast_pkts_low[0x20];
1902
1903         u8         if_in_broadcast_pkts_high[0x20];
1904
1905         u8         if_in_broadcast_pkts_low[0x20];
1906
1907         u8         if_out_multicast_pkts_high[0x20];
1908
1909         u8         if_out_multicast_pkts_low[0x20];
1910
1911         u8         if_out_broadcast_pkts_high[0x20];
1912
1913         u8         if_out_broadcast_pkts_low[0x20];
1914
1915         u8         reserved_at_340[0x480];
1916 };
1917
1918 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1919         u8         a_frames_transmitted_ok_high[0x20];
1920
1921         u8         a_frames_transmitted_ok_low[0x20];
1922
1923         u8         a_frames_received_ok_high[0x20];
1924
1925         u8         a_frames_received_ok_low[0x20];
1926
1927         u8         a_frame_check_sequence_errors_high[0x20];
1928
1929         u8         a_frame_check_sequence_errors_low[0x20];
1930
1931         u8         a_alignment_errors_high[0x20];
1932
1933         u8         a_alignment_errors_low[0x20];
1934
1935         u8         a_octets_transmitted_ok_high[0x20];
1936
1937         u8         a_octets_transmitted_ok_low[0x20];
1938
1939         u8         a_octets_received_ok_high[0x20];
1940
1941         u8         a_octets_received_ok_low[0x20];
1942
1943         u8         a_multicast_frames_xmitted_ok_high[0x20];
1944
1945         u8         a_multicast_frames_xmitted_ok_low[0x20];
1946
1947         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1948
1949         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1950
1951         u8         a_multicast_frames_received_ok_high[0x20];
1952
1953         u8         a_multicast_frames_received_ok_low[0x20];
1954
1955         u8         a_broadcast_frames_received_ok_high[0x20];
1956
1957         u8         a_broadcast_frames_received_ok_low[0x20];
1958
1959         u8         a_in_range_length_errors_high[0x20];
1960
1961         u8         a_in_range_length_errors_low[0x20];
1962
1963         u8         a_out_of_range_length_field_high[0x20];
1964
1965         u8         a_out_of_range_length_field_low[0x20];
1966
1967         u8         a_frame_too_long_errors_high[0x20];
1968
1969         u8         a_frame_too_long_errors_low[0x20];
1970
1971         u8         a_symbol_error_during_carrier_high[0x20];
1972
1973         u8         a_symbol_error_during_carrier_low[0x20];
1974
1975         u8         a_mac_control_frames_transmitted_high[0x20];
1976
1977         u8         a_mac_control_frames_transmitted_low[0x20];
1978
1979         u8         a_mac_control_frames_received_high[0x20];
1980
1981         u8         a_mac_control_frames_received_low[0x20];
1982
1983         u8         a_unsupported_opcodes_received_high[0x20];
1984
1985         u8         a_unsupported_opcodes_received_low[0x20];
1986
1987         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1988
1989         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1990
1991         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1992
1993         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1994
1995         u8         reserved_at_4c0[0x300];
1996 };
1997
1998 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1999         u8         life_time_counter_high[0x20];
2000
2001         u8         life_time_counter_low[0x20];
2002
2003         u8         rx_errors[0x20];
2004
2005         u8         tx_errors[0x20];
2006
2007         u8         l0_to_recovery_eieos[0x20];
2008
2009         u8         l0_to_recovery_ts[0x20];
2010
2011         u8         l0_to_recovery_framing[0x20];
2012
2013         u8         l0_to_recovery_retrain[0x20];
2014
2015         u8         crc_error_dllp[0x20];
2016
2017         u8         crc_error_tlp[0x20];
2018
2019         u8         tx_overflow_buffer_pkt_high[0x20];
2020
2021         u8         tx_overflow_buffer_pkt_low[0x20];
2022
2023         u8         outbound_stalled_reads[0x20];
2024
2025         u8         outbound_stalled_writes[0x20];
2026
2027         u8         outbound_stalled_reads_events[0x20];
2028
2029         u8         outbound_stalled_writes_events[0x20];
2030
2031         u8         reserved_at_200[0x5c0];
2032 };
2033
2034 struct mlx5_ifc_cmd_inter_comp_event_bits {
2035         u8         command_completion_vector[0x20];
2036
2037         u8         reserved_at_20[0xc0];
2038 };
2039
2040 struct mlx5_ifc_stall_vl_event_bits {
2041         u8         reserved_at_0[0x18];
2042         u8         port_num[0x1];
2043         u8         reserved_at_19[0x3];
2044         u8         vl[0x4];
2045
2046         u8         reserved_at_20[0xa0];
2047 };
2048
2049 struct mlx5_ifc_db_bf_congestion_event_bits {
2050         u8         event_subtype[0x8];
2051         u8         reserved_at_8[0x8];
2052         u8         congestion_level[0x8];
2053         u8         reserved_at_18[0x8];
2054
2055         u8         reserved_at_20[0xa0];
2056 };
2057
2058 struct mlx5_ifc_gpio_event_bits {
2059         u8         reserved_at_0[0x60];
2060
2061         u8         gpio_event_hi[0x20];
2062
2063         u8         gpio_event_lo[0x20];
2064
2065         u8         reserved_at_a0[0x40];
2066 };
2067
2068 struct mlx5_ifc_port_state_change_event_bits {
2069         u8         reserved_at_0[0x40];
2070
2071         u8         port_num[0x4];
2072         u8         reserved_at_44[0x1c];
2073
2074         u8         reserved_at_60[0x80];
2075 };
2076
2077 struct mlx5_ifc_dropped_packet_logged_bits {
2078         u8         reserved_at_0[0xe0];
2079 };
2080
2081 enum {
2082         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2083         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2084 };
2085
2086 struct mlx5_ifc_cq_error_bits {
2087         u8         reserved_at_0[0x8];
2088         u8         cqn[0x18];
2089
2090         u8         reserved_at_20[0x20];
2091
2092         u8         reserved_at_40[0x18];
2093         u8         syndrome[0x8];
2094
2095         u8         reserved_at_60[0x80];
2096 };
2097
2098 struct mlx5_ifc_rdma_page_fault_event_bits {
2099         u8         bytes_committed[0x20];
2100
2101         u8         r_key[0x20];
2102
2103         u8         reserved_at_40[0x10];
2104         u8         packet_len[0x10];
2105
2106         u8         rdma_op_len[0x20];
2107
2108         u8         rdma_va[0x40];
2109
2110         u8         reserved_at_c0[0x5];
2111         u8         rdma[0x1];
2112         u8         write[0x1];
2113         u8         requestor[0x1];
2114         u8         qp_number[0x18];
2115 };
2116
2117 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2118         u8         bytes_committed[0x20];
2119
2120         u8         reserved_at_20[0x10];
2121         u8         wqe_index[0x10];
2122
2123         u8         reserved_at_40[0x10];
2124         u8         len[0x10];
2125
2126         u8         reserved_at_60[0x60];
2127
2128         u8         reserved_at_c0[0x5];
2129         u8         rdma[0x1];
2130         u8         write_read[0x1];
2131         u8         requestor[0x1];
2132         u8         qpn[0x18];
2133 };
2134
2135 struct mlx5_ifc_qp_events_bits {
2136         u8         reserved_at_0[0xa0];
2137
2138         u8         type[0x8];
2139         u8         reserved_at_a8[0x18];
2140
2141         u8         reserved_at_c0[0x8];
2142         u8         qpn_rqn_sqn[0x18];
2143 };
2144
2145 struct mlx5_ifc_dct_events_bits {
2146         u8         reserved_at_0[0xc0];
2147
2148         u8         reserved_at_c0[0x8];
2149         u8         dct_number[0x18];
2150 };
2151
2152 struct mlx5_ifc_comp_event_bits {
2153         u8         reserved_at_0[0xc0];
2154
2155         u8         reserved_at_c0[0x8];
2156         u8         cq_number[0x18];
2157 };
2158
2159 enum {
2160         MLX5_QPC_STATE_RST        = 0x0,
2161         MLX5_QPC_STATE_INIT       = 0x1,
2162         MLX5_QPC_STATE_RTR        = 0x2,
2163         MLX5_QPC_STATE_RTS        = 0x3,
2164         MLX5_QPC_STATE_SQER       = 0x4,
2165         MLX5_QPC_STATE_ERR        = 0x6,
2166         MLX5_QPC_STATE_SQD        = 0x7,
2167         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2168 };
2169
2170 enum {
2171         MLX5_QPC_ST_RC            = 0x0,
2172         MLX5_QPC_ST_UC            = 0x1,
2173         MLX5_QPC_ST_UD            = 0x2,
2174         MLX5_QPC_ST_XRC           = 0x3,
2175         MLX5_QPC_ST_DCI           = 0x5,
2176         MLX5_QPC_ST_QP0           = 0x7,
2177         MLX5_QPC_ST_QP1           = 0x8,
2178         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2179         MLX5_QPC_ST_REG_UMR       = 0xc,
2180 };
2181
2182 enum {
2183         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2184         MLX5_QPC_PM_STATE_REARM     = 0x1,
2185         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2186         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2187 };
2188
2189 enum {
2190         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2191 };
2192
2193 enum {
2194         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2195         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2196 };
2197
2198 enum {
2199         MLX5_QPC_MTU_256_BYTES        = 0x1,
2200         MLX5_QPC_MTU_512_BYTES        = 0x2,
2201         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2202         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2203         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2204         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2205 };
2206
2207 enum {
2208         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2209         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2210         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2211         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2212         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2213         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2214         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2215         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2216 };
2217
2218 enum {
2219         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2220         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2221         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2222 };
2223
2224 enum {
2225         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2226         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2227         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2228 };
2229
2230 struct mlx5_ifc_qpc_bits {
2231         u8         state[0x4];
2232         u8         lag_tx_port_affinity[0x4];
2233         u8         st[0x8];
2234         u8         reserved_at_10[0x3];
2235         u8         pm_state[0x2];
2236         u8         reserved_at_15[0x3];
2237         u8         offload_type[0x4];
2238         u8         end_padding_mode[0x2];
2239         u8         reserved_at_1e[0x2];
2240
2241         u8         wq_signature[0x1];
2242         u8         block_lb_mc[0x1];
2243         u8         atomic_like_write_en[0x1];
2244         u8         latency_sensitive[0x1];
2245         u8         reserved_at_24[0x1];
2246         u8         drain_sigerr[0x1];
2247         u8         reserved_at_26[0x2];
2248         u8         pd[0x18];
2249
2250         u8         mtu[0x3];
2251         u8         log_msg_max[0x5];
2252         u8         reserved_at_48[0x1];
2253         u8         log_rq_size[0x4];
2254         u8         log_rq_stride[0x3];
2255         u8         no_sq[0x1];
2256         u8         log_sq_size[0x4];
2257         u8         reserved_at_55[0x6];
2258         u8         rlky[0x1];
2259         u8         ulp_stateless_offload_mode[0x4];
2260
2261         u8         counter_set_id[0x8];
2262         u8         uar_page[0x18];
2263
2264         u8         reserved_at_80[0x8];
2265         u8         user_index[0x18];
2266
2267         u8         reserved_at_a0[0x3];
2268         u8         log_page_size[0x5];
2269         u8         remote_qpn[0x18];
2270
2271         struct mlx5_ifc_ads_bits primary_address_path;
2272
2273         struct mlx5_ifc_ads_bits secondary_address_path;
2274
2275         u8         log_ack_req_freq[0x4];
2276         u8         reserved_at_384[0x4];
2277         u8         log_sra_max[0x3];
2278         u8         reserved_at_38b[0x2];
2279         u8         retry_count[0x3];
2280         u8         rnr_retry[0x3];
2281         u8         reserved_at_393[0x1];
2282         u8         fre[0x1];
2283         u8         cur_rnr_retry[0x3];
2284         u8         cur_retry_count[0x3];
2285         u8         reserved_at_39b[0x5];
2286
2287         u8         reserved_at_3a0[0x20];
2288
2289         u8         reserved_at_3c0[0x8];
2290         u8         next_send_psn[0x18];
2291
2292         u8         reserved_at_3e0[0x8];
2293         u8         cqn_snd[0x18];
2294
2295         u8         reserved_at_400[0x8];
2296         u8         deth_sqpn[0x18];
2297
2298         u8         reserved_at_420[0x20];
2299
2300         u8         reserved_at_440[0x8];
2301         u8         last_acked_psn[0x18];
2302
2303         u8         reserved_at_460[0x8];
2304         u8         ssn[0x18];
2305
2306         u8         reserved_at_480[0x8];
2307         u8         log_rra_max[0x3];
2308         u8         reserved_at_48b[0x1];
2309         u8         atomic_mode[0x4];
2310         u8         rre[0x1];
2311         u8         rwe[0x1];
2312         u8         rae[0x1];
2313         u8         reserved_at_493[0x1];
2314         u8         page_offset[0x6];
2315         u8         reserved_at_49a[0x3];
2316         u8         cd_slave_receive[0x1];
2317         u8         cd_slave_send[0x1];
2318         u8         cd_master[0x1];
2319
2320         u8         reserved_at_4a0[0x3];
2321         u8         min_rnr_nak[0x5];
2322         u8         next_rcv_psn[0x18];
2323
2324         u8         reserved_at_4c0[0x8];
2325         u8         xrcd[0x18];
2326
2327         u8         reserved_at_4e0[0x8];
2328         u8         cqn_rcv[0x18];
2329
2330         u8         dbr_addr[0x40];
2331
2332         u8         q_key[0x20];
2333
2334         u8         reserved_at_560[0x5];
2335         u8         rq_type[0x3];
2336         u8         srqn_rmpn_xrqn[0x18];
2337
2338         u8         reserved_at_580[0x8];
2339         u8         rmsn[0x18];
2340
2341         u8         hw_sq_wqebb_counter[0x10];
2342         u8         sw_sq_wqebb_counter[0x10];
2343
2344         u8         hw_rq_counter[0x20];
2345
2346         u8         sw_rq_counter[0x20];
2347
2348         u8         reserved_at_600[0x20];
2349
2350         u8         reserved_at_620[0xf];
2351         u8         cgs[0x1];
2352         u8         cs_req[0x8];
2353         u8         cs_res[0x8];
2354
2355         u8         dc_access_key[0x40];
2356
2357         u8         reserved_at_680[0xc0];
2358 };
2359
2360 struct mlx5_ifc_roce_addr_layout_bits {
2361         u8         source_l3_address[16][0x8];
2362
2363         u8         reserved_at_80[0x3];
2364         u8         vlan_valid[0x1];
2365         u8         vlan_id[0xc];
2366         u8         source_mac_47_32[0x10];
2367
2368         u8         source_mac_31_0[0x20];
2369
2370         u8         reserved_at_c0[0x14];
2371         u8         roce_l3_type[0x4];
2372         u8         roce_version[0x8];
2373
2374         u8         reserved_at_e0[0x20];
2375 };
2376
2377 union mlx5_ifc_hca_cap_union_bits {
2378         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2379         struct mlx5_ifc_odp_cap_bits odp_cap;
2380         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2381         struct mlx5_ifc_roce_cap_bits roce_cap;
2382         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2383         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2384         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2385         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2386         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2387         struct mlx5_ifc_qos_cap_bits qos_cap;
2388         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2389         u8         reserved_at_0[0x8000];
2390 };
2391
2392 enum {
2393         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2394         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2395         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2396         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2397         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2398         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2399         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2400         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2401         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2402         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2403         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2404 };
2405
2406 struct mlx5_ifc_vlan_bits {
2407         u8         ethtype[0x10];
2408         u8         prio[0x3];
2409         u8         cfi[0x1];
2410         u8         vid[0xc];
2411 };
2412
2413 struct mlx5_ifc_flow_context_bits {
2414         struct mlx5_ifc_vlan_bits push_vlan;
2415
2416         u8         group_id[0x20];
2417
2418         u8         reserved_at_40[0x8];
2419         u8         flow_tag[0x18];
2420
2421         u8         reserved_at_60[0x10];
2422         u8         action[0x10];
2423
2424         u8         reserved_at_80[0x8];
2425         u8         destination_list_size[0x18];
2426
2427         u8         reserved_at_a0[0x8];
2428         u8         flow_counter_list_size[0x18];
2429
2430         u8         encap_id[0x20];
2431
2432         u8         modify_header_id[0x20];
2433
2434         struct mlx5_ifc_vlan_bits push_vlan_2;
2435
2436         u8         reserved_at_120[0xe0];
2437
2438         struct mlx5_ifc_fte_match_param_bits match_value;
2439
2440         u8         reserved_at_1200[0x600];
2441
2442         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2443 };
2444
2445 enum {
2446         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2447         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2448 };
2449
2450 struct mlx5_ifc_xrc_srqc_bits {
2451         u8         state[0x4];
2452         u8         log_xrc_srq_size[0x4];
2453         u8         reserved_at_8[0x18];
2454
2455         u8         wq_signature[0x1];
2456         u8         cont_srq[0x1];
2457         u8         reserved_at_22[0x1];
2458         u8         rlky[0x1];
2459         u8         basic_cyclic_rcv_wqe[0x1];
2460         u8         log_rq_stride[0x3];
2461         u8         xrcd[0x18];
2462
2463         u8         page_offset[0x6];
2464         u8         reserved_at_46[0x2];
2465         u8         cqn[0x18];
2466
2467         u8         reserved_at_60[0x20];
2468
2469         u8         user_index_equal_xrc_srqn[0x1];
2470         u8         reserved_at_81[0x1];
2471         u8         log_page_size[0x6];
2472         u8         user_index[0x18];
2473
2474         u8         reserved_at_a0[0x20];
2475
2476         u8         reserved_at_c0[0x8];
2477         u8         pd[0x18];
2478
2479         u8         lwm[0x10];
2480         u8         wqe_cnt[0x10];
2481
2482         u8         reserved_at_100[0x40];
2483
2484         u8         db_record_addr_h[0x20];
2485
2486         u8         db_record_addr_l[0x1e];
2487         u8         reserved_at_17e[0x2];
2488
2489         u8         reserved_at_180[0x80];
2490 };
2491
2492 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2493         u8         counter_error_queues[0x20];
2494
2495         u8         total_error_queues[0x20];
2496
2497         u8         send_queue_priority_update_flow[0x20];
2498
2499         u8         reserved_at_60[0x20];
2500
2501         u8         nic_receive_steering_discard[0x40];
2502
2503         u8         receive_discard_vport_down[0x40];
2504
2505         u8         transmit_discard_vport_down[0x40];
2506
2507         u8         reserved_at_140[0xec0];
2508 };
2509
2510 struct mlx5_ifc_traffic_counter_bits {
2511         u8         packets[0x40];
2512
2513         u8         octets[0x40];
2514 };
2515
2516 struct mlx5_ifc_tisc_bits {
2517         u8         strict_lag_tx_port_affinity[0x1];
2518         u8         reserved_at_1[0x3];
2519         u8         lag_tx_port_affinity[0x04];
2520
2521         u8         reserved_at_8[0x4];
2522         u8         prio[0x4];
2523         u8         reserved_at_10[0x10];
2524
2525         u8         reserved_at_20[0x100];
2526
2527         u8         reserved_at_120[0x8];
2528         u8         transport_domain[0x18];
2529
2530         u8         reserved_at_140[0x8];
2531         u8         underlay_qpn[0x18];
2532         u8         reserved_at_160[0x3a0];
2533 };
2534
2535 enum {
2536         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2537         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2538 };
2539
2540 enum {
2541         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2542         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2543 };
2544
2545 enum {
2546         MLX5_RX_HASH_FN_NONE           = 0x0,
2547         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2548         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2549 };
2550
2551 enum {
2552         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2553         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2554 };
2555
2556 struct mlx5_ifc_tirc_bits {
2557         u8         reserved_at_0[0x20];
2558
2559         u8         disp_type[0x4];
2560         u8         reserved_at_24[0x1c];
2561
2562         u8         reserved_at_40[0x40];
2563
2564         u8         reserved_at_80[0x4];
2565         u8         lro_timeout_period_usecs[0x10];
2566         u8         lro_enable_mask[0x4];
2567         u8         lro_max_ip_payload_size[0x8];
2568
2569         u8         reserved_at_a0[0x40];
2570
2571         u8         reserved_at_e0[0x8];
2572         u8         inline_rqn[0x18];
2573
2574         u8         rx_hash_symmetric[0x1];
2575         u8         reserved_at_101[0x1];
2576         u8         tunneled_offload_en[0x1];
2577         u8         reserved_at_103[0x5];
2578         u8         indirect_table[0x18];
2579
2580         u8         rx_hash_fn[0x4];
2581         u8         reserved_at_124[0x2];
2582         u8         self_lb_block[0x2];
2583         u8         transport_domain[0x18];
2584
2585         u8         rx_hash_toeplitz_key[10][0x20];
2586
2587         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2588
2589         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2590
2591         u8         reserved_at_2c0[0x4c0];
2592 };
2593
2594 enum {
2595         MLX5_SRQC_STATE_GOOD   = 0x0,
2596         MLX5_SRQC_STATE_ERROR  = 0x1,
2597 };
2598
2599 struct mlx5_ifc_srqc_bits {
2600         u8         state[0x4];
2601         u8         log_srq_size[0x4];
2602         u8         reserved_at_8[0x18];
2603
2604         u8         wq_signature[0x1];
2605         u8         cont_srq[0x1];
2606         u8         reserved_at_22[0x1];
2607         u8         rlky[0x1];
2608         u8         reserved_at_24[0x1];
2609         u8         log_rq_stride[0x3];
2610         u8         xrcd[0x18];
2611
2612         u8         page_offset[0x6];
2613         u8         reserved_at_46[0x2];
2614         u8         cqn[0x18];
2615
2616         u8         reserved_at_60[0x20];
2617
2618         u8         reserved_at_80[0x2];
2619         u8         log_page_size[0x6];
2620         u8         reserved_at_88[0x18];
2621
2622         u8         reserved_at_a0[0x20];
2623
2624         u8         reserved_at_c0[0x8];
2625         u8         pd[0x18];
2626
2627         u8         lwm[0x10];
2628         u8         wqe_cnt[0x10];
2629
2630         u8         reserved_at_100[0x40];
2631
2632         u8         dbr_addr[0x40];
2633
2634         u8         reserved_at_180[0x80];
2635 };
2636
2637 enum {
2638         MLX5_SQC_STATE_RST  = 0x0,
2639         MLX5_SQC_STATE_RDY  = 0x1,
2640         MLX5_SQC_STATE_ERR  = 0x3,
2641 };
2642
2643 struct mlx5_ifc_sqc_bits {
2644         u8         rlky[0x1];
2645         u8         cd_master[0x1];
2646         u8         fre[0x1];
2647         u8         flush_in_error_en[0x1];
2648         u8         allow_multi_pkt_send_wqe[0x1];
2649         u8         min_wqe_inline_mode[0x3];
2650         u8         state[0x4];
2651         u8         reg_umr[0x1];
2652         u8         allow_swp[0x1];
2653         u8         hairpin[0x1];
2654         u8         reserved_at_f[0x11];
2655
2656         u8         reserved_at_20[0x8];
2657         u8         user_index[0x18];
2658
2659         u8         reserved_at_40[0x8];
2660         u8         cqn[0x18];
2661
2662         u8         reserved_at_60[0x8];
2663         u8         hairpin_peer_rq[0x18];
2664
2665         u8         reserved_at_80[0x10];
2666         u8         hairpin_peer_vhca[0x10];
2667
2668         u8         reserved_at_a0[0x50];
2669
2670         u8         packet_pacing_rate_limit_index[0x10];
2671         u8         tis_lst_sz[0x10];
2672         u8         reserved_at_110[0x10];
2673
2674         u8         reserved_at_120[0x40];
2675
2676         u8         reserved_at_160[0x8];
2677         u8         tis_num_0[0x18];
2678
2679         struct mlx5_ifc_wq_bits wq;
2680 };
2681
2682 enum {
2683         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2684         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2685         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2686         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2687 };
2688
2689 struct mlx5_ifc_scheduling_context_bits {
2690         u8         element_type[0x8];
2691         u8         reserved_at_8[0x18];
2692
2693         u8         element_attributes[0x20];
2694
2695         u8         parent_element_id[0x20];
2696
2697         u8         reserved_at_60[0x40];
2698
2699         u8         bw_share[0x20];
2700
2701         u8         max_average_bw[0x20];
2702
2703         u8         reserved_at_e0[0x120];
2704 };
2705
2706 struct mlx5_ifc_rqtc_bits {
2707         u8         reserved_at_0[0xa0];
2708
2709         u8         reserved_at_a0[0x10];
2710         u8         rqt_max_size[0x10];
2711
2712         u8         reserved_at_c0[0x10];
2713         u8         rqt_actual_size[0x10];
2714
2715         u8         reserved_at_e0[0x6a0];
2716
2717         struct mlx5_ifc_rq_num_bits rq_num[0];
2718 };
2719
2720 enum {
2721         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2722         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2723 };
2724
2725 enum {
2726         MLX5_RQC_STATE_RST  = 0x0,
2727         MLX5_RQC_STATE_RDY  = 0x1,
2728         MLX5_RQC_STATE_ERR  = 0x3,
2729 };
2730
2731 struct mlx5_ifc_rqc_bits {
2732         u8         rlky[0x1];
2733         u8         delay_drop_en[0x1];
2734         u8         scatter_fcs[0x1];
2735         u8         vsd[0x1];
2736         u8         mem_rq_type[0x4];
2737         u8         state[0x4];
2738         u8         reserved_at_c[0x1];
2739         u8         flush_in_error_en[0x1];
2740         u8         hairpin[0x1];
2741         u8         reserved_at_f[0x11];
2742
2743         u8         reserved_at_20[0x8];
2744         u8         user_index[0x18];
2745
2746         u8         reserved_at_40[0x8];
2747         u8         cqn[0x18];
2748
2749         u8         counter_set_id[0x8];
2750         u8         reserved_at_68[0x18];
2751
2752         u8         reserved_at_80[0x8];
2753         u8         rmpn[0x18];
2754
2755         u8         reserved_at_a0[0x8];
2756         u8         hairpin_peer_sq[0x18];
2757
2758         u8         reserved_at_c0[0x10];
2759         u8         hairpin_peer_vhca[0x10];
2760
2761         u8         reserved_at_e0[0xa0];
2762
2763         struct mlx5_ifc_wq_bits wq;
2764 };
2765
2766 enum {
2767         MLX5_RMPC_STATE_RDY  = 0x1,
2768         MLX5_RMPC_STATE_ERR  = 0x3,
2769 };
2770
2771 struct mlx5_ifc_rmpc_bits {
2772         u8         reserved_at_0[0x8];
2773         u8         state[0x4];
2774         u8         reserved_at_c[0x14];
2775
2776         u8         basic_cyclic_rcv_wqe[0x1];
2777         u8         reserved_at_21[0x1f];
2778
2779         u8         reserved_at_40[0x140];
2780
2781         struct mlx5_ifc_wq_bits wq;
2782 };
2783
2784 struct mlx5_ifc_nic_vport_context_bits {
2785         u8         reserved_at_0[0x5];
2786         u8         min_wqe_inline_mode[0x3];
2787         u8         reserved_at_8[0x15];
2788         u8         disable_mc_local_lb[0x1];
2789         u8         disable_uc_local_lb[0x1];
2790         u8         roce_en[0x1];
2791
2792         u8         arm_change_event[0x1];
2793         u8         reserved_at_21[0x1a];
2794         u8         event_on_mtu[0x1];
2795         u8         event_on_promisc_change[0x1];
2796         u8         event_on_vlan_change[0x1];
2797         u8         event_on_mc_address_change[0x1];
2798         u8         event_on_uc_address_change[0x1];
2799
2800         u8         reserved_at_40[0xc];
2801
2802         u8         affiliation_criteria[0x4];
2803         u8         affiliated_vhca_id[0x10];
2804
2805         u8         reserved_at_60[0xd0];
2806
2807         u8         mtu[0x10];
2808
2809         u8         system_image_guid[0x40];
2810         u8         port_guid[0x40];
2811         u8         node_guid[0x40];
2812
2813         u8         reserved_at_200[0x140];
2814         u8         qkey_violation_counter[0x10];
2815         u8         reserved_at_350[0x430];
2816
2817         u8         promisc_uc[0x1];
2818         u8         promisc_mc[0x1];
2819         u8         promisc_all[0x1];
2820         u8         reserved_at_783[0x2];
2821         u8         allowed_list_type[0x3];
2822         u8         reserved_at_788[0xc];
2823         u8         allowed_list_size[0xc];
2824
2825         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2826
2827         u8         reserved_at_7e0[0x20];
2828
2829         u8         current_uc_mac_address[0][0x40];
2830 };
2831
2832 enum {
2833         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2834         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2835         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2836         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2837         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2838 };
2839
2840 struct mlx5_ifc_mkc_bits {
2841         u8         reserved_at_0[0x1];
2842         u8         free[0x1];
2843         u8         reserved_at_2[0x1];
2844         u8         access_mode_4_2[0x3];
2845         u8         reserved_at_6[0x7];
2846         u8         relaxed_ordering_write[0x1];
2847         u8         reserved_at_e[0x1];
2848         u8         small_fence_on_rdma_read_response[0x1];
2849         u8         umr_en[0x1];
2850         u8         a[0x1];
2851         u8         rw[0x1];
2852         u8         rr[0x1];
2853         u8         lw[0x1];
2854         u8         lr[0x1];
2855         u8         access_mode_1_0[0x2];
2856         u8         reserved_at_18[0x8];
2857
2858         u8         qpn[0x18];
2859         u8         mkey_7_0[0x8];
2860
2861         u8         reserved_at_40[0x20];
2862
2863         u8         length64[0x1];
2864         u8         bsf_en[0x1];
2865         u8         sync_umr[0x1];
2866         u8         reserved_at_63[0x2];
2867         u8         expected_sigerr_count[0x1];
2868         u8         reserved_at_66[0x1];
2869         u8         en_rinval[0x1];
2870         u8         pd[0x18];
2871
2872         u8         start_addr[0x40];
2873
2874         u8         len[0x40];
2875
2876         u8         bsf_octword_size[0x20];
2877
2878         u8         reserved_at_120[0x80];
2879
2880         u8         translations_octword_size[0x20];
2881
2882         u8         reserved_at_1c0[0x1b];
2883         u8         log_page_size[0x5];
2884
2885         u8         reserved_at_1e0[0x20];
2886 };
2887
2888 struct mlx5_ifc_pkey_bits {
2889         u8         reserved_at_0[0x10];
2890         u8         pkey[0x10];
2891 };
2892
2893 struct mlx5_ifc_array128_auto_bits {
2894         u8         array128_auto[16][0x8];
2895 };
2896
2897 struct mlx5_ifc_hca_vport_context_bits {
2898         u8         field_select[0x20];
2899
2900         u8         reserved_at_20[0xe0];
2901
2902         u8         sm_virt_aware[0x1];
2903         u8         has_smi[0x1];
2904         u8         has_raw[0x1];
2905         u8         grh_required[0x1];
2906         u8         reserved_at_104[0xc];
2907         u8         port_physical_state[0x4];
2908         u8         vport_state_policy[0x4];
2909         u8         port_state[0x4];
2910         u8         vport_state[0x4];
2911
2912         u8         reserved_at_120[0x20];
2913
2914         u8         system_image_guid[0x40];
2915
2916         u8         port_guid[0x40];
2917
2918         u8         node_guid[0x40];
2919
2920         u8         cap_mask1[0x20];
2921
2922         u8         cap_mask1_field_select[0x20];
2923
2924         u8         cap_mask2[0x20];
2925
2926         u8         cap_mask2_field_select[0x20];
2927
2928         u8         reserved_at_280[0x80];
2929
2930         u8         lid[0x10];
2931         u8         reserved_at_310[0x4];
2932         u8         init_type_reply[0x4];
2933         u8         lmc[0x3];
2934         u8         subnet_timeout[0x5];
2935
2936         u8         sm_lid[0x10];
2937         u8         sm_sl[0x4];
2938         u8         reserved_at_334[0xc];
2939
2940         u8         qkey_violation_counter[0x10];
2941         u8         pkey_violation_counter[0x10];
2942
2943         u8         reserved_at_360[0xca0];
2944 };
2945
2946 struct mlx5_ifc_esw_vport_context_bits {
2947         u8         reserved_at_0[0x3];
2948         u8         vport_svlan_strip[0x1];
2949         u8         vport_cvlan_strip[0x1];
2950         u8         vport_svlan_insert[0x1];
2951         u8         vport_cvlan_insert[0x2];
2952         u8         reserved_at_8[0x18];
2953
2954         u8         reserved_at_20[0x20];
2955
2956         u8         svlan_cfi[0x1];
2957         u8         svlan_pcp[0x3];
2958         u8         svlan_id[0xc];
2959         u8         cvlan_cfi[0x1];
2960         u8         cvlan_pcp[0x3];
2961         u8         cvlan_id[0xc];
2962
2963         u8         reserved_at_60[0x7a0];
2964 };
2965
2966 enum {
2967         MLX5_EQC_STATUS_OK                = 0x0,
2968         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2969 };
2970
2971 enum {
2972         MLX5_EQC_ST_ARMED  = 0x9,
2973         MLX5_EQC_ST_FIRED  = 0xa,
2974 };
2975
2976 struct mlx5_ifc_eqc_bits {
2977         u8         status[0x4];
2978         u8         reserved_at_4[0x9];
2979         u8         ec[0x1];
2980         u8         oi[0x1];
2981         u8         reserved_at_f[0x5];
2982         u8         st[0x4];
2983         u8         reserved_at_18[0x8];
2984
2985         u8         reserved_at_20[0x20];
2986
2987         u8         reserved_at_40[0x14];
2988         u8         page_offset[0x6];
2989         u8         reserved_at_5a[0x6];
2990
2991         u8         reserved_at_60[0x3];
2992         u8         log_eq_size[0x5];
2993         u8         uar_page[0x18];
2994
2995         u8         reserved_at_80[0x20];
2996
2997         u8         reserved_at_a0[0x18];
2998         u8         intr[0x8];
2999
3000         u8         reserved_at_c0[0x3];
3001         u8         log_page_size[0x5];
3002         u8         reserved_at_c8[0x18];
3003
3004         u8         reserved_at_e0[0x60];
3005
3006         u8         reserved_at_140[0x8];
3007         u8         consumer_counter[0x18];
3008
3009         u8         reserved_at_160[0x8];
3010         u8         producer_counter[0x18];
3011
3012         u8         reserved_at_180[0x80];
3013 };
3014
3015 enum {
3016         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3017         MLX5_DCTC_STATE_DRAINING  = 0x1,
3018         MLX5_DCTC_STATE_DRAINED   = 0x2,
3019 };
3020
3021 enum {
3022         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3023         MLX5_DCTC_CS_RES_NA         = 0x1,
3024         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3025 };
3026
3027 enum {
3028         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3029         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3030         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3031         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3032         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3033 };
3034
3035 struct mlx5_ifc_dctc_bits {
3036         u8         reserved_at_0[0x4];
3037         u8         state[0x4];
3038         u8         reserved_at_8[0x18];
3039
3040         u8         reserved_at_20[0x8];
3041         u8         user_index[0x18];
3042
3043         u8         reserved_at_40[0x8];
3044         u8         cqn[0x18];
3045
3046         u8         counter_set_id[0x8];
3047         u8         atomic_mode[0x4];
3048         u8         rre[0x1];
3049         u8         rwe[0x1];
3050         u8         rae[0x1];
3051         u8         atomic_like_write_en[0x1];
3052         u8         latency_sensitive[0x1];
3053         u8         rlky[0x1];
3054         u8         free_ar[0x1];
3055         u8         reserved_at_73[0xd];
3056
3057         u8         reserved_at_80[0x8];
3058         u8         cs_res[0x8];
3059         u8         reserved_at_90[0x3];
3060         u8         min_rnr_nak[0x5];
3061         u8         reserved_at_98[0x8];
3062
3063         u8         reserved_at_a0[0x8];
3064         u8         srqn_xrqn[0x18];
3065
3066         u8         reserved_at_c0[0x8];
3067         u8         pd[0x18];
3068
3069         u8         tclass[0x8];
3070         u8         reserved_at_e8[0x4];
3071         u8         flow_label[0x14];
3072
3073         u8         dc_access_key[0x40];
3074
3075         u8         reserved_at_140[0x5];
3076         u8         mtu[0x3];
3077         u8         port[0x8];
3078         u8         pkey_index[0x10];
3079
3080         u8         reserved_at_160[0x8];
3081         u8         my_addr_index[0x8];
3082         u8         reserved_at_170[0x8];
3083         u8         hop_limit[0x8];
3084
3085         u8         dc_access_key_violation_count[0x20];
3086
3087         u8         reserved_at_1a0[0x14];
3088         u8         dei_cfi[0x1];
3089         u8         eth_prio[0x3];
3090         u8         ecn[0x2];
3091         u8         dscp[0x6];
3092
3093         u8         reserved_at_1c0[0x40];
3094 };
3095
3096 enum {
3097         MLX5_CQC_STATUS_OK             = 0x0,
3098         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3099         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3100 };
3101
3102 enum {
3103         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3104         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3105 };
3106
3107 enum {
3108         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3109         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3110         MLX5_CQC_ST_FIRED                                 = 0xa,
3111 };
3112
3113 enum {
3114         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3115         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3116         MLX5_CQ_PERIOD_NUM_MODES
3117 };
3118
3119 struct mlx5_ifc_cqc_bits {
3120         u8         status[0x4];
3121         u8         reserved_at_4[0x4];
3122         u8         cqe_sz[0x3];
3123         u8         cc[0x1];
3124         u8         reserved_at_c[0x1];
3125         u8         scqe_break_moderation_en[0x1];
3126         u8         oi[0x1];
3127         u8         cq_period_mode[0x2];
3128         u8         cqe_comp_en[0x1];
3129         u8         mini_cqe_res_format[0x2];
3130         u8         st[0x4];
3131         u8         reserved_at_18[0x8];
3132
3133         u8         reserved_at_20[0x20];
3134
3135         u8         reserved_at_40[0x14];
3136         u8         page_offset[0x6];
3137         u8         reserved_at_5a[0x6];
3138
3139         u8         reserved_at_60[0x3];
3140         u8         log_cq_size[0x5];
3141         u8         uar_page[0x18];
3142
3143         u8         reserved_at_80[0x4];
3144         u8         cq_period[0xc];
3145         u8         cq_max_count[0x10];
3146
3147         u8         reserved_at_a0[0x18];
3148         u8         c_eqn[0x8];
3149
3150         u8         reserved_at_c0[0x3];
3151         u8         log_page_size[0x5];
3152         u8         reserved_at_c8[0x18];
3153
3154         u8         reserved_at_e0[0x20];
3155
3156         u8         reserved_at_100[0x8];
3157         u8         last_notified_index[0x18];
3158
3159         u8         reserved_at_120[0x8];
3160         u8         last_solicit_index[0x18];
3161
3162         u8         reserved_at_140[0x8];
3163         u8         consumer_counter[0x18];
3164
3165         u8         reserved_at_160[0x8];
3166         u8         producer_counter[0x18];
3167
3168         u8         reserved_at_180[0x40];
3169
3170         u8         dbr_addr[0x40];
3171 };
3172
3173 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3174         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3175         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3176         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3177         u8         reserved_at_0[0x800];
3178 };
3179
3180 struct mlx5_ifc_query_adapter_param_block_bits {
3181         u8         reserved_at_0[0xc0];
3182
3183         u8         reserved_at_c0[0x8];
3184         u8         ieee_vendor_id[0x18];
3185
3186         u8         reserved_at_e0[0x10];
3187         u8         vsd_vendor_id[0x10];
3188
3189         u8         vsd[208][0x8];
3190
3191         u8         vsd_contd_psid[16][0x8];
3192 };
3193
3194 enum {
3195         MLX5_XRQC_STATE_GOOD   = 0x0,
3196         MLX5_XRQC_STATE_ERROR  = 0x1,
3197 };
3198
3199 enum {
3200         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3201         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3202 };
3203
3204 enum {
3205         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3206 };
3207
3208 struct mlx5_ifc_tag_matching_topology_context_bits {
3209         u8         log_matching_list_sz[0x4];
3210         u8         reserved_at_4[0xc];
3211         u8         append_next_index[0x10];
3212
3213         u8         sw_phase_cnt[0x10];
3214         u8         hw_phase_cnt[0x10];
3215
3216         u8         reserved_at_40[0x40];
3217 };
3218
3219 struct mlx5_ifc_xrqc_bits {
3220         u8         state[0x4];
3221         u8         rlkey[0x1];
3222         u8         reserved_at_5[0xf];
3223         u8         topology[0x4];
3224         u8         reserved_at_18[0x4];
3225         u8         offload[0x4];
3226
3227         u8         reserved_at_20[0x8];
3228         u8         user_index[0x18];
3229
3230         u8         reserved_at_40[0x8];
3231         u8         cqn[0x18];
3232
3233         u8         reserved_at_60[0xa0];
3234
3235         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3236
3237         u8         reserved_at_180[0x280];
3238
3239         struct mlx5_ifc_wq_bits wq;
3240 };
3241
3242 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3243         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3244         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3245         u8         reserved_at_0[0x20];
3246 };
3247
3248 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3249         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3250         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3251         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3252         u8         reserved_at_0[0x20];
3253 };
3254
3255 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3256         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3257         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3258         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3259         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3260         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3261         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3262         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3263         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3264         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3265         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3266         u8         reserved_at_0[0x7c0];
3267 };
3268
3269 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3270         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3271         u8         reserved_at_0[0x7c0];
3272 };
3273
3274 union mlx5_ifc_event_auto_bits {
3275         struct mlx5_ifc_comp_event_bits comp_event;
3276         struct mlx5_ifc_dct_events_bits dct_events;
3277         struct mlx5_ifc_qp_events_bits qp_events;
3278         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3279         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3280         struct mlx5_ifc_cq_error_bits cq_error;
3281         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3282         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3283         struct mlx5_ifc_gpio_event_bits gpio_event;
3284         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3285         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3286         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3287         u8         reserved_at_0[0xe0];
3288 };
3289
3290 struct mlx5_ifc_health_buffer_bits {
3291         u8         reserved_at_0[0x100];
3292
3293         u8         assert_existptr[0x20];
3294
3295         u8         assert_callra[0x20];
3296
3297         u8         reserved_at_140[0x40];
3298
3299         u8         fw_version[0x20];
3300
3301         u8         hw_id[0x20];
3302
3303         u8         reserved_at_1c0[0x20];
3304
3305         u8         irisc_index[0x8];
3306         u8         synd[0x8];
3307         u8         ext_synd[0x10];
3308 };
3309
3310 struct mlx5_ifc_register_loopback_control_bits {
3311         u8         no_lb[0x1];
3312         u8         reserved_at_1[0x7];
3313         u8         port[0x8];
3314         u8         reserved_at_10[0x10];
3315
3316         u8         reserved_at_20[0x60];
3317 };
3318
3319 struct mlx5_ifc_vport_tc_element_bits {
3320         u8         traffic_class[0x4];
3321         u8         reserved_at_4[0xc];
3322         u8         vport_number[0x10];
3323 };
3324
3325 struct mlx5_ifc_vport_element_bits {
3326         u8         reserved_at_0[0x10];
3327         u8         vport_number[0x10];
3328 };
3329
3330 enum {
3331         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3332         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3333         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3334 };
3335
3336 struct mlx5_ifc_tsar_element_bits {
3337         u8         reserved_at_0[0x8];
3338         u8         tsar_type[0x8];
3339         u8         reserved_at_10[0x10];
3340 };
3341
3342 enum {
3343         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3344         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3345 };
3346
3347 struct mlx5_ifc_teardown_hca_out_bits {
3348         u8         status[0x8];
3349         u8         reserved_at_8[0x18];
3350
3351         u8         syndrome[0x20];
3352
3353         u8         reserved_at_40[0x3f];
3354
3355         u8         force_state[0x1];
3356 };
3357
3358 enum {
3359         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3360         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3361 };
3362
3363 struct mlx5_ifc_teardown_hca_in_bits {
3364         u8         opcode[0x10];
3365         u8         reserved_at_10[0x10];
3366
3367         u8         reserved_at_20[0x10];
3368         u8         op_mod[0x10];
3369
3370         u8         reserved_at_40[0x10];
3371         u8         profile[0x10];
3372
3373         u8         reserved_at_60[0x20];
3374 };
3375
3376 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3377         u8         status[0x8];
3378         u8         reserved_at_8[0x18];
3379
3380         u8         syndrome[0x20];
3381
3382         u8         reserved_at_40[0x40];
3383 };
3384
3385 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3386         u8         opcode[0x10];
3387         u8         reserved_at_10[0x10];
3388
3389         u8         reserved_at_20[0x10];
3390         u8         op_mod[0x10];
3391
3392         u8         reserved_at_40[0x8];
3393         u8         qpn[0x18];
3394
3395         u8         reserved_at_60[0x20];
3396
3397         u8         opt_param_mask[0x20];
3398
3399         u8         reserved_at_a0[0x20];
3400
3401         struct mlx5_ifc_qpc_bits qpc;
3402
3403         u8         reserved_at_800[0x80];
3404 };
3405
3406 struct mlx5_ifc_sqd2rts_qp_out_bits {
3407         u8         status[0x8];
3408         u8         reserved_at_8[0x18];
3409
3410         u8         syndrome[0x20];
3411
3412         u8         reserved_at_40[0x40];
3413 };
3414
3415 struct mlx5_ifc_sqd2rts_qp_in_bits {
3416         u8         opcode[0x10];
3417         u8         reserved_at_10[0x10];
3418
3419         u8         reserved_at_20[0x10];
3420         u8         op_mod[0x10];
3421
3422         u8         reserved_at_40[0x8];
3423         u8         qpn[0x18];
3424
3425         u8         reserved_at_60[0x20];
3426
3427         u8         opt_param_mask[0x20];
3428
3429         u8         reserved_at_a0[0x20];
3430
3431         struct mlx5_ifc_qpc_bits qpc;
3432
3433         u8         reserved_at_800[0x80];
3434 };
3435
3436 struct mlx5_ifc_set_roce_address_out_bits {
3437         u8         status[0x8];
3438         u8         reserved_at_8[0x18];
3439
3440         u8         syndrome[0x20];
3441
3442         u8         reserved_at_40[0x40];
3443 };
3444
3445 struct mlx5_ifc_set_roce_address_in_bits {
3446         u8         opcode[0x10];
3447         u8         reserved_at_10[0x10];
3448
3449         u8         reserved_at_20[0x10];
3450         u8         op_mod[0x10];
3451
3452         u8         roce_address_index[0x10];
3453         u8         reserved_at_50[0xc];
3454         u8         vhca_port_num[0x4];
3455
3456         u8         reserved_at_60[0x20];
3457
3458         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3459 };
3460
3461 struct mlx5_ifc_set_mad_demux_out_bits {
3462         u8         status[0x8];
3463         u8         reserved_at_8[0x18];
3464
3465         u8         syndrome[0x20];
3466
3467         u8         reserved_at_40[0x40];
3468 };
3469
3470 enum {
3471         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3472         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3473 };
3474
3475 struct mlx5_ifc_set_mad_demux_in_bits {
3476         u8         opcode[0x10];
3477         u8         reserved_at_10[0x10];
3478
3479         u8         reserved_at_20[0x10];
3480         u8         op_mod[0x10];
3481
3482         u8         reserved_at_40[0x20];
3483
3484         u8         reserved_at_60[0x6];
3485         u8         demux_mode[0x2];
3486         u8         reserved_at_68[0x18];
3487 };
3488
3489 struct mlx5_ifc_set_l2_table_entry_out_bits {
3490         u8         status[0x8];
3491         u8         reserved_at_8[0x18];
3492
3493         u8         syndrome[0x20];
3494
3495         u8         reserved_at_40[0x40];
3496 };
3497
3498 struct mlx5_ifc_set_l2_table_entry_in_bits {
3499         u8         opcode[0x10];
3500         u8         reserved_at_10[0x10];
3501
3502         u8         reserved_at_20[0x10];
3503         u8         op_mod[0x10];
3504
3505         u8         reserved_at_40[0x60];
3506
3507         u8         reserved_at_a0[0x8];
3508         u8         table_index[0x18];
3509
3510         u8         reserved_at_c0[0x20];
3511
3512         u8         reserved_at_e0[0x13];
3513         u8         vlan_valid[0x1];
3514         u8         vlan[0xc];
3515
3516         struct mlx5_ifc_mac_address_layout_bits mac_address;
3517
3518         u8         reserved_at_140[0xc0];
3519 };
3520
3521 struct mlx5_ifc_set_issi_out_bits {
3522         u8         status[0x8];
3523         u8         reserved_at_8[0x18];
3524
3525         u8         syndrome[0x20];
3526
3527         u8         reserved_at_40[0x40];
3528 };
3529
3530 struct mlx5_ifc_set_issi_in_bits {
3531         u8         opcode[0x10];
3532         u8         reserved_at_10[0x10];
3533
3534         u8         reserved_at_20[0x10];
3535         u8         op_mod[0x10];
3536
3537         u8         reserved_at_40[0x10];
3538         u8         current_issi[0x10];
3539
3540         u8         reserved_at_60[0x20];
3541 };
3542
3543 struct mlx5_ifc_set_hca_cap_out_bits {
3544         u8         status[0x8];
3545         u8         reserved_at_8[0x18];
3546
3547         u8         syndrome[0x20];
3548
3549         u8         reserved_at_40[0x40];
3550 };
3551
3552 struct mlx5_ifc_set_hca_cap_in_bits {
3553         u8         opcode[0x10];
3554         u8         reserved_at_10[0x10];
3555
3556         u8         reserved_at_20[0x10];
3557         u8         op_mod[0x10];
3558
3559         u8         reserved_at_40[0x40];
3560
3561         union mlx5_ifc_hca_cap_union_bits capability;
3562 };
3563
3564 enum {
3565         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3566         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3567         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3568         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3569 };
3570
3571 struct mlx5_ifc_set_fte_out_bits {
3572         u8         status[0x8];
3573         u8         reserved_at_8[0x18];
3574
3575         u8         syndrome[0x20];
3576
3577         u8         reserved_at_40[0x40];
3578 };
3579
3580 struct mlx5_ifc_set_fte_in_bits {
3581         u8         opcode[0x10];
3582         u8         reserved_at_10[0x10];
3583
3584         u8         reserved_at_20[0x10];
3585         u8         op_mod[0x10];
3586
3587         u8         other_vport[0x1];
3588         u8         reserved_at_41[0xf];
3589         u8         vport_number[0x10];
3590
3591         u8         reserved_at_60[0x20];
3592
3593         u8         table_type[0x8];
3594         u8         reserved_at_88[0x18];
3595
3596         u8         reserved_at_a0[0x8];
3597         u8         table_id[0x18];
3598
3599         u8         reserved_at_c0[0x18];
3600         u8         modify_enable_mask[0x8];
3601
3602         u8         reserved_at_e0[0x20];
3603
3604         u8         flow_index[0x20];
3605
3606         u8         reserved_at_120[0xe0];
3607
3608         struct mlx5_ifc_flow_context_bits flow_context;
3609 };
3610
3611 struct mlx5_ifc_rts2rts_qp_out_bits {
3612         u8         status[0x8];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         syndrome[0x20];
3616
3617         u8         reserved_at_40[0x40];
3618 };
3619
3620 struct mlx5_ifc_rts2rts_qp_in_bits {
3621         u8         opcode[0x10];
3622         u8         reserved_at_10[0x10];
3623
3624         u8         reserved_at_20[0x10];
3625         u8         op_mod[0x10];
3626
3627         u8         reserved_at_40[0x8];
3628         u8         qpn[0x18];
3629
3630         u8         reserved_at_60[0x20];
3631
3632         u8         opt_param_mask[0x20];
3633
3634         u8         reserved_at_a0[0x20];
3635
3636         struct mlx5_ifc_qpc_bits qpc;
3637
3638         u8         reserved_at_800[0x80];
3639 };
3640
3641 struct mlx5_ifc_rtr2rts_qp_out_bits {
3642         u8         status[0x8];
3643         u8         reserved_at_8[0x18];
3644
3645         u8         syndrome[0x20];
3646
3647         u8         reserved_at_40[0x40];
3648 };
3649
3650 struct mlx5_ifc_rtr2rts_qp_in_bits {
3651         u8         opcode[0x10];
3652         u8         reserved_at_10[0x10];
3653
3654         u8         reserved_at_20[0x10];
3655         u8         op_mod[0x10];
3656
3657         u8         reserved_at_40[0x8];
3658         u8         qpn[0x18];
3659
3660         u8         reserved_at_60[0x20];
3661
3662         u8         opt_param_mask[0x20];
3663
3664         u8         reserved_at_a0[0x20];
3665
3666         struct mlx5_ifc_qpc_bits qpc;
3667
3668         u8         reserved_at_800[0x80];
3669 };
3670
3671 struct mlx5_ifc_rst2init_qp_out_bits {
3672         u8         status[0x8];
3673         u8         reserved_at_8[0x18];
3674
3675         u8         syndrome[0x20];
3676
3677         u8         reserved_at_40[0x40];
3678 };
3679
3680 struct mlx5_ifc_rst2init_qp_in_bits {
3681         u8         opcode[0x10];
3682         u8         reserved_at_10[0x10];
3683
3684         u8         reserved_at_20[0x10];
3685         u8         op_mod[0x10];
3686
3687         u8         reserved_at_40[0x8];
3688         u8         qpn[0x18];
3689
3690         u8         reserved_at_60[0x20];
3691
3692         u8         opt_param_mask[0x20];
3693
3694         u8         reserved_at_a0[0x20];
3695
3696         struct mlx5_ifc_qpc_bits qpc;
3697
3698         u8         reserved_at_800[0x80];
3699 };
3700
3701 struct mlx5_ifc_query_xrq_out_bits {
3702         u8         status[0x8];
3703         u8         reserved_at_8[0x18];
3704
3705         u8         syndrome[0x20];
3706
3707         u8         reserved_at_40[0x40];
3708
3709         struct mlx5_ifc_xrqc_bits xrq_context;
3710 };
3711
3712 struct mlx5_ifc_query_xrq_in_bits {
3713         u8         opcode[0x10];
3714         u8         reserved_at_10[0x10];
3715
3716         u8         reserved_at_20[0x10];
3717         u8         op_mod[0x10];
3718
3719         u8         reserved_at_40[0x8];
3720         u8         xrqn[0x18];
3721
3722         u8         reserved_at_60[0x20];
3723 };
3724
3725 struct mlx5_ifc_query_xrc_srq_out_bits {
3726         u8         status[0x8];
3727         u8         reserved_at_8[0x18];
3728
3729         u8         syndrome[0x20];
3730
3731         u8         reserved_at_40[0x40];
3732
3733         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3734
3735         u8         reserved_at_280[0x600];
3736
3737         u8         pas[0][0x40];
3738 };
3739
3740 struct mlx5_ifc_query_xrc_srq_in_bits {
3741         u8         opcode[0x10];
3742         u8         reserved_at_10[0x10];
3743
3744         u8         reserved_at_20[0x10];
3745         u8         op_mod[0x10];
3746
3747         u8         reserved_at_40[0x8];
3748         u8         xrc_srqn[0x18];
3749
3750         u8         reserved_at_60[0x20];
3751 };
3752
3753 enum {
3754         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3755         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3756 };
3757
3758 struct mlx5_ifc_query_vport_state_out_bits {
3759         u8         status[0x8];
3760         u8         reserved_at_8[0x18];
3761
3762         u8         syndrome[0x20];
3763
3764         u8         reserved_at_40[0x20];
3765
3766         u8         reserved_at_60[0x18];
3767         u8         admin_state[0x4];
3768         u8         state[0x4];
3769 };
3770
3771 enum {
3772         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
3773         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3774 };
3775
3776 struct mlx5_ifc_query_vport_state_in_bits {
3777         u8         opcode[0x10];
3778         u8         reserved_at_10[0x10];
3779
3780         u8         reserved_at_20[0x10];
3781         u8         op_mod[0x10];
3782
3783         u8         other_vport[0x1];
3784         u8         reserved_at_41[0xf];
3785         u8         vport_number[0x10];
3786
3787         u8         reserved_at_60[0x20];
3788 };
3789
3790 struct mlx5_ifc_query_vnic_env_out_bits {
3791         u8         status[0x8];
3792         u8         reserved_at_8[0x18];
3793
3794         u8         syndrome[0x20];
3795
3796         u8         reserved_at_40[0x40];
3797
3798         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3799 };
3800
3801 enum {
3802         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3803 };
3804
3805 struct mlx5_ifc_query_vnic_env_in_bits {
3806         u8         opcode[0x10];
3807         u8         reserved_at_10[0x10];
3808
3809         u8         reserved_at_20[0x10];
3810         u8         op_mod[0x10];
3811
3812         u8         other_vport[0x1];
3813         u8         reserved_at_41[0xf];
3814         u8         vport_number[0x10];
3815
3816         u8         reserved_at_60[0x20];
3817 };
3818
3819 struct mlx5_ifc_query_vport_counter_out_bits {
3820         u8         status[0x8];
3821         u8         reserved_at_8[0x18];
3822
3823         u8         syndrome[0x20];
3824
3825         u8         reserved_at_40[0x40];
3826
3827         struct mlx5_ifc_traffic_counter_bits received_errors;
3828
3829         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3830
3831         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3832
3833         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3834
3835         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3836
3837         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3838
3839         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3840
3841         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3842
3843         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3844
3845         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3846
3847         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3848
3849         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3850
3851         u8         reserved_at_680[0xa00];
3852 };
3853
3854 enum {
3855         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3856 };
3857
3858 struct mlx5_ifc_query_vport_counter_in_bits {
3859         u8         opcode[0x10];
3860         u8         reserved_at_10[0x10];
3861
3862         u8         reserved_at_20[0x10];
3863         u8         op_mod[0x10];
3864
3865         u8         other_vport[0x1];
3866         u8         reserved_at_41[0xb];
3867         u8         port_num[0x4];
3868         u8         vport_number[0x10];
3869
3870         u8         reserved_at_60[0x60];
3871
3872         u8         clear[0x1];
3873         u8         reserved_at_c1[0x1f];
3874
3875         u8         reserved_at_e0[0x20];
3876 };
3877
3878 struct mlx5_ifc_query_tis_out_bits {
3879         u8         status[0x8];
3880         u8         reserved_at_8[0x18];
3881
3882         u8         syndrome[0x20];
3883
3884         u8         reserved_at_40[0x40];
3885
3886         struct mlx5_ifc_tisc_bits tis_context;
3887 };
3888
3889 struct mlx5_ifc_query_tis_in_bits {
3890         u8         opcode[0x10];
3891         u8         reserved_at_10[0x10];
3892
3893         u8         reserved_at_20[0x10];
3894         u8         op_mod[0x10];
3895
3896         u8         reserved_at_40[0x8];
3897         u8         tisn[0x18];
3898
3899         u8         reserved_at_60[0x20];
3900 };
3901
3902 struct mlx5_ifc_query_tir_out_bits {
3903         u8         status[0x8];
3904         u8         reserved_at_8[0x18];
3905
3906         u8         syndrome[0x20];
3907
3908         u8         reserved_at_40[0xc0];
3909
3910         struct mlx5_ifc_tirc_bits tir_context;
3911 };
3912
3913 struct mlx5_ifc_query_tir_in_bits {
3914         u8         opcode[0x10];
3915         u8         reserved_at_10[0x10];
3916
3917         u8         reserved_at_20[0x10];
3918         u8         op_mod[0x10];
3919
3920         u8         reserved_at_40[0x8];
3921         u8         tirn[0x18];
3922
3923         u8         reserved_at_60[0x20];
3924 };
3925
3926 struct mlx5_ifc_query_srq_out_bits {
3927         u8         status[0x8];
3928         u8         reserved_at_8[0x18];
3929
3930         u8         syndrome[0x20];
3931
3932         u8         reserved_at_40[0x40];
3933
3934         struct mlx5_ifc_srqc_bits srq_context_entry;
3935
3936         u8         reserved_at_280[0x600];
3937
3938         u8         pas[0][0x40];
3939 };
3940
3941 struct mlx5_ifc_query_srq_in_bits {
3942         u8         opcode[0x10];
3943         u8         reserved_at_10[0x10];
3944
3945         u8         reserved_at_20[0x10];
3946         u8         op_mod[0x10];
3947
3948         u8         reserved_at_40[0x8];
3949         u8         srqn[0x18];
3950
3951         u8         reserved_at_60[0x20];
3952 };
3953
3954 struct mlx5_ifc_query_sq_out_bits {
3955         u8         status[0x8];
3956         u8         reserved_at_8[0x18];
3957
3958         u8         syndrome[0x20];
3959
3960         u8         reserved_at_40[0xc0];
3961
3962         struct mlx5_ifc_sqc_bits sq_context;
3963 };
3964
3965 struct mlx5_ifc_query_sq_in_bits {
3966         u8         opcode[0x10];
3967         u8         reserved_at_10[0x10];
3968
3969         u8         reserved_at_20[0x10];
3970         u8         op_mod[0x10];
3971
3972         u8         reserved_at_40[0x8];
3973         u8         sqn[0x18];
3974
3975         u8         reserved_at_60[0x20];
3976 };
3977
3978 struct mlx5_ifc_query_special_contexts_out_bits {
3979         u8         status[0x8];
3980         u8         reserved_at_8[0x18];
3981
3982         u8         syndrome[0x20];
3983
3984         u8         dump_fill_mkey[0x20];
3985
3986         u8         resd_lkey[0x20];
3987
3988         u8         null_mkey[0x20];
3989
3990         u8         reserved_at_a0[0x60];
3991 };
3992
3993 struct mlx5_ifc_query_special_contexts_in_bits {
3994         u8         opcode[0x10];
3995         u8         reserved_at_10[0x10];
3996
3997         u8         reserved_at_20[0x10];
3998         u8         op_mod[0x10];
3999
4000         u8         reserved_at_40[0x40];
4001 };
4002
4003 struct mlx5_ifc_query_scheduling_element_out_bits {
4004         u8         opcode[0x10];
4005         u8         reserved_at_10[0x10];
4006
4007         u8         reserved_at_20[0x10];
4008         u8         op_mod[0x10];
4009
4010         u8         reserved_at_40[0xc0];
4011
4012         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4013
4014         u8         reserved_at_300[0x100];
4015 };
4016
4017 enum {
4018         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4019 };
4020
4021 struct mlx5_ifc_query_scheduling_element_in_bits {
4022         u8         opcode[0x10];
4023         u8         reserved_at_10[0x10];
4024
4025         u8         reserved_at_20[0x10];
4026         u8         op_mod[0x10];
4027
4028         u8         scheduling_hierarchy[0x8];
4029         u8         reserved_at_48[0x18];
4030
4031         u8         scheduling_element_id[0x20];
4032
4033         u8         reserved_at_80[0x180];
4034 };
4035
4036 struct mlx5_ifc_query_rqt_out_bits {
4037         u8         status[0x8];
4038         u8         reserved_at_8[0x18];
4039
4040         u8         syndrome[0x20];
4041
4042         u8         reserved_at_40[0xc0];
4043
4044         struct mlx5_ifc_rqtc_bits rqt_context;
4045 };
4046
4047 struct mlx5_ifc_query_rqt_in_bits {
4048         u8         opcode[0x10];
4049         u8         reserved_at_10[0x10];
4050
4051         u8         reserved_at_20[0x10];
4052         u8         op_mod[0x10];
4053
4054         u8         reserved_at_40[0x8];
4055         u8         rqtn[0x18];
4056
4057         u8         reserved_at_60[0x20];
4058 };
4059
4060 struct mlx5_ifc_query_rq_out_bits {
4061         u8         status[0x8];
4062         u8         reserved_at_8[0x18];
4063
4064         u8         syndrome[0x20];
4065
4066         u8         reserved_at_40[0xc0];
4067
4068         struct mlx5_ifc_rqc_bits rq_context;
4069 };
4070
4071 struct mlx5_ifc_query_rq_in_bits {
4072         u8         opcode[0x10];
4073         u8         reserved_at_10[0x10];
4074
4075         u8         reserved_at_20[0x10];
4076         u8         op_mod[0x10];
4077
4078         u8         reserved_at_40[0x8];
4079         u8         rqn[0x18];
4080
4081         u8         reserved_at_60[0x20];
4082 };
4083
4084 struct mlx5_ifc_query_roce_address_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_at_8[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_at_40[0x40];
4091
4092         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4093 };
4094
4095 struct mlx5_ifc_query_roce_address_in_bits {
4096         u8         opcode[0x10];
4097         u8         reserved_at_10[0x10];
4098
4099         u8         reserved_at_20[0x10];
4100         u8         op_mod[0x10];
4101
4102         u8         roce_address_index[0x10];
4103         u8         reserved_at_50[0xc];
4104         u8         vhca_port_num[0x4];
4105
4106         u8         reserved_at_60[0x20];
4107 };
4108
4109 struct mlx5_ifc_query_rmp_out_bits {
4110         u8         status[0x8];
4111         u8         reserved_at_8[0x18];
4112
4113         u8         syndrome[0x20];
4114
4115         u8         reserved_at_40[0xc0];
4116
4117         struct mlx5_ifc_rmpc_bits rmp_context;
4118 };
4119
4120 struct mlx5_ifc_query_rmp_in_bits {
4121         u8         opcode[0x10];
4122         u8         reserved_at_10[0x10];
4123
4124         u8         reserved_at_20[0x10];
4125         u8         op_mod[0x10];
4126
4127         u8         reserved_at_40[0x8];
4128         u8         rmpn[0x18];
4129
4130         u8         reserved_at_60[0x20];
4131 };
4132
4133 struct mlx5_ifc_query_qp_out_bits {
4134         u8         status[0x8];
4135         u8         reserved_at_8[0x18];
4136
4137         u8         syndrome[0x20];
4138
4139         u8         reserved_at_40[0x40];
4140
4141         u8         opt_param_mask[0x20];
4142
4143         u8         reserved_at_a0[0x20];
4144
4145         struct mlx5_ifc_qpc_bits qpc;
4146
4147         u8         reserved_at_800[0x80];
4148
4149         u8         pas[0][0x40];
4150 };
4151
4152 struct mlx5_ifc_query_qp_in_bits {
4153         u8         opcode[0x10];
4154         u8         reserved_at_10[0x10];
4155
4156         u8         reserved_at_20[0x10];
4157         u8         op_mod[0x10];
4158
4159         u8         reserved_at_40[0x8];
4160         u8         qpn[0x18];
4161
4162         u8         reserved_at_60[0x20];
4163 };
4164
4165 struct mlx5_ifc_query_q_counter_out_bits {
4166         u8         status[0x8];
4167         u8         reserved_at_8[0x18];
4168
4169         u8         syndrome[0x20];
4170
4171         u8         reserved_at_40[0x40];
4172
4173         u8         rx_write_requests[0x20];
4174
4175         u8         reserved_at_a0[0x20];
4176
4177         u8         rx_read_requests[0x20];
4178
4179         u8         reserved_at_e0[0x20];
4180
4181         u8         rx_atomic_requests[0x20];
4182
4183         u8         reserved_at_120[0x20];
4184
4185         u8         rx_dct_connect[0x20];
4186
4187         u8         reserved_at_160[0x20];
4188
4189         u8         out_of_buffer[0x20];
4190
4191         u8         reserved_at_1a0[0x20];
4192
4193         u8         out_of_sequence[0x20];
4194
4195         u8         reserved_at_1e0[0x20];
4196
4197         u8         duplicate_request[0x20];
4198
4199         u8         reserved_at_220[0x20];
4200
4201         u8         rnr_nak_retry_err[0x20];
4202
4203         u8         reserved_at_260[0x20];
4204
4205         u8         packet_seq_err[0x20];
4206
4207         u8         reserved_at_2a0[0x20];
4208
4209         u8         implied_nak_seq_err[0x20];
4210
4211         u8         reserved_at_2e0[0x20];
4212
4213         u8         local_ack_timeout_err[0x20];
4214
4215         u8         reserved_at_320[0xa0];
4216
4217         u8         resp_local_length_error[0x20];
4218
4219         u8         req_local_length_error[0x20];
4220
4221         u8         resp_local_qp_error[0x20];
4222
4223         u8         local_operation_error[0x20];
4224
4225         u8         resp_local_protection[0x20];
4226
4227         u8         req_local_protection[0x20];
4228
4229         u8         resp_cqe_error[0x20];
4230
4231         u8         req_cqe_error[0x20];
4232
4233         u8         req_mw_binding[0x20];
4234
4235         u8         req_bad_response[0x20];
4236
4237         u8         req_remote_invalid_request[0x20];
4238
4239         u8         resp_remote_invalid_request[0x20];
4240
4241         u8         req_remote_access_errors[0x20];
4242
4243         u8         resp_remote_access_errors[0x20];
4244
4245         u8         req_remote_operation_errors[0x20];
4246
4247         u8         req_transport_retries_exceeded[0x20];
4248
4249         u8         cq_overflow[0x20];
4250
4251         u8         resp_cqe_flush_error[0x20];
4252
4253         u8         req_cqe_flush_error[0x20];
4254
4255         u8         reserved_at_620[0x1e0];
4256 };
4257
4258 struct mlx5_ifc_query_q_counter_in_bits {
4259         u8         opcode[0x10];
4260         u8         reserved_at_10[0x10];
4261
4262         u8         reserved_at_20[0x10];
4263         u8         op_mod[0x10];
4264
4265         u8         reserved_at_40[0x80];
4266
4267         u8         clear[0x1];
4268         u8         reserved_at_c1[0x1f];
4269
4270         u8         reserved_at_e0[0x18];
4271         u8         counter_set_id[0x8];
4272 };
4273
4274 struct mlx5_ifc_query_pages_out_bits {
4275         u8         status[0x8];
4276         u8         reserved_at_8[0x18];
4277
4278         u8         syndrome[0x20];
4279
4280         u8         reserved_at_40[0x10];
4281         u8         function_id[0x10];
4282
4283         u8         num_pages[0x20];
4284 };
4285
4286 enum {
4287         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4288         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4289         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4290 };
4291
4292 struct mlx5_ifc_query_pages_in_bits {
4293         u8         opcode[0x10];
4294         u8         reserved_at_10[0x10];
4295
4296         u8         reserved_at_20[0x10];
4297         u8         op_mod[0x10];
4298
4299         u8         reserved_at_40[0x10];
4300         u8         function_id[0x10];
4301
4302         u8         reserved_at_60[0x20];
4303 };
4304
4305 struct mlx5_ifc_query_nic_vport_context_out_bits {
4306         u8         status[0x8];
4307         u8         reserved_at_8[0x18];
4308
4309         u8         syndrome[0x20];
4310
4311         u8         reserved_at_40[0x40];
4312
4313         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4314 };
4315
4316 struct mlx5_ifc_query_nic_vport_context_in_bits {
4317         u8         opcode[0x10];
4318         u8         reserved_at_10[0x10];
4319
4320         u8         reserved_at_20[0x10];
4321         u8         op_mod[0x10];
4322
4323         u8         other_vport[0x1];
4324         u8         reserved_at_41[0xf];
4325         u8         vport_number[0x10];
4326
4327         u8         reserved_at_60[0x5];
4328         u8         allowed_list_type[0x3];
4329         u8         reserved_at_68[0x18];
4330 };
4331
4332 struct mlx5_ifc_query_mkey_out_bits {
4333         u8         status[0x8];
4334         u8         reserved_at_8[0x18];
4335
4336         u8         syndrome[0x20];
4337
4338         u8         reserved_at_40[0x40];
4339
4340         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4341
4342         u8         reserved_at_280[0x600];
4343
4344         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4345
4346         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4347 };
4348
4349 struct mlx5_ifc_query_mkey_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_at_10[0x10];
4352
4353         u8         reserved_at_20[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         reserved_at_40[0x8];
4357         u8         mkey_index[0x18];
4358
4359         u8         pg_access[0x1];
4360         u8         reserved_at_61[0x1f];
4361 };
4362
4363 struct mlx5_ifc_query_mad_demux_out_bits {
4364         u8         status[0x8];
4365         u8         reserved_at_8[0x18];
4366
4367         u8         syndrome[0x20];
4368
4369         u8         reserved_at_40[0x40];
4370
4371         u8         mad_dumux_parameters_block[0x20];
4372 };
4373
4374 struct mlx5_ifc_query_mad_demux_in_bits {
4375         u8         opcode[0x10];
4376         u8         reserved_at_10[0x10];
4377
4378         u8         reserved_at_20[0x10];
4379         u8         op_mod[0x10];
4380
4381         u8         reserved_at_40[0x40];
4382 };
4383
4384 struct mlx5_ifc_query_l2_table_entry_out_bits {
4385         u8         status[0x8];
4386         u8         reserved_at_8[0x18];
4387
4388         u8         syndrome[0x20];
4389
4390         u8         reserved_at_40[0xa0];
4391
4392         u8         reserved_at_e0[0x13];
4393         u8         vlan_valid[0x1];
4394         u8         vlan[0xc];
4395
4396         struct mlx5_ifc_mac_address_layout_bits mac_address;
4397
4398         u8         reserved_at_140[0xc0];
4399 };
4400
4401 struct mlx5_ifc_query_l2_table_entry_in_bits {
4402         u8         opcode[0x10];
4403         u8         reserved_at_10[0x10];
4404
4405         u8         reserved_at_20[0x10];
4406         u8         op_mod[0x10];
4407
4408         u8         reserved_at_40[0x60];
4409
4410         u8         reserved_at_a0[0x8];
4411         u8         table_index[0x18];
4412
4413         u8         reserved_at_c0[0x140];
4414 };
4415
4416 struct mlx5_ifc_query_issi_out_bits {
4417         u8         status[0x8];
4418         u8         reserved_at_8[0x18];
4419
4420         u8         syndrome[0x20];
4421
4422         u8         reserved_at_40[0x10];
4423         u8         current_issi[0x10];
4424
4425         u8         reserved_at_60[0xa0];
4426
4427         u8         reserved_at_100[76][0x8];
4428         u8         supported_issi_dw0[0x20];
4429 };
4430
4431 struct mlx5_ifc_query_issi_in_bits {
4432         u8         opcode[0x10];
4433         u8         reserved_at_10[0x10];
4434
4435         u8         reserved_at_20[0x10];
4436         u8         op_mod[0x10];
4437
4438         u8         reserved_at_40[0x40];
4439 };
4440
4441 struct mlx5_ifc_set_driver_version_out_bits {
4442         u8         status[0x8];
4443         u8         reserved_0[0x18];
4444
4445         u8         syndrome[0x20];
4446         u8         reserved_1[0x40];
4447 };
4448
4449 struct mlx5_ifc_set_driver_version_in_bits {
4450         u8         opcode[0x10];
4451         u8         reserved_0[0x10];
4452
4453         u8         reserved_1[0x10];
4454         u8         op_mod[0x10];
4455
4456         u8         reserved_2[0x40];
4457         u8         driver_version[64][0x8];
4458 };
4459
4460 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4461         u8         status[0x8];
4462         u8         reserved_at_8[0x18];
4463
4464         u8         syndrome[0x20];
4465
4466         u8         reserved_at_40[0x40];
4467
4468         struct mlx5_ifc_pkey_bits pkey[0];
4469 };
4470
4471 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4472         u8         opcode[0x10];
4473         u8         reserved_at_10[0x10];
4474
4475         u8         reserved_at_20[0x10];
4476         u8         op_mod[0x10];
4477
4478         u8         other_vport[0x1];
4479         u8         reserved_at_41[0xb];
4480         u8         port_num[0x4];
4481         u8         vport_number[0x10];
4482
4483         u8         reserved_at_60[0x10];
4484         u8         pkey_index[0x10];
4485 };
4486
4487 enum {
4488         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4489         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4490         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4491 };
4492
4493 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4494         u8         status[0x8];
4495         u8         reserved_at_8[0x18];
4496
4497         u8         syndrome[0x20];
4498
4499         u8         reserved_at_40[0x20];
4500
4501         u8         gids_num[0x10];
4502         u8         reserved_at_70[0x10];
4503
4504         struct mlx5_ifc_array128_auto_bits gid[0];
4505 };
4506
4507 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4508         u8         opcode[0x10];
4509         u8         reserved_at_10[0x10];
4510
4511         u8         reserved_at_20[0x10];
4512         u8         op_mod[0x10];
4513
4514         u8         other_vport[0x1];
4515         u8         reserved_at_41[0xb];
4516         u8         port_num[0x4];
4517         u8         vport_number[0x10];
4518
4519         u8         reserved_at_60[0x10];
4520         u8         gid_index[0x10];
4521 };
4522
4523 struct mlx5_ifc_query_hca_vport_context_out_bits {
4524         u8         status[0x8];
4525         u8         reserved_at_8[0x18];
4526
4527         u8         syndrome[0x20];
4528
4529         u8         reserved_at_40[0x40];
4530
4531         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4532 };
4533
4534 struct mlx5_ifc_query_hca_vport_context_in_bits {
4535         u8         opcode[0x10];
4536         u8         reserved_at_10[0x10];
4537
4538         u8         reserved_at_20[0x10];
4539         u8         op_mod[0x10];
4540
4541         u8         other_vport[0x1];
4542         u8         reserved_at_41[0xb];
4543         u8         port_num[0x4];
4544         u8         vport_number[0x10];
4545
4546         u8         reserved_at_60[0x20];
4547 };
4548
4549 struct mlx5_ifc_query_hca_cap_out_bits {
4550         u8         status[0x8];
4551         u8         reserved_at_8[0x18];
4552
4553         u8         syndrome[0x20];
4554
4555         u8         reserved_at_40[0x40];
4556
4557         union mlx5_ifc_hca_cap_union_bits capability;
4558 };
4559
4560 struct mlx5_ifc_query_hca_cap_in_bits {
4561         u8         opcode[0x10];
4562         u8         reserved_at_10[0x10];
4563
4564         u8         reserved_at_20[0x10];
4565         u8         op_mod[0x10];
4566
4567         u8         reserved_at_40[0x40];
4568 };
4569
4570 struct mlx5_ifc_query_flow_table_out_bits {
4571         u8         status[0x8];
4572         u8         reserved_at_8[0x18];
4573
4574         u8         syndrome[0x20];
4575
4576         u8         reserved_at_40[0x80];
4577
4578         u8         reserved_at_c0[0x8];
4579         u8         level[0x8];
4580         u8         reserved_at_d0[0x8];
4581         u8         log_size[0x8];
4582
4583         u8         reserved_at_e0[0x120];
4584 };
4585
4586 struct mlx5_ifc_query_flow_table_in_bits {
4587         u8         opcode[0x10];
4588         u8         reserved_at_10[0x10];
4589
4590         u8         reserved_at_20[0x10];
4591         u8         op_mod[0x10];
4592
4593         u8         reserved_at_40[0x40];
4594
4595         u8         table_type[0x8];
4596         u8         reserved_at_88[0x18];
4597
4598         u8         reserved_at_a0[0x8];
4599         u8         table_id[0x18];
4600
4601         u8         reserved_at_c0[0x140];
4602 };
4603
4604 struct mlx5_ifc_query_fte_out_bits {
4605         u8         status[0x8];
4606         u8         reserved_at_8[0x18];
4607
4608         u8         syndrome[0x20];
4609
4610         u8         reserved_at_40[0x1c0];
4611
4612         struct mlx5_ifc_flow_context_bits flow_context;
4613 };
4614
4615 struct mlx5_ifc_query_fte_in_bits {
4616         u8         opcode[0x10];
4617         u8         reserved_at_10[0x10];
4618
4619         u8         reserved_at_20[0x10];
4620         u8         op_mod[0x10];
4621
4622         u8         reserved_at_40[0x40];
4623
4624         u8         table_type[0x8];
4625         u8         reserved_at_88[0x18];
4626
4627         u8         reserved_at_a0[0x8];
4628         u8         table_id[0x18];
4629
4630         u8         reserved_at_c0[0x40];
4631
4632         u8         flow_index[0x20];
4633
4634         u8         reserved_at_120[0xe0];
4635 };
4636
4637 enum {
4638         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4639         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4640         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4641         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4642 };
4643
4644 struct mlx5_ifc_query_flow_group_out_bits {
4645         u8         status[0x8];
4646         u8         reserved_at_8[0x18];
4647
4648         u8         syndrome[0x20];
4649
4650         u8         reserved_at_40[0xa0];
4651
4652         u8         start_flow_index[0x20];
4653
4654         u8         reserved_at_100[0x20];
4655
4656         u8         end_flow_index[0x20];
4657
4658         u8         reserved_at_140[0xa0];
4659
4660         u8         reserved_at_1e0[0x18];
4661         u8         match_criteria_enable[0x8];
4662
4663         struct mlx5_ifc_fte_match_param_bits match_criteria;
4664
4665         u8         reserved_at_1200[0xe00];
4666 };
4667
4668 struct mlx5_ifc_query_flow_group_in_bits {
4669         u8         opcode[0x10];
4670         u8         reserved_at_10[0x10];
4671
4672         u8         reserved_at_20[0x10];
4673         u8         op_mod[0x10];
4674
4675         u8         reserved_at_40[0x40];
4676
4677         u8         table_type[0x8];
4678         u8         reserved_at_88[0x18];
4679
4680         u8         reserved_at_a0[0x8];
4681         u8         table_id[0x18];
4682
4683         u8         group_id[0x20];
4684
4685         u8         reserved_at_e0[0x120];
4686 };
4687
4688 struct mlx5_ifc_query_flow_counter_out_bits {
4689         u8         status[0x8];
4690         u8         reserved_at_8[0x18];
4691
4692         u8         syndrome[0x20];
4693
4694         u8         reserved_at_40[0x40];
4695
4696         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4697 };
4698
4699 struct mlx5_ifc_query_flow_counter_in_bits {
4700         u8         opcode[0x10];
4701         u8         reserved_at_10[0x10];
4702
4703         u8         reserved_at_20[0x10];
4704         u8         op_mod[0x10];
4705
4706         u8         reserved_at_40[0x80];
4707
4708         u8         clear[0x1];
4709         u8         reserved_at_c1[0xf];
4710         u8         num_of_counters[0x10];
4711
4712         u8         flow_counter_id[0x20];
4713 };
4714
4715 struct mlx5_ifc_query_esw_vport_context_out_bits {
4716         u8         status[0x8];
4717         u8         reserved_at_8[0x18];
4718
4719         u8         syndrome[0x20];
4720
4721         u8         reserved_at_40[0x40];
4722
4723         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4724 };
4725
4726 struct mlx5_ifc_query_esw_vport_context_in_bits {
4727         u8         opcode[0x10];
4728         u8         reserved_at_10[0x10];
4729
4730         u8         reserved_at_20[0x10];
4731         u8         op_mod[0x10];
4732
4733         u8         other_vport[0x1];
4734         u8         reserved_at_41[0xf];
4735         u8         vport_number[0x10];
4736
4737         u8         reserved_at_60[0x20];
4738 };
4739
4740 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4741         u8         status[0x8];
4742         u8         reserved_at_8[0x18];
4743
4744         u8         syndrome[0x20];
4745
4746         u8         reserved_at_40[0x40];
4747 };
4748
4749 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4750         u8         reserved_at_0[0x1c];
4751         u8         vport_cvlan_insert[0x1];
4752         u8         vport_svlan_insert[0x1];
4753         u8         vport_cvlan_strip[0x1];
4754         u8         vport_svlan_strip[0x1];
4755 };
4756
4757 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4758         u8         opcode[0x10];
4759         u8         reserved_at_10[0x10];
4760
4761         u8         reserved_at_20[0x10];
4762         u8         op_mod[0x10];
4763
4764         u8         other_vport[0x1];
4765         u8         reserved_at_41[0xf];
4766         u8         vport_number[0x10];
4767
4768         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4769
4770         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4771 };
4772
4773 struct mlx5_ifc_query_eq_out_bits {
4774         u8         status[0x8];
4775         u8         reserved_at_8[0x18];
4776
4777         u8         syndrome[0x20];
4778
4779         u8         reserved_at_40[0x40];
4780
4781         struct mlx5_ifc_eqc_bits eq_context_entry;
4782
4783         u8         reserved_at_280[0x40];
4784
4785         u8         event_bitmask[0x40];
4786
4787         u8         reserved_at_300[0x580];
4788
4789         u8         pas[0][0x40];
4790 };
4791
4792 struct mlx5_ifc_query_eq_in_bits {
4793         u8         opcode[0x10];
4794         u8         reserved_at_10[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         reserved_at_40[0x18];
4800         u8         eq_number[0x8];
4801
4802         u8         reserved_at_60[0x20];
4803 };
4804
4805 struct mlx5_ifc_encap_header_in_bits {
4806         u8         reserved_at_0[0x5];
4807         u8         header_type[0x3];
4808         u8         reserved_at_8[0xe];
4809         u8         encap_header_size[0xa];
4810
4811         u8         reserved_at_20[0x10];
4812         u8         encap_header[2][0x8];
4813
4814         u8         more_encap_header[0][0x8];
4815 };
4816
4817 struct mlx5_ifc_query_encap_header_out_bits {
4818         u8         status[0x8];
4819         u8         reserved_at_8[0x18];
4820
4821         u8         syndrome[0x20];
4822
4823         u8         reserved_at_40[0xa0];
4824
4825         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4826 };
4827
4828 struct mlx5_ifc_query_encap_header_in_bits {
4829         u8         opcode[0x10];
4830         u8         reserved_at_10[0x10];
4831
4832         u8         reserved_at_20[0x10];
4833         u8         op_mod[0x10];
4834
4835         u8         encap_id[0x20];
4836
4837         u8         reserved_at_60[0xa0];
4838 };
4839
4840 struct mlx5_ifc_alloc_encap_header_out_bits {
4841         u8         status[0x8];
4842         u8         reserved_at_8[0x18];
4843
4844         u8         syndrome[0x20];
4845
4846         u8         encap_id[0x20];
4847
4848         u8         reserved_at_60[0x20];
4849 };
4850
4851 struct mlx5_ifc_alloc_encap_header_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_at_10[0x10];
4854
4855         u8         reserved_at_20[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_at_40[0xa0];
4859
4860         struct mlx5_ifc_encap_header_in_bits encap_header;
4861 };
4862
4863 struct mlx5_ifc_dealloc_encap_header_out_bits {
4864         u8         status[0x8];
4865         u8         reserved_at_8[0x18];
4866
4867         u8         syndrome[0x20];
4868
4869         u8         reserved_at_40[0x40];
4870 };
4871
4872 struct mlx5_ifc_dealloc_encap_header_in_bits {
4873         u8         opcode[0x10];
4874         u8         reserved_at_10[0x10];
4875
4876         u8         reserved_20[0x10];
4877         u8         op_mod[0x10];
4878
4879         u8         encap_id[0x20];
4880
4881         u8         reserved_60[0x20];
4882 };
4883
4884 struct mlx5_ifc_set_action_in_bits {
4885         u8         action_type[0x4];
4886         u8         field[0xc];
4887         u8         reserved_at_10[0x3];
4888         u8         offset[0x5];
4889         u8         reserved_at_18[0x3];
4890         u8         length[0x5];
4891
4892         u8         data[0x20];
4893 };
4894
4895 struct mlx5_ifc_add_action_in_bits {
4896         u8         action_type[0x4];
4897         u8         field[0xc];
4898         u8         reserved_at_10[0x10];
4899
4900         u8         data[0x20];
4901 };
4902
4903 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4904         struct mlx5_ifc_set_action_in_bits set_action_in;
4905         struct mlx5_ifc_add_action_in_bits add_action_in;
4906         u8         reserved_at_0[0x40];
4907 };
4908
4909 enum {
4910         MLX5_ACTION_TYPE_SET   = 0x1,
4911         MLX5_ACTION_TYPE_ADD   = 0x2,
4912 };
4913
4914 enum {
4915         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4916         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4917         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4918         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4919         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4920         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4921         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4922         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4923         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4924         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4925         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4926         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4927         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4928         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4929         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4930         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4931         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4932         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4933         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4934         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4935         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4936         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4937         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4938 };
4939
4940 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4941         u8         status[0x8];
4942         u8         reserved_at_8[0x18];
4943
4944         u8         syndrome[0x20];
4945
4946         u8         modify_header_id[0x20];
4947
4948         u8         reserved_at_60[0x20];
4949 };
4950
4951 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_at_10[0x10];
4954
4955         u8         reserved_at_20[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         reserved_at_40[0x20];
4959
4960         u8         table_type[0x8];
4961         u8         reserved_at_68[0x10];
4962         u8         num_of_actions[0x8];
4963
4964         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4965 };
4966
4967 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4968         u8         status[0x8];
4969         u8         reserved_at_8[0x18];
4970
4971         u8         syndrome[0x20];
4972
4973         u8         reserved_at_40[0x40];
4974 };
4975
4976 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4977         u8         opcode[0x10];
4978         u8         reserved_at_10[0x10];
4979
4980         u8         reserved_at_20[0x10];
4981         u8         op_mod[0x10];
4982
4983         u8         modify_header_id[0x20];
4984
4985         u8         reserved_at_60[0x20];
4986 };
4987
4988 struct mlx5_ifc_query_dct_out_bits {
4989         u8         status[0x8];
4990         u8         reserved_at_8[0x18];
4991
4992         u8         syndrome[0x20];
4993
4994         u8         reserved_at_40[0x40];
4995
4996         struct mlx5_ifc_dctc_bits dct_context_entry;
4997
4998         u8         reserved_at_280[0x180];
4999 };
5000
5001 struct mlx5_ifc_query_dct_in_bits {
5002         u8         opcode[0x10];
5003         u8         reserved_at_10[0x10];
5004
5005         u8         reserved_at_20[0x10];
5006         u8         op_mod[0x10];
5007
5008         u8         reserved_at_40[0x8];
5009         u8         dctn[0x18];
5010
5011         u8         reserved_at_60[0x20];
5012 };
5013
5014 struct mlx5_ifc_query_cq_out_bits {
5015         u8         status[0x8];
5016         u8         reserved_at_8[0x18];
5017
5018         u8         syndrome[0x20];
5019
5020         u8         reserved_at_40[0x40];
5021
5022         struct mlx5_ifc_cqc_bits cq_context;
5023
5024         u8         reserved_at_280[0x600];
5025
5026         u8         pas[0][0x40];
5027 };
5028
5029 struct mlx5_ifc_query_cq_in_bits {
5030         u8         opcode[0x10];
5031         u8         reserved_at_10[0x10];
5032
5033         u8         reserved_at_20[0x10];
5034         u8         op_mod[0x10];
5035
5036         u8         reserved_at_40[0x8];
5037         u8         cqn[0x18];
5038
5039         u8         reserved_at_60[0x20];
5040 };
5041
5042 struct mlx5_ifc_query_cong_status_out_bits {
5043         u8         status[0x8];
5044         u8         reserved_at_8[0x18];
5045
5046         u8         syndrome[0x20];
5047
5048         u8         reserved_at_40[0x20];
5049
5050         u8         enable[0x1];
5051         u8         tag_enable[0x1];
5052         u8         reserved_at_62[0x1e];
5053 };
5054
5055 struct mlx5_ifc_query_cong_status_in_bits {
5056         u8         opcode[0x10];
5057         u8         reserved_at_10[0x10];
5058
5059         u8         reserved_at_20[0x10];
5060         u8         op_mod[0x10];
5061
5062         u8         reserved_at_40[0x18];
5063         u8         priority[0x4];
5064         u8         cong_protocol[0x4];
5065
5066         u8         reserved_at_60[0x20];
5067 };
5068
5069 struct mlx5_ifc_query_cong_statistics_out_bits {
5070         u8         status[0x8];
5071         u8         reserved_at_8[0x18];
5072
5073         u8         syndrome[0x20];
5074
5075         u8         reserved_at_40[0x40];
5076
5077         u8         rp_cur_flows[0x20];
5078
5079         u8         sum_flows[0x20];
5080
5081         u8         rp_cnp_ignored_high[0x20];
5082
5083         u8         rp_cnp_ignored_low[0x20];
5084
5085         u8         rp_cnp_handled_high[0x20];
5086
5087         u8         rp_cnp_handled_low[0x20];
5088
5089         u8         reserved_at_140[0x100];
5090
5091         u8         time_stamp_high[0x20];
5092
5093         u8         time_stamp_low[0x20];
5094
5095         u8         accumulators_period[0x20];
5096
5097         u8         np_ecn_marked_roce_packets_high[0x20];
5098
5099         u8         np_ecn_marked_roce_packets_low[0x20];
5100
5101         u8         np_cnp_sent_high[0x20];
5102
5103         u8         np_cnp_sent_low[0x20];
5104
5105         u8         reserved_at_320[0x560];
5106 };
5107
5108 struct mlx5_ifc_query_cong_statistics_in_bits {
5109         u8         opcode[0x10];
5110         u8         reserved_at_10[0x10];
5111
5112         u8         reserved_at_20[0x10];
5113         u8         op_mod[0x10];
5114
5115         u8         clear[0x1];
5116         u8         reserved_at_41[0x1f];
5117
5118         u8         reserved_at_60[0x20];
5119 };
5120
5121 struct mlx5_ifc_query_cong_params_out_bits {
5122         u8         status[0x8];
5123         u8         reserved_at_8[0x18];
5124
5125         u8         syndrome[0x20];
5126
5127         u8         reserved_at_40[0x40];
5128
5129         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5130 };
5131
5132 struct mlx5_ifc_query_cong_params_in_bits {
5133         u8         opcode[0x10];
5134         u8         reserved_at_10[0x10];
5135
5136         u8         reserved_at_20[0x10];
5137         u8         op_mod[0x10];
5138
5139         u8         reserved_at_40[0x1c];
5140         u8         cong_protocol[0x4];
5141
5142         u8         reserved_at_60[0x20];
5143 };
5144
5145 struct mlx5_ifc_query_adapter_out_bits {
5146         u8         status[0x8];
5147         u8         reserved_at_8[0x18];
5148
5149         u8         syndrome[0x20];
5150
5151         u8         reserved_at_40[0x40];
5152
5153         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5154 };
5155
5156 struct mlx5_ifc_query_adapter_in_bits {
5157         u8         opcode[0x10];
5158         u8         reserved_at_10[0x10];
5159
5160         u8         reserved_at_20[0x10];
5161         u8         op_mod[0x10];
5162
5163         u8         reserved_at_40[0x40];
5164 };
5165
5166 struct mlx5_ifc_qp_2rst_out_bits {
5167         u8         status[0x8];
5168         u8         reserved_at_8[0x18];
5169
5170         u8         syndrome[0x20];
5171
5172         u8         reserved_at_40[0x40];
5173 };
5174
5175 struct mlx5_ifc_qp_2rst_in_bits {
5176         u8         opcode[0x10];
5177         u8         reserved_at_10[0x10];
5178
5179         u8         reserved_at_20[0x10];
5180         u8         op_mod[0x10];
5181
5182         u8         reserved_at_40[0x8];
5183         u8         qpn[0x18];
5184
5185         u8         reserved_at_60[0x20];
5186 };
5187
5188 struct mlx5_ifc_qp_2err_out_bits {
5189         u8         status[0x8];
5190         u8         reserved_at_8[0x18];
5191
5192         u8         syndrome[0x20];
5193
5194         u8         reserved_at_40[0x40];
5195 };
5196
5197 struct mlx5_ifc_qp_2err_in_bits {
5198         u8         opcode[0x10];
5199         u8         reserved_at_10[0x10];
5200
5201         u8         reserved_at_20[0x10];
5202         u8         op_mod[0x10];
5203
5204         u8         reserved_at_40[0x8];
5205         u8         qpn[0x18];
5206
5207         u8         reserved_at_60[0x20];
5208 };
5209
5210 struct mlx5_ifc_page_fault_resume_out_bits {
5211         u8         status[0x8];
5212         u8         reserved_at_8[0x18];
5213
5214         u8         syndrome[0x20];
5215
5216         u8         reserved_at_40[0x40];
5217 };
5218
5219 struct mlx5_ifc_page_fault_resume_in_bits {
5220         u8         opcode[0x10];
5221         u8         reserved_at_10[0x10];
5222
5223         u8         reserved_at_20[0x10];
5224         u8         op_mod[0x10];
5225
5226         u8         error[0x1];
5227         u8         reserved_at_41[0x4];
5228         u8         page_fault_type[0x3];
5229         u8         wq_number[0x18];
5230
5231         u8         reserved_at_60[0x8];
5232         u8         token[0x18];
5233 };
5234
5235 struct mlx5_ifc_nop_out_bits {
5236         u8         status[0x8];
5237         u8         reserved_at_8[0x18];
5238
5239         u8         syndrome[0x20];
5240
5241         u8         reserved_at_40[0x40];
5242 };
5243
5244 struct mlx5_ifc_nop_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         reserved_at_40[0x40];
5252 };
5253
5254 struct mlx5_ifc_modify_vport_state_out_bits {
5255         u8         status[0x8];
5256         u8         reserved_at_8[0x18];
5257
5258         u8         syndrome[0x20];
5259
5260         u8         reserved_at_40[0x40];
5261 };
5262
5263 struct mlx5_ifc_modify_vport_state_in_bits {
5264         u8         opcode[0x10];
5265         u8         reserved_at_10[0x10];
5266
5267         u8         reserved_at_20[0x10];
5268         u8         op_mod[0x10];
5269
5270         u8         other_vport[0x1];
5271         u8         reserved_at_41[0xf];
5272         u8         vport_number[0x10];
5273
5274         u8         reserved_at_60[0x18];
5275         u8         admin_state[0x4];
5276         u8         reserved_at_7c[0x4];
5277 };
5278
5279 struct mlx5_ifc_modify_tis_out_bits {
5280         u8         status[0x8];
5281         u8         reserved_at_8[0x18];
5282
5283         u8         syndrome[0x20];
5284
5285         u8         reserved_at_40[0x40];
5286 };
5287
5288 struct mlx5_ifc_modify_tis_bitmask_bits {
5289         u8         reserved_at_0[0x20];
5290
5291         u8         reserved_at_20[0x1d];
5292         u8         lag_tx_port_affinity[0x1];
5293         u8         strict_lag_tx_port_affinity[0x1];
5294         u8         prio[0x1];
5295 };
5296
5297 struct mlx5_ifc_modify_tis_in_bits {
5298         u8         opcode[0x10];
5299         u8         reserved_at_10[0x10];
5300
5301         u8         reserved_at_20[0x10];
5302         u8         op_mod[0x10];
5303
5304         u8         reserved_at_40[0x8];
5305         u8         tisn[0x18];
5306
5307         u8         reserved_at_60[0x20];
5308
5309         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5310
5311         u8         reserved_at_c0[0x40];
5312
5313         struct mlx5_ifc_tisc_bits ctx;
5314 };
5315
5316 struct mlx5_ifc_modify_tir_bitmask_bits {
5317         u8         reserved_at_0[0x20];
5318
5319         u8         reserved_at_20[0x1b];
5320         u8         self_lb_en[0x1];
5321         u8         reserved_at_3c[0x1];
5322         u8         hash[0x1];
5323         u8         reserved_at_3e[0x1];
5324         u8         lro[0x1];
5325 };
5326
5327 struct mlx5_ifc_modify_tir_out_bits {
5328         u8         status[0x8];
5329         u8         reserved_at_8[0x18];
5330
5331         u8         syndrome[0x20];
5332
5333         u8         reserved_at_40[0x40];
5334 };
5335
5336 struct mlx5_ifc_modify_tir_in_bits {
5337         u8         opcode[0x10];
5338         u8         reserved_at_10[0x10];
5339
5340         u8         reserved_at_20[0x10];
5341         u8         op_mod[0x10];
5342
5343         u8         reserved_at_40[0x8];
5344         u8         tirn[0x18];
5345
5346         u8         reserved_at_60[0x20];
5347
5348         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5349
5350         u8         reserved_at_c0[0x40];
5351
5352         struct mlx5_ifc_tirc_bits ctx;
5353 };
5354
5355 struct mlx5_ifc_modify_sq_out_bits {
5356         u8         status[0x8];
5357         u8         reserved_at_8[0x18];
5358
5359         u8         syndrome[0x20];
5360
5361         u8         reserved_at_40[0x40];
5362 };
5363
5364 struct mlx5_ifc_modify_sq_in_bits {
5365         u8         opcode[0x10];
5366         u8         reserved_at_10[0x10];
5367
5368         u8         reserved_at_20[0x10];
5369         u8         op_mod[0x10];
5370
5371         u8         sq_state[0x4];
5372         u8         reserved_at_44[0x4];
5373         u8         sqn[0x18];
5374
5375         u8         reserved_at_60[0x20];
5376
5377         u8         modify_bitmask[0x40];
5378
5379         u8         reserved_at_c0[0x40];
5380
5381         struct mlx5_ifc_sqc_bits ctx;
5382 };
5383
5384 struct mlx5_ifc_modify_scheduling_element_out_bits {
5385         u8         status[0x8];
5386         u8         reserved_at_8[0x18];
5387
5388         u8         syndrome[0x20];
5389
5390         u8         reserved_at_40[0x1c0];
5391 };
5392
5393 enum {
5394         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5395         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5396 };
5397
5398 struct mlx5_ifc_modify_scheduling_element_in_bits {
5399         u8         opcode[0x10];
5400         u8         reserved_at_10[0x10];
5401
5402         u8         reserved_at_20[0x10];
5403         u8         op_mod[0x10];
5404
5405         u8         scheduling_hierarchy[0x8];
5406         u8         reserved_at_48[0x18];
5407
5408         u8         scheduling_element_id[0x20];
5409
5410         u8         reserved_at_80[0x20];
5411
5412         u8         modify_bitmask[0x20];
5413
5414         u8         reserved_at_c0[0x40];
5415
5416         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5417
5418         u8         reserved_at_300[0x100];
5419 };
5420
5421 struct mlx5_ifc_modify_rqt_out_bits {
5422         u8         status[0x8];
5423         u8         reserved_at_8[0x18];
5424
5425         u8         syndrome[0x20];
5426
5427         u8         reserved_at_40[0x40];
5428 };
5429
5430 struct mlx5_ifc_rqt_bitmask_bits {
5431         u8         reserved_at_0[0x20];
5432
5433         u8         reserved_at_20[0x1f];
5434         u8         rqn_list[0x1];
5435 };
5436
5437 struct mlx5_ifc_modify_rqt_in_bits {
5438         u8         opcode[0x10];
5439         u8         reserved_at_10[0x10];
5440
5441         u8         reserved_at_20[0x10];
5442         u8         op_mod[0x10];
5443
5444         u8         reserved_at_40[0x8];
5445         u8         rqtn[0x18];
5446
5447         u8         reserved_at_60[0x20];
5448
5449         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5450
5451         u8         reserved_at_c0[0x40];
5452
5453         struct mlx5_ifc_rqtc_bits ctx;
5454 };
5455
5456 struct mlx5_ifc_modify_rq_out_bits {
5457         u8         status[0x8];
5458         u8         reserved_at_8[0x18];
5459
5460         u8         syndrome[0x20];
5461
5462         u8         reserved_at_40[0x40];
5463 };
5464
5465 enum {
5466         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5467         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5468         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5469 };
5470
5471 struct mlx5_ifc_modify_rq_in_bits {
5472         u8         opcode[0x10];
5473         u8         reserved_at_10[0x10];
5474
5475         u8         reserved_at_20[0x10];
5476         u8         op_mod[0x10];
5477
5478         u8         rq_state[0x4];
5479         u8         reserved_at_44[0x4];
5480         u8         rqn[0x18];
5481
5482         u8         reserved_at_60[0x20];
5483
5484         u8         modify_bitmask[0x40];
5485
5486         u8         reserved_at_c0[0x40];
5487
5488         struct mlx5_ifc_rqc_bits ctx;
5489 };
5490
5491 struct mlx5_ifc_modify_rmp_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498 };
5499
5500 struct mlx5_ifc_rmp_bitmask_bits {
5501         u8         reserved_at_0[0x20];
5502
5503         u8         reserved_at_20[0x1f];
5504         u8         lwm[0x1];
5505 };
5506
5507 struct mlx5_ifc_modify_rmp_in_bits {
5508         u8         opcode[0x10];
5509         u8         reserved_at_10[0x10];
5510
5511         u8         reserved_at_20[0x10];
5512         u8         op_mod[0x10];
5513
5514         u8         rmp_state[0x4];
5515         u8         reserved_at_44[0x4];
5516         u8         rmpn[0x18];
5517
5518         u8         reserved_at_60[0x20];
5519
5520         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5521
5522         u8         reserved_at_c0[0x40];
5523
5524         struct mlx5_ifc_rmpc_bits ctx;
5525 };
5526
5527 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5528         u8         status[0x8];
5529         u8         reserved_at_8[0x18];
5530
5531         u8         syndrome[0x20];
5532
5533         u8         reserved_at_40[0x40];
5534 };
5535
5536 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5537         u8         reserved_at_0[0x12];
5538         u8         affiliation[0x1];
5539         u8         reserved_at_e[0x1];
5540         u8         disable_uc_local_lb[0x1];
5541         u8         disable_mc_local_lb[0x1];
5542         u8         node_guid[0x1];
5543         u8         port_guid[0x1];
5544         u8         min_inline[0x1];
5545         u8         mtu[0x1];
5546         u8         change_event[0x1];
5547         u8         promisc[0x1];
5548         u8         permanent_address[0x1];
5549         u8         addresses_list[0x1];
5550         u8         roce_en[0x1];
5551         u8         reserved_at_1f[0x1];
5552 };
5553
5554 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5555         u8         opcode[0x10];
5556         u8         reserved_at_10[0x10];
5557
5558         u8         reserved_at_20[0x10];
5559         u8         op_mod[0x10];
5560
5561         u8         other_vport[0x1];
5562         u8         reserved_at_41[0xf];
5563         u8         vport_number[0x10];
5564
5565         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5566
5567         u8         reserved_at_80[0x780];
5568
5569         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5570 };
5571
5572 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5573         u8         status[0x8];
5574         u8         reserved_at_8[0x18];
5575
5576         u8         syndrome[0x20];
5577
5578         u8         reserved_at_40[0x40];
5579 };
5580
5581 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5582         u8         opcode[0x10];
5583         u8         reserved_at_10[0x10];
5584
5585         u8         reserved_at_20[0x10];
5586         u8         op_mod[0x10];
5587
5588         u8         other_vport[0x1];
5589         u8         reserved_at_41[0xb];
5590         u8         port_num[0x4];
5591         u8         vport_number[0x10];
5592
5593         u8         reserved_at_60[0x20];
5594
5595         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5596 };
5597
5598 struct mlx5_ifc_modify_cq_out_bits {
5599         u8         status[0x8];
5600         u8         reserved_at_8[0x18];
5601
5602         u8         syndrome[0x20];
5603
5604         u8         reserved_at_40[0x40];
5605 };
5606
5607 enum {
5608         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5609         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5610 };
5611
5612 struct mlx5_ifc_modify_cq_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_at_10[0x10];
5615
5616         u8         reserved_at_20[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         reserved_at_40[0x8];
5620         u8         cqn[0x18];
5621
5622         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5623
5624         struct mlx5_ifc_cqc_bits cq_context;
5625
5626         u8         reserved_at_280[0x600];
5627
5628         u8         pas[0][0x40];
5629 };
5630
5631 struct mlx5_ifc_modify_cong_status_out_bits {
5632         u8         status[0x8];
5633         u8         reserved_at_8[0x18];
5634
5635         u8         syndrome[0x20];
5636
5637         u8         reserved_at_40[0x40];
5638 };
5639
5640 struct mlx5_ifc_modify_cong_status_in_bits {
5641         u8         opcode[0x10];
5642         u8         reserved_at_10[0x10];
5643
5644         u8         reserved_at_20[0x10];
5645         u8         op_mod[0x10];
5646
5647         u8         reserved_at_40[0x18];
5648         u8         priority[0x4];
5649         u8         cong_protocol[0x4];
5650
5651         u8         enable[0x1];
5652         u8         tag_enable[0x1];
5653         u8         reserved_at_62[0x1e];
5654 };
5655
5656 struct mlx5_ifc_modify_cong_params_out_bits {
5657         u8         status[0x8];
5658         u8         reserved_at_8[0x18];
5659
5660         u8         syndrome[0x20];
5661
5662         u8         reserved_at_40[0x40];
5663 };
5664
5665 struct mlx5_ifc_modify_cong_params_in_bits {
5666         u8         opcode[0x10];
5667         u8         reserved_at_10[0x10];
5668
5669         u8         reserved_at_20[0x10];
5670         u8         op_mod[0x10];
5671
5672         u8         reserved_at_40[0x1c];
5673         u8         cong_protocol[0x4];
5674
5675         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5676
5677         u8         reserved_at_80[0x80];
5678
5679         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5680 };
5681
5682 struct mlx5_ifc_manage_pages_out_bits {
5683         u8         status[0x8];
5684         u8         reserved_at_8[0x18];
5685
5686         u8         syndrome[0x20];
5687
5688         u8         output_num_entries[0x20];
5689
5690         u8         reserved_at_60[0x20];
5691
5692         u8         pas[0][0x40];
5693 };
5694
5695 enum {
5696         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5697         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5698         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5699 };
5700
5701 struct mlx5_ifc_manage_pages_in_bits {
5702         u8         opcode[0x10];
5703         u8         reserved_at_10[0x10];
5704
5705         u8         reserved_at_20[0x10];
5706         u8         op_mod[0x10];
5707
5708         u8         reserved_at_40[0x10];
5709         u8         function_id[0x10];
5710
5711         u8         input_num_entries[0x20];
5712
5713         u8         pas[0][0x40];
5714 };
5715
5716 struct mlx5_ifc_mad_ifc_out_bits {
5717         u8         status[0x8];
5718         u8         reserved_at_8[0x18];
5719
5720         u8         syndrome[0x20];
5721
5722         u8         reserved_at_40[0x40];
5723
5724         u8         response_mad_packet[256][0x8];
5725 };
5726
5727 struct mlx5_ifc_mad_ifc_in_bits {
5728         u8         opcode[0x10];
5729         u8         reserved_at_10[0x10];
5730
5731         u8         reserved_at_20[0x10];
5732         u8         op_mod[0x10];
5733
5734         u8         remote_lid[0x10];
5735         u8         reserved_at_50[0x8];
5736         u8         port[0x8];
5737
5738         u8         reserved_at_60[0x20];
5739
5740         u8         mad[256][0x8];
5741 };
5742
5743 struct mlx5_ifc_init_hca_out_bits {
5744         u8         status[0x8];
5745         u8         reserved_at_8[0x18];
5746
5747         u8         syndrome[0x20];
5748
5749         u8         reserved_at_40[0x40];
5750 };
5751
5752 struct mlx5_ifc_init_hca_in_bits {
5753         u8         opcode[0x10];
5754         u8         reserved_at_10[0x10];
5755
5756         u8         reserved_at_20[0x10];
5757         u8         op_mod[0x10];
5758
5759         u8         reserved_at_40[0x40];
5760         u8         sw_owner_id[4][0x20];
5761 };
5762
5763 struct mlx5_ifc_init2rtr_qp_out_bits {
5764         u8         status[0x8];
5765         u8         reserved_at_8[0x18];
5766
5767         u8         syndrome[0x20];
5768
5769         u8         reserved_at_40[0x40];
5770 };
5771
5772 struct mlx5_ifc_init2rtr_qp_in_bits {
5773         u8         opcode[0x10];
5774         u8         reserved_at_10[0x10];
5775
5776         u8         reserved_at_20[0x10];
5777         u8         op_mod[0x10];
5778
5779         u8         reserved_at_40[0x8];
5780         u8         qpn[0x18];
5781
5782         u8         reserved_at_60[0x20];
5783
5784         u8         opt_param_mask[0x20];
5785
5786         u8         reserved_at_a0[0x20];
5787
5788         struct mlx5_ifc_qpc_bits qpc;
5789
5790         u8         reserved_at_800[0x80];
5791 };
5792
5793 struct mlx5_ifc_init2init_qp_out_bits {
5794         u8         status[0x8];
5795         u8         reserved_at_8[0x18];
5796
5797         u8         syndrome[0x20];
5798
5799         u8         reserved_at_40[0x40];
5800 };
5801
5802 struct mlx5_ifc_init2init_qp_in_bits {
5803         u8         opcode[0x10];
5804         u8         reserved_at_10[0x10];
5805
5806         u8         reserved_at_20[0x10];
5807         u8         op_mod[0x10];
5808
5809         u8         reserved_at_40[0x8];
5810         u8         qpn[0x18];
5811
5812         u8         reserved_at_60[0x20];
5813
5814         u8         opt_param_mask[0x20];
5815
5816         u8         reserved_at_a0[0x20];
5817
5818         struct mlx5_ifc_qpc_bits qpc;
5819
5820         u8         reserved_at_800[0x80];
5821 };
5822
5823 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5824         u8         status[0x8];
5825         u8         reserved_at_8[0x18];
5826
5827         u8         syndrome[0x20];
5828
5829         u8         reserved_at_40[0x40];
5830
5831         u8         packet_headers_log[128][0x8];
5832
5833         u8         packet_syndrome[64][0x8];
5834 };
5835
5836 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5837         u8         opcode[0x10];
5838         u8         reserved_at_10[0x10];
5839
5840         u8         reserved_at_20[0x10];
5841         u8         op_mod[0x10];
5842
5843         u8         reserved_at_40[0x40];
5844 };
5845
5846 struct mlx5_ifc_gen_eqe_in_bits {
5847         u8         opcode[0x10];
5848         u8         reserved_at_10[0x10];
5849
5850         u8         reserved_at_20[0x10];
5851         u8         op_mod[0x10];
5852
5853         u8         reserved_at_40[0x18];
5854         u8         eq_number[0x8];
5855
5856         u8         reserved_at_60[0x20];
5857
5858         u8         eqe[64][0x8];
5859 };
5860
5861 struct mlx5_ifc_gen_eq_out_bits {
5862         u8         status[0x8];
5863         u8         reserved_at_8[0x18];
5864
5865         u8         syndrome[0x20];
5866
5867         u8         reserved_at_40[0x40];
5868 };
5869
5870 struct mlx5_ifc_enable_hca_out_bits {
5871         u8         status[0x8];
5872         u8         reserved_at_8[0x18];
5873
5874         u8         syndrome[0x20];
5875
5876         u8         reserved_at_40[0x20];
5877 };
5878
5879 struct mlx5_ifc_enable_hca_in_bits {
5880         u8         opcode[0x10];
5881         u8         reserved_at_10[0x10];
5882
5883         u8         reserved_at_20[0x10];
5884         u8         op_mod[0x10];
5885
5886         u8         reserved_at_40[0x10];
5887         u8         function_id[0x10];
5888
5889         u8         reserved_at_60[0x20];
5890 };
5891
5892 struct mlx5_ifc_drain_dct_out_bits {
5893         u8         status[0x8];
5894         u8         reserved_at_8[0x18];
5895
5896         u8         syndrome[0x20];
5897
5898         u8         reserved_at_40[0x40];
5899 };
5900
5901 struct mlx5_ifc_drain_dct_in_bits {
5902         u8         opcode[0x10];
5903         u8         reserved_at_10[0x10];
5904
5905         u8         reserved_at_20[0x10];
5906         u8         op_mod[0x10];
5907
5908         u8         reserved_at_40[0x8];
5909         u8         dctn[0x18];
5910
5911         u8         reserved_at_60[0x20];
5912 };
5913
5914 struct mlx5_ifc_disable_hca_out_bits {
5915         u8         status[0x8];
5916         u8         reserved_at_8[0x18];
5917
5918         u8         syndrome[0x20];
5919
5920         u8         reserved_at_40[0x20];
5921 };
5922
5923 struct mlx5_ifc_disable_hca_in_bits {
5924         u8         opcode[0x10];
5925         u8         reserved_at_10[0x10];
5926
5927         u8         reserved_at_20[0x10];
5928         u8         op_mod[0x10];
5929
5930         u8         reserved_at_40[0x10];
5931         u8         function_id[0x10];
5932
5933         u8         reserved_at_60[0x20];
5934 };
5935
5936 struct mlx5_ifc_detach_from_mcg_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_at_8[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_at_40[0x40];
5943 };
5944
5945 struct mlx5_ifc_detach_from_mcg_in_bits {
5946         u8         opcode[0x10];
5947         u8         reserved_at_10[0x10];
5948
5949         u8         reserved_at_20[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_at_40[0x8];
5953         u8         qpn[0x18];
5954
5955         u8         reserved_at_60[0x20];
5956
5957         u8         multicast_gid[16][0x8];
5958 };
5959
5960 struct mlx5_ifc_destroy_xrq_out_bits {
5961         u8         status[0x8];
5962         u8         reserved_at_8[0x18];
5963
5964         u8         syndrome[0x20];
5965
5966         u8         reserved_at_40[0x40];
5967 };
5968
5969 struct mlx5_ifc_destroy_xrq_in_bits {
5970         u8         opcode[0x10];
5971         u8         reserved_at_10[0x10];
5972
5973         u8         reserved_at_20[0x10];
5974         u8         op_mod[0x10];
5975
5976         u8         reserved_at_40[0x8];
5977         u8         xrqn[0x18];
5978
5979         u8         reserved_at_60[0x20];
5980 };
5981
5982 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5983         u8         status[0x8];
5984         u8         reserved_at_8[0x18];
5985
5986         u8         syndrome[0x20];
5987
5988         u8         reserved_at_40[0x40];
5989 };
5990
5991 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5992         u8         opcode[0x10];
5993         u8         reserved_at_10[0x10];
5994
5995         u8         reserved_at_20[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         reserved_at_40[0x8];
5999         u8         xrc_srqn[0x18];
6000
6001         u8         reserved_at_60[0x20];
6002 };
6003
6004 struct mlx5_ifc_destroy_tis_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x40];
6011 };
6012
6013 struct mlx5_ifc_destroy_tis_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_at_10[0x10];
6016
6017         u8         reserved_at_20[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_at_40[0x8];
6021         u8         tisn[0x18];
6022
6023         u8         reserved_at_60[0x20];
6024 };
6025
6026 struct mlx5_ifc_destroy_tir_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_at_8[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_at_40[0x40];
6033 };
6034
6035 struct mlx5_ifc_destroy_tir_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_at_10[0x10];
6038
6039         u8         reserved_at_20[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_at_40[0x8];
6043         u8         tirn[0x18];
6044
6045         u8         reserved_at_60[0x20];
6046 };
6047
6048 struct mlx5_ifc_destroy_srq_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_at_8[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_at_40[0x40];
6055 };
6056
6057 struct mlx5_ifc_destroy_srq_in_bits {
6058         u8         opcode[0x10];
6059         u8         reserved_at_10[0x10];
6060
6061         u8         reserved_at_20[0x10];
6062         u8         op_mod[0x10];
6063
6064         u8         reserved_at_40[0x8];
6065         u8         srqn[0x18];
6066
6067         u8         reserved_at_60[0x20];
6068 };
6069
6070 struct mlx5_ifc_destroy_sq_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x40];
6077 };
6078
6079 struct mlx5_ifc_destroy_sq_in_bits {
6080         u8         opcode[0x10];
6081         u8         reserved_at_10[0x10];
6082
6083         u8         reserved_at_20[0x10];
6084         u8         op_mod[0x10];
6085
6086         u8         reserved_at_40[0x8];
6087         u8         sqn[0x18];
6088
6089         u8         reserved_at_60[0x20];
6090 };
6091
6092 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0x1c0];
6099 };
6100
6101 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6102         u8         opcode[0x10];
6103         u8         reserved_at_10[0x10];
6104
6105         u8         reserved_at_20[0x10];
6106         u8         op_mod[0x10];
6107
6108         u8         scheduling_hierarchy[0x8];
6109         u8         reserved_at_48[0x18];
6110
6111         u8         scheduling_element_id[0x20];
6112
6113         u8         reserved_at_80[0x180];
6114 };
6115
6116 struct mlx5_ifc_destroy_rqt_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x40];
6123 };
6124
6125 struct mlx5_ifc_destroy_rqt_in_bits {
6126         u8         opcode[0x10];
6127         u8         reserved_at_10[0x10];
6128
6129         u8         reserved_at_20[0x10];
6130         u8         op_mod[0x10];
6131
6132         u8         reserved_at_40[0x8];
6133         u8         rqtn[0x18];
6134
6135         u8         reserved_at_60[0x20];
6136 };
6137
6138 struct mlx5_ifc_destroy_rq_out_bits {
6139         u8         status[0x8];
6140         u8         reserved_at_8[0x18];
6141
6142         u8         syndrome[0x20];
6143
6144         u8         reserved_at_40[0x40];
6145 };
6146
6147 struct mlx5_ifc_destroy_rq_in_bits {
6148         u8         opcode[0x10];
6149         u8         reserved_at_10[0x10];
6150
6151         u8         reserved_at_20[0x10];
6152         u8         op_mod[0x10];
6153
6154         u8         reserved_at_40[0x8];
6155         u8         rqn[0x18];
6156
6157         u8         reserved_at_60[0x20];
6158 };
6159
6160 struct mlx5_ifc_set_delay_drop_params_in_bits {
6161         u8         opcode[0x10];
6162         u8         reserved_at_10[0x10];
6163
6164         u8         reserved_at_20[0x10];
6165         u8         op_mod[0x10];
6166
6167         u8         reserved_at_40[0x20];
6168
6169         u8         reserved_at_60[0x10];
6170         u8         delay_drop_timeout[0x10];
6171 };
6172
6173 struct mlx5_ifc_set_delay_drop_params_out_bits {
6174         u8         status[0x8];
6175         u8         reserved_at_8[0x18];
6176
6177         u8         syndrome[0x20];
6178
6179         u8         reserved_at_40[0x40];
6180 };
6181
6182 struct mlx5_ifc_destroy_rmp_out_bits {
6183         u8         status[0x8];
6184         u8         reserved_at_8[0x18];
6185
6186         u8         syndrome[0x20];
6187
6188         u8         reserved_at_40[0x40];
6189 };
6190
6191 struct mlx5_ifc_destroy_rmp_in_bits {
6192         u8         opcode[0x10];
6193         u8         reserved_at_10[0x10];
6194
6195         u8         reserved_at_20[0x10];
6196         u8         op_mod[0x10];
6197
6198         u8         reserved_at_40[0x8];
6199         u8         rmpn[0x18];
6200
6201         u8         reserved_at_60[0x20];
6202 };
6203
6204 struct mlx5_ifc_destroy_qp_out_bits {
6205         u8         status[0x8];
6206         u8         reserved_at_8[0x18];
6207
6208         u8         syndrome[0x20];
6209
6210         u8         reserved_at_40[0x40];
6211 };
6212
6213 struct mlx5_ifc_destroy_qp_in_bits {
6214         u8         opcode[0x10];
6215         u8         reserved_at_10[0x10];
6216
6217         u8         reserved_at_20[0x10];
6218         u8         op_mod[0x10];
6219
6220         u8         reserved_at_40[0x8];
6221         u8         qpn[0x18];
6222
6223         u8         reserved_at_60[0x20];
6224 };
6225
6226 struct mlx5_ifc_destroy_psv_out_bits {
6227         u8         status[0x8];
6228         u8         reserved_at_8[0x18];
6229
6230         u8         syndrome[0x20];
6231
6232         u8         reserved_at_40[0x40];
6233 };
6234
6235 struct mlx5_ifc_destroy_psv_in_bits {
6236         u8         opcode[0x10];
6237         u8         reserved_at_10[0x10];
6238
6239         u8         reserved_at_20[0x10];
6240         u8         op_mod[0x10];
6241
6242         u8         reserved_at_40[0x8];
6243         u8         psvn[0x18];
6244
6245         u8         reserved_at_60[0x20];
6246 };
6247
6248 struct mlx5_ifc_destroy_mkey_out_bits {
6249         u8         status[0x8];
6250         u8         reserved_at_8[0x18];
6251
6252         u8         syndrome[0x20];
6253
6254         u8         reserved_at_40[0x40];
6255 };
6256
6257 struct mlx5_ifc_destroy_mkey_in_bits {
6258         u8         opcode[0x10];
6259         u8         reserved_at_10[0x10];
6260
6261         u8         reserved_at_20[0x10];
6262         u8         op_mod[0x10];
6263
6264         u8         reserved_at_40[0x8];
6265         u8         mkey_index[0x18];
6266
6267         u8         reserved_at_60[0x20];
6268 };
6269
6270 struct mlx5_ifc_destroy_flow_table_out_bits {
6271         u8         status[0x8];
6272         u8         reserved_at_8[0x18];
6273
6274         u8         syndrome[0x20];
6275
6276         u8         reserved_at_40[0x40];
6277 };
6278
6279 struct mlx5_ifc_destroy_flow_table_in_bits {
6280         u8         opcode[0x10];
6281         u8         reserved_at_10[0x10];
6282
6283         u8         reserved_at_20[0x10];
6284         u8         op_mod[0x10];
6285
6286         u8         other_vport[0x1];
6287         u8         reserved_at_41[0xf];
6288         u8         vport_number[0x10];
6289
6290         u8         reserved_at_60[0x20];
6291
6292         u8         table_type[0x8];
6293         u8         reserved_at_88[0x18];
6294
6295         u8         reserved_at_a0[0x8];
6296         u8         table_id[0x18];
6297
6298         u8         reserved_at_c0[0x140];
6299 };
6300
6301 struct mlx5_ifc_destroy_flow_group_out_bits {
6302         u8         status[0x8];
6303         u8         reserved_at_8[0x18];
6304
6305         u8         syndrome[0x20];
6306
6307         u8         reserved_at_40[0x40];
6308 };
6309
6310 struct mlx5_ifc_destroy_flow_group_in_bits {
6311         u8         opcode[0x10];
6312         u8         reserved_at_10[0x10];
6313
6314         u8         reserved_at_20[0x10];
6315         u8         op_mod[0x10];
6316
6317         u8         other_vport[0x1];
6318         u8         reserved_at_41[0xf];
6319         u8         vport_number[0x10];
6320
6321         u8         reserved_at_60[0x20];
6322
6323         u8         table_type[0x8];
6324         u8         reserved_at_88[0x18];
6325
6326         u8         reserved_at_a0[0x8];
6327         u8         table_id[0x18];
6328
6329         u8         group_id[0x20];
6330
6331         u8         reserved_at_e0[0x120];
6332 };
6333
6334 struct mlx5_ifc_destroy_eq_out_bits {
6335         u8         status[0x8];
6336         u8         reserved_at_8[0x18];
6337
6338         u8         syndrome[0x20];
6339
6340         u8         reserved_at_40[0x40];
6341 };
6342
6343 struct mlx5_ifc_destroy_eq_in_bits {
6344         u8         opcode[0x10];
6345         u8         reserved_at_10[0x10];
6346
6347         u8         reserved_at_20[0x10];
6348         u8         op_mod[0x10];
6349
6350         u8         reserved_at_40[0x18];
6351         u8         eq_number[0x8];
6352
6353         u8         reserved_at_60[0x20];
6354 };
6355
6356 struct mlx5_ifc_destroy_dct_out_bits {
6357         u8         status[0x8];
6358         u8         reserved_at_8[0x18];
6359
6360         u8         syndrome[0x20];
6361
6362         u8         reserved_at_40[0x40];
6363 };
6364
6365 struct mlx5_ifc_destroy_dct_in_bits {
6366         u8         opcode[0x10];
6367         u8         reserved_at_10[0x10];
6368
6369         u8         reserved_at_20[0x10];
6370         u8         op_mod[0x10];
6371
6372         u8         reserved_at_40[0x8];
6373         u8         dctn[0x18];
6374
6375         u8         reserved_at_60[0x20];
6376 };
6377
6378 struct mlx5_ifc_destroy_cq_out_bits {
6379         u8         status[0x8];
6380         u8         reserved_at_8[0x18];
6381
6382         u8         syndrome[0x20];
6383
6384         u8         reserved_at_40[0x40];
6385 };
6386
6387 struct mlx5_ifc_destroy_cq_in_bits {
6388         u8         opcode[0x10];
6389         u8         reserved_at_10[0x10];
6390
6391         u8         reserved_at_20[0x10];
6392         u8         op_mod[0x10];
6393
6394         u8         reserved_at_40[0x8];
6395         u8         cqn[0x18];
6396
6397         u8         reserved_at_60[0x20];
6398 };
6399
6400 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6401         u8         status[0x8];
6402         u8         reserved_at_8[0x18];
6403
6404         u8         syndrome[0x20];
6405
6406         u8         reserved_at_40[0x40];
6407 };
6408
6409 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6410         u8         opcode[0x10];
6411         u8         reserved_at_10[0x10];
6412
6413         u8         reserved_at_20[0x10];
6414         u8         op_mod[0x10];
6415
6416         u8         reserved_at_40[0x20];
6417
6418         u8         reserved_at_60[0x10];
6419         u8         vxlan_udp_port[0x10];
6420 };
6421
6422 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6423         u8         status[0x8];
6424         u8         reserved_at_8[0x18];
6425
6426         u8         syndrome[0x20];
6427
6428         u8         reserved_at_40[0x40];
6429 };
6430
6431 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6432         u8         opcode[0x10];
6433         u8         reserved_at_10[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         reserved_at_40[0x60];
6439
6440         u8         reserved_at_a0[0x8];
6441         u8         table_index[0x18];
6442
6443         u8         reserved_at_c0[0x140];
6444 };
6445
6446 struct mlx5_ifc_delete_fte_out_bits {
6447         u8         status[0x8];
6448         u8         reserved_at_8[0x18];
6449
6450         u8         syndrome[0x20];
6451
6452         u8         reserved_at_40[0x40];
6453 };
6454
6455 struct mlx5_ifc_delete_fte_in_bits {
6456         u8         opcode[0x10];
6457         u8         reserved_at_10[0x10];
6458
6459         u8         reserved_at_20[0x10];
6460         u8         op_mod[0x10];
6461
6462         u8         other_vport[0x1];
6463         u8         reserved_at_41[0xf];
6464         u8         vport_number[0x10];
6465
6466         u8         reserved_at_60[0x20];
6467
6468         u8         table_type[0x8];
6469         u8         reserved_at_88[0x18];
6470
6471         u8         reserved_at_a0[0x8];
6472         u8         table_id[0x18];
6473
6474         u8         reserved_at_c0[0x40];
6475
6476         u8         flow_index[0x20];
6477
6478         u8         reserved_at_120[0xe0];
6479 };
6480
6481 struct mlx5_ifc_dealloc_xrcd_out_bits {
6482         u8         status[0x8];
6483         u8         reserved_at_8[0x18];
6484
6485         u8         syndrome[0x20];
6486
6487         u8         reserved_at_40[0x40];
6488 };
6489
6490 struct mlx5_ifc_dealloc_xrcd_in_bits {
6491         u8         opcode[0x10];
6492         u8         reserved_at_10[0x10];
6493
6494         u8         reserved_at_20[0x10];
6495         u8         op_mod[0x10];
6496
6497         u8         reserved_at_40[0x8];
6498         u8         xrcd[0x18];
6499
6500         u8         reserved_at_60[0x20];
6501 };
6502
6503 struct mlx5_ifc_dealloc_uar_out_bits {
6504         u8         status[0x8];
6505         u8         reserved_at_8[0x18];
6506
6507         u8         syndrome[0x20];
6508
6509         u8         reserved_at_40[0x40];
6510 };
6511
6512 struct mlx5_ifc_dealloc_uar_in_bits {
6513         u8         opcode[0x10];
6514         u8         reserved_at_10[0x10];
6515
6516         u8         reserved_at_20[0x10];
6517         u8         op_mod[0x10];
6518
6519         u8         reserved_at_40[0x8];
6520         u8         uar[0x18];
6521
6522         u8         reserved_at_60[0x20];
6523 };
6524
6525 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6526         u8         status[0x8];
6527         u8         reserved_at_8[0x18];
6528
6529         u8         syndrome[0x20];
6530
6531         u8         reserved_at_40[0x40];
6532 };
6533
6534 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6535         u8         opcode[0x10];
6536         u8         reserved_at_10[0x10];
6537
6538         u8         reserved_at_20[0x10];
6539         u8         op_mod[0x10];
6540
6541         u8         reserved_at_40[0x8];
6542         u8         transport_domain[0x18];
6543
6544         u8         reserved_at_60[0x20];
6545 };
6546
6547 struct mlx5_ifc_dealloc_q_counter_out_bits {
6548         u8         status[0x8];
6549         u8         reserved_at_8[0x18];
6550
6551         u8         syndrome[0x20];
6552
6553         u8         reserved_at_40[0x40];
6554 };
6555
6556 struct mlx5_ifc_dealloc_q_counter_in_bits {
6557         u8         opcode[0x10];
6558         u8         reserved_at_10[0x10];
6559
6560         u8         reserved_at_20[0x10];
6561         u8         op_mod[0x10];
6562
6563         u8         reserved_at_40[0x18];
6564         u8         counter_set_id[0x8];
6565
6566         u8         reserved_at_60[0x20];
6567 };
6568
6569 struct mlx5_ifc_dealloc_pd_out_bits {
6570         u8         status[0x8];
6571         u8         reserved_at_8[0x18];
6572
6573         u8         syndrome[0x20];
6574
6575         u8         reserved_at_40[0x40];
6576 };
6577
6578 struct mlx5_ifc_dealloc_pd_in_bits {
6579         u8         opcode[0x10];
6580         u8         reserved_at_10[0x10];
6581
6582         u8         reserved_at_20[0x10];
6583         u8         op_mod[0x10];
6584
6585         u8         reserved_at_40[0x8];
6586         u8         pd[0x18];
6587
6588         u8         reserved_at_60[0x20];
6589 };
6590
6591 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6592         u8         status[0x8];
6593         u8         reserved_at_8[0x18];
6594
6595         u8         syndrome[0x20];
6596
6597         u8         reserved_at_40[0x40];
6598 };
6599
6600 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6601         u8         opcode[0x10];
6602         u8         reserved_at_10[0x10];
6603
6604         u8         reserved_at_20[0x10];
6605         u8         op_mod[0x10];
6606
6607         u8         flow_counter_id[0x20];
6608
6609         u8         reserved_at_60[0x20];
6610 };
6611
6612 struct mlx5_ifc_create_xrq_out_bits {
6613         u8         status[0x8];
6614         u8         reserved_at_8[0x18];
6615
6616         u8         syndrome[0x20];
6617
6618         u8         reserved_at_40[0x8];
6619         u8         xrqn[0x18];
6620
6621         u8         reserved_at_60[0x20];
6622 };
6623
6624 struct mlx5_ifc_create_xrq_in_bits {
6625         u8         opcode[0x10];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x40];
6632
6633         struct mlx5_ifc_xrqc_bits xrq_context;
6634 };
6635
6636 struct mlx5_ifc_create_xrc_srq_out_bits {
6637         u8         status[0x8];
6638         u8         reserved_at_8[0x18];
6639
6640         u8         syndrome[0x20];
6641
6642         u8         reserved_at_40[0x8];
6643         u8         xrc_srqn[0x18];
6644
6645         u8         reserved_at_60[0x20];
6646 };
6647
6648 struct mlx5_ifc_create_xrc_srq_in_bits {
6649         u8         opcode[0x10];
6650         u8         reserved_at_10[0x10];
6651
6652         u8         reserved_at_20[0x10];
6653         u8         op_mod[0x10];
6654
6655         u8         reserved_at_40[0x40];
6656
6657         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6658
6659         u8         reserved_at_280[0x600];
6660
6661         u8         pas[0][0x40];
6662 };
6663
6664 struct mlx5_ifc_create_tis_out_bits {
6665         u8         status[0x8];
6666         u8         reserved_at_8[0x18];
6667
6668         u8         syndrome[0x20];
6669
6670         u8         reserved_at_40[0x8];
6671         u8         tisn[0x18];
6672
6673         u8         reserved_at_60[0x20];
6674 };
6675
6676 struct mlx5_ifc_create_tis_in_bits {
6677         u8         opcode[0x10];
6678         u8         reserved_at_10[0x10];
6679
6680         u8         reserved_at_20[0x10];
6681         u8         op_mod[0x10];
6682
6683         u8         reserved_at_40[0xc0];
6684
6685         struct mlx5_ifc_tisc_bits ctx;
6686 };
6687
6688 struct mlx5_ifc_create_tir_out_bits {
6689         u8         status[0x8];
6690         u8         reserved_at_8[0x18];
6691
6692         u8         syndrome[0x20];
6693
6694         u8         reserved_at_40[0x8];
6695         u8         tirn[0x18];
6696
6697         u8         reserved_at_60[0x20];
6698 };
6699
6700 struct mlx5_ifc_create_tir_in_bits {
6701         u8         opcode[0x10];
6702         u8         reserved_at_10[0x10];
6703
6704         u8         reserved_at_20[0x10];
6705         u8         op_mod[0x10];
6706
6707         u8         reserved_at_40[0xc0];
6708
6709         struct mlx5_ifc_tirc_bits ctx;
6710 };
6711
6712 struct mlx5_ifc_create_srq_out_bits {
6713         u8         status[0x8];
6714         u8         reserved_at_8[0x18];
6715
6716         u8         syndrome[0x20];
6717
6718         u8         reserved_at_40[0x8];
6719         u8         srqn[0x18];
6720
6721         u8         reserved_at_60[0x20];
6722 };
6723
6724 struct mlx5_ifc_create_srq_in_bits {
6725         u8         opcode[0x10];
6726         u8         reserved_at_10[0x10];
6727
6728         u8         reserved_at_20[0x10];
6729         u8         op_mod[0x10];
6730
6731         u8         reserved_at_40[0x40];
6732
6733         struct mlx5_ifc_srqc_bits srq_context_entry;
6734
6735         u8         reserved_at_280[0x600];
6736
6737         u8         pas[0][0x40];
6738 };
6739
6740 struct mlx5_ifc_create_sq_out_bits {
6741         u8         status[0x8];
6742         u8         reserved_at_8[0x18];
6743
6744         u8         syndrome[0x20];
6745
6746         u8         reserved_at_40[0x8];
6747         u8         sqn[0x18];
6748
6749         u8         reserved_at_60[0x20];
6750 };
6751
6752 struct mlx5_ifc_create_sq_in_bits {
6753         u8         opcode[0x10];
6754         u8         reserved_at_10[0x10];
6755
6756         u8         reserved_at_20[0x10];
6757         u8         op_mod[0x10];
6758
6759         u8         reserved_at_40[0xc0];
6760
6761         struct mlx5_ifc_sqc_bits ctx;
6762 };
6763
6764 struct mlx5_ifc_create_scheduling_element_out_bits {
6765         u8         status[0x8];
6766         u8         reserved_at_8[0x18];
6767
6768         u8         syndrome[0x20];
6769
6770         u8         reserved_at_40[0x40];
6771
6772         u8         scheduling_element_id[0x20];
6773
6774         u8         reserved_at_a0[0x160];
6775 };
6776
6777 struct mlx5_ifc_create_scheduling_element_in_bits {
6778         u8         opcode[0x10];
6779         u8         reserved_at_10[0x10];
6780
6781         u8         reserved_at_20[0x10];
6782         u8         op_mod[0x10];
6783
6784         u8         scheduling_hierarchy[0x8];
6785         u8         reserved_at_48[0x18];
6786
6787         u8         reserved_at_60[0xa0];
6788
6789         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6790
6791         u8         reserved_at_300[0x100];
6792 };
6793
6794 struct mlx5_ifc_create_rqt_out_bits {
6795         u8         status[0x8];
6796         u8         reserved_at_8[0x18];
6797
6798         u8         syndrome[0x20];
6799
6800         u8         reserved_at_40[0x8];
6801         u8         rqtn[0x18];
6802
6803         u8         reserved_at_60[0x20];
6804 };
6805
6806 struct mlx5_ifc_create_rqt_in_bits {
6807         u8         opcode[0x10];
6808         u8         reserved_at_10[0x10];
6809
6810         u8         reserved_at_20[0x10];
6811         u8         op_mod[0x10];
6812
6813         u8         reserved_at_40[0xc0];
6814
6815         struct mlx5_ifc_rqtc_bits rqt_context;
6816 };
6817
6818 struct mlx5_ifc_create_rq_out_bits {
6819         u8         status[0x8];
6820         u8         reserved_at_8[0x18];
6821
6822         u8         syndrome[0x20];
6823
6824         u8         reserved_at_40[0x8];
6825         u8         rqn[0x18];
6826
6827         u8         reserved_at_60[0x20];
6828 };
6829
6830 struct mlx5_ifc_create_rq_in_bits {
6831         u8         opcode[0x10];
6832         u8         reserved_at_10[0x10];
6833
6834         u8         reserved_at_20[0x10];
6835         u8         op_mod[0x10];
6836
6837         u8         reserved_at_40[0xc0];
6838
6839         struct mlx5_ifc_rqc_bits ctx;
6840 };
6841
6842 struct mlx5_ifc_create_rmp_out_bits {
6843         u8         status[0x8];
6844         u8         reserved_at_8[0x18];
6845
6846         u8         syndrome[0x20];
6847
6848         u8         reserved_at_40[0x8];
6849         u8         rmpn[0x18];
6850
6851         u8         reserved_at_60[0x20];
6852 };
6853
6854 struct mlx5_ifc_create_rmp_in_bits {
6855         u8         opcode[0x10];
6856         u8         reserved_at_10[0x10];
6857
6858         u8         reserved_at_20[0x10];
6859         u8         op_mod[0x10];
6860
6861         u8         reserved_at_40[0xc0];
6862
6863         struct mlx5_ifc_rmpc_bits ctx;
6864 };
6865
6866 struct mlx5_ifc_create_qp_out_bits {
6867         u8         status[0x8];
6868         u8         reserved_at_8[0x18];
6869
6870         u8         syndrome[0x20];
6871
6872         u8         reserved_at_40[0x8];
6873         u8         qpn[0x18];
6874
6875         u8         reserved_at_60[0x20];
6876 };
6877
6878 struct mlx5_ifc_create_qp_in_bits {
6879         u8         opcode[0x10];
6880         u8         reserved_at_10[0x10];
6881
6882         u8         reserved_at_20[0x10];
6883         u8         op_mod[0x10];
6884
6885         u8         reserved_at_40[0x40];
6886
6887         u8         opt_param_mask[0x20];
6888
6889         u8         reserved_at_a0[0x20];
6890
6891         struct mlx5_ifc_qpc_bits qpc;
6892
6893         u8         reserved_at_800[0x80];
6894
6895         u8         pas[0][0x40];
6896 };
6897
6898 struct mlx5_ifc_create_psv_out_bits {
6899         u8         status[0x8];
6900         u8         reserved_at_8[0x18];
6901
6902         u8         syndrome[0x20];
6903
6904         u8         reserved_at_40[0x40];
6905
6906         u8         reserved_at_80[0x8];
6907         u8         psv0_index[0x18];
6908
6909         u8         reserved_at_a0[0x8];
6910         u8         psv1_index[0x18];
6911
6912         u8         reserved_at_c0[0x8];
6913         u8         psv2_index[0x18];
6914
6915         u8         reserved_at_e0[0x8];
6916         u8         psv3_index[0x18];
6917 };
6918
6919 struct mlx5_ifc_create_psv_in_bits {
6920         u8         opcode[0x10];
6921         u8         reserved_at_10[0x10];
6922
6923         u8         reserved_at_20[0x10];
6924         u8         op_mod[0x10];
6925
6926         u8         num_psv[0x4];
6927         u8         reserved_at_44[0x4];
6928         u8         pd[0x18];
6929
6930         u8         reserved_at_60[0x20];
6931 };
6932
6933 struct mlx5_ifc_create_mkey_out_bits {
6934         u8         status[0x8];
6935         u8         reserved_at_8[0x18];
6936
6937         u8         syndrome[0x20];
6938
6939         u8         reserved_at_40[0x8];
6940         u8         mkey_index[0x18];
6941
6942         u8         reserved_at_60[0x20];
6943 };
6944
6945 struct mlx5_ifc_create_mkey_in_bits {
6946         u8         opcode[0x10];
6947         u8         reserved_at_10[0x10];
6948
6949         u8         reserved_at_20[0x10];
6950         u8         op_mod[0x10];
6951
6952         u8         reserved_at_40[0x20];
6953
6954         u8         pg_access[0x1];
6955         u8         reserved_at_61[0x1f];
6956
6957         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6958
6959         u8         reserved_at_280[0x80];
6960
6961         u8         translations_octword_actual_size[0x20];
6962
6963         u8         reserved_at_320[0x560];
6964
6965         u8         klm_pas_mtt[0][0x20];
6966 };
6967
6968 struct mlx5_ifc_create_flow_table_out_bits {
6969         u8         status[0x8];
6970         u8         reserved_at_8[0x18];
6971
6972         u8         syndrome[0x20];
6973
6974         u8         reserved_at_40[0x8];
6975         u8         table_id[0x18];
6976
6977         u8         reserved_at_60[0x20];
6978 };
6979
6980 struct mlx5_ifc_flow_table_context_bits {
6981         u8         encap_en[0x1];
6982         u8         decap_en[0x1];
6983         u8         reserved_at_2[0x2];
6984         u8         table_miss_action[0x4];
6985         u8         level[0x8];
6986         u8         reserved_at_10[0x8];
6987         u8         log_size[0x8];
6988
6989         u8         reserved_at_20[0x8];
6990         u8         table_miss_id[0x18];
6991
6992         u8         reserved_at_40[0x8];
6993         u8         lag_master_next_table_id[0x18];
6994
6995         u8         reserved_at_60[0xe0];
6996 };
6997
6998 struct mlx5_ifc_create_flow_table_in_bits {
6999         u8         opcode[0x10];
7000         u8         reserved_at_10[0x10];
7001
7002         u8         reserved_at_20[0x10];
7003         u8         op_mod[0x10];
7004
7005         u8         other_vport[0x1];
7006         u8         reserved_at_41[0xf];
7007         u8         vport_number[0x10];
7008
7009         u8         reserved_at_60[0x20];
7010
7011         u8         table_type[0x8];
7012         u8         reserved_at_88[0x18];
7013
7014         u8         reserved_at_a0[0x20];
7015
7016         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7017 };
7018
7019 struct mlx5_ifc_create_flow_group_out_bits {
7020         u8         status[0x8];
7021         u8         reserved_at_8[0x18];
7022
7023         u8         syndrome[0x20];
7024
7025         u8         reserved_at_40[0x8];
7026         u8         group_id[0x18];
7027
7028         u8         reserved_at_60[0x20];
7029 };
7030
7031 enum {
7032         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7033         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7034         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7035         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7036 };
7037
7038 struct mlx5_ifc_create_flow_group_in_bits {
7039         u8         opcode[0x10];
7040         u8         reserved_at_10[0x10];
7041
7042         u8         reserved_at_20[0x10];
7043         u8         op_mod[0x10];
7044
7045         u8         other_vport[0x1];
7046         u8         reserved_at_41[0xf];
7047         u8         vport_number[0x10];
7048
7049         u8         reserved_at_60[0x20];
7050
7051         u8         table_type[0x8];
7052         u8         reserved_at_88[0x18];
7053
7054         u8         reserved_at_a0[0x8];
7055         u8         table_id[0x18];
7056
7057         u8         source_eswitch_owner_vhca_id_valid[0x1];
7058
7059         u8         reserved_at_c1[0x1f];
7060
7061         u8         start_flow_index[0x20];
7062
7063         u8         reserved_at_100[0x20];
7064
7065         u8         end_flow_index[0x20];
7066
7067         u8         reserved_at_140[0xa0];
7068
7069         u8         reserved_at_1e0[0x18];
7070         u8         match_criteria_enable[0x8];
7071
7072         struct mlx5_ifc_fte_match_param_bits match_criteria;
7073
7074         u8         reserved_at_1200[0xe00];
7075 };
7076
7077 struct mlx5_ifc_create_eq_out_bits {
7078         u8         status[0x8];
7079         u8         reserved_at_8[0x18];
7080
7081         u8         syndrome[0x20];
7082
7083         u8         reserved_at_40[0x18];
7084         u8         eq_number[0x8];
7085
7086         u8         reserved_at_60[0x20];
7087 };
7088
7089 struct mlx5_ifc_create_eq_in_bits {
7090         u8         opcode[0x10];
7091         u8         reserved_at_10[0x10];
7092
7093         u8         reserved_at_20[0x10];
7094         u8         op_mod[0x10];
7095
7096         u8         reserved_at_40[0x40];
7097
7098         struct mlx5_ifc_eqc_bits eq_context_entry;
7099
7100         u8         reserved_at_280[0x40];
7101
7102         u8         event_bitmask[0x40];
7103
7104         u8         reserved_at_300[0x580];
7105
7106         u8         pas[0][0x40];
7107 };
7108
7109 struct mlx5_ifc_create_dct_out_bits {
7110         u8         status[0x8];
7111         u8         reserved_at_8[0x18];
7112
7113         u8         syndrome[0x20];
7114
7115         u8         reserved_at_40[0x8];
7116         u8         dctn[0x18];
7117
7118         u8         reserved_at_60[0x20];
7119 };
7120
7121 struct mlx5_ifc_create_dct_in_bits {
7122         u8         opcode[0x10];
7123         u8         reserved_at_10[0x10];
7124
7125         u8         reserved_at_20[0x10];
7126         u8         op_mod[0x10];
7127
7128         u8         reserved_at_40[0x40];
7129
7130         struct mlx5_ifc_dctc_bits dct_context_entry;
7131
7132         u8         reserved_at_280[0x180];
7133 };
7134
7135 struct mlx5_ifc_create_cq_out_bits {
7136         u8         status[0x8];
7137         u8         reserved_at_8[0x18];
7138
7139         u8         syndrome[0x20];
7140
7141         u8         reserved_at_40[0x8];
7142         u8         cqn[0x18];
7143
7144         u8         reserved_at_60[0x20];
7145 };
7146
7147 struct mlx5_ifc_create_cq_in_bits {
7148         u8         opcode[0x10];
7149         u8         reserved_at_10[0x10];
7150
7151         u8         reserved_at_20[0x10];
7152         u8         op_mod[0x10];
7153
7154         u8         reserved_at_40[0x40];
7155
7156         struct mlx5_ifc_cqc_bits cq_context;
7157
7158         u8         reserved_at_280[0x600];
7159
7160         u8         pas[0][0x40];
7161 };
7162
7163 struct mlx5_ifc_config_int_moderation_out_bits {
7164         u8         status[0x8];
7165         u8         reserved_at_8[0x18];
7166
7167         u8         syndrome[0x20];
7168
7169         u8         reserved_at_40[0x4];
7170         u8         min_delay[0xc];
7171         u8         int_vector[0x10];
7172
7173         u8         reserved_at_60[0x20];
7174 };
7175
7176 enum {
7177         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7178         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7179 };
7180
7181 struct mlx5_ifc_config_int_moderation_in_bits {
7182         u8         opcode[0x10];
7183         u8         reserved_at_10[0x10];
7184
7185         u8         reserved_at_20[0x10];
7186         u8         op_mod[0x10];
7187
7188         u8         reserved_at_40[0x4];
7189         u8         min_delay[0xc];
7190         u8         int_vector[0x10];
7191
7192         u8         reserved_at_60[0x20];
7193 };
7194
7195 struct mlx5_ifc_attach_to_mcg_out_bits {
7196         u8         status[0x8];
7197         u8         reserved_at_8[0x18];
7198
7199         u8         syndrome[0x20];
7200
7201         u8         reserved_at_40[0x40];
7202 };
7203
7204 struct mlx5_ifc_attach_to_mcg_in_bits {
7205         u8         opcode[0x10];
7206         u8         reserved_at_10[0x10];
7207
7208         u8         reserved_at_20[0x10];
7209         u8         op_mod[0x10];
7210
7211         u8         reserved_at_40[0x8];
7212         u8         qpn[0x18];
7213
7214         u8         reserved_at_60[0x20];
7215
7216         u8         multicast_gid[16][0x8];
7217 };
7218
7219 struct mlx5_ifc_arm_xrq_out_bits {
7220         u8         status[0x8];
7221         u8         reserved_at_8[0x18];
7222
7223         u8         syndrome[0x20];
7224
7225         u8         reserved_at_40[0x40];
7226 };
7227
7228 struct mlx5_ifc_arm_xrq_in_bits {
7229         u8         opcode[0x10];
7230         u8         reserved_at_10[0x10];
7231
7232         u8         reserved_at_20[0x10];
7233         u8         op_mod[0x10];
7234
7235         u8         reserved_at_40[0x8];
7236         u8         xrqn[0x18];
7237
7238         u8         reserved_at_60[0x10];
7239         u8         lwm[0x10];
7240 };
7241
7242 struct mlx5_ifc_arm_xrc_srq_out_bits {
7243         u8         status[0x8];
7244         u8         reserved_at_8[0x18];
7245
7246         u8         syndrome[0x20];
7247
7248         u8         reserved_at_40[0x40];
7249 };
7250
7251 enum {
7252         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7253 };
7254
7255 struct mlx5_ifc_arm_xrc_srq_in_bits {
7256         u8         opcode[0x10];
7257         u8         reserved_at_10[0x10];
7258
7259         u8         reserved_at_20[0x10];
7260         u8         op_mod[0x10];
7261
7262         u8         reserved_at_40[0x8];
7263         u8         xrc_srqn[0x18];
7264
7265         u8         reserved_at_60[0x10];
7266         u8         lwm[0x10];
7267 };
7268
7269 struct mlx5_ifc_arm_rq_out_bits {
7270         u8         status[0x8];
7271         u8         reserved_at_8[0x18];
7272
7273         u8         syndrome[0x20];
7274
7275         u8         reserved_at_40[0x40];
7276 };
7277
7278 enum {
7279         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7280         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7281 };
7282
7283 struct mlx5_ifc_arm_rq_in_bits {
7284         u8         opcode[0x10];
7285         u8         reserved_at_10[0x10];
7286
7287         u8         reserved_at_20[0x10];
7288         u8         op_mod[0x10];
7289
7290         u8         reserved_at_40[0x8];
7291         u8         srq_number[0x18];
7292
7293         u8         reserved_at_60[0x10];
7294         u8         lwm[0x10];
7295 };
7296
7297 struct mlx5_ifc_arm_dct_out_bits {
7298         u8         status[0x8];
7299         u8         reserved_at_8[0x18];
7300
7301         u8         syndrome[0x20];
7302
7303         u8         reserved_at_40[0x40];
7304 };
7305
7306 struct mlx5_ifc_arm_dct_in_bits {
7307         u8         opcode[0x10];
7308         u8         reserved_at_10[0x10];
7309
7310         u8         reserved_at_20[0x10];
7311         u8         op_mod[0x10];
7312
7313         u8         reserved_at_40[0x8];
7314         u8         dct_number[0x18];
7315
7316         u8         reserved_at_60[0x20];
7317 };
7318
7319 struct mlx5_ifc_alloc_xrcd_out_bits {
7320         u8         status[0x8];
7321         u8         reserved_at_8[0x18];
7322
7323         u8         syndrome[0x20];
7324
7325         u8         reserved_at_40[0x8];
7326         u8         xrcd[0x18];
7327
7328         u8         reserved_at_60[0x20];
7329 };
7330
7331 struct mlx5_ifc_alloc_xrcd_in_bits {
7332         u8         opcode[0x10];
7333         u8         reserved_at_10[0x10];
7334
7335         u8         reserved_at_20[0x10];
7336         u8         op_mod[0x10];
7337
7338         u8         reserved_at_40[0x40];
7339 };
7340
7341 struct mlx5_ifc_alloc_uar_out_bits {
7342         u8         status[0x8];
7343         u8         reserved_at_8[0x18];
7344
7345         u8         syndrome[0x20];
7346
7347         u8         reserved_at_40[0x8];
7348         u8         uar[0x18];
7349
7350         u8         reserved_at_60[0x20];
7351 };
7352
7353 struct mlx5_ifc_alloc_uar_in_bits {
7354         u8         opcode[0x10];
7355         u8         reserved_at_10[0x10];
7356
7357         u8         reserved_at_20[0x10];
7358         u8         op_mod[0x10];
7359
7360         u8         reserved_at_40[0x40];
7361 };
7362
7363 struct mlx5_ifc_alloc_transport_domain_out_bits {
7364         u8         status[0x8];
7365         u8         reserved_at_8[0x18];
7366
7367         u8         syndrome[0x20];
7368
7369         u8         reserved_at_40[0x8];
7370         u8         transport_domain[0x18];
7371
7372         u8         reserved_at_60[0x20];
7373 };
7374
7375 struct mlx5_ifc_alloc_transport_domain_in_bits {
7376         u8         opcode[0x10];
7377         u8         reserved_at_10[0x10];
7378
7379         u8         reserved_at_20[0x10];
7380         u8         op_mod[0x10];
7381
7382         u8         reserved_at_40[0x40];
7383 };
7384
7385 struct mlx5_ifc_alloc_q_counter_out_bits {
7386         u8         status[0x8];
7387         u8         reserved_at_8[0x18];
7388
7389         u8         syndrome[0x20];
7390
7391         u8         reserved_at_40[0x18];
7392         u8         counter_set_id[0x8];
7393
7394         u8         reserved_at_60[0x20];
7395 };
7396
7397 struct mlx5_ifc_alloc_q_counter_in_bits {
7398         u8         opcode[0x10];
7399         u8         reserved_at_10[0x10];
7400
7401         u8         reserved_at_20[0x10];
7402         u8         op_mod[0x10];
7403
7404         u8         reserved_at_40[0x40];
7405 };
7406
7407 struct mlx5_ifc_alloc_pd_out_bits {
7408         u8         status[0x8];
7409         u8         reserved_at_8[0x18];
7410
7411         u8         syndrome[0x20];
7412
7413         u8         reserved_at_40[0x8];
7414         u8         pd[0x18];
7415
7416         u8         reserved_at_60[0x20];
7417 };
7418
7419 struct mlx5_ifc_alloc_pd_in_bits {
7420         u8         opcode[0x10];
7421         u8         reserved_at_10[0x10];
7422
7423         u8         reserved_at_20[0x10];
7424         u8         op_mod[0x10];
7425
7426         u8         reserved_at_40[0x40];
7427 };
7428
7429 struct mlx5_ifc_alloc_flow_counter_out_bits {
7430         u8         status[0x8];
7431         u8         reserved_at_8[0x18];
7432
7433         u8         syndrome[0x20];
7434
7435         u8         flow_counter_id[0x20];
7436
7437         u8         reserved_at_60[0x20];
7438 };
7439
7440 struct mlx5_ifc_alloc_flow_counter_in_bits {
7441         u8         opcode[0x10];
7442         u8         reserved_at_10[0x10];
7443
7444         u8         reserved_at_20[0x10];
7445         u8         op_mod[0x10];
7446
7447         u8         reserved_at_40[0x40];
7448 };
7449
7450 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7451         u8         status[0x8];
7452         u8         reserved_at_8[0x18];
7453
7454         u8         syndrome[0x20];
7455
7456         u8         reserved_at_40[0x40];
7457 };
7458
7459 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7460         u8         opcode[0x10];
7461         u8         reserved_at_10[0x10];
7462
7463         u8         reserved_at_20[0x10];
7464         u8         op_mod[0x10];
7465
7466         u8         reserved_at_40[0x20];
7467
7468         u8         reserved_at_60[0x10];
7469         u8         vxlan_udp_port[0x10];
7470 };
7471
7472 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7473         u8         status[0x8];
7474         u8         reserved_at_8[0x18];
7475
7476         u8         syndrome[0x20];
7477
7478         u8         reserved_at_40[0x40];
7479 };
7480
7481 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7482         u8         opcode[0x10];
7483         u8         reserved_at_10[0x10];
7484
7485         u8         reserved_at_20[0x10];
7486         u8         op_mod[0x10];
7487
7488         u8         reserved_at_40[0x10];
7489         u8         rate_limit_index[0x10];
7490
7491         u8         reserved_at_60[0x20];
7492
7493         u8         rate_limit[0x20];
7494
7495         u8         burst_upper_bound[0x20];
7496
7497         u8         reserved_at_c0[0x10];
7498         u8         typical_packet_size[0x10];
7499
7500         u8         reserved_at_e0[0x120];
7501 };
7502
7503 struct mlx5_ifc_access_register_out_bits {
7504         u8         status[0x8];
7505         u8         reserved_at_8[0x18];
7506
7507         u8         syndrome[0x20];
7508
7509         u8         reserved_at_40[0x40];
7510
7511         u8         register_data[0][0x20];
7512 };
7513
7514 enum {
7515         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7516         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7517 };
7518
7519 struct mlx5_ifc_access_register_in_bits {
7520         u8         opcode[0x10];
7521         u8         reserved_at_10[0x10];
7522
7523         u8         reserved_at_20[0x10];
7524         u8         op_mod[0x10];
7525
7526         u8         reserved_at_40[0x10];
7527         u8         register_id[0x10];
7528
7529         u8         argument[0x20];
7530
7531         u8         register_data[0][0x20];
7532 };
7533
7534 struct mlx5_ifc_sltp_reg_bits {
7535         u8         status[0x4];
7536         u8         version[0x4];
7537         u8         local_port[0x8];
7538         u8         pnat[0x2];
7539         u8         reserved_at_12[0x2];
7540         u8         lane[0x4];
7541         u8         reserved_at_18[0x8];
7542
7543         u8         reserved_at_20[0x20];
7544
7545         u8         reserved_at_40[0x7];
7546         u8         polarity[0x1];
7547         u8         ob_tap0[0x8];
7548         u8         ob_tap1[0x8];
7549         u8         ob_tap2[0x8];
7550
7551         u8         reserved_at_60[0xc];
7552         u8         ob_preemp_mode[0x4];
7553         u8         ob_reg[0x8];
7554         u8         ob_bias[0x8];
7555
7556         u8         reserved_at_80[0x20];
7557 };
7558
7559 struct mlx5_ifc_slrg_reg_bits {
7560         u8         status[0x4];
7561         u8         version[0x4];
7562         u8         local_port[0x8];
7563         u8         pnat[0x2];
7564         u8         reserved_at_12[0x2];
7565         u8         lane[0x4];
7566         u8         reserved_at_18[0x8];
7567
7568         u8         time_to_link_up[0x10];
7569         u8         reserved_at_30[0xc];
7570         u8         grade_lane_speed[0x4];
7571
7572         u8         grade_version[0x8];
7573         u8         grade[0x18];
7574
7575         u8         reserved_at_60[0x4];
7576         u8         height_grade_type[0x4];
7577         u8         height_grade[0x18];
7578
7579         u8         height_dz[0x10];
7580         u8         height_dv[0x10];
7581
7582         u8         reserved_at_a0[0x10];
7583         u8         height_sigma[0x10];
7584
7585         u8         reserved_at_c0[0x20];
7586
7587         u8         reserved_at_e0[0x4];
7588         u8         phase_grade_type[0x4];
7589         u8         phase_grade[0x18];
7590
7591         u8         reserved_at_100[0x8];
7592         u8         phase_eo_pos[0x8];
7593         u8         reserved_at_110[0x8];
7594         u8         phase_eo_neg[0x8];
7595
7596         u8         ffe_set_tested[0x10];
7597         u8         test_errors_per_lane[0x10];
7598 };
7599
7600 struct mlx5_ifc_pvlc_reg_bits {
7601         u8         reserved_at_0[0x8];
7602         u8         local_port[0x8];
7603         u8         reserved_at_10[0x10];
7604
7605         u8         reserved_at_20[0x1c];
7606         u8         vl_hw_cap[0x4];
7607
7608         u8         reserved_at_40[0x1c];
7609         u8         vl_admin[0x4];
7610
7611         u8         reserved_at_60[0x1c];
7612         u8         vl_operational[0x4];
7613 };
7614
7615 struct mlx5_ifc_pude_reg_bits {
7616         u8         swid[0x8];
7617         u8         local_port[0x8];
7618         u8         reserved_at_10[0x4];
7619         u8         admin_status[0x4];
7620         u8         reserved_at_18[0x4];
7621         u8         oper_status[0x4];
7622
7623         u8         reserved_at_20[0x60];
7624 };
7625
7626 struct mlx5_ifc_ptys_reg_bits {
7627         u8         reserved_at_0[0x1];
7628         u8         an_disable_admin[0x1];
7629         u8         an_disable_cap[0x1];
7630         u8         reserved_at_3[0x5];
7631         u8         local_port[0x8];
7632         u8         reserved_at_10[0xd];
7633         u8         proto_mask[0x3];
7634
7635         u8         an_status[0x4];
7636         u8         reserved_at_24[0x3c];
7637
7638         u8         eth_proto_capability[0x20];
7639
7640         u8         ib_link_width_capability[0x10];
7641         u8         ib_proto_capability[0x10];
7642
7643         u8         reserved_at_a0[0x20];
7644
7645         u8         eth_proto_admin[0x20];
7646
7647         u8         ib_link_width_admin[0x10];
7648         u8         ib_proto_admin[0x10];
7649
7650         u8         reserved_at_100[0x20];
7651
7652         u8         eth_proto_oper[0x20];
7653
7654         u8         ib_link_width_oper[0x10];
7655         u8         ib_proto_oper[0x10];
7656
7657         u8         reserved_at_160[0x1c];
7658         u8         connector_type[0x4];
7659
7660         u8         eth_proto_lp_advertise[0x20];
7661
7662         u8         reserved_at_1a0[0x60];
7663 };
7664
7665 struct mlx5_ifc_mlcr_reg_bits {
7666         u8         reserved_at_0[0x8];
7667         u8         local_port[0x8];
7668         u8         reserved_at_10[0x20];
7669
7670         u8         beacon_duration[0x10];
7671         u8         reserved_at_40[0x10];
7672
7673         u8         beacon_remain[0x10];
7674 };
7675
7676 struct mlx5_ifc_ptas_reg_bits {
7677         u8         reserved_at_0[0x20];
7678
7679         u8         algorithm_options[0x10];
7680         u8         reserved_at_30[0x4];
7681         u8         repetitions_mode[0x4];
7682         u8         num_of_repetitions[0x8];
7683
7684         u8         grade_version[0x8];
7685         u8         height_grade_type[0x4];
7686         u8         phase_grade_type[0x4];
7687         u8         height_grade_weight[0x8];
7688         u8         phase_grade_weight[0x8];
7689
7690         u8         gisim_measure_bits[0x10];
7691         u8         adaptive_tap_measure_bits[0x10];
7692
7693         u8         ber_bath_high_error_threshold[0x10];
7694         u8         ber_bath_mid_error_threshold[0x10];
7695
7696         u8         ber_bath_low_error_threshold[0x10];
7697         u8         one_ratio_high_threshold[0x10];
7698
7699         u8         one_ratio_high_mid_threshold[0x10];
7700         u8         one_ratio_low_mid_threshold[0x10];
7701
7702         u8         one_ratio_low_threshold[0x10];
7703         u8         ndeo_error_threshold[0x10];
7704
7705         u8         mixer_offset_step_size[0x10];
7706         u8         reserved_at_110[0x8];
7707         u8         mix90_phase_for_voltage_bath[0x8];
7708
7709         u8         mixer_offset_start[0x10];
7710         u8         mixer_offset_end[0x10];
7711
7712         u8         reserved_at_140[0x15];
7713         u8         ber_test_time[0xb];
7714 };
7715
7716 struct mlx5_ifc_pspa_reg_bits {
7717         u8         swid[0x8];
7718         u8         local_port[0x8];
7719         u8         sub_port[0x8];
7720         u8         reserved_at_18[0x8];
7721
7722         u8         reserved_at_20[0x20];
7723 };
7724
7725 struct mlx5_ifc_pqdr_reg_bits {
7726         u8         reserved_at_0[0x8];
7727         u8         local_port[0x8];
7728         u8         reserved_at_10[0x5];
7729         u8         prio[0x3];
7730         u8         reserved_at_18[0x6];
7731         u8         mode[0x2];
7732
7733         u8         reserved_at_20[0x20];
7734
7735         u8         reserved_at_40[0x10];
7736         u8         min_threshold[0x10];
7737
7738         u8         reserved_at_60[0x10];
7739         u8         max_threshold[0x10];
7740
7741         u8         reserved_at_80[0x10];
7742         u8         mark_probability_denominator[0x10];
7743
7744         u8         reserved_at_a0[0x60];
7745 };
7746
7747 struct mlx5_ifc_ppsc_reg_bits {
7748         u8         reserved_at_0[0x8];
7749         u8         local_port[0x8];
7750         u8         reserved_at_10[0x10];
7751
7752         u8         reserved_at_20[0x60];
7753
7754         u8         reserved_at_80[0x1c];
7755         u8         wrps_admin[0x4];
7756
7757         u8         reserved_at_a0[0x1c];
7758         u8         wrps_status[0x4];
7759
7760         u8         reserved_at_c0[0x8];
7761         u8         up_threshold[0x8];
7762         u8         reserved_at_d0[0x8];
7763         u8         down_threshold[0x8];
7764
7765         u8         reserved_at_e0[0x20];
7766
7767         u8         reserved_at_100[0x1c];
7768         u8         srps_admin[0x4];
7769
7770         u8         reserved_at_120[0x1c];
7771         u8         srps_status[0x4];
7772
7773         u8         reserved_at_140[0x40];
7774 };
7775
7776 struct mlx5_ifc_pplr_reg_bits {
7777         u8         reserved_at_0[0x8];
7778         u8         local_port[0x8];
7779         u8         reserved_at_10[0x10];
7780
7781         u8         reserved_at_20[0x8];
7782         u8         lb_cap[0x8];
7783         u8         reserved_at_30[0x8];
7784         u8         lb_en[0x8];
7785 };
7786
7787 struct mlx5_ifc_pplm_reg_bits {
7788         u8         reserved_at_0[0x8];
7789         u8         local_port[0x8];
7790         u8         reserved_at_10[0x10];
7791
7792         u8         reserved_at_20[0x20];
7793
7794         u8         port_profile_mode[0x8];
7795         u8         static_port_profile[0x8];
7796         u8         active_port_profile[0x8];
7797         u8         reserved_at_58[0x8];
7798
7799         u8         retransmission_active[0x8];
7800         u8         fec_mode_active[0x18];
7801
7802         u8         reserved_at_80[0x20];
7803 };
7804
7805 struct mlx5_ifc_ppcnt_reg_bits {
7806         u8         swid[0x8];
7807         u8         local_port[0x8];
7808         u8         pnat[0x2];
7809         u8         reserved_at_12[0x8];
7810         u8         grp[0x6];
7811
7812         u8         clr[0x1];
7813         u8         reserved_at_21[0x1c];
7814         u8         prio_tc[0x3];
7815
7816         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7817 };
7818
7819 struct mlx5_ifc_mpcnt_reg_bits {
7820         u8         reserved_at_0[0x8];
7821         u8         pcie_index[0x8];
7822         u8         reserved_at_10[0xa];
7823         u8         grp[0x6];
7824
7825         u8         clr[0x1];
7826         u8         reserved_at_21[0x1f];
7827
7828         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7829 };
7830
7831 struct mlx5_ifc_ppad_reg_bits {
7832         u8         reserved_at_0[0x3];
7833         u8         single_mac[0x1];
7834         u8         reserved_at_4[0x4];
7835         u8         local_port[0x8];
7836         u8         mac_47_32[0x10];
7837
7838         u8         mac_31_0[0x20];
7839
7840         u8         reserved_at_40[0x40];
7841 };
7842
7843 struct mlx5_ifc_pmtu_reg_bits {
7844         u8         reserved_at_0[0x8];
7845         u8         local_port[0x8];
7846         u8         reserved_at_10[0x10];
7847
7848         u8         max_mtu[0x10];
7849         u8         reserved_at_30[0x10];
7850
7851         u8         admin_mtu[0x10];
7852         u8         reserved_at_50[0x10];
7853
7854         u8         oper_mtu[0x10];
7855         u8         reserved_at_70[0x10];
7856 };
7857
7858 struct mlx5_ifc_pmpr_reg_bits {
7859         u8         reserved_at_0[0x8];
7860         u8         module[0x8];
7861         u8         reserved_at_10[0x10];
7862
7863         u8         reserved_at_20[0x18];
7864         u8         attenuation_5g[0x8];
7865
7866         u8         reserved_at_40[0x18];
7867         u8         attenuation_7g[0x8];
7868
7869         u8         reserved_at_60[0x18];
7870         u8         attenuation_12g[0x8];
7871 };
7872
7873 struct mlx5_ifc_pmpe_reg_bits {
7874         u8         reserved_at_0[0x8];
7875         u8         module[0x8];
7876         u8         reserved_at_10[0xc];
7877         u8         module_status[0x4];
7878
7879         u8         reserved_at_20[0x60];
7880 };
7881
7882 struct mlx5_ifc_pmpc_reg_bits {
7883         u8         module_state_updated[32][0x8];
7884 };
7885
7886 struct mlx5_ifc_pmlpn_reg_bits {
7887         u8         reserved_at_0[0x4];
7888         u8         mlpn_status[0x4];
7889         u8         local_port[0x8];
7890         u8         reserved_at_10[0x10];
7891
7892         u8         e[0x1];
7893         u8         reserved_at_21[0x1f];
7894 };
7895
7896 struct mlx5_ifc_pmlp_reg_bits {
7897         u8         rxtx[0x1];
7898         u8         reserved_at_1[0x7];
7899         u8         local_port[0x8];
7900         u8         reserved_at_10[0x8];
7901         u8         width[0x8];
7902
7903         u8         lane0_module_mapping[0x20];
7904
7905         u8         lane1_module_mapping[0x20];
7906
7907         u8         lane2_module_mapping[0x20];
7908
7909         u8         lane3_module_mapping[0x20];
7910
7911         u8         reserved_at_a0[0x160];
7912 };
7913
7914 struct mlx5_ifc_pmaos_reg_bits {
7915         u8         reserved_at_0[0x8];
7916         u8         module[0x8];
7917         u8         reserved_at_10[0x4];
7918         u8         admin_status[0x4];
7919         u8         reserved_at_18[0x4];
7920         u8         oper_status[0x4];
7921
7922         u8         ase[0x1];
7923         u8         ee[0x1];
7924         u8         reserved_at_22[0x1c];
7925         u8         e[0x2];
7926
7927         u8         reserved_at_40[0x40];
7928 };
7929
7930 struct mlx5_ifc_plpc_reg_bits {
7931         u8         reserved_at_0[0x4];
7932         u8         profile_id[0xc];
7933         u8         reserved_at_10[0x4];
7934         u8         proto_mask[0x4];
7935         u8         reserved_at_18[0x8];
7936
7937         u8         reserved_at_20[0x10];
7938         u8         lane_speed[0x10];
7939
7940         u8         reserved_at_40[0x17];
7941         u8         lpbf[0x1];
7942         u8         fec_mode_policy[0x8];
7943
7944         u8         retransmission_capability[0x8];
7945         u8         fec_mode_capability[0x18];
7946
7947         u8         retransmission_support_admin[0x8];
7948         u8         fec_mode_support_admin[0x18];
7949
7950         u8         retransmission_request_admin[0x8];
7951         u8         fec_mode_request_admin[0x18];
7952
7953         u8         reserved_at_c0[0x80];
7954 };
7955
7956 struct mlx5_ifc_plib_reg_bits {
7957         u8         reserved_at_0[0x8];
7958         u8         local_port[0x8];
7959         u8         reserved_at_10[0x8];
7960         u8         ib_port[0x8];
7961
7962         u8         reserved_at_20[0x60];
7963 };
7964
7965 struct mlx5_ifc_plbf_reg_bits {
7966         u8         reserved_at_0[0x8];
7967         u8         local_port[0x8];
7968         u8         reserved_at_10[0xd];
7969         u8         lbf_mode[0x3];
7970
7971         u8         reserved_at_20[0x20];
7972 };
7973
7974 struct mlx5_ifc_pipg_reg_bits {
7975         u8         reserved_at_0[0x8];
7976         u8         local_port[0x8];
7977         u8         reserved_at_10[0x10];
7978
7979         u8         dic[0x1];
7980         u8         reserved_at_21[0x19];
7981         u8         ipg[0x4];
7982         u8         reserved_at_3e[0x2];
7983 };
7984
7985 struct mlx5_ifc_pifr_reg_bits {
7986         u8         reserved_at_0[0x8];
7987         u8         local_port[0x8];
7988         u8         reserved_at_10[0x10];
7989
7990         u8         reserved_at_20[0xe0];
7991
7992         u8         port_filter[8][0x20];
7993
7994         u8         port_filter_update_en[8][0x20];
7995 };
7996
7997 struct mlx5_ifc_pfcc_reg_bits {
7998         u8         reserved_at_0[0x8];
7999         u8         local_port[0x8];
8000         u8         reserved_at_10[0xb];
8001         u8         ppan_mask_n[0x1];
8002         u8         minor_stall_mask[0x1];
8003         u8         critical_stall_mask[0x1];
8004         u8         reserved_at_1e[0x2];
8005
8006         u8         ppan[0x4];
8007         u8         reserved_at_24[0x4];
8008         u8         prio_mask_tx[0x8];
8009         u8         reserved_at_30[0x8];
8010         u8         prio_mask_rx[0x8];
8011
8012         u8         pptx[0x1];
8013         u8         aptx[0x1];
8014         u8         pptx_mask_n[0x1];
8015         u8         reserved_at_43[0x5];
8016         u8         pfctx[0x8];
8017         u8         reserved_at_50[0x10];
8018
8019         u8         pprx[0x1];
8020         u8         aprx[0x1];
8021         u8         pprx_mask_n[0x1];
8022         u8         reserved_at_63[0x5];
8023         u8         pfcrx[0x8];
8024         u8         reserved_at_70[0x10];
8025
8026         u8         device_stall_minor_watermark[0x10];
8027         u8         device_stall_critical_watermark[0x10];
8028
8029         u8         reserved_at_a0[0x60];
8030 };
8031
8032 struct mlx5_ifc_pelc_reg_bits {
8033         u8         op[0x4];
8034         u8         reserved_at_4[0x4];
8035         u8         local_port[0x8];
8036         u8         reserved_at_10[0x10];
8037
8038         u8         op_admin[0x8];
8039         u8         op_capability[0x8];
8040         u8         op_request[0x8];
8041         u8         op_active[0x8];
8042
8043         u8         admin[0x40];
8044
8045         u8         capability[0x40];
8046
8047         u8         request[0x40];
8048
8049         u8         active[0x40];
8050
8051         u8         reserved_at_140[0x80];
8052 };
8053
8054 struct mlx5_ifc_peir_reg_bits {
8055         u8         reserved_at_0[0x8];
8056         u8         local_port[0x8];
8057         u8         reserved_at_10[0x10];
8058
8059         u8         reserved_at_20[0xc];
8060         u8         error_count[0x4];
8061         u8         reserved_at_30[0x10];
8062
8063         u8         reserved_at_40[0xc];
8064         u8         lane[0x4];
8065         u8         reserved_at_50[0x8];
8066         u8         error_type[0x8];
8067 };
8068
8069 struct mlx5_ifc_mpegc_reg_bits {
8070         u8         reserved_at_0[0x30];
8071         u8         field_select[0x10];
8072
8073         u8         tx_overflow_sense[0x1];
8074         u8         mark_cqe[0x1];
8075         u8         mark_cnp[0x1];
8076         u8         reserved_at_43[0x1b];
8077         u8         tx_lossy_overflow_oper[0x2];
8078
8079         u8         reserved_at_60[0x100];
8080 };
8081
8082 struct mlx5_ifc_pcam_enhanced_features_bits {
8083         u8         reserved_at_0[0x6d];
8084         u8         rx_icrc_encapsulated_counter[0x1];
8085         u8         reserved_at_6e[0x8];
8086         u8         pfcc_mask[0x1];
8087         u8         reserved_at_77[0x4];
8088         u8         rx_buffer_fullness_counters[0x1];
8089         u8         ptys_connector_type[0x1];
8090         u8         reserved_at_7d[0x1];
8091         u8         ppcnt_discard_group[0x1];
8092         u8         ppcnt_statistical_group[0x1];
8093 };
8094
8095 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8096         u8         port_access_reg_cap_mask_127_to_96[0x20];
8097         u8         port_access_reg_cap_mask_95_to_64[0x20];
8098         u8         port_access_reg_cap_mask_63_to_32[0x20];
8099
8100         u8         port_access_reg_cap_mask_31_to_13[0x13];
8101         u8         pbmc[0x1];
8102         u8         pptb[0x1];
8103         u8         port_access_reg_cap_mask_10_to_0[0xb];
8104 };
8105
8106 struct mlx5_ifc_pcam_reg_bits {
8107         u8         reserved_at_0[0x8];
8108         u8         feature_group[0x8];
8109         u8         reserved_at_10[0x8];
8110         u8         access_reg_group[0x8];
8111
8112         u8         reserved_at_20[0x20];
8113
8114         union {
8115                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8116                 u8         reserved_at_0[0x80];
8117         } port_access_reg_cap_mask;
8118
8119         u8         reserved_at_c0[0x80];
8120
8121         union {
8122                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8123                 u8         reserved_at_0[0x80];
8124         } feature_cap_mask;
8125
8126         u8         reserved_at_1c0[0xc0];
8127 };
8128
8129 struct mlx5_ifc_mcam_enhanced_features_bits {
8130         u8         reserved_at_0[0x74];
8131         u8         mark_tx_action_cnp[0x1];
8132         u8         mark_tx_action_cqe[0x1];
8133         u8         dynamic_tx_overflow[0x1];
8134         u8         reserved_at_77[0x4];
8135         u8         pcie_outbound_stalled[0x1];
8136         u8         tx_overflow_buffer_pkt[0x1];
8137         u8         mtpps_enh_out_per_adj[0x1];
8138         u8         mtpps_fs[0x1];
8139         u8         pcie_performance_group[0x1];
8140 };
8141
8142 struct mlx5_ifc_mcam_access_reg_bits {
8143         u8         reserved_at_0[0x1c];
8144         u8         mcda[0x1];
8145         u8         mcc[0x1];
8146         u8         mcqi[0x1];
8147         u8         reserved_at_1f[0x1];
8148
8149         u8         regs_95_to_87[0x9];
8150         u8         mpegc[0x1];
8151         u8         regs_85_to_68[0x12];
8152         u8         tracer_registers[0x4];
8153
8154         u8         regs_63_to_32[0x20];
8155         u8         regs_31_to_0[0x20];
8156 };
8157
8158 struct mlx5_ifc_mcam_reg_bits {
8159         u8         reserved_at_0[0x8];
8160         u8         feature_group[0x8];
8161         u8         reserved_at_10[0x8];
8162         u8         access_reg_group[0x8];
8163
8164         u8         reserved_at_20[0x20];
8165
8166         union {
8167                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8168                 u8         reserved_at_0[0x80];
8169         } mng_access_reg_cap_mask;
8170
8171         u8         reserved_at_c0[0x80];
8172
8173         union {
8174                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8175                 u8         reserved_at_0[0x80];
8176         } mng_feature_cap_mask;
8177
8178         u8         reserved_at_1c0[0x80];
8179 };
8180
8181 struct mlx5_ifc_qcam_access_reg_cap_mask {
8182         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8183         u8         qpdpm[0x1];
8184         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8185         u8         qdpm[0x1];
8186         u8         qpts[0x1];
8187         u8         qcap[0x1];
8188         u8         qcam_access_reg_cap_mask_0[0x1];
8189 };
8190
8191 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8192         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8193         u8         qpts_trust_both[0x1];
8194 };
8195
8196 struct mlx5_ifc_qcam_reg_bits {
8197         u8         reserved_at_0[0x8];
8198         u8         feature_group[0x8];
8199         u8         reserved_at_10[0x8];
8200         u8         access_reg_group[0x8];
8201         u8         reserved_at_20[0x20];
8202
8203         union {
8204                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8205                 u8  reserved_at_0[0x80];
8206         } qos_access_reg_cap_mask;
8207
8208         u8         reserved_at_c0[0x80];
8209
8210         union {
8211                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8212                 u8  reserved_at_0[0x80];
8213         } qos_feature_cap_mask;
8214
8215         u8         reserved_at_1c0[0x80];
8216 };
8217
8218 struct mlx5_ifc_pcap_reg_bits {
8219         u8         reserved_at_0[0x8];
8220         u8         local_port[0x8];
8221         u8         reserved_at_10[0x10];
8222
8223         u8         port_capability_mask[4][0x20];
8224 };
8225
8226 struct mlx5_ifc_paos_reg_bits {
8227         u8         swid[0x8];
8228         u8         local_port[0x8];
8229         u8         reserved_at_10[0x4];
8230         u8         admin_status[0x4];
8231         u8         reserved_at_18[0x4];
8232         u8         oper_status[0x4];
8233
8234         u8         ase[0x1];
8235         u8         ee[0x1];
8236         u8         reserved_at_22[0x1c];
8237         u8         e[0x2];
8238
8239         u8         reserved_at_40[0x40];
8240 };
8241
8242 struct mlx5_ifc_pamp_reg_bits {
8243         u8         reserved_at_0[0x8];
8244         u8         opamp_group[0x8];
8245         u8         reserved_at_10[0xc];
8246         u8         opamp_group_type[0x4];
8247
8248         u8         start_index[0x10];
8249         u8         reserved_at_30[0x4];
8250         u8         num_of_indices[0xc];
8251
8252         u8         index_data[18][0x10];
8253 };
8254
8255 struct mlx5_ifc_pcmr_reg_bits {
8256         u8         reserved_at_0[0x8];
8257         u8         local_port[0x8];
8258         u8         reserved_at_10[0x2e];
8259         u8         fcs_cap[0x1];
8260         u8         reserved_at_3f[0x1f];
8261         u8         fcs_chk[0x1];
8262         u8         reserved_at_5f[0x1];
8263 };
8264
8265 struct mlx5_ifc_lane_2_module_mapping_bits {
8266         u8         reserved_at_0[0x6];
8267         u8         rx_lane[0x2];
8268         u8         reserved_at_8[0x6];
8269         u8         tx_lane[0x2];
8270         u8         reserved_at_10[0x8];
8271         u8         module[0x8];
8272 };
8273
8274 struct mlx5_ifc_bufferx_reg_bits {
8275         u8         reserved_at_0[0x6];
8276         u8         lossy[0x1];
8277         u8         epsb[0x1];
8278         u8         reserved_at_8[0xc];
8279         u8         size[0xc];
8280
8281         u8         xoff_threshold[0x10];
8282         u8         xon_threshold[0x10];
8283 };
8284
8285 struct mlx5_ifc_set_node_in_bits {
8286         u8         node_description[64][0x8];
8287 };
8288
8289 struct mlx5_ifc_register_power_settings_bits {
8290         u8         reserved_at_0[0x18];
8291         u8         power_settings_level[0x8];
8292
8293         u8         reserved_at_20[0x60];
8294 };
8295
8296 struct mlx5_ifc_register_host_endianness_bits {
8297         u8         he[0x1];
8298         u8         reserved_at_1[0x1f];
8299
8300         u8         reserved_at_20[0x60];
8301 };
8302
8303 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8304         u8         reserved_at_0[0x20];
8305
8306         u8         mkey[0x20];
8307
8308         u8         addressh_63_32[0x20];
8309
8310         u8         addressl_31_0[0x20];
8311 };
8312
8313 struct mlx5_ifc_ud_adrs_vector_bits {
8314         u8         dc_key[0x40];
8315
8316         u8         ext[0x1];
8317         u8         reserved_at_41[0x7];
8318         u8         destination_qp_dct[0x18];
8319
8320         u8         static_rate[0x4];
8321         u8         sl_eth_prio[0x4];
8322         u8         fl[0x1];
8323         u8         mlid[0x7];
8324         u8         rlid_udp_sport[0x10];
8325
8326         u8         reserved_at_80[0x20];
8327
8328         u8         rmac_47_16[0x20];
8329
8330         u8         rmac_15_0[0x10];
8331         u8         tclass[0x8];
8332         u8         hop_limit[0x8];
8333
8334         u8         reserved_at_e0[0x1];
8335         u8         grh[0x1];
8336         u8         reserved_at_e2[0x2];
8337         u8         src_addr_index[0x8];
8338         u8         flow_label[0x14];
8339
8340         u8         rgid_rip[16][0x8];
8341 };
8342
8343 struct mlx5_ifc_pages_req_event_bits {
8344         u8         reserved_at_0[0x10];
8345         u8         function_id[0x10];
8346
8347         u8         num_pages[0x20];
8348
8349         u8         reserved_at_40[0xa0];
8350 };
8351
8352 struct mlx5_ifc_eqe_bits {
8353         u8         reserved_at_0[0x8];
8354         u8         event_type[0x8];
8355         u8         reserved_at_10[0x8];
8356         u8         event_sub_type[0x8];
8357
8358         u8         reserved_at_20[0xe0];
8359
8360         union mlx5_ifc_event_auto_bits event_data;
8361
8362         u8         reserved_at_1e0[0x10];
8363         u8         signature[0x8];
8364         u8         reserved_at_1f8[0x7];
8365         u8         owner[0x1];
8366 };
8367
8368 enum {
8369         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8370 };
8371
8372 struct mlx5_ifc_cmd_queue_entry_bits {
8373         u8         type[0x8];
8374         u8         reserved_at_8[0x18];
8375
8376         u8         input_length[0x20];
8377
8378         u8         input_mailbox_pointer_63_32[0x20];
8379
8380         u8         input_mailbox_pointer_31_9[0x17];
8381         u8         reserved_at_77[0x9];
8382
8383         u8         command_input_inline_data[16][0x8];
8384
8385         u8         command_output_inline_data[16][0x8];
8386
8387         u8         output_mailbox_pointer_63_32[0x20];
8388
8389         u8         output_mailbox_pointer_31_9[0x17];
8390         u8         reserved_at_1b7[0x9];
8391
8392         u8         output_length[0x20];
8393
8394         u8         token[0x8];
8395         u8         signature[0x8];
8396         u8         reserved_at_1f0[0x8];
8397         u8         status[0x7];
8398         u8         ownership[0x1];
8399 };
8400
8401 struct mlx5_ifc_cmd_out_bits {
8402         u8         status[0x8];
8403         u8         reserved_at_8[0x18];
8404
8405         u8         syndrome[0x20];
8406
8407         u8         command_output[0x20];
8408 };
8409
8410 struct mlx5_ifc_cmd_in_bits {
8411         u8         opcode[0x10];
8412         u8         reserved_at_10[0x10];
8413
8414         u8         reserved_at_20[0x10];
8415         u8         op_mod[0x10];
8416
8417         u8         command[0][0x20];
8418 };
8419
8420 struct mlx5_ifc_cmd_if_box_bits {
8421         u8         mailbox_data[512][0x8];
8422
8423         u8         reserved_at_1000[0x180];
8424
8425         u8         next_pointer_63_32[0x20];
8426
8427         u8         next_pointer_31_10[0x16];
8428         u8         reserved_at_11b6[0xa];
8429
8430         u8         block_number[0x20];
8431
8432         u8         reserved_at_11e0[0x8];
8433         u8         token[0x8];
8434         u8         ctrl_signature[0x8];
8435         u8         signature[0x8];
8436 };
8437
8438 struct mlx5_ifc_mtt_bits {
8439         u8         ptag_63_32[0x20];
8440
8441         u8         ptag_31_8[0x18];
8442         u8         reserved_at_38[0x6];
8443         u8         wr_en[0x1];
8444         u8         rd_en[0x1];
8445 };
8446
8447 struct mlx5_ifc_query_wol_rol_out_bits {
8448         u8         status[0x8];
8449         u8         reserved_at_8[0x18];
8450
8451         u8         syndrome[0x20];
8452
8453         u8         reserved_at_40[0x10];
8454         u8         rol_mode[0x8];
8455         u8         wol_mode[0x8];
8456
8457         u8         reserved_at_60[0x20];
8458 };
8459
8460 struct mlx5_ifc_query_wol_rol_in_bits {
8461         u8         opcode[0x10];
8462         u8         reserved_at_10[0x10];
8463
8464         u8         reserved_at_20[0x10];
8465         u8         op_mod[0x10];
8466
8467         u8         reserved_at_40[0x40];
8468 };
8469
8470 struct mlx5_ifc_set_wol_rol_out_bits {
8471         u8         status[0x8];
8472         u8         reserved_at_8[0x18];
8473
8474         u8         syndrome[0x20];
8475
8476         u8         reserved_at_40[0x40];
8477 };
8478
8479 struct mlx5_ifc_set_wol_rol_in_bits {
8480         u8         opcode[0x10];
8481         u8         reserved_at_10[0x10];
8482
8483         u8         reserved_at_20[0x10];
8484         u8         op_mod[0x10];
8485
8486         u8         rol_mode_valid[0x1];
8487         u8         wol_mode_valid[0x1];
8488         u8         reserved_at_42[0xe];
8489         u8         rol_mode[0x8];
8490         u8         wol_mode[0x8];
8491
8492         u8         reserved_at_60[0x20];
8493 };
8494
8495 enum {
8496         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8497         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8498         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8499 };
8500
8501 enum {
8502         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8503         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8504         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8505 };
8506
8507 enum {
8508         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8509         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8510         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8511         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8512         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8513         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8514         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8515         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8516         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8517         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8518         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8519 };
8520
8521 struct mlx5_ifc_initial_seg_bits {
8522         u8         fw_rev_minor[0x10];
8523         u8         fw_rev_major[0x10];
8524
8525         u8         cmd_interface_rev[0x10];
8526         u8         fw_rev_subminor[0x10];
8527
8528         u8         reserved_at_40[0x40];
8529
8530         u8         cmdq_phy_addr_63_32[0x20];
8531
8532         u8         cmdq_phy_addr_31_12[0x14];
8533         u8         reserved_at_b4[0x2];
8534         u8         nic_interface[0x2];
8535         u8         log_cmdq_size[0x4];
8536         u8         log_cmdq_stride[0x4];
8537
8538         u8         command_doorbell_vector[0x20];
8539
8540         u8         reserved_at_e0[0xf00];
8541
8542         u8         initializing[0x1];
8543         u8         reserved_at_fe1[0x4];
8544         u8         nic_interface_supported[0x3];
8545         u8         reserved_at_fe8[0x18];
8546
8547         struct mlx5_ifc_health_buffer_bits health_buffer;
8548
8549         u8         no_dram_nic_offset[0x20];
8550
8551         u8         reserved_at_1220[0x6e40];
8552
8553         u8         reserved_at_8060[0x1f];
8554         u8         clear_int[0x1];
8555
8556         u8         health_syndrome[0x8];
8557         u8         health_counter[0x18];
8558
8559         u8         reserved_at_80a0[0x17fc0];
8560 };
8561
8562 struct mlx5_ifc_mtpps_reg_bits {
8563         u8         reserved_at_0[0xc];
8564         u8         cap_number_of_pps_pins[0x4];
8565         u8         reserved_at_10[0x4];
8566         u8         cap_max_num_of_pps_in_pins[0x4];
8567         u8         reserved_at_18[0x4];
8568         u8         cap_max_num_of_pps_out_pins[0x4];
8569
8570         u8         reserved_at_20[0x24];
8571         u8         cap_pin_3_mode[0x4];
8572         u8         reserved_at_48[0x4];
8573         u8         cap_pin_2_mode[0x4];
8574         u8         reserved_at_50[0x4];
8575         u8         cap_pin_1_mode[0x4];
8576         u8         reserved_at_58[0x4];
8577         u8         cap_pin_0_mode[0x4];
8578
8579         u8         reserved_at_60[0x4];
8580         u8         cap_pin_7_mode[0x4];
8581         u8         reserved_at_68[0x4];
8582         u8         cap_pin_6_mode[0x4];
8583         u8         reserved_at_70[0x4];
8584         u8         cap_pin_5_mode[0x4];
8585         u8         reserved_at_78[0x4];
8586         u8         cap_pin_4_mode[0x4];
8587
8588         u8         field_select[0x20];
8589         u8         reserved_at_a0[0x60];
8590
8591         u8         enable[0x1];
8592         u8         reserved_at_101[0xb];
8593         u8         pattern[0x4];
8594         u8         reserved_at_110[0x4];
8595         u8         pin_mode[0x4];
8596         u8         pin[0x8];
8597
8598         u8         reserved_at_120[0x20];
8599
8600         u8         time_stamp[0x40];
8601
8602         u8         out_pulse_duration[0x10];
8603         u8         out_periodic_adjustment[0x10];
8604         u8         enhanced_out_periodic_adjustment[0x20];
8605
8606         u8         reserved_at_1c0[0x20];
8607 };
8608
8609 struct mlx5_ifc_mtppse_reg_bits {
8610         u8         reserved_at_0[0x18];
8611         u8         pin[0x8];
8612         u8         event_arm[0x1];
8613         u8         reserved_at_21[0x1b];
8614         u8         event_generation_mode[0x4];
8615         u8         reserved_at_40[0x40];
8616 };
8617
8618 struct mlx5_ifc_mcqi_cap_bits {
8619         u8         supported_info_bitmask[0x20];
8620
8621         u8         component_size[0x20];
8622
8623         u8         max_component_size[0x20];
8624
8625         u8         log_mcda_word_size[0x4];
8626         u8         reserved_at_64[0xc];
8627         u8         mcda_max_write_size[0x10];
8628
8629         u8         rd_en[0x1];
8630         u8         reserved_at_81[0x1];
8631         u8         match_chip_id[0x1];
8632         u8         match_psid[0x1];
8633         u8         check_user_timestamp[0x1];
8634         u8         match_base_guid_mac[0x1];
8635         u8         reserved_at_86[0x1a];
8636 };
8637
8638 struct mlx5_ifc_mcqi_reg_bits {
8639         u8         read_pending_component[0x1];
8640         u8         reserved_at_1[0xf];
8641         u8         component_index[0x10];
8642
8643         u8         reserved_at_20[0x20];
8644
8645         u8         reserved_at_40[0x1b];
8646         u8         info_type[0x5];
8647
8648         u8         info_size[0x20];
8649
8650         u8         offset[0x20];
8651
8652         u8         reserved_at_a0[0x10];
8653         u8         data_size[0x10];
8654
8655         u8         data[0][0x20];
8656 };
8657
8658 struct mlx5_ifc_mcc_reg_bits {
8659         u8         reserved_at_0[0x4];
8660         u8         time_elapsed_since_last_cmd[0xc];
8661         u8         reserved_at_10[0x8];
8662         u8         instruction[0x8];
8663
8664         u8         reserved_at_20[0x10];
8665         u8         component_index[0x10];
8666
8667         u8         reserved_at_40[0x8];
8668         u8         update_handle[0x18];
8669
8670         u8         handle_owner_type[0x4];
8671         u8         handle_owner_host_id[0x4];
8672         u8         reserved_at_68[0x1];
8673         u8         control_progress[0x7];
8674         u8         error_code[0x8];
8675         u8         reserved_at_78[0x4];
8676         u8         control_state[0x4];
8677
8678         u8         component_size[0x20];
8679
8680         u8         reserved_at_a0[0x60];
8681 };
8682
8683 struct mlx5_ifc_mcda_reg_bits {
8684         u8         reserved_at_0[0x8];
8685         u8         update_handle[0x18];
8686
8687         u8         offset[0x20];
8688
8689         u8         reserved_at_40[0x10];
8690         u8         size[0x10];
8691
8692         u8         reserved_at_60[0x20];
8693
8694         u8         data[0][0x20];
8695 };
8696
8697 union mlx5_ifc_ports_control_registers_document_bits {
8698         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8699         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8700         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8701         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8702         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8703         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8704         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8705         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8706         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8707         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8708         struct mlx5_ifc_paos_reg_bits paos_reg;
8709         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8710         struct mlx5_ifc_peir_reg_bits peir_reg;
8711         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8712         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8713         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8714         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8715         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8716         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8717         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8718         struct mlx5_ifc_plib_reg_bits plib_reg;
8719         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8720         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8721         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8722         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8723         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8724         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8725         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8726         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8727         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8728         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8729         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8730         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8731         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8732         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8733         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8734         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8735         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8736         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8737         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8738         struct mlx5_ifc_pude_reg_bits pude_reg;
8739         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8740         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8741         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8742         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8743         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8744         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8745         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8746         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8747         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8748         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8749         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8750         u8         reserved_at_0[0x60e0];
8751 };
8752
8753 union mlx5_ifc_debug_enhancements_document_bits {
8754         struct mlx5_ifc_health_buffer_bits health_buffer;
8755         u8         reserved_at_0[0x200];
8756 };
8757
8758 union mlx5_ifc_uplink_pci_interface_document_bits {
8759         struct mlx5_ifc_initial_seg_bits initial_seg;
8760         u8         reserved_at_0[0x20060];
8761 };
8762
8763 struct mlx5_ifc_set_flow_table_root_out_bits {
8764         u8         status[0x8];
8765         u8         reserved_at_8[0x18];
8766
8767         u8         syndrome[0x20];
8768
8769         u8         reserved_at_40[0x40];
8770 };
8771
8772 struct mlx5_ifc_set_flow_table_root_in_bits {
8773         u8         opcode[0x10];
8774         u8         reserved_at_10[0x10];
8775
8776         u8         reserved_at_20[0x10];
8777         u8         op_mod[0x10];
8778
8779         u8         other_vport[0x1];
8780         u8         reserved_at_41[0xf];
8781         u8         vport_number[0x10];
8782
8783         u8         reserved_at_60[0x20];
8784
8785         u8         table_type[0x8];
8786         u8         reserved_at_88[0x18];
8787
8788         u8         reserved_at_a0[0x8];
8789         u8         table_id[0x18];
8790
8791         u8         reserved_at_c0[0x8];
8792         u8         underlay_qpn[0x18];
8793         u8         reserved_at_e0[0x120];
8794 };
8795
8796 enum {
8797         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8798         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8799 };
8800
8801 struct mlx5_ifc_modify_flow_table_out_bits {
8802         u8         status[0x8];
8803         u8         reserved_at_8[0x18];
8804
8805         u8         syndrome[0x20];
8806
8807         u8         reserved_at_40[0x40];
8808 };
8809
8810 struct mlx5_ifc_modify_flow_table_in_bits {
8811         u8         opcode[0x10];
8812         u8         reserved_at_10[0x10];
8813
8814         u8         reserved_at_20[0x10];
8815         u8         op_mod[0x10];
8816
8817         u8         other_vport[0x1];
8818         u8         reserved_at_41[0xf];
8819         u8         vport_number[0x10];
8820
8821         u8         reserved_at_60[0x10];
8822         u8         modify_field_select[0x10];
8823
8824         u8         table_type[0x8];
8825         u8         reserved_at_88[0x18];
8826
8827         u8         reserved_at_a0[0x8];
8828         u8         table_id[0x18];
8829
8830         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8831 };
8832
8833 struct mlx5_ifc_ets_tcn_config_reg_bits {
8834         u8         g[0x1];
8835         u8         b[0x1];
8836         u8         r[0x1];
8837         u8         reserved_at_3[0x9];
8838         u8         group[0x4];
8839         u8         reserved_at_10[0x9];
8840         u8         bw_allocation[0x7];
8841
8842         u8         reserved_at_20[0xc];
8843         u8         max_bw_units[0x4];
8844         u8         reserved_at_30[0x8];
8845         u8         max_bw_value[0x8];
8846 };
8847
8848 struct mlx5_ifc_ets_global_config_reg_bits {
8849         u8         reserved_at_0[0x2];
8850         u8         r[0x1];
8851         u8         reserved_at_3[0x1d];
8852
8853         u8         reserved_at_20[0xc];
8854         u8         max_bw_units[0x4];
8855         u8         reserved_at_30[0x8];
8856         u8         max_bw_value[0x8];
8857 };
8858
8859 struct mlx5_ifc_qetc_reg_bits {
8860         u8                                         reserved_at_0[0x8];
8861         u8                                         port_number[0x8];
8862         u8                                         reserved_at_10[0x30];
8863
8864         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8865         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8866 };
8867
8868 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8869         u8         e[0x1];
8870         u8         reserved_at_01[0x0b];
8871         u8         prio[0x04];
8872 };
8873
8874 struct mlx5_ifc_qpdpm_reg_bits {
8875         u8                                     reserved_at_0[0x8];
8876         u8                                     local_port[0x8];
8877         u8                                     reserved_at_10[0x10];
8878         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8879 };
8880
8881 struct mlx5_ifc_qpts_reg_bits {
8882         u8         reserved_at_0[0x8];
8883         u8         local_port[0x8];
8884         u8         reserved_at_10[0x2d];
8885         u8         trust_state[0x3];
8886 };
8887
8888 struct mlx5_ifc_pptb_reg_bits {
8889         u8         reserved_at_0[0x2];
8890         u8         mm[0x2];
8891         u8         reserved_at_4[0x4];
8892         u8         local_port[0x8];
8893         u8         reserved_at_10[0x6];
8894         u8         cm[0x1];
8895         u8         um[0x1];
8896         u8         pm[0x8];
8897
8898         u8         prio_x_buff[0x20];
8899
8900         u8         pm_msb[0x8];
8901         u8         reserved_at_48[0x10];
8902         u8         ctrl_buff[0x4];
8903         u8         untagged_buff[0x4];
8904 };
8905
8906 struct mlx5_ifc_pbmc_reg_bits {
8907         u8         reserved_at_0[0x8];
8908         u8         local_port[0x8];
8909         u8         reserved_at_10[0x10];
8910
8911         u8         xoff_timer_value[0x10];
8912         u8         xoff_refresh[0x10];
8913
8914         u8         reserved_at_40[0x9];
8915         u8         fullness_threshold[0x7];
8916         u8         port_buffer_size[0x10];
8917
8918         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8919
8920         u8         reserved_at_2e0[0x40];
8921 };
8922
8923 struct mlx5_ifc_qtct_reg_bits {
8924         u8         reserved_at_0[0x8];
8925         u8         port_number[0x8];
8926         u8         reserved_at_10[0xd];
8927         u8         prio[0x3];
8928
8929         u8         reserved_at_20[0x1d];
8930         u8         tclass[0x3];
8931 };
8932
8933 struct mlx5_ifc_mcia_reg_bits {
8934         u8         l[0x1];
8935         u8         reserved_at_1[0x7];
8936         u8         module[0x8];
8937         u8         reserved_at_10[0x8];
8938         u8         status[0x8];
8939
8940         u8         i2c_device_address[0x8];
8941         u8         page_number[0x8];
8942         u8         device_address[0x10];
8943
8944         u8         reserved_at_40[0x10];
8945         u8         size[0x10];
8946
8947         u8         reserved_at_60[0x20];
8948
8949         u8         dword_0[0x20];
8950         u8         dword_1[0x20];
8951         u8         dword_2[0x20];
8952         u8         dword_3[0x20];
8953         u8         dword_4[0x20];
8954         u8         dword_5[0x20];
8955         u8         dword_6[0x20];
8956         u8         dword_7[0x20];
8957         u8         dword_8[0x20];
8958         u8         dword_9[0x20];
8959         u8         dword_10[0x20];
8960         u8         dword_11[0x20];
8961 };
8962
8963 struct mlx5_ifc_dcbx_param_bits {
8964         u8         dcbx_cee_cap[0x1];
8965         u8         dcbx_ieee_cap[0x1];
8966         u8         dcbx_standby_cap[0x1];
8967         u8         reserved_at_0[0x5];
8968         u8         port_number[0x8];
8969         u8         reserved_at_10[0xa];
8970         u8         max_application_table_size[6];
8971         u8         reserved_at_20[0x15];
8972         u8         version_oper[0x3];
8973         u8         reserved_at_38[5];
8974         u8         version_admin[0x3];
8975         u8         willing_admin[0x1];
8976         u8         reserved_at_41[0x3];
8977         u8         pfc_cap_oper[0x4];
8978         u8         reserved_at_48[0x4];
8979         u8         pfc_cap_admin[0x4];
8980         u8         reserved_at_50[0x4];
8981         u8         num_of_tc_oper[0x4];
8982         u8         reserved_at_58[0x4];
8983         u8         num_of_tc_admin[0x4];
8984         u8         remote_willing[0x1];
8985         u8         reserved_at_61[3];
8986         u8         remote_pfc_cap[4];
8987         u8         reserved_at_68[0x14];
8988         u8         remote_num_of_tc[0x4];
8989         u8         reserved_at_80[0x18];
8990         u8         error[0x8];
8991         u8         reserved_at_a0[0x160];
8992 };
8993
8994 struct mlx5_ifc_lagc_bits {
8995         u8         reserved_at_0[0x1d];
8996         u8         lag_state[0x3];
8997
8998         u8         reserved_at_20[0x14];
8999         u8         tx_remap_affinity_2[0x4];
9000         u8         reserved_at_38[0x4];
9001         u8         tx_remap_affinity_1[0x4];
9002 };
9003
9004 struct mlx5_ifc_create_lag_out_bits {
9005         u8         status[0x8];
9006         u8         reserved_at_8[0x18];
9007
9008         u8         syndrome[0x20];
9009
9010         u8         reserved_at_40[0x40];
9011 };
9012
9013 struct mlx5_ifc_create_lag_in_bits {
9014         u8         opcode[0x10];
9015         u8         reserved_at_10[0x10];
9016
9017         u8         reserved_at_20[0x10];
9018         u8         op_mod[0x10];
9019
9020         struct mlx5_ifc_lagc_bits ctx;
9021 };
9022
9023 struct mlx5_ifc_modify_lag_out_bits {
9024         u8         status[0x8];
9025         u8         reserved_at_8[0x18];
9026
9027         u8         syndrome[0x20];
9028
9029         u8         reserved_at_40[0x40];
9030 };
9031
9032 struct mlx5_ifc_modify_lag_in_bits {
9033         u8         opcode[0x10];
9034         u8         reserved_at_10[0x10];
9035
9036         u8         reserved_at_20[0x10];
9037         u8         op_mod[0x10];
9038
9039         u8         reserved_at_40[0x20];
9040         u8         field_select[0x20];
9041
9042         struct mlx5_ifc_lagc_bits ctx;
9043 };
9044
9045 struct mlx5_ifc_query_lag_out_bits {
9046         u8         status[0x8];
9047         u8         reserved_at_8[0x18];
9048
9049         u8         syndrome[0x20];
9050
9051         u8         reserved_at_40[0x40];
9052
9053         struct mlx5_ifc_lagc_bits ctx;
9054 };
9055
9056 struct mlx5_ifc_query_lag_in_bits {
9057         u8         opcode[0x10];
9058         u8         reserved_at_10[0x10];
9059
9060         u8         reserved_at_20[0x10];
9061         u8         op_mod[0x10];
9062
9063         u8         reserved_at_40[0x40];
9064 };
9065
9066 struct mlx5_ifc_destroy_lag_out_bits {
9067         u8         status[0x8];
9068         u8         reserved_at_8[0x18];
9069
9070         u8         syndrome[0x20];
9071
9072         u8         reserved_at_40[0x40];
9073 };
9074
9075 struct mlx5_ifc_destroy_lag_in_bits {
9076         u8         opcode[0x10];
9077         u8         reserved_at_10[0x10];
9078
9079         u8         reserved_at_20[0x10];
9080         u8         op_mod[0x10];
9081
9082         u8         reserved_at_40[0x40];
9083 };
9084
9085 struct mlx5_ifc_create_vport_lag_out_bits {
9086         u8         status[0x8];
9087         u8         reserved_at_8[0x18];
9088
9089         u8         syndrome[0x20];
9090
9091         u8         reserved_at_40[0x40];
9092 };
9093
9094 struct mlx5_ifc_create_vport_lag_in_bits {
9095         u8         opcode[0x10];
9096         u8         reserved_at_10[0x10];
9097
9098         u8         reserved_at_20[0x10];
9099         u8         op_mod[0x10];
9100
9101         u8         reserved_at_40[0x40];
9102 };
9103
9104 struct mlx5_ifc_destroy_vport_lag_out_bits {
9105         u8         status[0x8];
9106         u8         reserved_at_8[0x18];
9107
9108         u8         syndrome[0x20];
9109
9110         u8         reserved_at_40[0x40];
9111 };
9112
9113 struct mlx5_ifc_destroy_vport_lag_in_bits {
9114         u8         opcode[0x10];
9115         u8         reserved_at_10[0x10];
9116
9117         u8         reserved_at_20[0x10];
9118         u8         op_mod[0x10];
9119
9120         u8         reserved_at_40[0x40];
9121 };
9122
9123 struct mlx5_ifc_alloc_memic_in_bits {
9124         u8         opcode[0x10];
9125         u8         reserved_at_10[0x10];
9126
9127         u8         reserved_at_20[0x10];
9128         u8         op_mod[0x10];
9129
9130         u8         reserved_at_30[0x20];
9131
9132         u8         reserved_at_40[0x18];
9133         u8         log_memic_addr_alignment[0x8];
9134
9135         u8         range_start_addr[0x40];
9136
9137         u8         range_size[0x20];
9138
9139         u8         memic_size[0x20];
9140 };
9141
9142 struct mlx5_ifc_alloc_memic_out_bits {
9143         u8         status[0x8];
9144         u8         reserved_at_8[0x18];
9145
9146         u8         syndrome[0x20];
9147
9148         u8         memic_start_addr[0x40];
9149 };
9150
9151 struct mlx5_ifc_dealloc_memic_in_bits {
9152         u8         opcode[0x10];
9153         u8         reserved_at_10[0x10];
9154
9155         u8         reserved_at_20[0x10];
9156         u8         op_mod[0x10];
9157
9158         u8         reserved_at_40[0x40];
9159
9160         u8         memic_start_addr[0x40];
9161
9162         u8         memic_size[0x20];
9163
9164         u8         reserved_at_e0[0x20];
9165 };
9166
9167 struct mlx5_ifc_dealloc_memic_out_bits {
9168         u8         status[0x8];
9169         u8         reserved_at_8[0x18];
9170
9171         u8         syndrome[0x20];
9172
9173         u8         reserved_at_40[0x40];
9174 };
9175
9176 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9177         u8         opcode[0x10];
9178         u8         uid[0x10];
9179
9180         u8         reserved_at_20[0x10];
9181         u8         obj_type[0x10];
9182
9183         u8         obj_id[0x20];
9184
9185         u8         reserved_at_60[0x20];
9186 };
9187
9188 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9189         u8         status[0x8];
9190         u8         reserved_at_8[0x18];
9191
9192         u8         syndrome[0x20];
9193
9194         u8         obj_id[0x20];
9195
9196         u8         reserved_at_60[0x20];
9197 };
9198
9199 struct mlx5_ifc_umem_bits {
9200         u8         modify_field_select[0x40];
9201
9202         u8         reserved_at_40[0x5b];
9203         u8         log_page_size[0x5];
9204
9205         u8         page_offset[0x20];
9206
9207         u8         num_of_mtt[0x40];
9208
9209         struct mlx5_ifc_mtt_bits  mtt[0];
9210 };
9211
9212 struct mlx5_ifc_uctx_bits {
9213         u8         modify_field_select[0x40];
9214
9215         u8         reserved_at_40[0x1c0];
9216 };
9217
9218 struct mlx5_ifc_create_umem_in_bits {
9219         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9220         struct mlx5_ifc_umem_bits                     umem;
9221 };
9222
9223 struct mlx5_ifc_create_uctx_in_bits {
9224         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9225         struct mlx5_ifc_uctx_bits                     uctx;
9226 };
9227
9228 struct mlx5_ifc_mtrc_string_db_param_bits {
9229         u8         string_db_base_address[0x20];
9230
9231         u8         reserved_at_20[0x8];
9232         u8         string_db_size[0x18];
9233 };
9234
9235 struct mlx5_ifc_mtrc_cap_bits {
9236         u8         trace_owner[0x1];
9237         u8         trace_to_memory[0x1];
9238         u8         reserved_at_2[0x4];
9239         u8         trc_ver[0x2];
9240         u8         reserved_at_8[0x14];
9241         u8         num_string_db[0x4];
9242
9243         u8         first_string_trace[0x8];
9244         u8         num_string_trace[0x8];
9245         u8         reserved_at_30[0x28];
9246
9247         u8         log_max_trace_buffer_size[0x8];
9248
9249         u8         reserved_at_60[0x20];
9250
9251         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9252
9253         u8         reserved_at_280[0x180];
9254 };
9255
9256 struct mlx5_ifc_mtrc_conf_bits {
9257         u8         reserved_at_0[0x1c];
9258         u8         trace_mode[0x4];
9259         u8         reserved_at_20[0x18];
9260         u8         log_trace_buffer_size[0x8];
9261         u8         trace_mkey[0x20];
9262         u8         reserved_at_60[0x3a0];
9263 };
9264
9265 struct mlx5_ifc_mtrc_stdb_bits {
9266         u8         string_db_index[0x4];
9267         u8         reserved_at_4[0x4];
9268         u8         read_size[0x18];
9269         u8         start_offset[0x20];
9270         u8         string_db_data[0];
9271 };
9272
9273 struct mlx5_ifc_mtrc_ctrl_bits {
9274         u8         trace_status[0x2];
9275         u8         reserved_at_2[0x2];
9276         u8         arm_event[0x1];
9277         u8         reserved_at_5[0xb];
9278         u8         modify_field_select[0x10];
9279         u8         reserved_at_20[0x2b];
9280         u8         current_timestamp52_32[0x15];
9281         u8         current_timestamp31_0[0x20];
9282         u8         reserved_at_80[0x180];
9283 };
9284
9285 #endif /* MLX5_IFC_H */