include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
  96         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
  97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 132         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 133         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 134         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 135         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 136         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 137         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 138         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 139         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 140         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 141         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 142         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 143         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 145         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 146         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 147         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 148         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 149         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 150         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 151         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 152         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 153         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 154         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 155         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 156         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 157         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 158         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 159         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 160         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 161         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 162         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 163         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 164         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 165         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 166         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 167         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 168         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 169         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 170         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 171         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 172         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 173         MLX5_CMD_OP_NOP                           = 0x80d,
 174         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 175         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 178         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 179         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 180         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 181         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 182         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 183         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 184         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 185         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 186         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 187         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 188         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 189         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 190         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 191         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 192         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 193         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 194         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 195         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 196         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 197         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 198         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 199         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 200         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 201         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 202         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 203         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 204         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 205         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 206         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 207         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 208         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 209         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 210         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 211         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 212         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 213         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 214         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 215         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 216         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 217         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 218         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 219         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 220         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 222         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 223         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 224         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 225         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 226         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 227         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 228         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 229         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 230         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 231         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 232         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 233         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 234         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 235         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 236         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 237         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 238         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 239         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 240         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 241         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 242         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 243         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 244         MLX5_CMD_OP_MAX
 245 };
 246
 247 struct mlx5_ifc_flow_table_fields_supported_bits {
 248         u8         outer_dmac[0x1];
 249         u8         outer_smac[0x1];
 250         u8         outer_ether_type[0x1];
 251         u8         outer_ip_version[0x1];
 252         u8         outer_first_prio[0x1];
 253         u8         outer_first_cfi[0x1];
 254         u8         outer_first_vid[0x1];
 255         u8         outer_ipv4_ttl[0x1];
 256         u8         outer_second_prio[0x1];
 257         u8         outer_second_cfi[0x1];
 258         u8         outer_second_vid[0x1];
 259         u8         reserved_at_b[0x1];
 260         u8         outer_sip[0x1];
 261         u8         outer_dip[0x1];
 262         u8         outer_frag[0x1];
 263         u8         outer_ip_protocol[0x1];
 264         u8         outer_ip_ecn[0x1];
 265         u8         outer_ip_dscp[0x1];
 266         u8         outer_udp_sport[0x1];
 267         u8         outer_udp_dport[0x1];
 268         u8         outer_tcp_sport[0x1];
 269         u8         outer_tcp_dport[0x1];
 270         u8         outer_tcp_flags[0x1];
 271         u8         outer_gre_protocol[0x1];
 272         u8         outer_gre_key[0x1];
 273         u8         outer_vxlan_vni[0x1];
 274         u8         reserved_at_1a[0x5];
 275         u8         source_eswitch_port[0x1];
 276
 277         u8         inner_dmac[0x1];
 278         u8         inner_smac[0x1];
 279         u8         inner_ether_type[0x1];
 280         u8         inner_ip_version[0x1];
 281         u8         inner_first_prio[0x1];
 282         u8         inner_first_cfi[0x1];
 283         u8         inner_first_vid[0x1];
 284         u8         reserved_at_27[0x1];
 285         u8         inner_second_prio[0x1];
 286         u8         inner_second_cfi[0x1];
 287         u8         inner_second_vid[0x1];
 288         u8         reserved_at_2b[0x1];
 289         u8         inner_sip[0x1];
 290         u8         inner_dip[0x1];
 291         u8         inner_frag[0x1];
 292         u8         inner_ip_protocol[0x1];
 293         u8         inner_ip_ecn[0x1];
 294         u8         inner_ip_dscp[0x1];
 295         u8         inner_udp_sport[0x1];
 296         u8         inner_udp_dport[0x1];
 297         u8         inner_tcp_sport[0x1];
 298         u8         inner_tcp_dport[0x1];
 299         u8         inner_tcp_flags[0x1];
 300         u8         reserved_at_37[0x9];
 301         u8         reserved_at_40[0x17];
 302         u8         outer_esp_spi[0x1];
 303         u8         reserved_at_58[0x2];
 304         u8         bth_dst_qp[0x1];
 305
 306         u8         reserved_at_5b[0x25];
 307 };
 308
 309 struct mlx5_ifc_flow_table_prop_layout_bits {
 310         u8         ft_support[0x1];
 311         u8         reserved_at_1[0x1];
 312         u8         flow_counter[0x1];
 313         u8         flow_modify_en[0x1];
 314         u8         modify_root[0x1];
 315         u8         identified_miss_table_mode[0x1];
 316         u8         flow_table_modify[0x1];
 317         u8         encap[0x1];
 318         u8         decap[0x1];
 319         u8         reserved_at_9[0x1];
 320         u8         pop_vlan[0x1];
 321         u8         push_vlan[0x1];
 322         u8         reserved_at_c[0x14];
 323
 324         u8         reserved_at_20[0x2];
 325         u8         log_max_ft_size[0x6];
 326         u8         log_max_modify_header_context[0x8];
 327         u8         max_modify_header_actions[0x8];
 328         u8         max_ft_level[0x8];
 329
 330         u8         reserved_at_40[0x20];
 331
 332         u8         reserved_at_60[0x18];
 333         u8         log_max_ft_num[0x8];
 334
 335         u8         reserved_at_80[0x18];
 336         u8         log_max_destination[0x8];
 337
 338         u8         log_max_flow_counter[0x8];
 339         u8         reserved_at_a8[0x10];
 340         u8         log_max_flow[0x8];
 341
 342         u8         reserved_at_c0[0x40];
 343
 344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 345
 346         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 347 };
 348
 349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 350         u8         send[0x1];
 351         u8         receive[0x1];
 352         u8         write[0x1];
 353         u8         read[0x1];
 354         u8         atomic[0x1];
 355         u8         srq_receive[0x1];
 356         u8         reserved_at_6[0x1a];
 357 };
 358
 359 struct mlx5_ifc_ipv4_layout_bits {
 360         u8         reserved_at_0[0x60];
 361
 362         u8         ipv4[0x20];
 363 };
 364
 365 struct mlx5_ifc_ipv6_layout_bits {
 366         u8         ipv6[16][0x8];
 367 };
 368
 369 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 370         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 371         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 372         u8         reserved_at_0[0x80];
 373 };
 374
 375 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 376         u8         smac_47_16[0x20];
 377
 378         u8         smac_15_0[0x10];
 379         u8         ethertype[0x10];
 380
 381         u8         dmac_47_16[0x20];
 382
 383         u8         dmac_15_0[0x10];
 384         u8         first_prio[0x3];
 385         u8         first_cfi[0x1];
 386         u8         first_vid[0xc];
 387
 388         u8         ip_protocol[0x8];
 389         u8         ip_dscp[0x6];
 390         u8         ip_ecn[0x2];
 391         u8         cvlan_tag[0x1];
 392         u8         svlan_tag[0x1];
 393         u8         frag[0x1];
 394         u8         ip_version[0x4];
 395         u8         tcp_flags[0x9];
 396
 397         u8         tcp_sport[0x10];
 398         u8         tcp_dport[0x10];
 399
 400         u8         reserved_at_c0[0x18];
 401         u8         ttl_hoplimit[0x8];
 402
 403         u8         udp_sport[0x10];
 404         u8         udp_dport[0x10];
 405
 406         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 407
 408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 409 };
 410
 411 struct mlx5_ifc_fte_match_set_misc_bits {
 412         u8         reserved_at_0[0x8];
 413         u8         source_sqn[0x18];
 414
 415         u8         reserved_at_20[0x10];
 416         u8         source_port[0x10];
 417
 418         u8         outer_second_prio[0x3];
 419         u8         outer_second_cfi[0x1];
 420         u8         outer_second_vid[0xc];
 421         u8         inner_second_prio[0x3];
 422         u8         inner_second_cfi[0x1];
 423         u8         inner_second_vid[0xc];
 424
 425         u8         outer_second_cvlan_tag[0x1];
 426         u8         inner_second_cvlan_tag[0x1];
 427         u8         outer_second_svlan_tag[0x1];
 428         u8         inner_second_svlan_tag[0x1];
 429         u8         reserved_at_64[0xc];
 430         u8         gre_protocol[0x10];
 431
 432         u8         gre_key_h[0x18];
 433         u8         gre_key_l[0x8];
 434
 435         u8         vxlan_vni[0x18];
 436         u8         reserved_at_b8[0x8];
 437
 438         u8         reserved_at_c0[0x20];
 439
 440         u8         reserved_at_e0[0xc];
 441         u8         outer_ipv6_flow_label[0x14];
 442
 443         u8         reserved_at_100[0xc];
 444         u8         inner_ipv6_flow_label[0x14];
 445
 446         u8         reserved_at_120[0x28];
 447         u8         bth_dst_qp[0x18];
 448         u8         reserved_at_160[0x20];
 449         u8         outer_esp_spi[0x20];
 450         u8         reserved_at_1a0[0x60];
 451 };
 452
 453 struct mlx5_ifc_cmd_pas_bits {
 454         u8         pa_h[0x20];
 455
 456         u8         pa_l[0x14];
 457         u8         reserved_at_34[0xc];
 458 };
 459
 460 struct mlx5_ifc_uint64_bits {
 461         u8         hi[0x20];
 462
 463         u8         lo[0x20];
 464 };
 465
 466 enum {
 467         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 468         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 469         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 470         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 471         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 472         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 473         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 474         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 475         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 476         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 477 };
 478
 479 struct mlx5_ifc_ads_bits {
 480         u8         fl[0x1];
 481         u8         free_ar[0x1];
 482         u8         reserved_at_2[0xe];
 483         u8         pkey_index[0x10];
 484
 485         u8         reserved_at_20[0x8];
 486         u8         grh[0x1];
 487         u8         mlid[0x7];
 488         u8         rlid[0x10];
 489
 490         u8         ack_timeout[0x5];
 491         u8         reserved_at_45[0x3];
 492         u8         src_addr_index[0x8];
 493         u8         reserved_at_50[0x4];
 494         u8         stat_rate[0x4];
 495         u8         hop_limit[0x8];
 496
 497         u8         reserved_at_60[0x4];
 498         u8         tclass[0x8];
 499         u8         flow_label[0x14];
 500
 501         u8         rgid_rip[16][0x8];
 502
 503         u8         reserved_at_100[0x4];
 504         u8         f_dscp[0x1];
 505         u8         f_ecn[0x1];
 506         u8         reserved_at_106[0x1];
 507         u8         f_eth_prio[0x1];
 508         u8         ecn[0x2];
 509         u8         dscp[0x6];
 510         u8         udp_sport[0x10];
 511
 512         u8         dei_cfi[0x1];
 513         u8         eth_prio[0x3];
 514         u8         sl[0x4];
 515         u8         vhca_port_num[0x8];
 516         u8         rmac_47_32[0x10];
 517
 518         u8         rmac_31_0[0x20];
 519 };
 520
 521 struct mlx5_ifc_flow_table_nic_cap_bits {
 522         u8         nic_rx_multi_path_tirs[0x1];
 523         u8         nic_rx_multi_path_tirs_fts[0x1];
 524         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 525         u8         reserved_at_3[0x1fd];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 528
 529         u8         reserved_at_400[0x200];
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 532
 533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 534
 535         u8         reserved_at_a00[0x200];
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 538
 539         u8         reserved_at_e00[0x7200];
 540 };
 541
 542 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 543         u8     reserved_at_0[0x200];
 544
 545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 546
 547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 548
 549         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 550
 551         u8      reserved_at_800[0x7800];
 552 };
 553
 554 struct mlx5_ifc_e_switch_cap_bits {
 555         u8         vport_svlan_strip[0x1];
 556         u8         vport_cvlan_strip[0x1];
 557         u8         vport_svlan_insert[0x1];
 558         u8         vport_cvlan_insert_if_not_exist[0x1];
 559         u8         vport_cvlan_insert_overwrite[0x1];
 560         u8         reserved_at_5[0x18];
 561         u8         merged_eswitch[0x1];
 562         u8         nic_vport_node_guid_modify[0x1];
 563         u8         nic_vport_port_guid_modify[0x1];
 564
 565         u8         vxlan_encap_decap[0x1];
 566         u8         nvgre_encap_decap[0x1];
 567         u8         reserved_at_22[0x9];
 568         u8         log_max_encap_headers[0x5];
 569         u8         reserved_2b[0x6];
 570         u8         max_encap_header_size[0xa];
 571
 572         u8         reserved_40[0x7c0];
 573
 574 };
 575
 576 struct mlx5_ifc_qos_cap_bits {
 577         u8         packet_pacing[0x1];
 578         u8         esw_scheduling[0x1];
 579         u8         esw_bw_share[0x1];
 580         u8         esw_rate_limit[0x1];
 581         u8         reserved_at_4[0x1];
 582         u8         packet_pacing_burst_bound[0x1];
 583         u8         packet_pacing_typical_size[0x1];
 584         u8         reserved_at_7[0x19];
 585
 586         u8         reserved_at_20[0x20];
 587
 588         u8         packet_pacing_max_rate[0x20];
 589
 590         u8         packet_pacing_min_rate[0x20];
 591
 592         u8         reserved_at_80[0x10];
 593         u8         packet_pacing_rate_table_size[0x10];
 594
 595         u8         esw_element_type[0x10];
 596         u8         esw_tsar_type[0x10];
 597
 598         u8         reserved_at_c0[0x10];
 599         u8         max_qos_para_vport[0x10];
 600
 601         u8         max_tsar_bw_share[0x20];
 602
 603         u8         reserved_at_100[0x700];
 604 };
 605
 606 struct mlx5_ifc_debug_cap_bits {
 607         u8         reserved_at_0[0x20];
 608
 609         u8         reserved_at_20[0x2];
 610         u8         stall_detect[0x1];
 611         u8         reserved_at_23[0x1d];
 612
 613         u8         reserved_at_40[0x7c0];
 614 };
 615
 616 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 617         u8         csum_cap[0x1];
 618         u8         vlan_cap[0x1];
 619         u8         lro_cap[0x1];
 620         u8         lro_psh_flag[0x1];
 621         u8         lro_time_stamp[0x1];
 622         u8         reserved_at_5[0x2];
 623         u8         wqe_vlan_insert[0x1];
 624         u8         self_lb_en_modifiable[0x1];
 625         u8         reserved_at_9[0x2];
 626         u8         max_lso_cap[0x5];
 627         u8         multi_pkt_send_wqe[0x2];
 628         u8         wqe_inline_mode[0x2];
 629         u8         rss_ind_tbl_cap[0x4];
 630         u8         reg_umr_sq[0x1];
 631         u8         scatter_fcs[0x1];
 632         u8         enhanced_multi_pkt_send_wqe[0x1];
 633         u8         tunnel_lso_const_out_ip_id[0x1];
 634         u8         reserved_at_1c[0x2];
 635         u8         tunnel_stateless_gre[0x1];
 636         u8         tunnel_stateless_vxlan[0x1];
 637
 638         u8         swp[0x1];
 639         u8         swp_csum[0x1];
 640         u8         swp_lso[0x1];
 641         u8         reserved_at_23[0x1b];
 642         u8         max_geneve_opt_len[0x1];
 643         u8         tunnel_stateless_geneve_rx[0x1];
 644
 645         u8         reserved_at_40[0x10];
 646         u8         lro_min_mss_size[0x10];
 647
 648         u8         reserved_at_60[0x120];
 649
 650         u8         lro_timer_supported_periods[4][0x20];
 651
 652         u8         reserved_at_200[0x600];
 653 };
 654
 655 struct mlx5_ifc_roce_cap_bits {
 656         u8         roce_apm[0x1];
 657         u8         reserved_at_1[0x1f];
 658
 659         u8         reserved_at_20[0x60];
 660
 661         u8         reserved_at_80[0xc];
 662         u8         l3_type[0x4];
 663         u8         reserved_at_90[0x8];
 664         u8         roce_version[0x8];
 665
 666         u8         reserved_at_a0[0x10];
 667         u8         r_roce_dest_udp_port[0x10];
 668
 669         u8         r_roce_max_src_udp_port[0x10];
 670         u8         r_roce_min_src_udp_port[0x10];
 671
 672         u8         reserved_at_e0[0x10];
 673         u8         roce_address_table_size[0x10];
 674
 675         u8         reserved_at_100[0x700];
 676 };
 677
 678 struct mlx5_ifc_device_mem_cap_bits {
 679         u8         memic[0x1];
 680         u8         reserved_at_1[0x1f];
 681
 682         u8         reserved_at_20[0xb];
 683         u8         log_min_memic_alloc_size[0x5];
 684         u8         reserved_at_30[0x8];
 685         u8         log_max_memic_addr_alignment[0x8];
 686
 687         u8         memic_bar_start_addr[0x40];
 688
 689         u8         memic_bar_size[0x20];
 690
 691         u8         max_memic_size[0x20];
 692
 693         u8         reserved_at_c0[0x740];
 694 };
 695
 696 enum {
 697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 701         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 702         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 703         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 704         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 705         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 706 };
 707
 708 enum {
 709         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 710         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 711         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 712         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 717         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 718 };
 719
 720 struct mlx5_ifc_atomic_caps_bits {
 721         u8         reserved_at_0[0x40];
 722
 723         u8         atomic_req_8B_endianness_mode[0x2];
 724         u8         reserved_at_42[0x4];
 725         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 726
 727         u8         reserved_at_47[0x19];
 728
 729         u8         reserved_at_60[0x20];
 730
 731         u8         reserved_at_80[0x10];
 732         u8         atomic_operations[0x10];
 733
 734         u8         reserved_at_a0[0x10];
 735         u8         atomic_size_qp[0x10];
 736
 737         u8         reserved_at_c0[0x10];
 738         u8         atomic_size_dc[0x10];
 739
 740         u8         reserved_at_e0[0x720];
 741 };
 742
 743 struct mlx5_ifc_odp_cap_bits {
 744         u8         reserved_at_0[0x40];
 745
 746         u8         sig[0x1];
 747         u8         reserved_at_41[0x1f];
 748
 749         u8         reserved_at_60[0x20];
 750
 751         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 752
 753         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 754
 755         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 756
 757         u8         reserved_at_e0[0x720];
 758 };
 759
 760 struct mlx5_ifc_calc_op {
 761         u8        reserved_at_0[0x10];
 762         u8        reserved_at_10[0x9];
 763         u8        op_swap_endianness[0x1];
 764         u8        op_min[0x1];
 765         u8        op_xor[0x1];
 766         u8        op_or[0x1];
 767         u8        op_and[0x1];
 768         u8        op_max[0x1];
 769         u8        op_add[0x1];
 770 };
 771
 772 struct mlx5_ifc_vector_calc_cap_bits {
 773         u8         calc_matrix[0x1];
 774         u8         reserved_at_1[0x1f];
 775         u8         reserved_at_20[0x8];
 776         u8         max_vec_count[0x8];
 777         u8         reserved_at_30[0xd];
 778         u8         max_chunk_size[0x3];
 779         struct mlx5_ifc_calc_op calc0;
 780         struct mlx5_ifc_calc_op calc1;
 781         struct mlx5_ifc_calc_op calc2;
 782         struct mlx5_ifc_calc_op calc3;
 783
 784         u8         reserved_at_e0[0x720];
 785 };
 786
 787 enum {
 788         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 789         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 790         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 791         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 792 };
 793
 794 enum {
 795         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 796         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 797 };
 798
 799 enum {
 800         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 801         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 802         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 803         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 804         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 805 };
 806
 807 enum {
 808         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 809         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 810         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 811         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 812         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 813         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 814 };
 815
 816 enum {
 817         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 818         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 819 };
 820
 821 enum {
 822         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 823         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 824         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 825 };
 826
 827 enum {
 828         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 829         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 830 };
 831
 832 enum {
 833         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 834         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 835         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 836 };
 837
 838 struct mlx5_ifc_cmd_hca_cap_bits {
 839         u8         reserved_at_0[0x30];
 840         u8         vhca_id[0x10];
 841
 842         u8         reserved_at_40[0x40];
 843
 844         u8         log_max_srq_sz[0x8];
 845         u8         log_max_qp_sz[0x8];
 846         u8         reserved_at_90[0xb];
 847         u8         log_max_qp[0x5];
 848
 849         u8         reserved_at_a0[0xb];
 850         u8         log_max_srq[0x5];
 851         u8         reserved_at_b0[0x10];
 852
 853         u8         reserved_at_c0[0x8];
 854         u8         log_max_cq_sz[0x8];
 855         u8         reserved_at_d0[0xb];
 856         u8         log_max_cq[0x5];
 857
 858         u8         log_max_eq_sz[0x8];
 859         u8         reserved_at_e8[0x2];
 860         u8         log_max_mkey[0x6];
 861         u8         reserved_at_f0[0xc];
 862         u8         log_max_eq[0x4];
 863
 864         u8         max_indirection[0x8];
 865         u8         fixed_buffer_size[0x1];
 866         u8         log_max_mrw_sz[0x7];
 867         u8         force_teardown[0x1];
 868         u8         reserved_at_111[0x1];
 869         u8         log_max_bsf_list_size[0x6];
 870         u8         umr_extended_translation_offset[0x1];
 871         u8         null_mkey[0x1];
 872         u8         log_max_klm_list_size[0x6];
 873
 874         u8         reserved_at_120[0xa];
 875         u8         log_max_ra_req_dc[0x6];
 876         u8         reserved_at_130[0xa];
 877         u8         log_max_ra_res_dc[0x6];
 878
 879         u8         reserved_at_140[0xa];
 880         u8         log_max_ra_req_qp[0x6];
 881         u8         reserved_at_150[0xa];
 882         u8         log_max_ra_res_qp[0x6];
 883
 884         u8         end_pad[0x1];
 885         u8         cc_query_allowed[0x1];
 886         u8         cc_modify_allowed[0x1];
 887         u8         start_pad[0x1];
 888         u8         cache_line_128byte[0x1];
 889         u8         reserved_at_165[0xa];
 890         u8         qcam_reg[0x1];
 891         u8         gid_table_size[0x10];
 892
 893         u8         out_of_seq_cnt[0x1];
 894         u8         vport_counters[0x1];
 895         u8         retransmission_q_counters[0x1];
 896         u8         debug[0x1];
 897         u8         modify_rq_counter_set_id[0x1];
 898         u8         rq_delay_drop[0x1];
 899         u8         max_qp_cnt[0xa];
 900         u8         pkey_table_size[0x10];
 901
 902         u8         vport_group_manager[0x1];
 903         u8         vhca_group_manager[0x1];
 904         u8         ib_virt[0x1];
 905         u8         eth_virt[0x1];
 906         u8         vnic_env_queue_counters[0x1];
 907         u8         ets[0x1];
 908         u8         nic_flow_table[0x1];
 909         u8         eswitch_flow_table[0x1];
 910         u8         device_memory[0x1];
 911         u8         mcam_reg[0x1];
 912         u8         pcam_reg[0x1];
 913         u8         local_ca_ack_delay[0x5];
 914         u8         port_module_event[0x1];
 915         u8         enhanced_error_q_counters[0x1];
 916         u8         ports_check[0x1];
 917         u8         reserved_at_1b3[0x1];
 918         u8         disable_link_up[0x1];
 919         u8         beacon_led[0x1];
 920         u8         port_type[0x2];
 921         u8         num_ports[0x8];
 922
 923         u8         reserved_at_1c0[0x1];
 924         u8         pps[0x1];
 925         u8         pps_modify[0x1];
 926         u8         log_max_msg[0x5];
 927         u8         reserved_at_1c8[0x4];
 928         u8         max_tc[0x4];
 929         u8         reserved_at_1d0[0x1];
 930         u8         dcbx[0x1];
 931         u8         general_notification_event[0x1];
 932         u8         reserved_at_1d3[0x2];
 933         u8         fpga[0x1];
 934         u8         rol_s[0x1];
 935         u8         rol_g[0x1];
 936         u8         reserved_at_1d8[0x1];
 937         u8         wol_s[0x1];
 938         u8         wol_g[0x1];
 939         u8         wol_a[0x1];
 940         u8         wol_b[0x1];
 941         u8         wol_m[0x1];
 942         u8         wol_u[0x1];
 943         u8         wol_p[0x1];
 944
 945         u8         stat_rate_support[0x10];
 946         u8         reserved_at_1f0[0xc];
 947         u8         cqe_version[0x4];
 948
 949         u8         compact_address_vector[0x1];
 950         u8         striding_rq[0x1];
 951         u8         reserved_at_202[0x1];
 952         u8         ipoib_enhanced_offloads[0x1];
 953         u8         ipoib_basic_offloads[0x1];
 954         u8         reserved_at_205[0x1];
 955         u8         repeated_block_disabled[0x1];
 956         u8         umr_modify_entity_size_disabled[0x1];
 957         u8         umr_modify_atomic_disabled[0x1];
 958         u8         umr_indirect_mkey_disabled[0x1];
 959         u8         umr_fence[0x2];
 960         u8         reserved_at_20c[0x3];
 961         u8         drain_sigerr[0x1];
 962         u8         cmdif_checksum[0x2];
 963         u8         sigerr_cqe[0x1];
 964         u8         reserved_at_213[0x1];
 965         u8         wq_signature[0x1];
 966         u8         sctr_data_cqe[0x1];
 967         u8         reserved_at_216[0x1];
 968         u8         sho[0x1];
 969         u8         tph[0x1];
 970         u8         rf[0x1];
 971         u8         dct[0x1];
 972         u8         qos[0x1];
 973         u8         eth_net_offloads[0x1];
 974         u8         roce[0x1];
 975         u8         atomic[0x1];
 976         u8         reserved_at_21f[0x1];
 977
 978         u8         cq_oi[0x1];
 979         u8         cq_resize[0x1];
 980         u8         cq_moderation[0x1];
 981         u8         reserved_at_223[0x3];
 982         u8         cq_eq_remap[0x1];
 983         u8         pg[0x1];
 984         u8         block_lb_mc[0x1];
 985         u8         reserved_at_229[0x1];
 986         u8         scqe_break_moderation[0x1];
 987         u8         cq_period_start_from_cqe[0x1];
 988         u8         cd[0x1];
 989         u8         reserved_at_22d[0x1];
 990         u8         apm[0x1];
 991         u8         vector_calc[0x1];
 992         u8         umr_ptr_rlky[0x1];
 993         u8         imaicl[0x1];
 994         u8         reserved_at_232[0x4];
 995         u8         qkv[0x1];
 996         u8         pkv[0x1];
 997         u8         set_deth_sqpn[0x1];
 998         u8         reserved_at_239[0x3];
 999         u8         xrc[0x1];
1000         u8         ud[0x1];
1001         u8         uc[0x1];
1002         u8         rc[0x1];
1003
1004         u8         uar_4k[0x1];
1005         u8         reserved_at_241[0x9];
1006         u8         uar_sz[0x6];
1007         u8         reserved_at_250[0x8];
1008         u8         log_pg_sz[0x8];
1009
1010         u8         bf[0x1];
1011         u8         driver_version[0x1];
1012         u8         pad_tx_eth_packet[0x1];
1013         u8         reserved_at_263[0x8];
1014         u8         log_bf_reg_size[0x5];
1015
1016         u8         reserved_at_270[0xb];
1017         u8         lag_master[0x1];
1018         u8         num_lag_ports[0x4];
1019
1020         u8         reserved_at_280[0x10];
1021         u8         max_wqe_sz_sq[0x10];
1022
1023         u8         reserved_at_2a0[0x10];
1024         u8         max_wqe_sz_rq[0x10];
1025
1026         u8         max_flow_counter_31_16[0x10];
1027         u8         max_wqe_sz_sq_dc[0x10];
1028
1029         u8         reserved_at_2e0[0x7];
1030         u8         max_qp_mcg[0x19];
1031
1032         u8         reserved_at_300[0x18];
1033         u8         log_max_mcg[0x8];
1034
1035         u8         reserved_at_320[0x3];
1036         u8         log_max_transport_domain[0x5];
1037         u8         reserved_at_328[0x3];
1038         u8         log_max_pd[0x5];
1039         u8         reserved_at_330[0xb];
1040         u8         log_max_xrcd[0x5];
1041
1042         u8         nic_receive_steering_discard[0x1];
1043         u8         receive_discard_vport_down[0x1];
1044         u8         transmit_discard_vport_down[0x1];
1045         u8         reserved_at_343[0x5];
1046         u8         log_max_flow_counter_bulk[0x8];
1047         u8         max_flow_counter_15_0[0x10];
1048
1049
1050         u8         reserved_at_360[0x3];
1051         u8         log_max_rq[0x5];
1052         u8         reserved_at_368[0x3];
1053         u8         log_max_sq[0x5];
1054         u8         reserved_at_370[0x3];
1055         u8         log_max_tir[0x5];
1056         u8         reserved_at_378[0x3];
1057         u8         log_max_tis[0x5];
1058
1059         u8         basic_cyclic_rcv_wqe[0x1];
1060         u8         reserved_at_381[0x2];
1061         u8         log_max_rmp[0x5];
1062         u8         reserved_at_388[0x3];
1063         u8         log_max_rqt[0x5];
1064         u8         reserved_at_390[0x3];
1065         u8         log_max_rqt_size[0x5];
1066         u8         reserved_at_398[0x3];
1067         u8         log_max_tis_per_sq[0x5];
1068
1069         u8         ext_stride_num_range[0x1];
1070         u8         reserved_at_3a1[0x2];
1071         u8         log_max_stride_sz_rq[0x5];
1072         u8         reserved_at_3a8[0x3];
1073         u8         log_min_stride_sz_rq[0x5];
1074         u8         reserved_at_3b0[0x3];
1075         u8         log_max_stride_sz_sq[0x5];
1076         u8         reserved_at_3b8[0x3];
1077         u8         log_min_stride_sz_sq[0x5];
1078
1079         u8         hairpin[0x1];
1080         u8         reserved_at_3c1[0x2];
1081         u8         log_max_hairpin_queues[0x5];
1082         u8         reserved_at_3c8[0x3];
1083         u8         log_max_hairpin_wq_data_sz[0x5];
1084         u8         reserved_at_3d0[0x3];
1085         u8         log_max_hairpin_num_packets[0x5];
1086         u8         reserved_at_3d8[0x3];
1087         u8         log_max_wq_sz[0x5];
1088
1089         u8         nic_vport_change_event[0x1];
1090         u8         disable_local_lb_uc[0x1];
1091         u8         disable_local_lb_mc[0x1];
1092         u8         log_min_hairpin_wq_data_sz[0x5];
1093         u8         reserved_at_3e8[0x3];
1094         u8         log_max_vlan_list[0x5];
1095         u8         reserved_at_3f0[0x3];
1096         u8         log_max_current_mc_list[0x5];
1097         u8         reserved_at_3f8[0x3];
1098         u8         log_max_current_uc_list[0x5];
1099
1100         u8         reserved_at_400[0x80];
1101
1102         u8         reserved_at_480[0x3];
1103         u8         log_max_l2_table[0x5];
1104         u8         reserved_at_488[0x8];
1105         u8         log_uar_page_sz[0x10];
1106
1107         u8         reserved_at_4a0[0x20];
1108         u8         device_frequency_mhz[0x20];
1109         u8         device_frequency_khz[0x20];
1110
1111         u8         reserved_at_500[0x20];
1112         u8         num_of_uars_per_page[0x20];
1113         u8         reserved_at_540[0x40];
1114
1115         u8         reserved_at_580[0x3d];
1116         u8         cqe_128_always[0x1];
1117         u8         cqe_compression_128[0x1];
1118         u8         cqe_compression[0x1];
1119
1120         u8         cqe_compression_timeout[0x10];
1121         u8         cqe_compression_max_num[0x10];
1122
1123         u8         reserved_at_5e0[0x10];
1124         u8         tag_matching[0x1];
1125         u8         rndv_offload_rc[0x1];
1126         u8         rndv_offload_dc[0x1];
1127         u8         log_tag_matching_list_sz[0x5];
1128         u8         reserved_at_5f8[0x3];
1129         u8         log_max_xrq[0x5];
1130
1131         u8         affiliate_nic_vport_criteria[0x8];
1132         u8         native_port_num[0x8];
1133         u8         num_vhca_ports[0x8];
1134         u8         reserved_at_618[0x6];
1135         u8         sw_owner_id[0x1];
1136         u8         reserved_at_61f[0x1e1];
1137 };
1138
1139 enum mlx5_flow_destination_type {
1140         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1141         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1142         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1143
1144         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1145         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1146 };
1147
1148 struct mlx5_ifc_dest_format_struct_bits {
1149         u8         destination_type[0x8];
1150         u8         destination_id[0x18];
1151         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1152         u8         reserved_at_21[0xf];
1153         u8         destination_eswitch_owner_vhca_id[0x10];
1154 };
1155
1156 struct mlx5_ifc_flow_counter_list_bits {
1157         u8         flow_counter_id[0x20];
1158
1159         u8         reserved_at_20[0x20];
1160 };
1161
1162 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1163         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1164         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1165         u8         reserved_at_0[0x40];
1166 };
1167
1168 struct mlx5_ifc_fte_match_param_bits {
1169         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1170
1171         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1172
1173         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1174
1175         u8         reserved_at_600[0xa00];
1176 };
1177
1178 enum {
1179         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1180         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1181         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1182         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1183         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1184 };
1185
1186 struct mlx5_ifc_rx_hash_field_select_bits {
1187         u8         l3_prot_type[0x1];
1188         u8         l4_prot_type[0x1];
1189         u8         selected_fields[0x1e];
1190 };
1191
1192 enum {
1193         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1194         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1195 };
1196
1197 enum {
1198         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1199         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1200 };
1201
1202 struct mlx5_ifc_wq_bits {
1203         u8         wq_type[0x4];
1204         u8         wq_signature[0x1];
1205         u8         end_padding_mode[0x2];
1206         u8         cd_slave[0x1];
1207         u8         reserved_at_8[0x18];
1208
1209         u8         hds_skip_first_sge[0x1];
1210         u8         log2_hds_buf_size[0x3];
1211         u8         reserved_at_24[0x7];
1212         u8         page_offset[0x5];
1213         u8         lwm[0x10];
1214
1215         u8         reserved_at_40[0x8];
1216         u8         pd[0x18];
1217
1218         u8         reserved_at_60[0x8];
1219         u8         uar_page[0x18];
1220
1221         u8         dbr_addr[0x40];
1222
1223         u8         hw_counter[0x20];
1224
1225         u8         sw_counter[0x20];
1226
1227         u8         reserved_at_100[0xc];
1228         u8         log_wq_stride[0x4];
1229         u8         reserved_at_110[0x3];
1230         u8         log_wq_pg_sz[0x5];
1231         u8         reserved_at_118[0x3];
1232         u8         log_wq_sz[0x5];
1233
1234         u8         reserved_at_120[0x3];
1235         u8         log_hairpin_num_packets[0x5];
1236         u8         reserved_at_128[0x3];
1237         u8         log_hairpin_data_sz[0x5];
1238
1239         u8         reserved_at_130[0x4];
1240         u8         log_wqe_num_of_strides[0x4];
1241         u8         two_byte_shift_en[0x1];
1242         u8         reserved_at_139[0x4];
1243         u8         log_wqe_stride_size[0x3];
1244
1245         u8         reserved_at_140[0x4c0];
1246
1247         struct mlx5_ifc_cmd_pas_bits pas[0];
1248 };
1249
1250 struct mlx5_ifc_rq_num_bits {
1251         u8         reserved_at_0[0x8];
1252         u8         rq_num[0x18];
1253 };
1254
1255 struct mlx5_ifc_mac_address_layout_bits {
1256         u8         reserved_at_0[0x10];
1257         u8         mac_addr_47_32[0x10];
1258
1259         u8         mac_addr_31_0[0x20];
1260 };
1261
1262 struct mlx5_ifc_vlan_layout_bits {
1263         u8         reserved_at_0[0x14];
1264         u8         vlan[0x0c];
1265
1266         u8         reserved_at_20[0x20];
1267 };
1268
1269 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1270         u8         reserved_at_0[0xa0];
1271
1272         u8         min_time_between_cnps[0x20];
1273
1274         u8         reserved_at_c0[0x12];
1275         u8         cnp_dscp[0x6];
1276         u8         reserved_at_d8[0x4];
1277         u8         cnp_prio_mode[0x1];
1278         u8         cnp_802p_prio[0x3];
1279
1280         u8         reserved_at_e0[0x720];
1281 };
1282
1283 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1284         u8         reserved_at_0[0x60];
1285
1286         u8         reserved_at_60[0x4];
1287         u8         clamp_tgt_rate[0x1];
1288         u8         reserved_at_65[0x3];
1289         u8         clamp_tgt_rate_after_time_inc[0x1];
1290         u8         reserved_at_69[0x17];
1291
1292         u8         reserved_at_80[0x20];
1293
1294         u8         rpg_time_reset[0x20];
1295
1296         u8         rpg_byte_reset[0x20];
1297
1298         u8         rpg_threshold[0x20];
1299
1300         u8         rpg_max_rate[0x20];
1301
1302         u8         rpg_ai_rate[0x20];
1303
1304         u8         rpg_hai_rate[0x20];
1305
1306         u8         rpg_gd[0x20];
1307
1308         u8         rpg_min_dec_fac[0x20];
1309
1310         u8         rpg_min_rate[0x20];
1311
1312         u8         reserved_at_1c0[0xe0];
1313
1314         u8         rate_to_set_on_first_cnp[0x20];
1315
1316         u8         dce_tcp_g[0x20];
1317
1318         u8         dce_tcp_rtt[0x20];
1319
1320         u8         rate_reduce_monitor_period[0x20];
1321
1322         u8         reserved_at_320[0x20];
1323
1324         u8         initial_alpha_value[0x20];
1325
1326         u8         reserved_at_360[0x4a0];
1327 };
1328
1329 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1330         u8         reserved_at_0[0x80];
1331
1332         u8         rppp_max_rps[0x20];
1333
1334         u8         rpg_time_reset[0x20];
1335
1336         u8         rpg_byte_reset[0x20];
1337
1338         u8         rpg_threshold[0x20];
1339
1340         u8         rpg_max_rate[0x20];
1341
1342         u8         rpg_ai_rate[0x20];
1343
1344         u8         rpg_hai_rate[0x20];
1345
1346         u8         rpg_gd[0x20];
1347
1348         u8         rpg_min_dec_fac[0x20];
1349
1350         u8         rpg_min_rate[0x20];
1351
1352         u8         reserved_at_1c0[0x640];
1353 };
1354
1355 enum {
1356         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1357         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1358         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1359 };
1360
1361 struct mlx5_ifc_resize_field_select_bits {
1362         u8         resize_field_select[0x20];
1363 };
1364
1365 enum {
1366         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1367         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1368         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1369         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1370 };
1371
1372 struct mlx5_ifc_modify_field_select_bits {
1373         u8         modify_field_select[0x20];
1374 };
1375
1376 struct mlx5_ifc_field_select_r_roce_np_bits {
1377         u8         field_select_r_roce_np[0x20];
1378 };
1379
1380 struct mlx5_ifc_field_select_r_roce_rp_bits {
1381         u8         field_select_r_roce_rp[0x20];
1382 };
1383
1384 enum {
1385         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1392         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1393         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1394         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1395 };
1396
1397 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1398         u8         field_select_8021qaurp[0x20];
1399 };
1400
1401 struct mlx5_ifc_phys_layer_cntrs_bits {
1402         u8         time_since_last_clear_high[0x20];
1403
1404         u8         time_since_last_clear_low[0x20];
1405
1406         u8         symbol_errors_high[0x20];
1407
1408         u8         symbol_errors_low[0x20];
1409
1410         u8         sync_headers_errors_high[0x20];
1411
1412         u8         sync_headers_errors_low[0x20];
1413
1414         u8         edpl_bip_errors_lane0_high[0x20];
1415
1416         u8         edpl_bip_errors_lane0_low[0x20];
1417
1418         u8         edpl_bip_errors_lane1_high[0x20];
1419
1420         u8         edpl_bip_errors_lane1_low[0x20];
1421
1422         u8         edpl_bip_errors_lane2_high[0x20];
1423
1424         u8         edpl_bip_errors_lane2_low[0x20];
1425
1426         u8         edpl_bip_errors_lane3_high[0x20];
1427
1428         u8         edpl_bip_errors_lane3_low[0x20];
1429
1430         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1431
1432         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1433
1434         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1435
1436         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1437
1438         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1439
1440         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1441
1442         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1443
1444         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1445
1446         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1447
1448         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1449
1450         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1451
1452         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1453
1454         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1455
1456         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1457
1458         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1459
1460         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1461
1462         u8         rs_fec_corrected_blocks_high[0x20];
1463
1464         u8         rs_fec_corrected_blocks_low[0x20];
1465
1466         u8         rs_fec_uncorrectable_blocks_high[0x20];
1467
1468         u8         rs_fec_uncorrectable_blocks_low[0x20];
1469
1470         u8         rs_fec_no_errors_blocks_high[0x20];
1471
1472         u8         rs_fec_no_errors_blocks_low[0x20];
1473
1474         u8         rs_fec_single_error_blocks_high[0x20];
1475
1476         u8         rs_fec_single_error_blocks_low[0x20];
1477
1478         u8         rs_fec_corrected_symbols_total_high[0x20];
1479
1480         u8         rs_fec_corrected_symbols_total_low[0x20];
1481
1482         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1483
1484         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1485
1486         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1487
1488         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1489
1490         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1491
1492         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1493
1494         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1495
1496         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1497
1498         u8         link_down_events[0x20];
1499
1500         u8         successful_recovery_events[0x20];
1501
1502         u8         reserved_at_640[0x180];
1503 };
1504
1505 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1506         u8         time_since_last_clear_high[0x20];
1507
1508         u8         time_since_last_clear_low[0x20];
1509
1510         u8         phy_received_bits_high[0x20];
1511
1512         u8         phy_received_bits_low[0x20];
1513
1514         u8         phy_symbol_errors_high[0x20];
1515
1516         u8         phy_symbol_errors_low[0x20];
1517
1518         u8         phy_corrected_bits_high[0x20];
1519
1520         u8         phy_corrected_bits_low[0x20];
1521
1522         u8         phy_corrected_bits_lane0_high[0x20];
1523
1524         u8         phy_corrected_bits_lane0_low[0x20];
1525
1526         u8         phy_corrected_bits_lane1_high[0x20];
1527
1528         u8         phy_corrected_bits_lane1_low[0x20];
1529
1530         u8         phy_corrected_bits_lane2_high[0x20];
1531
1532         u8         phy_corrected_bits_lane2_low[0x20];
1533
1534         u8         phy_corrected_bits_lane3_high[0x20];
1535
1536         u8         phy_corrected_bits_lane3_low[0x20];
1537
1538         u8         reserved_at_200[0x5c0];
1539 };
1540
1541 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1542         u8         symbol_error_counter[0x10];
1543
1544         u8         link_error_recovery_counter[0x8];
1545
1546         u8         link_downed_counter[0x8];
1547
1548         u8         port_rcv_errors[0x10];
1549
1550         u8         port_rcv_remote_physical_errors[0x10];
1551
1552         u8         port_rcv_switch_relay_errors[0x10];
1553
1554         u8         port_xmit_discards[0x10];
1555
1556         u8         port_xmit_constraint_errors[0x8];
1557
1558         u8         port_rcv_constraint_errors[0x8];
1559
1560         u8         reserved_at_70[0x8];
1561
1562         u8         link_overrun_errors[0x8];
1563
1564         u8         reserved_at_80[0x10];
1565
1566         u8         vl_15_dropped[0x10];
1567
1568         u8         reserved_at_a0[0x80];
1569
1570         u8         port_xmit_wait[0x20];
1571 };
1572
1573 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1574         u8         transmit_queue_high[0x20];
1575
1576         u8         transmit_queue_low[0x20];
1577
1578         u8         reserved_at_40[0x780];
1579 };
1580
1581 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1582         u8         rx_octets_high[0x20];
1583
1584         u8         rx_octets_low[0x20];
1585
1586         u8         reserved_at_40[0xc0];
1587
1588         u8         rx_frames_high[0x20];
1589
1590         u8         rx_frames_low[0x20];
1591
1592         u8         tx_octets_high[0x20];
1593
1594         u8         tx_octets_low[0x20];
1595
1596         u8         reserved_at_180[0xc0];
1597
1598         u8         tx_frames_high[0x20];
1599
1600         u8         tx_frames_low[0x20];
1601
1602         u8         rx_pause_high[0x20];
1603
1604         u8         rx_pause_low[0x20];
1605
1606         u8         rx_pause_duration_high[0x20];
1607
1608         u8         rx_pause_duration_low[0x20];
1609
1610         u8         tx_pause_high[0x20];
1611
1612         u8         tx_pause_low[0x20];
1613
1614         u8         tx_pause_duration_high[0x20];
1615
1616         u8         tx_pause_duration_low[0x20];
1617
1618         u8         rx_pause_transition_high[0x20];
1619
1620         u8         rx_pause_transition_low[0x20];
1621
1622         u8         reserved_at_3c0[0x40];
1623
1624         u8         device_stall_minor_watermark_cnt_high[0x20];
1625
1626         u8         device_stall_minor_watermark_cnt_low[0x20];
1627
1628         u8         device_stall_critical_watermark_cnt_high[0x20];
1629
1630         u8         device_stall_critical_watermark_cnt_low[0x20];
1631
1632         u8         reserved_at_480[0x340];
1633 };
1634
1635 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1636         u8         port_transmit_wait_high[0x20];
1637
1638         u8         port_transmit_wait_low[0x20];
1639
1640         u8         reserved_at_40[0x100];
1641
1642         u8         rx_buffer_almost_full_high[0x20];
1643
1644         u8         rx_buffer_almost_full_low[0x20];
1645
1646         u8         rx_buffer_full_high[0x20];
1647
1648         u8         rx_buffer_full_low[0x20];
1649
1650         u8         reserved_at_1c0[0x600];
1651 };
1652
1653 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1654         u8         dot3stats_alignment_errors_high[0x20];
1655
1656         u8         dot3stats_alignment_errors_low[0x20];
1657
1658         u8         dot3stats_fcs_errors_high[0x20];
1659
1660         u8         dot3stats_fcs_errors_low[0x20];
1661
1662         u8         dot3stats_single_collision_frames_high[0x20];
1663
1664         u8         dot3stats_single_collision_frames_low[0x20];
1665
1666         u8         dot3stats_multiple_collision_frames_high[0x20];
1667
1668         u8         dot3stats_multiple_collision_frames_low[0x20];
1669
1670         u8         dot3stats_sqe_test_errors_high[0x20];
1671
1672         u8         dot3stats_sqe_test_errors_low[0x20];
1673
1674         u8         dot3stats_deferred_transmissions_high[0x20];
1675
1676         u8         dot3stats_deferred_transmissions_low[0x20];
1677
1678         u8         dot3stats_late_collisions_high[0x20];
1679
1680         u8         dot3stats_late_collisions_low[0x20];
1681
1682         u8         dot3stats_excessive_collisions_high[0x20];
1683
1684         u8         dot3stats_excessive_collisions_low[0x20];
1685
1686         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1687
1688         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1689
1690         u8         dot3stats_carrier_sense_errors_high[0x20];
1691
1692         u8         dot3stats_carrier_sense_errors_low[0x20];
1693
1694         u8         dot3stats_frame_too_longs_high[0x20];
1695
1696         u8         dot3stats_frame_too_longs_low[0x20];
1697
1698         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1699
1700         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1701
1702         u8         dot3stats_symbol_errors_high[0x20];
1703
1704         u8         dot3stats_symbol_errors_low[0x20];
1705
1706         u8         dot3control_in_unknown_opcodes_high[0x20];
1707
1708         u8         dot3control_in_unknown_opcodes_low[0x20];
1709
1710         u8         dot3in_pause_frames_high[0x20];
1711
1712         u8         dot3in_pause_frames_low[0x20];
1713
1714         u8         dot3out_pause_frames_high[0x20];
1715
1716         u8         dot3out_pause_frames_low[0x20];
1717
1718         u8         reserved_at_400[0x3c0];
1719 };
1720
1721 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1722         u8         ether_stats_drop_events_high[0x20];
1723
1724         u8         ether_stats_drop_events_low[0x20];
1725
1726         u8         ether_stats_octets_high[0x20];
1727
1728         u8         ether_stats_octets_low[0x20];
1729
1730         u8         ether_stats_pkts_high[0x20];
1731
1732         u8         ether_stats_pkts_low[0x20];
1733
1734         u8         ether_stats_broadcast_pkts_high[0x20];
1735
1736         u8         ether_stats_broadcast_pkts_low[0x20];
1737
1738         u8         ether_stats_multicast_pkts_high[0x20];
1739
1740         u8         ether_stats_multicast_pkts_low[0x20];
1741
1742         u8         ether_stats_crc_align_errors_high[0x20];
1743
1744         u8         ether_stats_crc_align_errors_low[0x20];
1745
1746         u8         ether_stats_undersize_pkts_high[0x20];
1747
1748         u8         ether_stats_undersize_pkts_low[0x20];
1749
1750         u8         ether_stats_oversize_pkts_high[0x20];
1751
1752         u8         ether_stats_oversize_pkts_low[0x20];
1753
1754         u8         ether_stats_fragments_high[0x20];
1755
1756         u8         ether_stats_fragments_low[0x20];
1757
1758         u8         ether_stats_jabbers_high[0x20];
1759
1760         u8         ether_stats_jabbers_low[0x20];
1761
1762         u8         ether_stats_collisions_high[0x20];
1763
1764         u8         ether_stats_collisions_low[0x20];
1765
1766         u8         ether_stats_pkts64octets_high[0x20];
1767
1768         u8         ether_stats_pkts64octets_low[0x20];
1769
1770         u8         ether_stats_pkts65to127octets_high[0x20];
1771
1772         u8         ether_stats_pkts65to127octets_low[0x20];
1773
1774         u8         ether_stats_pkts128to255octets_high[0x20];
1775
1776         u8         ether_stats_pkts128to255octets_low[0x20];
1777
1778         u8         ether_stats_pkts256to511octets_high[0x20];
1779
1780         u8         ether_stats_pkts256to511octets_low[0x20];
1781
1782         u8         ether_stats_pkts512to1023octets_high[0x20];
1783
1784         u8         ether_stats_pkts512to1023octets_low[0x20];
1785
1786         u8         ether_stats_pkts1024to1518octets_high[0x20];
1787
1788         u8         ether_stats_pkts1024to1518octets_low[0x20];
1789
1790         u8         ether_stats_pkts1519to2047octets_high[0x20];
1791
1792         u8         ether_stats_pkts1519to2047octets_low[0x20];
1793
1794         u8         ether_stats_pkts2048to4095octets_high[0x20];
1795
1796         u8         ether_stats_pkts2048to4095octets_low[0x20];
1797
1798         u8         ether_stats_pkts4096to8191octets_high[0x20];
1799
1800         u8         ether_stats_pkts4096to8191octets_low[0x20];
1801
1802         u8         ether_stats_pkts8192to10239octets_high[0x20];
1803
1804         u8         ether_stats_pkts8192to10239octets_low[0x20];
1805
1806         u8         reserved_at_540[0x280];
1807 };
1808
1809 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1810         u8         if_in_octets_high[0x20];
1811
1812         u8         if_in_octets_low[0x20];
1813
1814         u8         if_in_ucast_pkts_high[0x20];
1815
1816         u8         if_in_ucast_pkts_low[0x20];
1817
1818         u8         if_in_discards_high[0x20];
1819
1820         u8         if_in_discards_low[0x20];
1821
1822         u8         if_in_errors_high[0x20];
1823
1824         u8         if_in_errors_low[0x20];
1825
1826         u8         if_in_unknown_protos_high[0x20];
1827
1828         u8         if_in_unknown_protos_low[0x20];
1829
1830         u8         if_out_octets_high[0x20];
1831
1832         u8         if_out_octets_low[0x20];
1833
1834         u8         if_out_ucast_pkts_high[0x20];
1835
1836         u8         if_out_ucast_pkts_low[0x20];
1837
1838         u8         if_out_discards_high[0x20];
1839
1840         u8         if_out_discards_low[0x20];
1841
1842         u8         if_out_errors_high[0x20];
1843
1844         u8         if_out_errors_low[0x20];
1845
1846         u8         if_in_multicast_pkts_high[0x20];
1847
1848         u8         if_in_multicast_pkts_low[0x20];
1849
1850         u8         if_in_broadcast_pkts_high[0x20];
1851
1852         u8         if_in_broadcast_pkts_low[0x20];
1853
1854         u8         if_out_multicast_pkts_high[0x20];
1855
1856         u8         if_out_multicast_pkts_low[0x20];
1857
1858         u8         if_out_broadcast_pkts_high[0x20];
1859
1860         u8         if_out_broadcast_pkts_low[0x20];
1861
1862         u8         reserved_at_340[0x480];
1863 };
1864
1865 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1866         u8         a_frames_transmitted_ok_high[0x20];
1867
1868         u8         a_frames_transmitted_ok_low[0x20];
1869
1870         u8         a_frames_received_ok_high[0x20];
1871
1872         u8         a_frames_received_ok_low[0x20];
1873
1874         u8         a_frame_check_sequence_errors_high[0x20];
1875
1876         u8         a_frame_check_sequence_errors_low[0x20];
1877
1878         u8         a_alignment_errors_high[0x20];
1879
1880         u8         a_alignment_errors_low[0x20];
1881
1882         u8         a_octets_transmitted_ok_high[0x20];
1883
1884         u8         a_octets_transmitted_ok_low[0x20];
1885
1886         u8         a_octets_received_ok_high[0x20];
1887
1888         u8         a_octets_received_ok_low[0x20];
1889
1890         u8         a_multicast_frames_xmitted_ok_high[0x20];
1891
1892         u8         a_multicast_frames_xmitted_ok_low[0x20];
1893
1894         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1895
1896         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1897
1898         u8         a_multicast_frames_received_ok_high[0x20];
1899
1900         u8         a_multicast_frames_received_ok_low[0x20];
1901
1902         u8         a_broadcast_frames_received_ok_high[0x20];
1903
1904         u8         a_broadcast_frames_received_ok_low[0x20];
1905
1906         u8         a_in_range_length_errors_high[0x20];
1907
1908         u8         a_in_range_length_errors_low[0x20];
1909
1910         u8         a_out_of_range_length_field_high[0x20];
1911
1912         u8         a_out_of_range_length_field_low[0x20];
1913
1914         u8         a_frame_too_long_errors_high[0x20];
1915
1916         u8         a_frame_too_long_errors_low[0x20];
1917
1918         u8         a_symbol_error_during_carrier_high[0x20];
1919
1920         u8         a_symbol_error_during_carrier_low[0x20];
1921
1922         u8         a_mac_control_frames_transmitted_high[0x20];
1923
1924         u8         a_mac_control_frames_transmitted_low[0x20];
1925
1926         u8         a_mac_control_frames_received_high[0x20];
1927
1928         u8         a_mac_control_frames_received_low[0x20];
1929
1930         u8         a_unsupported_opcodes_received_high[0x20];
1931
1932         u8         a_unsupported_opcodes_received_low[0x20];
1933
1934         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1935
1936         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1937
1938         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1939
1940         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1941
1942         u8         reserved_at_4c0[0x300];
1943 };
1944
1945 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1946         u8         life_time_counter_high[0x20];
1947
1948         u8         life_time_counter_low[0x20];
1949
1950         u8         rx_errors[0x20];
1951
1952         u8         tx_errors[0x20];
1953
1954         u8         l0_to_recovery_eieos[0x20];
1955
1956         u8         l0_to_recovery_ts[0x20];
1957
1958         u8         l0_to_recovery_framing[0x20];
1959
1960         u8         l0_to_recovery_retrain[0x20];
1961
1962         u8         crc_error_dllp[0x20];
1963
1964         u8         crc_error_tlp[0x20];
1965
1966         u8         tx_overflow_buffer_pkt_high[0x20];
1967
1968         u8         tx_overflow_buffer_pkt_low[0x20];
1969
1970         u8         outbound_stalled_reads[0x20];
1971
1972         u8         outbound_stalled_writes[0x20];
1973
1974         u8         outbound_stalled_reads_events[0x20];
1975
1976         u8         outbound_stalled_writes_events[0x20];
1977
1978         u8         reserved_at_200[0x5c0];
1979 };
1980
1981 struct mlx5_ifc_cmd_inter_comp_event_bits {
1982         u8         command_completion_vector[0x20];
1983
1984         u8         reserved_at_20[0xc0];
1985 };
1986
1987 struct mlx5_ifc_stall_vl_event_bits {
1988         u8         reserved_at_0[0x18];
1989         u8         port_num[0x1];
1990         u8         reserved_at_19[0x3];
1991         u8         vl[0x4];
1992
1993         u8         reserved_at_20[0xa0];
1994 };
1995
1996 struct mlx5_ifc_db_bf_congestion_event_bits {
1997         u8         event_subtype[0x8];
1998         u8         reserved_at_8[0x8];
1999         u8         congestion_level[0x8];
2000         u8         reserved_at_18[0x8];
2001
2002         u8         reserved_at_20[0xa0];
2003 };
2004
2005 struct mlx5_ifc_gpio_event_bits {
2006         u8         reserved_at_0[0x60];
2007
2008         u8         gpio_event_hi[0x20];
2009
2010         u8         gpio_event_lo[0x20];
2011
2012         u8         reserved_at_a0[0x40];
2013 };
2014
2015 struct mlx5_ifc_port_state_change_event_bits {
2016         u8         reserved_at_0[0x40];
2017
2018         u8         port_num[0x4];
2019         u8         reserved_at_44[0x1c];
2020
2021         u8         reserved_at_60[0x80];
2022 };
2023
2024 struct mlx5_ifc_dropped_packet_logged_bits {
2025         u8         reserved_at_0[0xe0];
2026 };
2027
2028 enum {
2029         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2030         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2031 };
2032
2033 struct mlx5_ifc_cq_error_bits {
2034         u8         reserved_at_0[0x8];
2035         u8         cqn[0x18];
2036
2037         u8         reserved_at_20[0x20];
2038
2039         u8         reserved_at_40[0x18];
2040         u8         syndrome[0x8];
2041
2042         u8         reserved_at_60[0x80];
2043 };
2044
2045 struct mlx5_ifc_rdma_page_fault_event_bits {
2046         u8         bytes_committed[0x20];
2047
2048         u8         r_key[0x20];
2049
2050         u8         reserved_at_40[0x10];
2051         u8         packet_len[0x10];
2052
2053         u8         rdma_op_len[0x20];
2054
2055         u8         rdma_va[0x40];
2056
2057         u8         reserved_at_c0[0x5];
2058         u8         rdma[0x1];
2059         u8         write[0x1];
2060         u8         requestor[0x1];
2061         u8         qp_number[0x18];
2062 };
2063
2064 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2065         u8         bytes_committed[0x20];
2066
2067         u8         reserved_at_20[0x10];
2068         u8         wqe_index[0x10];
2069
2070         u8         reserved_at_40[0x10];
2071         u8         len[0x10];
2072
2073         u8         reserved_at_60[0x60];
2074
2075         u8         reserved_at_c0[0x5];
2076         u8         rdma[0x1];
2077         u8         write_read[0x1];
2078         u8         requestor[0x1];
2079         u8         qpn[0x18];
2080 };
2081
2082 struct mlx5_ifc_qp_events_bits {
2083         u8         reserved_at_0[0xa0];
2084
2085         u8         type[0x8];
2086         u8         reserved_at_a8[0x18];
2087
2088         u8         reserved_at_c0[0x8];
2089         u8         qpn_rqn_sqn[0x18];
2090 };
2091
2092 struct mlx5_ifc_dct_events_bits {
2093         u8         reserved_at_0[0xc0];
2094
2095         u8         reserved_at_c0[0x8];
2096         u8         dct_number[0x18];
2097 };
2098
2099 struct mlx5_ifc_comp_event_bits {
2100         u8         reserved_at_0[0xc0];
2101
2102         u8         reserved_at_c0[0x8];
2103         u8         cq_number[0x18];
2104 };
2105
2106 enum {
2107         MLX5_QPC_STATE_RST        = 0x0,
2108         MLX5_QPC_STATE_INIT       = 0x1,
2109         MLX5_QPC_STATE_RTR        = 0x2,
2110         MLX5_QPC_STATE_RTS        = 0x3,
2111         MLX5_QPC_STATE_SQER       = 0x4,
2112         MLX5_QPC_STATE_ERR        = 0x6,
2113         MLX5_QPC_STATE_SQD        = 0x7,
2114         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2115 };
2116
2117 enum {
2118         MLX5_QPC_ST_RC            = 0x0,
2119         MLX5_QPC_ST_UC            = 0x1,
2120         MLX5_QPC_ST_UD            = 0x2,
2121         MLX5_QPC_ST_XRC           = 0x3,
2122         MLX5_QPC_ST_DCI           = 0x5,
2123         MLX5_QPC_ST_QP0           = 0x7,
2124         MLX5_QPC_ST_QP1           = 0x8,
2125         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2126         MLX5_QPC_ST_REG_UMR       = 0xc,
2127 };
2128
2129 enum {
2130         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2131         MLX5_QPC_PM_STATE_REARM     = 0x1,
2132         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2133         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2134 };
2135
2136 enum {
2137         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2138 };
2139
2140 enum {
2141         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2142         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2143 };
2144
2145 enum {
2146         MLX5_QPC_MTU_256_BYTES        = 0x1,
2147         MLX5_QPC_MTU_512_BYTES        = 0x2,
2148         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2149         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2150         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2151         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2152 };
2153
2154 enum {
2155         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2156         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2157         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2158         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2159         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2160         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2161         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2162         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2163 };
2164
2165 enum {
2166         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2167         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2168         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2169 };
2170
2171 enum {
2172         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2173         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2174         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2175 };
2176
2177 struct mlx5_ifc_qpc_bits {
2178         u8         state[0x4];
2179         u8         lag_tx_port_affinity[0x4];
2180         u8         st[0x8];
2181         u8         reserved_at_10[0x3];
2182         u8         pm_state[0x2];
2183         u8         reserved_at_15[0x3];
2184         u8         offload_type[0x4];
2185         u8         end_padding_mode[0x2];
2186         u8         reserved_at_1e[0x2];
2187
2188         u8         wq_signature[0x1];
2189         u8         block_lb_mc[0x1];
2190         u8         atomic_like_write_en[0x1];
2191         u8         latency_sensitive[0x1];
2192         u8         reserved_at_24[0x1];
2193         u8         drain_sigerr[0x1];
2194         u8         reserved_at_26[0x2];
2195         u8         pd[0x18];
2196
2197         u8         mtu[0x3];
2198         u8         log_msg_max[0x5];
2199         u8         reserved_at_48[0x1];
2200         u8         log_rq_size[0x4];
2201         u8         log_rq_stride[0x3];
2202         u8         no_sq[0x1];
2203         u8         log_sq_size[0x4];
2204         u8         reserved_at_55[0x6];
2205         u8         rlky[0x1];
2206         u8         ulp_stateless_offload_mode[0x4];
2207
2208         u8         counter_set_id[0x8];
2209         u8         uar_page[0x18];
2210
2211         u8         reserved_at_80[0x8];
2212         u8         user_index[0x18];
2213
2214         u8         reserved_at_a0[0x3];
2215         u8         log_page_size[0x5];
2216         u8         remote_qpn[0x18];
2217
2218         struct mlx5_ifc_ads_bits primary_address_path;
2219
2220         struct mlx5_ifc_ads_bits secondary_address_path;
2221
2222         u8         log_ack_req_freq[0x4];
2223         u8         reserved_at_384[0x4];
2224         u8         log_sra_max[0x3];
2225         u8         reserved_at_38b[0x2];
2226         u8         retry_count[0x3];
2227         u8         rnr_retry[0x3];
2228         u8         reserved_at_393[0x1];
2229         u8         fre[0x1];
2230         u8         cur_rnr_retry[0x3];
2231         u8         cur_retry_count[0x3];
2232         u8         reserved_at_39b[0x5];
2233
2234         u8         reserved_at_3a0[0x20];
2235
2236         u8         reserved_at_3c0[0x8];
2237         u8         next_send_psn[0x18];
2238
2239         u8         reserved_at_3e0[0x8];
2240         u8         cqn_snd[0x18];
2241
2242         u8         reserved_at_400[0x8];
2243         u8         deth_sqpn[0x18];
2244
2245         u8         reserved_at_420[0x20];
2246
2247         u8         reserved_at_440[0x8];
2248         u8         last_acked_psn[0x18];
2249
2250         u8         reserved_at_460[0x8];
2251         u8         ssn[0x18];
2252
2253         u8         reserved_at_480[0x8];
2254         u8         log_rra_max[0x3];
2255         u8         reserved_at_48b[0x1];
2256         u8         atomic_mode[0x4];
2257         u8         rre[0x1];
2258         u8         rwe[0x1];
2259         u8         rae[0x1];
2260         u8         reserved_at_493[0x1];
2261         u8         page_offset[0x6];
2262         u8         reserved_at_49a[0x3];
2263         u8         cd_slave_receive[0x1];
2264         u8         cd_slave_send[0x1];
2265         u8         cd_master[0x1];
2266
2267         u8         reserved_at_4a0[0x3];
2268         u8         min_rnr_nak[0x5];
2269         u8         next_rcv_psn[0x18];
2270
2271         u8         reserved_at_4c0[0x8];
2272         u8         xrcd[0x18];
2273
2274         u8         reserved_at_4e0[0x8];
2275         u8         cqn_rcv[0x18];
2276
2277         u8         dbr_addr[0x40];
2278
2279         u8         q_key[0x20];
2280
2281         u8         reserved_at_560[0x5];
2282         u8         rq_type[0x3];
2283         u8         srqn_rmpn_xrqn[0x18];
2284
2285         u8         reserved_at_580[0x8];
2286         u8         rmsn[0x18];
2287
2288         u8         hw_sq_wqebb_counter[0x10];
2289         u8         sw_sq_wqebb_counter[0x10];
2290
2291         u8         hw_rq_counter[0x20];
2292
2293         u8         sw_rq_counter[0x20];
2294
2295         u8         reserved_at_600[0x20];
2296
2297         u8         reserved_at_620[0xf];
2298         u8         cgs[0x1];
2299         u8         cs_req[0x8];
2300         u8         cs_res[0x8];
2301
2302         u8         dc_access_key[0x40];
2303
2304         u8         reserved_at_680[0xc0];
2305 };
2306
2307 struct mlx5_ifc_roce_addr_layout_bits {
2308         u8         source_l3_address[16][0x8];
2309
2310         u8         reserved_at_80[0x3];
2311         u8         vlan_valid[0x1];
2312         u8         vlan_id[0xc];
2313         u8         source_mac_47_32[0x10];
2314
2315         u8         source_mac_31_0[0x20];
2316
2317         u8         reserved_at_c0[0x14];
2318         u8         roce_l3_type[0x4];
2319         u8         roce_version[0x8];
2320
2321         u8         reserved_at_e0[0x20];
2322 };
2323
2324 union mlx5_ifc_hca_cap_union_bits {
2325         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2326         struct mlx5_ifc_odp_cap_bits odp_cap;
2327         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2328         struct mlx5_ifc_roce_cap_bits roce_cap;
2329         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2330         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2331         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2332         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2333         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2334         struct mlx5_ifc_qos_cap_bits qos_cap;
2335         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2336         u8         reserved_at_0[0x8000];
2337 };
2338
2339 enum {
2340         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2341         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2342         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2343         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2344         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2345         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2346         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2347         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2348         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2349 };
2350
2351 struct mlx5_ifc_vlan_bits {
2352         u8         ethtype[0x10];
2353         u8         prio[0x3];
2354         u8         cfi[0x1];
2355         u8         vid[0xc];
2356 };
2357
2358 struct mlx5_ifc_flow_context_bits {
2359         struct mlx5_ifc_vlan_bits push_vlan;
2360
2361         u8         group_id[0x20];
2362
2363         u8         reserved_at_40[0x8];
2364         u8         flow_tag[0x18];
2365
2366         u8         reserved_at_60[0x10];
2367         u8         action[0x10];
2368
2369         u8         reserved_at_80[0x8];
2370         u8         destination_list_size[0x18];
2371
2372         u8         reserved_at_a0[0x8];
2373         u8         flow_counter_list_size[0x18];
2374
2375         u8         encap_id[0x20];
2376
2377         u8         modify_header_id[0x20];
2378
2379         u8         reserved_at_100[0x100];
2380
2381         struct mlx5_ifc_fte_match_param_bits match_value;
2382
2383         u8         reserved_at_1200[0x600];
2384
2385         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2386 };
2387
2388 enum {
2389         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2390         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2391 };
2392
2393 struct mlx5_ifc_xrc_srqc_bits {
2394         u8         state[0x4];
2395         u8         log_xrc_srq_size[0x4];
2396         u8         reserved_at_8[0x18];
2397
2398         u8         wq_signature[0x1];
2399         u8         cont_srq[0x1];
2400         u8         reserved_at_22[0x1];
2401         u8         rlky[0x1];
2402         u8         basic_cyclic_rcv_wqe[0x1];
2403         u8         log_rq_stride[0x3];
2404         u8         xrcd[0x18];
2405
2406         u8         page_offset[0x6];
2407         u8         reserved_at_46[0x2];
2408         u8         cqn[0x18];
2409
2410         u8         reserved_at_60[0x20];
2411
2412         u8         user_index_equal_xrc_srqn[0x1];
2413         u8         reserved_at_81[0x1];
2414         u8         log_page_size[0x6];
2415         u8         user_index[0x18];
2416
2417         u8         reserved_at_a0[0x20];
2418
2419         u8         reserved_at_c0[0x8];
2420         u8         pd[0x18];
2421
2422         u8         lwm[0x10];
2423         u8         wqe_cnt[0x10];
2424
2425         u8         reserved_at_100[0x40];
2426
2427         u8         db_record_addr_h[0x20];
2428
2429         u8         db_record_addr_l[0x1e];
2430         u8         reserved_at_17e[0x2];
2431
2432         u8         reserved_at_180[0x80];
2433 };
2434
2435 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2436         u8         counter_error_queues[0x20];
2437
2438         u8         total_error_queues[0x20];
2439
2440         u8         send_queue_priority_update_flow[0x20];
2441
2442         u8         reserved_at_60[0x20];
2443
2444         u8         nic_receive_steering_discard[0x40];
2445
2446         u8         receive_discard_vport_down[0x40];
2447
2448         u8         transmit_discard_vport_down[0x40];
2449
2450         u8         reserved_at_140[0xec0];
2451 };
2452
2453 struct mlx5_ifc_traffic_counter_bits {
2454         u8         packets[0x40];
2455
2456         u8         octets[0x40];
2457 };
2458
2459 struct mlx5_ifc_tisc_bits {
2460         u8         strict_lag_tx_port_affinity[0x1];
2461         u8         reserved_at_1[0x3];
2462         u8         lag_tx_port_affinity[0x04];
2463
2464         u8         reserved_at_8[0x4];
2465         u8         prio[0x4];
2466         u8         reserved_at_10[0x10];
2467
2468         u8         reserved_at_20[0x100];
2469
2470         u8         reserved_at_120[0x8];
2471         u8         transport_domain[0x18];
2472
2473         u8         reserved_at_140[0x8];
2474         u8         underlay_qpn[0x18];
2475         u8         reserved_at_160[0x3a0];
2476 };
2477
2478 enum {
2479         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2480         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2481 };
2482
2483 enum {
2484         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2485         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2486 };
2487
2488 enum {
2489         MLX5_RX_HASH_FN_NONE           = 0x0,
2490         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2491         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2492 };
2493
2494 enum {
2495         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2496         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2497 };
2498
2499 struct mlx5_ifc_tirc_bits {
2500         u8         reserved_at_0[0x20];
2501
2502         u8         disp_type[0x4];
2503         u8         reserved_at_24[0x1c];
2504
2505         u8         reserved_at_40[0x40];
2506
2507         u8         reserved_at_80[0x4];
2508         u8         lro_timeout_period_usecs[0x10];
2509         u8         lro_enable_mask[0x4];
2510         u8         lro_max_ip_payload_size[0x8];
2511
2512         u8         reserved_at_a0[0x40];
2513
2514         u8         reserved_at_e0[0x8];
2515         u8         inline_rqn[0x18];
2516
2517         u8         rx_hash_symmetric[0x1];
2518         u8         reserved_at_101[0x1];
2519         u8         tunneled_offload_en[0x1];
2520         u8         reserved_at_103[0x5];
2521         u8         indirect_table[0x18];
2522
2523         u8         rx_hash_fn[0x4];
2524         u8         reserved_at_124[0x2];
2525         u8         self_lb_block[0x2];
2526         u8         transport_domain[0x18];
2527
2528         u8         rx_hash_toeplitz_key[10][0x20];
2529
2530         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2531
2532         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2533
2534         u8         reserved_at_2c0[0x4c0];
2535 };
2536
2537 enum {
2538         MLX5_SRQC_STATE_GOOD   = 0x0,
2539         MLX5_SRQC_STATE_ERROR  = 0x1,
2540 };
2541
2542 struct mlx5_ifc_srqc_bits {
2543         u8         state[0x4];
2544         u8         log_srq_size[0x4];
2545         u8         reserved_at_8[0x18];
2546
2547         u8         wq_signature[0x1];
2548         u8         cont_srq[0x1];
2549         u8         reserved_at_22[0x1];
2550         u8         rlky[0x1];
2551         u8         reserved_at_24[0x1];
2552         u8         log_rq_stride[0x3];
2553         u8         xrcd[0x18];
2554
2555         u8         page_offset[0x6];
2556         u8         reserved_at_46[0x2];
2557         u8         cqn[0x18];
2558
2559         u8         reserved_at_60[0x20];
2560
2561         u8         reserved_at_80[0x2];
2562         u8         log_page_size[0x6];
2563         u8         reserved_at_88[0x18];
2564
2565         u8         reserved_at_a0[0x20];
2566
2567         u8         reserved_at_c0[0x8];
2568         u8         pd[0x18];
2569
2570         u8         lwm[0x10];
2571         u8         wqe_cnt[0x10];
2572
2573         u8         reserved_at_100[0x40];
2574
2575         u8         dbr_addr[0x40];
2576
2577         u8         reserved_at_180[0x80];
2578 };
2579
2580 enum {
2581         MLX5_SQC_STATE_RST  = 0x0,
2582         MLX5_SQC_STATE_RDY  = 0x1,
2583         MLX5_SQC_STATE_ERR  = 0x3,
2584 };
2585
2586 struct mlx5_ifc_sqc_bits {
2587         u8         rlky[0x1];
2588         u8         cd_master[0x1];
2589         u8         fre[0x1];
2590         u8         flush_in_error_en[0x1];
2591         u8         allow_multi_pkt_send_wqe[0x1];
2592         u8         min_wqe_inline_mode[0x3];
2593         u8         state[0x4];
2594         u8         reg_umr[0x1];
2595         u8         allow_swp[0x1];
2596         u8         hairpin[0x1];
2597         u8         reserved_at_f[0x11];
2598
2599         u8         reserved_at_20[0x8];
2600         u8         user_index[0x18];
2601
2602         u8         reserved_at_40[0x8];
2603         u8         cqn[0x18];
2604
2605         u8         reserved_at_60[0x8];
2606         u8         hairpin_peer_rq[0x18];
2607
2608         u8         reserved_at_80[0x10];
2609         u8         hairpin_peer_vhca[0x10];
2610
2611         u8         reserved_at_a0[0x50];
2612
2613         u8         packet_pacing_rate_limit_index[0x10];
2614         u8         tis_lst_sz[0x10];
2615         u8         reserved_at_110[0x10];
2616
2617         u8         reserved_at_120[0x40];
2618
2619         u8         reserved_at_160[0x8];
2620         u8         tis_num_0[0x18];
2621
2622         struct mlx5_ifc_wq_bits wq;
2623 };
2624
2625 enum {
2626         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2627         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2628         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2629         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2630 };
2631
2632 struct mlx5_ifc_scheduling_context_bits {
2633         u8         element_type[0x8];
2634         u8         reserved_at_8[0x18];
2635
2636         u8         element_attributes[0x20];
2637
2638         u8         parent_element_id[0x20];
2639
2640         u8         reserved_at_60[0x40];
2641
2642         u8         bw_share[0x20];
2643
2644         u8         max_average_bw[0x20];
2645
2646         u8         reserved_at_e0[0x120];
2647 };
2648
2649 struct mlx5_ifc_rqtc_bits {
2650         u8         reserved_at_0[0xa0];
2651
2652         u8         reserved_at_a0[0x10];
2653         u8         rqt_max_size[0x10];
2654
2655         u8         reserved_at_c0[0x10];
2656         u8         rqt_actual_size[0x10];
2657
2658         u8         reserved_at_e0[0x6a0];
2659
2660         struct mlx5_ifc_rq_num_bits rq_num[0];
2661 };
2662
2663 enum {
2664         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2665         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2666 };
2667
2668 enum {
2669         MLX5_RQC_STATE_RST  = 0x0,
2670         MLX5_RQC_STATE_RDY  = 0x1,
2671         MLX5_RQC_STATE_ERR  = 0x3,
2672 };
2673
2674 struct mlx5_ifc_rqc_bits {
2675         u8         rlky[0x1];
2676         u8         delay_drop_en[0x1];
2677         u8         scatter_fcs[0x1];
2678         u8         vsd[0x1];
2679         u8         mem_rq_type[0x4];
2680         u8         state[0x4];
2681         u8         reserved_at_c[0x1];
2682         u8         flush_in_error_en[0x1];
2683         u8         hairpin[0x1];
2684         u8         reserved_at_f[0x11];
2685
2686         u8         reserved_at_20[0x8];
2687         u8         user_index[0x18];
2688
2689         u8         reserved_at_40[0x8];
2690         u8         cqn[0x18];
2691
2692         u8         counter_set_id[0x8];
2693         u8         reserved_at_68[0x18];
2694
2695         u8         reserved_at_80[0x8];
2696         u8         rmpn[0x18];
2697
2698         u8         reserved_at_a0[0x8];
2699         u8         hairpin_peer_sq[0x18];
2700
2701         u8         reserved_at_c0[0x10];
2702         u8         hairpin_peer_vhca[0x10];
2703
2704         u8         reserved_at_e0[0xa0];
2705
2706         struct mlx5_ifc_wq_bits wq;
2707 };
2708
2709 enum {
2710         MLX5_RMPC_STATE_RDY  = 0x1,
2711         MLX5_RMPC_STATE_ERR  = 0x3,
2712 };
2713
2714 struct mlx5_ifc_rmpc_bits {
2715         u8         reserved_at_0[0x8];
2716         u8         state[0x4];
2717         u8         reserved_at_c[0x14];
2718
2719         u8         basic_cyclic_rcv_wqe[0x1];
2720         u8         reserved_at_21[0x1f];
2721
2722         u8         reserved_at_40[0x140];
2723
2724         struct mlx5_ifc_wq_bits wq;
2725 };
2726
2727 struct mlx5_ifc_nic_vport_context_bits {
2728         u8         reserved_at_0[0x5];
2729         u8         min_wqe_inline_mode[0x3];
2730         u8         reserved_at_8[0x15];
2731         u8         disable_mc_local_lb[0x1];
2732         u8         disable_uc_local_lb[0x1];
2733         u8         roce_en[0x1];
2734
2735         u8         arm_change_event[0x1];
2736         u8         reserved_at_21[0x1a];
2737         u8         event_on_mtu[0x1];
2738         u8         event_on_promisc_change[0x1];
2739         u8         event_on_vlan_change[0x1];
2740         u8         event_on_mc_address_change[0x1];
2741         u8         event_on_uc_address_change[0x1];
2742
2743         u8         reserved_at_40[0xc];
2744
2745         u8         affiliation_criteria[0x4];
2746         u8         affiliated_vhca_id[0x10];
2747
2748         u8         reserved_at_60[0xd0];
2749
2750         u8         mtu[0x10];
2751
2752         u8         system_image_guid[0x40];
2753         u8         port_guid[0x40];
2754         u8         node_guid[0x40];
2755
2756         u8         reserved_at_200[0x140];
2757         u8         qkey_violation_counter[0x10];
2758         u8         reserved_at_350[0x430];
2759
2760         u8         promisc_uc[0x1];
2761         u8         promisc_mc[0x1];
2762         u8         promisc_all[0x1];
2763         u8         reserved_at_783[0x2];
2764         u8         allowed_list_type[0x3];
2765         u8         reserved_at_788[0xc];
2766         u8         allowed_list_size[0xc];
2767
2768         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2769
2770         u8         reserved_at_7e0[0x20];
2771
2772         u8         current_uc_mac_address[0][0x40];
2773 };
2774
2775 enum {
2776         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2777         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2778         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2779         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2780         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2781 };
2782
2783 struct mlx5_ifc_mkc_bits {
2784         u8         reserved_at_0[0x1];
2785         u8         free[0x1];
2786         u8         reserved_at_2[0x1];
2787         u8         access_mode_4_2[0x3];
2788         u8         reserved_at_6[0x7];
2789         u8         relaxed_ordering_write[0x1];
2790         u8         reserved_at_e[0x1];
2791         u8         small_fence_on_rdma_read_response[0x1];
2792         u8         umr_en[0x1];
2793         u8         a[0x1];
2794         u8         rw[0x1];
2795         u8         rr[0x1];
2796         u8         lw[0x1];
2797         u8         lr[0x1];
2798         u8         access_mode_1_0[0x2];
2799         u8         reserved_at_18[0x8];
2800
2801         u8         qpn[0x18];
2802         u8         mkey_7_0[0x8];
2803
2804         u8         reserved_at_40[0x20];
2805
2806         u8         length64[0x1];
2807         u8         bsf_en[0x1];
2808         u8         sync_umr[0x1];
2809         u8         reserved_at_63[0x2];
2810         u8         expected_sigerr_count[0x1];
2811         u8         reserved_at_66[0x1];
2812         u8         en_rinval[0x1];
2813         u8         pd[0x18];
2814
2815         u8         start_addr[0x40];
2816
2817         u8         len[0x40];
2818
2819         u8         bsf_octword_size[0x20];
2820
2821         u8         reserved_at_120[0x80];
2822
2823         u8         translations_octword_size[0x20];
2824
2825         u8         reserved_at_1c0[0x1b];
2826         u8         log_page_size[0x5];
2827
2828         u8         reserved_at_1e0[0x20];
2829 };
2830
2831 struct mlx5_ifc_pkey_bits {
2832         u8         reserved_at_0[0x10];
2833         u8         pkey[0x10];
2834 };
2835
2836 struct mlx5_ifc_array128_auto_bits {
2837         u8         array128_auto[16][0x8];
2838 };
2839
2840 struct mlx5_ifc_hca_vport_context_bits {
2841         u8         field_select[0x20];
2842
2843         u8         reserved_at_20[0xe0];
2844
2845         u8         sm_virt_aware[0x1];
2846         u8         has_smi[0x1];
2847         u8         has_raw[0x1];
2848         u8         grh_required[0x1];
2849         u8         reserved_at_104[0xc];
2850         u8         port_physical_state[0x4];
2851         u8         vport_state_policy[0x4];
2852         u8         port_state[0x4];
2853         u8         vport_state[0x4];
2854
2855         u8         reserved_at_120[0x20];
2856
2857         u8         system_image_guid[0x40];
2858
2859         u8         port_guid[0x40];
2860
2861         u8         node_guid[0x40];
2862
2863         u8         cap_mask1[0x20];
2864
2865         u8         cap_mask1_field_select[0x20];
2866
2867         u8         cap_mask2[0x20];
2868
2869         u8         cap_mask2_field_select[0x20];
2870
2871         u8         reserved_at_280[0x80];
2872
2873         u8         lid[0x10];
2874         u8         reserved_at_310[0x4];
2875         u8         init_type_reply[0x4];
2876         u8         lmc[0x3];
2877         u8         subnet_timeout[0x5];
2878
2879         u8         sm_lid[0x10];
2880         u8         sm_sl[0x4];
2881         u8         reserved_at_334[0xc];
2882
2883         u8         qkey_violation_counter[0x10];
2884         u8         pkey_violation_counter[0x10];
2885
2886         u8         reserved_at_360[0xca0];
2887 };
2888
2889 struct mlx5_ifc_esw_vport_context_bits {
2890         u8         reserved_at_0[0x3];
2891         u8         vport_svlan_strip[0x1];
2892         u8         vport_cvlan_strip[0x1];
2893         u8         vport_svlan_insert[0x1];
2894         u8         vport_cvlan_insert[0x2];
2895         u8         reserved_at_8[0x18];
2896
2897         u8         reserved_at_20[0x20];
2898
2899         u8         svlan_cfi[0x1];
2900         u8         svlan_pcp[0x3];
2901         u8         svlan_id[0xc];
2902         u8         cvlan_cfi[0x1];
2903         u8         cvlan_pcp[0x3];
2904         u8         cvlan_id[0xc];
2905
2906         u8         reserved_at_60[0x7a0];
2907 };
2908
2909 enum {
2910         MLX5_EQC_STATUS_OK                = 0x0,
2911         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2912 };
2913
2914 enum {
2915         MLX5_EQC_ST_ARMED  = 0x9,
2916         MLX5_EQC_ST_FIRED  = 0xa,
2917 };
2918
2919 struct mlx5_ifc_eqc_bits {
2920         u8         status[0x4];
2921         u8         reserved_at_4[0x9];
2922         u8         ec[0x1];
2923         u8         oi[0x1];
2924         u8         reserved_at_f[0x5];
2925         u8         st[0x4];
2926         u8         reserved_at_18[0x8];
2927
2928         u8         reserved_at_20[0x20];
2929
2930         u8         reserved_at_40[0x14];
2931         u8         page_offset[0x6];
2932         u8         reserved_at_5a[0x6];
2933
2934         u8         reserved_at_60[0x3];
2935         u8         log_eq_size[0x5];
2936         u8         uar_page[0x18];
2937
2938         u8         reserved_at_80[0x20];
2939
2940         u8         reserved_at_a0[0x18];
2941         u8         intr[0x8];
2942
2943         u8         reserved_at_c0[0x3];
2944         u8         log_page_size[0x5];
2945         u8         reserved_at_c8[0x18];
2946
2947         u8         reserved_at_e0[0x60];
2948
2949         u8         reserved_at_140[0x8];
2950         u8         consumer_counter[0x18];
2951
2952         u8         reserved_at_160[0x8];
2953         u8         producer_counter[0x18];
2954
2955         u8         reserved_at_180[0x80];
2956 };
2957
2958 enum {
2959         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2960         MLX5_DCTC_STATE_DRAINING  = 0x1,
2961         MLX5_DCTC_STATE_DRAINED   = 0x2,
2962 };
2963
2964 enum {
2965         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2966         MLX5_DCTC_CS_RES_NA         = 0x1,
2967         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2968 };
2969
2970 enum {
2971         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2972         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2973         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2974         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2975         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2976 };
2977
2978 struct mlx5_ifc_dctc_bits {
2979         u8         reserved_at_0[0x4];
2980         u8         state[0x4];
2981         u8         reserved_at_8[0x18];
2982
2983         u8         reserved_at_20[0x8];
2984         u8         user_index[0x18];
2985
2986         u8         reserved_at_40[0x8];
2987         u8         cqn[0x18];
2988
2989         u8         counter_set_id[0x8];
2990         u8         atomic_mode[0x4];
2991         u8         rre[0x1];
2992         u8         rwe[0x1];
2993         u8         rae[0x1];
2994         u8         atomic_like_write_en[0x1];
2995         u8         latency_sensitive[0x1];
2996         u8         rlky[0x1];
2997         u8         free_ar[0x1];
2998         u8         reserved_at_73[0xd];
2999
3000         u8         reserved_at_80[0x8];
3001         u8         cs_res[0x8];
3002         u8         reserved_at_90[0x3];
3003         u8         min_rnr_nak[0x5];
3004         u8         reserved_at_98[0x8];
3005
3006         u8         reserved_at_a0[0x8];
3007         u8         srqn_xrqn[0x18];
3008
3009         u8         reserved_at_c0[0x8];
3010         u8         pd[0x18];
3011
3012         u8         tclass[0x8];
3013         u8         reserved_at_e8[0x4];
3014         u8         flow_label[0x14];
3015
3016         u8         dc_access_key[0x40];
3017
3018         u8         reserved_at_140[0x5];
3019         u8         mtu[0x3];
3020         u8         port[0x8];
3021         u8         pkey_index[0x10];
3022
3023         u8         reserved_at_160[0x8];
3024         u8         my_addr_index[0x8];
3025         u8         reserved_at_170[0x8];
3026         u8         hop_limit[0x8];
3027
3028         u8         dc_access_key_violation_count[0x20];
3029
3030         u8         reserved_at_1a0[0x14];
3031         u8         dei_cfi[0x1];
3032         u8         eth_prio[0x3];
3033         u8         ecn[0x2];
3034         u8         dscp[0x6];
3035
3036         u8         reserved_at_1c0[0x40];
3037 };
3038
3039 enum {
3040         MLX5_CQC_STATUS_OK             = 0x0,
3041         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3042         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3043 };
3044
3045 enum {
3046         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3047         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3048 };
3049
3050 enum {
3051         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3052         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3053         MLX5_CQC_ST_FIRED                                 = 0xa,
3054 };
3055
3056 enum {
3057         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3058         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3059         MLX5_CQ_PERIOD_NUM_MODES
3060 };
3061
3062 struct mlx5_ifc_cqc_bits {
3063         u8         status[0x4];
3064         u8         reserved_at_4[0x4];
3065         u8         cqe_sz[0x3];
3066         u8         cc[0x1];
3067         u8         reserved_at_c[0x1];
3068         u8         scqe_break_moderation_en[0x1];
3069         u8         oi[0x1];
3070         u8         cq_period_mode[0x2];
3071         u8         cqe_comp_en[0x1];
3072         u8         mini_cqe_res_format[0x2];
3073         u8         st[0x4];
3074         u8         reserved_at_18[0x8];
3075
3076         u8         reserved_at_20[0x20];
3077
3078         u8         reserved_at_40[0x14];
3079         u8         page_offset[0x6];
3080         u8         reserved_at_5a[0x6];
3081
3082         u8         reserved_at_60[0x3];
3083         u8         log_cq_size[0x5];
3084         u8         uar_page[0x18];
3085
3086         u8         reserved_at_80[0x4];
3087         u8         cq_period[0xc];
3088         u8         cq_max_count[0x10];
3089
3090         u8         reserved_at_a0[0x18];
3091         u8         c_eqn[0x8];
3092
3093         u8         reserved_at_c0[0x3];
3094         u8         log_page_size[0x5];
3095         u8         reserved_at_c8[0x18];
3096
3097         u8         reserved_at_e0[0x20];
3098
3099         u8         reserved_at_100[0x8];
3100         u8         last_notified_index[0x18];
3101
3102         u8         reserved_at_120[0x8];
3103         u8         last_solicit_index[0x18];
3104
3105         u8         reserved_at_140[0x8];
3106         u8         consumer_counter[0x18];
3107
3108         u8         reserved_at_160[0x8];
3109         u8         producer_counter[0x18];
3110
3111         u8         reserved_at_180[0x40];
3112
3113         u8         dbr_addr[0x40];
3114 };
3115
3116 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3117         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3118         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3119         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3120         u8         reserved_at_0[0x800];
3121 };
3122
3123 struct mlx5_ifc_query_adapter_param_block_bits {
3124         u8         reserved_at_0[0xc0];
3125
3126         u8         reserved_at_c0[0x8];
3127         u8         ieee_vendor_id[0x18];
3128
3129         u8         reserved_at_e0[0x10];
3130         u8         vsd_vendor_id[0x10];
3131
3132         u8         vsd[208][0x8];
3133
3134         u8         vsd_contd_psid[16][0x8];
3135 };
3136
3137 enum {
3138         MLX5_XRQC_STATE_GOOD   = 0x0,
3139         MLX5_XRQC_STATE_ERROR  = 0x1,
3140 };
3141
3142 enum {
3143         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3144         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3145 };
3146
3147 enum {
3148         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3149 };
3150
3151 struct mlx5_ifc_tag_matching_topology_context_bits {
3152         u8         log_matching_list_sz[0x4];
3153         u8         reserved_at_4[0xc];
3154         u8         append_next_index[0x10];
3155
3156         u8         sw_phase_cnt[0x10];
3157         u8         hw_phase_cnt[0x10];
3158
3159         u8         reserved_at_40[0x40];
3160 };
3161
3162 struct mlx5_ifc_xrqc_bits {
3163         u8         state[0x4];
3164         u8         rlkey[0x1];
3165         u8         reserved_at_5[0xf];
3166         u8         topology[0x4];
3167         u8         reserved_at_18[0x4];
3168         u8         offload[0x4];
3169
3170         u8         reserved_at_20[0x8];
3171         u8         user_index[0x18];
3172
3173         u8         reserved_at_40[0x8];
3174         u8         cqn[0x18];
3175
3176         u8         reserved_at_60[0xa0];
3177
3178         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3179
3180         u8         reserved_at_180[0x280];
3181
3182         struct mlx5_ifc_wq_bits wq;
3183 };
3184
3185 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3186         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3187         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3188         u8         reserved_at_0[0x20];
3189 };
3190
3191 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3192         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3193         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3194         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3195         u8         reserved_at_0[0x20];
3196 };
3197
3198 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3199         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3200         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3201         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3202         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3203         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3204         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3205         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3206         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3207         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3208         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3209         u8         reserved_at_0[0x7c0];
3210 };
3211
3212 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3213         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3214         u8         reserved_at_0[0x7c0];
3215 };
3216
3217 union mlx5_ifc_event_auto_bits {
3218         struct mlx5_ifc_comp_event_bits comp_event;
3219         struct mlx5_ifc_dct_events_bits dct_events;
3220         struct mlx5_ifc_qp_events_bits qp_events;
3221         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3222         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3223         struct mlx5_ifc_cq_error_bits cq_error;
3224         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3225         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3226         struct mlx5_ifc_gpio_event_bits gpio_event;
3227         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3228         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3229         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3230         u8         reserved_at_0[0xe0];
3231 };
3232
3233 struct mlx5_ifc_health_buffer_bits {
3234         u8         reserved_at_0[0x100];
3235
3236         u8         assert_existptr[0x20];
3237
3238         u8         assert_callra[0x20];
3239
3240         u8         reserved_at_140[0x40];
3241
3242         u8         fw_version[0x20];
3243
3244         u8         hw_id[0x20];
3245
3246         u8         reserved_at_1c0[0x20];
3247
3248         u8         irisc_index[0x8];
3249         u8         synd[0x8];
3250         u8         ext_synd[0x10];
3251 };
3252
3253 struct mlx5_ifc_register_loopback_control_bits {
3254         u8         no_lb[0x1];
3255         u8         reserved_at_1[0x7];
3256         u8         port[0x8];
3257         u8         reserved_at_10[0x10];
3258
3259         u8         reserved_at_20[0x60];
3260 };
3261
3262 struct mlx5_ifc_vport_tc_element_bits {
3263         u8         traffic_class[0x4];
3264         u8         reserved_at_4[0xc];
3265         u8         vport_number[0x10];
3266 };
3267
3268 struct mlx5_ifc_vport_element_bits {
3269         u8         reserved_at_0[0x10];
3270         u8         vport_number[0x10];
3271 };
3272
3273 enum {
3274         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3275         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3276         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3277 };
3278
3279 struct mlx5_ifc_tsar_element_bits {
3280         u8         reserved_at_0[0x8];
3281         u8         tsar_type[0x8];
3282         u8         reserved_at_10[0x10];
3283 };
3284
3285 enum {
3286         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3287         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3288 };
3289
3290 struct mlx5_ifc_teardown_hca_out_bits {
3291         u8         status[0x8];
3292         u8         reserved_at_8[0x18];
3293
3294         u8         syndrome[0x20];
3295
3296         u8         reserved_at_40[0x3f];
3297
3298         u8         force_state[0x1];
3299 };
3300
3301 enum {
3302         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3303         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3304 };
3305
3306 struct mlx5_ifc_teardown_hca_in_bits {
3307         u8         opcode[0x10];
3308         u8         reserved_at_10[0x10];
3309
3310         u8         reserved_at_20[0x10];
3311         u8         op_mod[0x10];
3312
3313         u8         reserved_at_40[0x10];
3314         u8         profile[0x10];
3315
3316         u8         reserved_at_60[0x20];
3317 };
3318
3319 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3320         u8         status[0x8];
3321         u8         reserved_at_8[0x18];
3322
3323         u8         syndrome[0x20];
3324
3325         u8         reserved_at_40[0x40];
3326 };
3327
3328 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3329         u8         opcode[0x10];
3330         u8         reserved_at_10[0x10];
3331
3332         u8         reserved_at_20[0x10];
3333         u8         op_mod[0x10];
3334
3335         u8         reserved_at_40[0x8];
3336         u8         qpn[0x18];
3337
3338         u8         reserved_at_60[0x20];
3339
3340         u8         opt_param_mask[0x20];
3341
3342         u8         reserved_at_a0[0x20];
3343
3344         struct mlx5_ifc_qpc_bits qpc;
3345
3346         u8         reserved_at_800[0x80];
3347 };
3348
3349 struct mlx5_ifc_sqd2rts_qp_out_bits {
3350         u8         status[0x8];
3351         u8         reserved_at_8[0x18];
3352
3353         u8         syndrome[0x20];
3354
3355         u8         reserved_at_40[0x40];
3356 };
3357
3358 struct mlx5_ifc_sqd2rts_qp_in_bits {
3359         u8         opcode[0x10];
3360         u8         reserved_at_10[0x10];
3361
3362         u8         reserved_at_20[0x10];
3363         u8         op_mod[0x10];
3364
3365         u8         reserved_at_40[0x8];
3366         u8         qpn[0x18];
3367
3368         u8         reserved_at_60[0x20];
3369
3370         u8         opt_param_mask[0x20];
3371
3372         u8         reserved_at_a0[0x20];
3373
3374         struct mlx5_ifc_qpc_bits qpc;
3375
3376         u8         reserved_at_800[0x80];
3377 };
3378
3379 struct mlx5_ifc_set_roce_address_out_bits {
3380         u8         status[0x8];
3381         u8         reserved_at_8[0x18];
3382
3383         u8         syndrome[0x20];
3384
3385         u8         reserved_at_40[0x40];
3386 };
3387
3388 struct mlx5_ifc_set_roce_address_in_bits {
3389         u8         opcode[0x10];
3390         u8         reserved_at_10[0x10];
3391
3392         u8         reserved_at_20[0x10];
3393         u8         op_mod[0x10];
3394
3395         u8         roce_address_index[0x10];
3396         u8         reserved_at_50[0xc];
3397         u8         vhca_port_num[0x4];
3398
3399         u8         reserved_at_60[0x20];
3400
3401         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3402 };
3403
3404 struct mlx5_ifc_set_mad_demux_out_bits {
3405         u8         status[0x8];
3406         u8         reserved_at_8[0x18];
3407
3408         u8         syndrome[0x20];
3409
3410         u8         reserved_at_40[0x40];
3411 };
3412
3413 enum {
3414         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3415         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3416 };
3417
3418 struct mlx5_ifc_set_mad_demux_in_bits {
3419         u8         opcode[0x10];
3420         u8         reserved_at_10[0x10];
3421
3422         u8         reserved_at_20[0x10];
3423         u8         op_mod[0x10];
3424
3425         u8         reserved_at_40[0x20];
3426
3427         u8         reserved_at_60[0x6];
3428         u8         demux_mode[0x2];
3429         u8         reserved_at_68[0x18];
3430 };
3431
3432 struct mlx5_ifc_set_l2_table_entry_out_bits {
3433         u8         status[0x8];
3434         u8         reserved_at_8[0x18];
3435
3436         u8         syndrome[0x20];
3437
3438         u8         reserved_at_40[0x40];
3439 };
3440
3441 struct mlx5_ifc_set_l2_table_entry_in_bits {
3442         u8         opcode[0x10];
3443         u8         reserved_at_10[0x10];
3444
3445         u8         reserved_at_20[0x10];
3446         u8         op_mod[0x10];
3447
3448         u8         reserved_at_40[0x60];
3449
3450         u8         reserved_at_a0[0x8];
3451         u8         table_index[0x18];
3452
3453         u8         reserved_at_c0[0x20];
3454
3455         u8         reserved_at_e0[0x13];
3456         u8         vlan_valid[0x1];
3457         u8         vlan[0xc];
3458
3459         struct mlx5_ifc_mac_address_layout_bits mac_address;
3460
3461         u8         reserved_at_140[0xc0];
3462 };
3463
3464 struct mlx5_ifc_set_issi_out_bits {
3465         u8         status[0x8];
3466         u8         reserved_at_8[0x18];
3467
3468         u8         syndrome[0x20];
3469
3470         u8         reserved_at_40[0x40];
3471 };
3472
3473 struct mlx5_ifc_set_issi_in_bits {
3474         u8         opcode[0x10];
3475         u8         reserved_at_10[0x10];
3476
3477         u8         reserved_at_20[0x10];
3478         u8         op_mod[0x10];
3479
3480         u8         reserved_at_40[0x10];
3481         u8         current_issi[0x10];
3482
3483         u8         reserved_at_60[0x20];
3484 };
3485
3486 struct mlx5_ifc_set_hca_cap_out_bits {
3487         u8         status[0x8];
3488         u8         reserved_at_8[0x18];
3489
3490         u8         syndrome[0x20];
3491
3492         u8         reserved_at_40[0x40];
3493 };
3494
3495 struct mlx5_ifc_set_hca_cap_in_bits {
3496         u8         opcode[0x10];
3497         u8         reserved_at_10[0x10];
3498
3499         u8         reserved_at_20[0x10];
3500         u8         op_mod[0x10];
3501
3502         u8         reserved_at_40[0x40];
3503
3504         union mlx5_ifc_hca_cap_union_bits capability;
3505 };
3506
3507 enum {
3508         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3509         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3510         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3511         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3512 };
3513
3514 struct mlx5_ifc_set_fte_out_bits {
3515         u8         status[0x8];
3516         u8         reserved_at_8[0x18];
3517
3518         u8         syndrome[0x20];
3519
3520         u8         reserved_at_40[0x40];
3521 };
3522
3523 struct mlx5_ifc_set_fte_in_bits {
3524         u8         opcode[0x10];
3525         u8         reserved_at_10[0x10];
3526
3527         u8         reserved_at_20[0x10];
3528         u8         op_mod[0x10];
3529
3530         u8         other_vport[0x1];
3531         u8         reserved_at_41[0xf];
3532         u8         vport_number[0x10];
3533
3534         u8         reserved_at_60[0x20];
3535
3536         u8         table_type[0x8];
3537         u8         reserved_at_88[0x18];
3538
3539         u8         reserved_at_a0[0x8];
3540         u8         table_id[0x18];
3541
3542         u8         reserved_at_c0[0x18];
3543         u8         modify_enable_mask[0x8];
3544
3545         u8         reserved_at_e0[0x20];
3546
3547         u8         flow_index[0x20];
3548
3549         u8         reserved_at_120[0xe0];
3550
3551         struct mlx5_ifc_flow_context_bits flow_context;
3552 };
3553
3554 struct mlx5_ifc_rts2rts_qp_out_bits {
3555         u8         status[0x8];
3556         u8         reserved_at_8[0x18];
3557
3558         u8         syndrome[0x20];
3559
3560         u8         reserved_at_40[0x40];
3561 };
3562
3563 struct mlx5_ifc_rts2rts_qp_in_bits {
3564         u8         opcode[0x10];
3565         u8         reserved_at_10[0x10];
3566
3567         u8         reserved_at_20[0x10];
3568         u8         op_mod[0x10];
3569
3570         u8         reserved_at_40[0x8];
3571         u8         qpn[0x18];
3572
3573         u8         reserved_at_60[0x20];
3574
3575         u8         opt_param_mask[0x20];
3576
3577         u8         reserved_at_a0[0x20];
3578
3579         struct mlx5_ifc_qpc_bits qpc;
3580
3581         u8         reserved_at_800[0x80];
3582 };
3583
3584 struct mlx5_ifc_rtr2rts_qp_out_bits {
3585         u8         status[0x8];
3586         u8         reserved_at_8[0x18];
3587
3588         u8         syndrome[0x20];
3589
3590         u8         reserved_at_40[0x40];
3591 };
3592
3593 struct mlx5_ifc_rtr2rts_qp_in_bits {
3594         u8         opcode[0x10];
3595         u8         reserved_at_10[0x10];
3596
3597         u8         reserved_at_20[0x10];
3598         u8         op_mod[0x10];
3599
3600         u8         reserved_at_40[0x8];
3601         u8         qpn[0x18];
3602
3603         u8         reserved_at_60[0x20];
3604
3605         u8         opt_param_mask[0x20];
3606
3607         u8         reserved_at_a0[0x20];
3608
3609         struct mlx5_ifc_qpc_bits qpc;
3610
3611         u8         reserved_at_800[0x80];
3612 };
3613
3614 struct mlx5_ifc_rst2init_qp_out_bits {
3615         u8         status[0x8];
3616         u8         reserved_at_8[0x18];
3617
3618         u8         syndrome[0x20];
3619
3620         u8         reserved_at_40[0x40];
3621 };
3622
3623 struct mlx5_ifc_rst2init_qp_in_bits {
3624         u8         opcode[0x10];
3625         u8         reserved_at_10[0x10];
3626
3627         u8         reserved_at_20[0x10];
3628         u8         op_mod[0x10];
3629
3630         u8         reserved_at_40[0x8];
3631         u8         qpn[0x18];
3632
3633         u8         reserved_at_60[0x20];
3634
3635         u8         opt_param_mask[0x20];
3636
3637         u8         reserved_at_a0[0x20];
3638
3639         struct mlx5_ifc_qpc_bits qpc;
3640
3641         u8         reserved_at_800[0x80];
3642 };
3643
3644 struct mlx5_ifc_query_xrq_out_bits {
3645         u8         status[0x8];
3646         u8         reserved_at_8[0x18];
3647
3648         u8         syndrome[0x20];
3649
3650         u8         reserved_at_40[0x40];
3651
3652         struct mlx5_ifc_xrqc_bits xrq_context;
3653 };
3654
3655 struct mlx5_ifc_query_xrq_in_bits {
3656         u8         opcode[0x10];
3657         u8         reserved_at_10[0x10];
3658
3659         u8         reserved_at_20[0x10];
3660         u8         op_mod[0x10];
3661
3662         u8         reserved_at_40[0x8];
3663         u8         xrqn[0x18];
3664
3665         u8         reserved_at_60[0x20];
3666 };
3667
3668 struct mlx5_ifc_query_xrc_srq_out_bits {
3669         u8         status[0x8];
3670         u8         reserved_at_8[0x18];
3671
3672         u8         syndrome[0x20];
3673
3674         u8         reserved_at_40[0x40];
3675
3676         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3677
3678         u8         reserved_at_280[0x600];
3679
3680         u8         pas[0][0x40];
3681 };
3682
3683 struct mlx5_ifc_query_xrc_srq_in_bits {
3684         u8         opcode[0x10];
3685         u8         reserved_at_10[0x10];
3686
3687         u8         reserved_at_20[0x10];
3688         u8         op_mod[0x10];
3689
3690         u8         reserved_at_40[0x8];
3691         u8         xrc_srqn[0x18];
3692
3693         u8         reserved_at_60[0x20];
3694 };
3695
3696 enum {
3697         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3698         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3699 };
3700
3701 struct mlx5_ifc_query_vport_state_out_bits {
3702         u8         status[0x8];
3703         u8         reserved_at_8[0x18];
3704
3705         u8         syndrome[0x20];
3706
3707         u8         reserved_at_40[0x20];
3708
3709         u8         reserved_at_60[0x18];
3710         u8         admin_state[0x4];
3711         u8         state[0x4];
3712 };
3713
3714 enum {
3715         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3716         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3717 };
3718
3719 struct mlx5_ifc_query_vport_state_in_bits {
3720         u8         opcode[0x10];
3721         u8         reserved_at_10[0x10];
3722
3723         u8         reserved_at_20[0x10];
3724         u8         op_mod[0x10];
3725
3726         u8         other_vport[0x1];
3727         u8         reserved_at_41[0xf];
3728         u8         vport_number[0x10];
3729
3730         u8         reserved_at_60[0x20];
3731 };
3732
3733 struct mlx5_ifc_query_vnic_env_out_bits {
3734         u8         status[0x8];
3735         u8         reserved_at_8[0x18];
3736
3737         u8         syndrome[0x20];
3738
3739         u8         reserved_at_40[0x40];
3740
3741         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3742 };
3743
3744 enum {
3745         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3746 };
3747
3748 struct mlx5_ifc_query_vnic_env_in_bits {
3749         u8         opcode[0x10];
3750         u8         reserved_at_10[0x10];
3751
3752         u8         reserved_at_20[0x10];
3753         u8         op_mod[0x10];
3754
3755         u8         other_vport[0x1];
3756         u8         reserved_at_41[0xf];
3757         u8         vport_number[0x10];
3758
3759         u8         reserved_at_60[0x20];
3760 };
3761
3762 struct mlx5_ifc_query_vport_counter_out_bits {
3763         u8         status[0x8];
3764         u8         reserved_at_8[0x18];
3765
3766         u8         syndrome[0x20];
3767
3768         u8         reserved_at_40[0x40];
3769
3770         struct mlx5_ifc_traffic_counter_bits received_errors;
3771
3772         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3773
3774         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3775
3776         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3777
3778         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3779
3780         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3781
3782         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3783
3784         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3785
3786         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3787
3788         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3789
3790         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3791
3792         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3793
3794         u8         reserved_at_680[0xa00];
3795 };
3796
3797 enum {
3798         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3799 };
3800
3801 struct mlx5_ifc_query_vport_counter_in_bits {
3802         u8         opcode[0x10];
3803         u8         reserved_at_10[0x10];
3804
3805         u8         reserved_at_20[0x10];
3806         u8         op_mod[0x10];
3807
3808         u8         other_vport[0x1];
3809         u8         reserved_at_41[0xb];
3810         u8         port_num[0x4];
3811         u8         vport_number[0x10];
3812
3813         u8         reserved_at_60[0x60];
3814
3815         u8         clear[0x1];
3816         u8         reserved_at_c1[0x1f];
3817
3818         u8         reserved_at_e0[0x20];
3819 };
3820
3821 struct mlx5_ifc_query_tis_out_bits {
3822         u8         status[0x8];
3823         u8         reserved_at_8[0x18];
3824
3825         u8         syndrome[0x20];
3826
3827         u8         reserved_at_40[0x40];
3828
3829         struct mlx5_ifc_tisc_bits tis_context;
3830 };
3831
3832 struct mlx5_ifc_query_tis_in_bits {
3833         u8         opcode[0x10];
3834         u8         reserved_at_10[0x10];
3835
3836         u8         reserved_at_20[0x10];
3837         u8         op_mod[0x10];
3838
3839         u8         reserved_at_40[0x8];
3840         u8         tisn[0x18];
3841
3842         u8         reserved_at_60[0x20];
3843 };
3844
3845 struct mlx5_ifc_query_tir_out_bits {
3846         u8         status[0x8];
3847         u8         reserved_at_8[0x18];
3848
3849         u8         syndrome[0x20];
3850
3851         u8         reserved_at_40[0xc0];
3852
3853         struct mlx5_ifc_tirc_bits tir_context;
3854 };
3855
3856 struct mlx5_ifc_query_tir_in_bits {
3857         u8         opcode[0x10];
3858         u8         reserved_at_10[0x10];
3859
3860         u8         reserved_at_20[0x10];
3861         u8         op_mod[0x10];
3862
3863         u8         reserved_at_40[0x8];
3864         u8         tirn[0x18];
3865
3866         u8         reserved_at_60[0x20];
3867 };
3868
3869 struct mlx5_ifc_query_srq_out_bits {
3870         u8         status[0x8];
3871         u8         reserved_at_8[0x18];
3872
3873         u8         syndrome[0x20];
3874
3875         u8         reserved_at_40[0x40];
3876
3877         struct mlx5_ifc_srqc_bits srq_context_entry;
3878
3879         u8         reserved_at_280[0x600];
3880
3881         u8         pas[0][0x40];
3882 };
3883
3884 struct mlx5_ifc_query_srq_in_bits {
3885         u8         opcode[0x10];
3886         u8         reserved_at_10[0x10];
3887
3888         u8         reserved_at_20[0x10];
3889         u8         op_mod[0x10];
3890
3891         u8         reserved_at_40[0x8];
3892         u8         srqn[0x18];
3893
3894         u8         reserved_at_60[0x20];
3895 };
3896
3897 struct mlx5_ifc_query_sq_out_bits {
3898         u8         status[0x8];
3899         u8         reserved_at_8[0x18];
3900
3901         u8         syndrome[0x20];
3902
3903         u8         reserved_at_40[0xc0];
3904
3905         struct mlx5_ifc_sqc_bits sq_context;
3906 };
3907
3908 struct mlx5_ifc_query_sq_in_bits {
3909         u8         opcode[0x10];
3910         u8         reserved_at_10[0x10];
3911
3912         u8         reserved_at_20[0x10];
3913         u8         op_mod[0x10];
3914
3915         u8         reserved_at_40[0x8];
3916         u8         sqn[0x18];
3917
3918         u8         reserved_at_60[0x20];
3919 };
3920
3921 struct mlx5_ifc_query_special_contexts_out_bits {
3922         u8         status[0x8];
3923         u8         reserved_at_8[0x18];
3924
3925         u8         syndrome[0x20];
3926
3927         u8         dump_fill_mkey[0x20];
3928
3929         u8         resd_lkey[0x20];
3930
3931         u8         null_mkey[0x20];
3932
3933         u8         reserved_at_a0[0x60];
3934 };
3935
3936 struct mlx5_ifc_query_special_contexts_in_bits {
3937         u8         opcode[0x10];
3938         u8         reserved_at_10[0x10];
3939
3940         u8         reserved_at_20[0x10];
3941         u8         op_mod[0x10];
3942
3943         u8         reserved_at_40[0x40];
3944 };
3945
3946 struct mlx5_ifc_query_scheduling_element_out_bits {
3947         u8         opcode[0x10];
3948         u8         reserved_at_10[0x10];
3949
3950         u8         reserved_at_20[0x10];
3951         u8         op_mod[0x10];
3952
3953         u8         reserved_at_40[0xc0];
3954
3955         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3956
3957         u8         reserved_at_300[0x100];
3958 };
3959
3960 enum {
3961         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3962 };
3963
3964 struct mlx5_ifc_query_scheduling_element_in_bits {
3965         u8         opcode[0x10];
3966         u8         reserved_at_10[0x10];
3967
3968         u8         reserved_at_20[0x10];
3969         u8         op_mod[0x10];
3970
3971         u8         scheduling_hierarchy[0x8];
3972         u8         reserved_at_48[0x18];
3973
3974         u8         scheduling_element_id[0x20];
3975
3976         u8         reserved_at_80[0x180];
3977 };
3978
3979 struct mlx5_ifc_query_rqt_out_bits {
3980         u8         status[0x8];
3981         u8         reserved_at_8[0x18];
3982
3983         u8         syndrome[0x20];
3984
3985         u8         reserved_at_40[0xc0];
3986
3987         struct mlx5_ifc_rqtc_bits rqt_context;
3988 };
3989
3990 struct mlx5_ifc_query_rqt_in_bits {
3991         u8         opcode[0x10];
3992         u8         reserved_at_10[0x10];
3993
3994         u8         reserved_at_20[0x10];
3995         u8         op_mod[0x10];
3996
3997         u8         reserved_at_40[0x8];
3998         u8         rqtn[0x18];
3999
4000         u8         reserved_at_60[0x20];
4001 };
4002
4003 struct mlx5_ifc_query_rq_out_bits {
4004         u8         status[0x8];
4005         u8         reserved_at_8[0x18];
4006
4007         u8         syndrome[0x20];
4008
4009         u8         reserved_at_40[0xc0];
4010
4011         struct mlx5_ifc_rqc_bits rq_context;
4012 };
4013
4014 struct mlx5_ifc_query_rq_in_bits {
4015         u8         opcode[0x10];
4016         u8         reserved_at_10[0x10];
4017
4018         u8         reserved_at_20[0x10];
4019         u8         op_mod[0x10];
4020
4021         u8         reserved_at_40[0x8];
4022         u8         rqn[0x18];
4023
4024         u8         reserved_at_60[0x20];
4025 };
4026
4027 struct mlx5_ifc_query_roce_address_out_bits {
4028         u8         status[0x8];
4029         u8         reserved_at_8[0x18];
4030
4031         u8         syndrome[0x20];
4032
4033         u8         reserved_at_40[0x40];
4034
4035         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4036 };
4037
4038 struct mlx5_ifc_query_roce_address_in_bits {
4039         u8         opcode[0x10];
4040         u8         reserved_at_10[0x10];
4041
4042         u8         reserved_at_20[0x10];
4043         u8         op_mod[0x10];
4044
4045         u8         roce_address_index[0x10];
4046         u8         reserved_at_50[0xc];
4047         u8         vhca_port_num[0x4];
4048
4049         u8         reserved_at_60[0x20];
4050 };
4051
4052 struct mlx5_ifc_query_rmp_out_bits {
4053         u8         status[0x8];
4054         u8         reserved_at_8[0x18];
4055
4056         u8         syndrome[0x20];
4057
4058         u8         reserved_at_40[0xc0];
4059
4060         struct mlx5_ifc_rmpc_bits rmp_context;
4061 };
4062
4063 struct mlx5_ifc_query_rmp_in_bits {
4064         u8         opcode[0x10];
4065         u8         reserved_at_10[0x10];
4066
4067         u8         reserved_at_20[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_at_40[0x8];
4071         u8         rmpn[0x18];
4072
4073         u8         reserved_at_60[0x20];
4074 };
4075
4076 struct mlx5_ifc_query_qp_out_bits {
4077         u8         status[0x8];
4078         u8         reserved_at_8[0x18];
4079
4080         u8         syndrome[0x20];
4081
4082         u8         reserved_at_40[0x40];
4083
4084         u8         opt_param_mask[0x20];
4085
4086         u8         reserved_at_a0[0x20];
4087
4088         struct mlx5_ifc_qpc_bits qpc;
4089
4090         u8         reserved_at_800[0x80];
4091
4092         u8         pas[0][0x40];
4093 };
4094
4095 struct mlx5_ifc_query_qp_in_bits {
4096         u8         opcode[0x10];
4097         u8         reserved_at_10[0x10];
4098
4099         u8         reserved_at_20[0x10];
4100         u8         op_mod[0x10];
4101
4102         u8         reserved_at_40[0x8];
4103         u8         qpn[0x18];
4104
4105         u8         reserved_at_60[0x20];
4106 };
4107
4108 struct mlx5_ifc_query_q_counter_out_bits {
4109         u8         status[0x8];
4110         u8         reserved_at_8[0x18];
4111
4112         u8         syndrome[0x20];
4113
4114         u8         reserved_at_40[0x40];
4115
4116         u8         rx_write_requests[0x20];
4117
4118         u8         reserved_at_a0[0x20];
4119
4120         u8         rx_read_requests[0x20];
4121
4122         u8         reserved_at_e0[0x20];
4123
4124         u8         rx_atomic_requests[0x20];
4125
4126         u8         reserved_at_120[0x20];
4127
4128         u8         rx_dct_connect[0x20];
4129
4130         u8         reserved_at_160[0x20];
4131
4132         u8         out_of_buffer[0x20];
4133
4134         u8         reserved_at_1a0[0x20];
4135
4136         u8         out_of_sequence[0x20];
4137
4138         u8         reserved_at_1e0[0x20];
4139
4140         u8         duplicate_request[0x20];
4141
4142         u8         reserved_at_220[0x20];
4143
4144         u8         rnr_nak_retry_err[0x20];
4145
4146         u8         reserved_at_260[0x20];
4147
4148         u8         packet_seq_err[0x20];
4149
4150         u8         reserved_at_2a0[0x20];
4151
4152         u8         implied_nak_seq_err[0x20];
4153
4154         u8         reserved_at_2e0[0x20];
4155
4156         u8         local_ack_timeout_err[0x20];
4157
4158         u8         reserved_at_320[0xa0];
4159
4160         u8         resp_local_length_error[0x20];
4161
4162         u8         req_local_length_error[0x20];
4163
4164         u8         resp_local_qp_error[0x20];
4165
4166         u8         local_operation_error[0x20];
4167
4168         u8         resp_local_protection[0x20];
4169
4170         u8         req_local_protection[0x20];
4171
4172         u8         resp_cqe_error[0x20];
4173
4174         u8         req_cqe_error[0x20];
4175
4176         u8         req_mw_binding[0x20];
4177
4178         u8         req_bad_response[0x20];
4179
4180         u8         req_remote_invalid_request[0x20];
4181
4182         u8         resp_remote_invalid_request[0x20];
4183
4184         u8         req_remote_access_errors[0x20];
4185
4186         u8         resp_remote_access_errors[0x20];
4187
4188         u8         req_remote_operation_errors[0x20];
4189
4190         u8         req_transport_retries_exceeded[0x20];
4191
4192         u8         cq_overflow[0x20];
4193
4194         u8         resp_cqe_flush_error[0x20];
4195
4196         u8         req_cqe_flush_error[0x20];
4197
4198         u8         reserved_at_620[0x1e0];
4199 };
4200
4201 struct mlx5_ifc_query_q_counter_in_bits {
4202         u8         opcode[0x10];
4203         u8         reserved_at_10[0x10];
4204
4205         u8         reserved_at_20[0x10];
4206         u8         op_mod[0x10];
4207
4208         u8         reserved_at_40[0x80];
4209
4210         u8         clear[0x1];
4211         u8         reserved_at_c1[0x1f];
4212
4213         u8         reserved_at_e0[0x18];
4214         u8         counter_set_id[0x8];
4215 };
4216
4217 struct mlx5_ifc_query_pages_out_bits {
4218         u8         status[0x8];
4219         u8         reserved_at_8[0x18];
4220
4221         u8         syndrome[0x20];
4222
4223         u8         reserved_at_40[0x10];
4224         u8         function_id[0x10];
4225
4226         u8         num_pages[0x20];
4227 };
4228
4229 enum {
4230         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4231         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4232         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4233 };
4234
4235 struct mlx5_ifc_query_pages_in_bits {
4236         u8         opcode[0x10];
4237         u8         reserved_at_10[0x10];
4238
4239         u8         reserved_at_20[0x10];
4240         u8         op_mod[0x10];
4241
4242         u8         reserved_at_40[0x10];
4243         u8         function_id[0x10];
4244
4245         u8         reserved_at_60[0x20];
4246 };
4247
4248 struct mlx5_ifc_query_nic_vport_context_out_bits {
4249         u8         status[0x8];
4250         u8         reserved_at_8[0x18];
4251
4252         u8         syndrome[0x20];
4253
4254         u8         reserved_at_40[0x40];
4255
4256         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4257 };
4258
4259 struct mlx5_ifc_query_nic_vport_context_in_bits {
4260         u8         opcode[0x10];
4261         u8         reserved_at_10[0x10];
4262
4263         u8         reserved_at_20[0x10];
4264         u8         op_mod[0x10];
4265
4266         u8         other_vport[0x1];
4267         u8         reserved_at_41[0xf];
4268         u8         vport_number[0x10];
4269
4270         u8         reserved_at_60[0x5];
4271         u8         allowed_list_type[0x3];
4272         u8         reserved_at_68[0x18];
4273 };
4274
4275 struct mlx5_ifc_query_mkey_out_bits {
4276         u8         status[0x8];
4277         u8         reserved_at_8[0x18];
4278
4279         u8         syndrome[0x20];
4280
4281         u8         reserved_at_40[0x40];
4282
4283         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4284
4285         u8         reserved_at_280[0x600];
4286
4287         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4288
4289         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4290 };
4291
4292 struct mlx5_ifc_query_mkey_in_bits {
4293         u8         opcode[0x10];
4294         u8         reserved_at_10[0x10];
4295
4296         u8         reserved_at_20[0x10];
4297         u8         op_mod[0x10];
4298
4299         u8         reserved_at_40[0x8];
4300         u8         mkey_index[0x18];
4301
4302         u8         pg_access[0x1];
4303         u8         reserved_at_61[0x1f];
4304 };
4305
4306 struct mlx5_ifc_query_mad_demux_out_bits {
4307         u8         status[0x8];
4308         u8         reserved_at_8[0x18];
4309
4310         u8         syndrome[0x20];
4311
4312         u8         reserved_at_40[0x40];
4313
4314         u8         mad_dumux_parameters_block[0x20];
4315 };
4316
4317 struct mlx5_ifc_query_mad_demux_in_bits {
4318         u8         opcode[0x10];
4319         u8         reserved_at_10[0x10];
4320
4321         u8         reserved_at_20[0x10];
4322         u8         op_mod[0x10];
4323
4324         u8         reserved_at_40[0x40];
4325 };
4326
4327 struct mlx5_ifc_query_l2_table_entry_out_bits {
4328         u8         status[0x8];
4329         u8         reserved_at_8[0x18];
4330
4331         u8         syndrome[0x20];
4332
4333         u8         reserved_at_40[0xa0];
4334
4335         u8         reserved_at_e0[0x13];
4336         u8         vlan_valid[0x1];
4337         u8         vlan[0xc];
4338
4339         struct mlx5_ifc_mac_address_layout_bits mac_address;
4340
4341         u8         reserved_at_140[0xc0];
4342 };
4343
4344 struct mlx5_ifc_query_l2_table_entry_in_bits {
4345         u8         opcode[0x10];
4346         u8         reserved_at_10[0x10];
4347
4348         u8         reserved_at_20[0x10];
4349         u8         op_mod[0x10];
4350
4351         u8         reserved_at_40[0x60];
4352
4353         u8         reserved_at_a0[0x8];
4354         u8         table_index[0x18];
4355
4356         u8         reserved_at_c0[0x140];
4357 };
4358
4359 struct mlx5_ifc_query_issi_out_bits {
4360         u8         status[0x8];
4361         u8         reserved_at_8[0x18];
4362
4363         u8         syndrome[0x20];
4364
4365         u8         reserved_at_40[0x10];
4366         u8         current_issi[0x10];
4367
4368         u8         reserved_at_60[0xa0];
4369
4370         u8         reserved_at_100[76][0x8];
4371         u8         supported_issi_dw0[0x20];
4372 };
4373
4374 struct mlx5_ifc_query_issi_in_bits {
4375         u8         opcode[0x10];
4376         u8         reserved_at_10[0x10];
4377
4378         u8         reserved_at_20[0x10];
4379         u8         op_mod[0x10];
4380
4381         u8         reserved_at_40[0x40];
4382 };
4383
4384 struct mlx5_ifc_set_driver_version_out_bits {
4385         u8         status[0x8];
4386         u8         reserved_0[0x18];
4387
4388         u8         syndrome[0x20];
4389         u8         reserved_1[0x40];
4390 };
4391
4392 struct mlx5_ifc_set_driver_version_in_bits {
4393         u8         opcode[0x10];
4394         u8         reserved_0[0x10];
4395
4396         u8         reserved_1[0x10];
4397         u8         op_mod[0x10];
4398
4399         u8         reserved_2[0x40];
4400         u8         driver_version[64][0x8];
4401 };
4402
4403 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4404         u8         status[0x8];
4405         u8         reserved_at_8[0x18];
4406
4407         u8         syndrome[0x20];
4408
4409         u8         reserved_at_40[0x40];
4410
4411         struct mlx5_ifc_pkey_bits pkey[0];
4412 };
4413
4414 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4415         u8         opcode[0x10];
4416         u8         reserved_at_10[0x10];
4417
4418         u8         reserved_at_20[0x10];
4419         u8         op_mod[0x10];
4420
4421         u8         other_vport[0x1];
4422         u8         reserved_at_41[0xb];
4423         u8         port_num[0x4];
4424         u8         vport_number[0x10];
4425
4426         u8         reserved_at_60[0x10];
4427         u8         pkey_index[0x10];
4428 };
4429
4430 enum {
4431         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4432         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4433         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4434 };
4435
4436 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4437         u8         status[0x8];
4438         u8         reserved_at_8[0x18];
4439
4440         u8         syndrome[0x20];
4441
4442         u8         reserved_at_40[0x20];
4443
4444         u8         gids_num[0x10];
4445         u8         reserved_at_70[0x10];
4446
4447         struct mlx5_ifc_array128_auto_bits gid[0];
4448 };
4449
4450 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4451         u8         opcode[0x10];
4452         u8         reserved_at_10[0x10];
4453
4454         u8         reserved_at_20[0x10];
4455         u8         op_mod[0x10];
4456
4457         u8         other_vport[0x1];
4458         u8         reserved_at_41[0xb];
4459         u8         port_num[0x4];
4460         u8         vport_number[0x10];
4461
4462         u8         reserved_at_60[0x10];
4463         u8         gid_index[0x10];
4464 };
4465
4466 struct mlx5_ifc_query_hca_vport_context_out_bits {
4467         u8         status[0x8];
4468         u8         reserved_at_8[0x18];
4469
4470         u8         syndrome[0x20];
4471
4472         u8         reserved_at_40[0x40];
4473
4474         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4475 };
4476
4477 struct mlx5_ifc_query_hca_vport_context_in_bits {
4478         u8         opcode[0x10];
4479         u8         reserved_at_10[0x10];
4480
4481         u8         reserved_at_20[0x10];
4482         u8         op_mod[0x10];
4483
4484         u8         other_vport[0x1];
4485         u8         reserved_at_41[0xb];
4486         u8         port_num[0x4];
4487         u8         vport_number[0x10];
4488
4489         u8         reserved_at_60[0x20];
4490 };
4491
4492 struct mlx5_ifc_query_hca_cap_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_at_8[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         reserved_at_40[0x40];
4499
4500         union mlx5_ifc_hca_cap_union_bits capability;
4501 };
4502
4503 struct mlx5_ifc_query_hca_cap_in_bits {
4504         u8         opcode[0x10];
4505         u8         reserved_at_10[0x10];
4506
4507         u8         reserved_at_20[0x10];
4508         u8         op_mod[0x10];
4509
4510         u8         reserved_at_40[0x40];
4511 };
4512
4513 struct mlx5_ifc_query_flow_table_out_bits {
4514         u8         status[0x8];
4515         u8         reserved_at_8[0x18];
4516
4517         u8         syndrome[0x20];
4518
4519         u8         reserved_at_40[0x80];
4520
4521         u8         reserved_at_c0[0x8];
4522         u8         level[0x8];
4523         u8         reserved_at_d0[0x8];
4524         u8         log_size[0x8];
4525
4526         u8         reserved_at_e0[0x120];
4527 };
4528
4529 struct mlx5_ifc_query_flow_table_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_at_10[0x10];
4532
4533         u8         reserved_at_20[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         reserved_at_40[0x40];
4537
4538         u8         table_type[0x8];
4539         u8         reserved_at_88[0x18];
4540
4541         u8         reserved_at_a0[0x8];
4542         u8         table_id[0x18];
4543
4544         u8         reserved_at_c0[0x140];
4545 };
4546
4547 struct mlx5_ifc_query_fte_out_bits {
4548         u8         status[0x8];
4549         u8         reserved_at_8[0x18];
4550
4551         u8         syndrome[0x20];
4552
4553         u8         reserved_at_40[0x1c0];
4554
4555         struct mlx5_ifc_flow_context_bits flow_context;
4556 };
4557
4558 struct mlx5_ifc_query_fte_in_bits {
4559         u8         opcode[0x10];
4560         u8         reserved_at_10[0x10];
4561
4562         u8         reserved_at_20[0x10];
4563         u8         op_mod[0x10];
4564
4565         u8         reserved_at_40[0x40];
4566
4567         u8         table_type[0x8];
4568         u8         reserved_at_88[0x18];
4569
4570         u8         reserved_at_a0[0x8];
4571         u8         table_id[0x18];
4572
4573         u8         reserved_at_c0[0x40];
4574
4575         u8         flow_index[0x20];
4576
4577         u8         reserved_at_120[0xe0];
4578 };
4579
4580 enum {
4581         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4582         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4583         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4584 };
4585
4586 struct mlx5_ifc_query_flow_group_out_bits {
4587         u8         status[0x8];
4588         u8         reserved_at_8[0x18];
4589
4590         u8         syndrome[0x20];
4591
4592         u8         reserved_at_40[0xa0];
4593
4594         u8         start_flow_index[0x20];
4595
4596         u8         reserved_at_100[0x20];
4597
4598         u8         end_flow_index[0x20];
4599
4600         u8         reserved_at_140[0xa0];
4601
4602         u8         reserved_at_1e0[0x18];
4603         u8         match_criteria_enable[0x8];
4604
4605         struct mlx5_ifc_fte_match_param_bits match_criteria;
4606
4607         u8         reserved_at_1200[0xe00];
4608 };
4609
4610 struct mlx5_ifc_query_flow_group_in_bits {
4611         u8         opcode[0x10];
4612         u8         reserved_at_10[0x10];
4613
4614         u8         reserved_at_20[0x10];
4615         u8         op_mod[0x10];
4616
4617         u8         reserved_at_40[0x40];
4618
4619         u8         table_type[0x8];
4620         u8         reserved_at_88[0x18];
4621
4622         u8         reserved_at_a0[0x8];
4623         u8         table_id[0x18];
4624
4625         u8         group_id[0x20];
4626
4627         u8         reserved_at_e0[0x120];
4628 };
4629
4630 struct mlx5_ifc_query_flow_counter_out_bits {
4631         u8         status[0x8];
4632         u8         reserved_at_8[0x18];
4633
4634         u8         syndrome[0x20];
4635
4636         u8         reserved_at_40[0x40];
4637
4638         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4639 };
4640
4641 struct mlx5_ifc_query_flow_counter_in_bits {
4642         u8         opcode[0x10];
4643         u8         reserved_at_10[0x10];
4644
4645         u8         reserved_at_20[0x10];
4646         u8         op_mod[0x10];
4647
4648         u8         reserved_at_40[0x80];
4649
4650         u8         clear[0x1];
4651         u8         reserved_at_c1[0xf];
4652         u8         num_of_counters[0x10];
4653
4654         u8         flow_counter_id[0x20];
4655 };
4656
4657 struct mlx5_ifc_query_esw_vport_context_out_bits {
4658         u8         status[0x8];
4659         u8         reserved_at_8[0x18];
4660
4661         u8         syndrome[0x20];
4662
4663         u8         reserved_at_40[0x40];
4664
4665         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4666 };
4667
4668 struct mlx5_ifc_query_esw_vport_context_in_bits {
4669         u8         opcode[0x10];
4670         u8         reserved_at_10[0x10];
4671
4672         u8         reserved_at_20[0x10];
4673         u8         op_mod[0x10];
4674
4675         u8         other_vport[0x1];
4676         u8         reserved_at_41[0xf];
4677         u8         vport_number[0x10];
4678
4679         u8         reserved_at_60[0x20];
4680 };
4681
4682 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4683         u8         status[0x8];
4684         u8         reserved_at_8[0x18];
4685
4686         u8         syndrome[0x20];
4687
4688         u8         reserved_at_40[0x40];
4689 };
4690
4691 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4692         u8         reserved_at_0[0x1c];
4693         u8         vport_cvlan_insert[0x1];
4694         u8         vport_svlan_insert[0x1];
4695         u8         vport_cvlan_strip[0x1];
4696         u8         vport_svlan_strip[0x1];
4697 };
4698
4699 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4700         u8         opcode[0x10];
4701         u8         reserved_at_10[0x10];
4702
4703         u8         reserved_at_20[0x10];
4704         u8         op_mod[0x10];
4705
4706         u8         other_vport[0x1];
4707         u8         reserved_at_41[0xf];
4708         u8         vport_number[0x10];
4709
4710         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4711
4712         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4713 };
4714
4715 struct mlx5_ifc_query_eq_out_bits {
4716         u8         status[0x8];
4717         u8         reserved_at_8[0x18];
4718
4719         u8         syndrome[0x20];
4720
4721         u8         reserved_at_40[0x40];
4722
4723         struct mlx5_ifc_eqc_bits eq_context_entry;
4724
4725         u8         reserved_at_280[0x40];
4726
4727         u8         event_bitmask[0x40];
4728
4729         u8         reserved_at_300[0x580];
4730
4731         u8         pas[0][0x40];
4732 };
4733
4734 struct mlx5_ifc_query_eq_in_bits {
4735         u8         opcode[0x10];
4736         u8         reserved_at_10[0x10];
4737
4738         u8         reserved_at_20[0x10];
4739         u8         op_mod[0x10];
4740
4741         u8         reserved_at_40[0x18];
4742         u8         eq_number[0x8];
4743
4744         u8         reserved_at_60[0x20];
4745 };
4746
4747 struct mlx5_ifc_encap_header_in_bits {
4748         u8         reserved_at_0[0x5];
4749         u8         header_type[0x3];
4750         u8         reserved_at_8[0xe];
4751         u8         encap_header_size[0xa];
4752
4753         u8         reserved_at_20[0x10];
4754         u8         encap_header[2][0x8];
4755
4756         u8         more_encap_header[0][0x8];
4757 };
4758
4759 struct mlx5_ifc_query_encap_header_out_bits {
4760         u8         status[0x8];
4761         u8         reserved_at_8[0x18];
4762
4763         u8         syndrome[0x20];
4764
4765         u8         reserved_at_40[0xa0];
4766
4767         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4768 };
4769
4770 struct mlx5_ifc_query_encap_header_in_bits {
4771         u8         opcode[0x10];
4772         u8         reserved_at_10[0x10];
4773
4774         u8         reserved_at_20[0x10];
4775         u8         op_mod[0x10];
4776
4777         u8         encap_id[0x20];
4778
4779         u8         reserved_at_60[0xa0];
4780 };
4781
4782 struct mlx5_ifc_alloc_encap_header_out_bits {
4783         u8         status[0x8];
4784         u8         reserved_at_8[0x18];
4785
4786         u8         syndrome[0x20];
4787
4788         u8         encap_id[0x20];
4789
4790         u8         reserved_at_60[0x20];
4791 };
4792
4793 struct mlx5_ifc_alloc_encap_header_in_bits {
4794         u8         opcode[0x10];
4795         u8         reserved_at_10[0x10];
4796
4797         u8         reserved_at_20[0x10];
4798         u8         op_mod[0x10];
4799
4800         u8         reserved_at_40[0xa0];
4801
4802         struct mlx5_ifc_encap_header_in_bits encap_header;
4803 };
4804
4805 struct mlx5_ifc_dealloc_encap_header_out_bits {
4806         u8         status[0x8];
4807         u8         reserved_at_8[0x18];
4808
4809         u8         syndrome[0x20];
4810
4811         u8         reserved_at_40[0x40];
4812 };
4813
4814 struct mlx5_ifc_dealloc_encap_header_in_bits {
4815         u8         opcode[0x10];
4816         u8         reserved_at_10[0x10];
4817
4818         u8         reserved_20[0x10];
4819         u8         op_mod[0x10];
4820
4821         u8         encap_id[0x20];
4822
4823         u8         reserved_60[0x20];
4824 };
4825
4826 struct mlx5_ifc_set_action_in_bits {
4827         u8         action_type[0x4];
4828         u8         field[0xc];
4829         u8         reserved_at_10[0x3];
4830         u8         offset[0x5];
4831         u8         reserved_at_18[0x3];
4832         u8         length[0x5];
4833
4834         u8         data[0x20];
4835 };
4836
4837 struct mlx5_ifc_add_action_in_bits {
4838         u8         action_type[0x4];
4839         u8         field[0xc];
4840         u8         reserved_at_10[0x10];
4841
4842         u8         data[0x20];
4843 };
4844
4845 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4846         struct mlx5_ifc_set_action_in_bits set_action_in;
4847         struct mlx5_ifc_add_action_in_bits add_action_in;
4848         u8         reserved_at_0[0x40];
4849 };
4850
4851 enum {
4852         MLX5_ACTION_TYPE_SET   = 0x1,
4853         MLX5_ACTION_TYPE_ADD   = 0x2,
4854 };
4855
4856 enum {
4857         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4858         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4859         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4860         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4861         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4862         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4863         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4864         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4865         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4866         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4867         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4868         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4869         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4870         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4871         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4872         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4873         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4874         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4875         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4876         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4877         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4878         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4879         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4880 };
4881
4882 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         modify_header_id[0x20];
4889
4890         u8         reserved_at_60[0x20];
4891 };
4892
4893 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4894         u8         opcode[0x10];
4895         u8         reserved_at_10[0x10];
4896
4897         u8         reserved_at_20[0x10];
4898         u8         op_mod[0x10];
4899
4900         u8         reserved_at_40[0x20];
4901
4902         u8         table_type[0x8];
4903         u8         reserved_at_68[0x10];
4904         u8         num_of_actions[0x8];
4905
4906         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4907 };
4908
4909 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_at_8[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_at_40[0x40];
4916 };
4917
4918 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4919         u8         opcode[0x10];
4920         u8         reserved_at_10[0x10];
4921
4922         u8         reserved_at_20[0x10];
4923         u8         op_mod[0x10];
4924
4925         u8         modify_header_id[0x20];
4926
4927         u8         reserved_at_60[0x20];
4928 };
4929
4930 struct mlx5_ifc_query_dct_out_bits {
4931         u8         status[0x8];
4932         u8         reserved_at_8[0x18];
4933
4934         u8         syndrome[0x20];
4935
4936         u8         reserved_at_40[0x40];
4937
4938         struct mlx5_ifc_dctc_bits dct_context_entry;
4939
4940         u8         reserved_at_280[0x180];
4941 };
4942
4943 struct mlx5_ifc_query_dct_in_bits {
4944         u8         opcode[0x10];
4945         u8         reserved_at_10[0x10];
4946
4947         u8         reserved_at_20[0x10];
4948         u8         op_mod[0x10];
4949
4950         u8         reserved_at_40[0x8];
4951         u8         dctn[0x18];
4952
4953         u8         reserved_at_60[0x20];
4954 };
4955
4956 struct mlx5_ifc_query_cq_out_bits {
4957         u8         status[0x8];
4958         u8         reserved_at_8[0x18];
4959
4960         u8         syndrome[0x20];
4961
4962         u8         reserved_at_40[0x40];
4963
4964         struct mlx5_ifc_cqc_bits cq_context;
4965
4966         u8         reserved_at_280[0x600];
4967
4968         u8         pas[0][0x40];
4969 };
4970
4971 struct mlx5_ifc_query_cq_in_bits {
4972         u8         opcode[0x10];
4973         u8         reserved_at_10[0x10];
4974
4975         u8         reserved_at_20[0x10];
4976         u8         op_mod[0x10];
4977
4978         u8         reserved_at_40[0x8];
4979         u8         cqn[0x18];
4980
4981         u8         reserved_at_60[0x20];
4982 };
4983
4984 struct mlx5_ifc_query_cong_status_out_bits {
4985         u8         status[0x8];
4986         u8         reserved_at_8[0x18];
4987
4988         u8         syndrome[0x20];
4989
4990         u8         reserved_at_40[0x20];
4991
4992         u8         enable[0x1];
4993         u8         tag_enable[0x1];
4994         u8         reserved_at_62[0x1e];
4995 };
4996
4997 struct mlx5_ifc_query_cong_status_in_bits {
4998         u8         opcode[0x10];
4999         u8         reserved_at_10[0x10];
5000
5001         u8         reserved_at_20[0x10];
5002         u8         op_mod[0x10];
5003
5004         u8         reserved_at_40[0x18];
5005         u8         priority[0x4];
5006         u8         cong_protocol[0x4];
5007
5008         u8         reserved_at_60[0x20];
5009 };
5010
5011 struct mlx5_ifc_query_cong_statistics_out_bits {
5012         u8         status[0x8];
5013         u8         reserved_at_8[0x18];
5014
5015         u8         syndrome[0x20];
5016
5017         u8         reserved_at_40[0x40];
5018
5019         u8         rp_cur_flows[0x20];
5020
5021         u8         sum_flows[0x20];
5022
5023         u8         rp_cnp_ignored_high[0x20];
5024
5025         u8         rp_cnp_ignored_low[0x20];
5026
5027         u8         rp_cnp_handled_high[0x20];
5028
5029         u8         rp_cnp_handled_low[0x20];
5030
5031         u8         reserved_at_140[0x100];
5032
5033         u8         time_stamp_high[0x20];
5034
5035         u8         time_stamp_low[0x20];
5036
5037         u8         accumulators_period[0x20];
5038
5039         u8         np_ecn_marked_roce_packets_high[0x20];
5040
5041         u8         np_ecn_marked_roce_packets_low[0x20];
5042
5043         u8         np_cnp_sent_high[0x20];
5044
5045         u8         np_cnp_sent_low[0x20];
5046
5047         u8         reserved_at_320[0x560];
5048 };
5049
5050 struct mlx5_ifc_query_cong_statistics_in_bits {
5051         u8         opcode[0x10];
5052         u8         reserved_at_10[0x10];
5053
5054         u8         reserved_at_20[0x10];
5055         u8         op_mod[0x10];
5056
5057         u8         clear[0x1];
5058         u8         reserved_at_41[0x1f];
5059
5060         u8         reserved_at_60[0x20];
5061 };
5062
5063 struct mlx5_ifc_query_cong_params_out_bits {
5064         u8         status[0x8];
5065         u8         reserved_at_8[0x18];
5066
5067         u8         syndrome[0x20];
5068
5069         u8         reserved_at_40[0x40];
5070
5071         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5072 };
5073
5074 struct mlx5_ifc_query_cong_params_in_bits {
5075         u8         opcode[0x10];
5076         u8         reserved_at_10[0x10];
5077
5078         u8         reserved_at_20[0x10];
5079         u8         op_mod[0x10];
5080
5081         u8         reserved_at_40[0x1c];
5082         u8         cong_protocol[0x4];
5083
5084         u8         reserved_at_60[0x20];
5085 };
5086
5087 struct mlx5_ifc_query_adapter_out_bits {
5088         u8         status[0x8];
5089         u8         reserved_at_8[0x18];
5090
5091         u8         syndrome[0x20];
5092
5093         u8         reserved_at_40[0x40];
5094
5095         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5096 };
5097
5098 struct mlx5_ifc_query_adapter_in_bits {
5099         u8         opcode[0x10];
5100         u8         reserved_at_10[0x10];
5101
5102         u8         reserved_at_20[0x10];
5103         u8         op_mod[0x10];
5104
5105         u8         reserved_at_40[0x40];
5106 };
5107
5108 struct mlx5_ifc_qp_2rst_out_bits {
5109         u8         status[0x8];
5110         u8         reserved_at_8[0x18];
5111
5112         u8         syndrome[0x20];
5113
5114         u8         reserved_at_40[0x40];
5115 };
5116
5117 struct mlx5_ifc_qp_2rst_in_bits {
5118         u8         opcode[0x10];
5119         u8         reserved_at_10[0x10];
5120
5121         u8         reserved_at_20[0x10];
5122         u8         op_mod[0x10];
5123
5124         u8         reserved_at_40[0x8];
5125         u8         qpn[0x18];
5126
5127         u8         reserved_at_60[0x20];
5128 };
5129
5130 struct mlx5_ifc_qp_2err_out_bits {
5131         u8         status[0x8];
5132         u8         reserved_at_8[0x18];
5133
5134         u8         syndrome[0x20];
5135
5136         u8         reserved_at_40[0x40];
5137 };
5138
5139 struct mlx5_ifc_qp_2err_in_bits {
5140         u8         opcode[0x10];
5141         u8         reserved_at_10[0x10];
5142
5143         u8         reserved_at_20[0x10];
5144         u8         op_mod[0x10];
5145
5146         u8         reserved_at_40[0x8];
5147         u8         qpn[0x18];
5148
5149         u8         reserved_at_60[0x20];
5150 };
5151
5152 struct mlx5_ifc_page_fault_resume_out_bits {
5153         u8         status[0x8];
5154         u8         reserved_at_8[0x18];
5155
5156         u8         syndrome[0x20];
5157
5158         u8         reserved_at_40[0x40];
5159 };
5160
5161 struct mlx5_ifc_page_fault_resume_in_bits {
5162         u8         opcode[0x10];
5163         u8         reserved_at_10[0x10];
5164
5165         u8         reserved_at_20[0x10];
5166         u8         op_mod[0x10];
5167
5168         u8         error[0x1];
5169         u8         reserved_at_41[0x4];
5170         u8         page_fault_type[0x3];
5171         u8         wq_number[0x18];
5172
5173         u8         reserved_at_60[0x8];
5174         u8         token[0x18];
5175 };
5176
5177 struct mlx5_ifc_nop_out_bits {
5178         u8         status[0x8];
5179         u8         reserved_at_8[0x18];
5180
5181         u8         syndrome[0x20];
5182
5183         u8         reserved_at_40[0x40];
5184 };
5185
5186 struct mlx5_ifc_nop_in_bits {
5187         u8         opcode[0x10];
5188         u8         reserved_at_10[0x10];
5189
5190         u8         reserved_at_20[0x10];
5191         u8         op_mod[0x10];
5192
5193         u8         reserved_at_40[0x40];
5194 };
5195
5196 struct mlx5_ifc_modify_vport_state_out_bits {
5197         u8         status[0x8];
5198         u8         reserved_at_8[0x18];
5199
5200         u8         syndrome[0x20];
5201
5202         u8         reserved_at_40[0x40];
5203 };
5204
5205 struct mlx5_ifc_modify_vport_state_in_bits {
5206         u8         opcode[0x10];
5207         u8         reserved_at_10[0x10];
5208
5209         u8         reserved_at_20[0x10];
5210         u8         op_mod[0x10];
5211
5212         u8         other_vport[0x1];
5213         u8         reserved_at_41[0xf];
5214         u8         vport_number[0x10];
5215
5216         u8         reserved_at_60[0x18];
5217         u8         admin_state[0x4];
5218         u8         reserved_at_7c[0x4];
5219 };
5220
5221 struct mlx5_ifc_modify_tis_out_bits {
5222         u8         status[0x8];
5223         u8         reserved_at_8[0x18];
5224
5225         u8         syndrome[0x20];
5226
5227         u8         reserved_at_40[0x40];
5228 };
5229
5230 struct mlx5_ifc_modify_tis_bitmask_bits {
5231         u8         reserved_at_0[0x20];
5232
5233         u8         reserved_at_20[0x1d];
5234         u8         lag_tx_port_affinity[0x1];
5235         u8         strict_lag_tx_port_affinity[0x1];
5236         u8         prio[0x1];
5237 };
5238
5239 struct mlx5_ifc_modify_tis_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x8];
5247         u8         tisn[0x18];
5248
5249         u8         reserved_at_60[0x20];
5250
5251         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5252
5253         u8         reserved_at_c0[0x40];
5254
5255         struct mlx5_ifc_tisc_bits ctx;
5256 };
5257
5258 struct mlx5_ifc_modify_tir_bitmask_bits {
5259         u8         reserved_at_0[0x20];
5260
5261         u8         reserved_at_20[0x1b];
5262         u8         self_lb_en[0x1];
5263         u8         reserved_at_3c[0x1];
5264         u8         hash[0x1];
5265         u8         reserved_at_3e[0x1];
5266         u8         lro[0x1];
5267 };
5268
5269 struct mlx5_ifc_modify_tir_out_bits {
5270         u8         status[0x8];
5271         u8         reserved_at_8[0x18];
5272
5273         u8         syndrome[0x20];
5274
5275         u8         reserved_at_40[0x40];
5276 };
5277
5278 struct mlx5_ifc_modify_tir_in_bits {
5279         u8         opcode[0x10];
5280         u8         reserved_at_10[0x10];
5281
5282         u8         reserved_at_20[0x10];
5283         u8         op_mod[0x10];
5284
5285         u8         reserved_at_40[0x8];
5286         u8         tirn[0x18];
5287
5288         u8         reserved_at_60[0x20];
5289
5290         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5291
5292         u8         reserved_at_c0[0x40];
5293
5294         struct mlx5_ifc_tirc_bits ctx;
5295 };
5296
5297 struct mlx5_ifc_modify_sq_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_at_8[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_at_40[0x40];
5304 };
5305
5306 struct mlx5_ifc_modify_sq_in_bits {
5307         u8         opcode[0x10];
5308         u8         reserved_at_10[0x10];
5309
5310         u8         reserved_at_20[0x10];
5311         u8         op_mod[0x10];
5312
5313         u8         sq_state[0x4];
5314         u8         reserved_at_44[0x4];
5315         u8         sqn[0x18];
5316
5317         u8         reserved_at_60[0x20];
5318
5319         u8         modify_bitmask[0x40];
5320
5321         u8         reserved_at_c0[0x40];
5322
5323         struct mlx5_ifc_sqc_bits ctx;
5324 };
5325
5326 struct mlx5_ifc_modify_scheduling_element_out_bits {
5327         u8         status[0x8];
5328         u8         reserved_at_8[0x18];
5329
5330         u8         syndrome[0x20];
5331
5332         u8         reserved_at_40[0x1c0];
5333 };
5334
5335 enum {
5336         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5337         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5338 };
5339
5340 struct mlx5_ifc_modify_scheduling_element_in_bits {
5341         u8         opcode[0x10];
5342         u8         reserved_at_10[0x10];
5343
5344         u8         reserved_at_20[0x10];
5345         u8         op_mod[0x10];
5346
5347         u8         scheduling_hierarchy[0x8];
5348         u8         reserved_at_48[0x18];
5349
5350         u8         scheduling_element_id[0x20];
5351
5352         u8         reserved_at_80[0x20];
5353
5354         u8         modify_bitmask[0x20];
5355
5356         u8         reserved_at_c0[0x40];
5357
5358         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5359
5360         u8         reserved_at_300[0x100];
5361 };
5362
5363 struct mlx5_ifc_modify_rqt_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_at_8[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         reserved_at_40[0x40];
5370 };
5371
5372 struct mlx5_ifc_rqt_bitmask_bits {
5373         u8         reserved_at_0[0x20];
5374
5375         u8         reserved_at_20[0x1f];
5376         u8         rqn_list[0x1];
5377 };
5378
5379 struct mlx5_ifc_modify_rqt_in_bits {
5380         u8         opcode[0x10];
5381         u8         reserved_at_10[0x10];
5382
5383         u8         reserved_at_20[0x10];
5384         u8         op_mod[0x10];
5385
5386         u8         reserved_at_40[0x8];
5387         u8         rqtn[0x18];
5388
5389         u8         reserved_at_60[0x20];
5390
5391         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5392
5393         u8         reserved_at_c0[0x40];
5394
5395         struct mlx5_ifc_rqtc_bits ctx;
5396 };
5397
5398 struct mlx5_ifc_modify_rq_out_bits {
5399         u8         status[0x8];
5400         u8         reserved_at_8[0x18];
5401
5402         u8         syndrome[0x20];
5403
5404         u8         reserved_at_40[0x40];
5405 };
5406
5407 enum {
5408         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5409         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5410         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5411 };
5412
5413 struct mlx5_ifc_modify_rq_in_bits {
5414         u8         opcode[0x10];
5415         u8         reserved_at_10[0x10];
5416
5417         u8         reserved_at_20[0x10];
5418         u8         op_mod[0x10];
5419
5420         u8         rq_state[0x4];
5421         u8         reserved_at_44[0x4];
5422         u8         rqn[0x18];
5423
5424         u8         reserved_at_60[0x20];
5425
5426         u8         modify_bitmask[0x40];
5427
5428         u8         reserved_at_c0[0x40];
5429
5430         struct mlx5_ifc_rqc_bits ctx;
5431 };
5432
5433 struct mlx5_ifc_modify_rmp_out_bits {
5434         u8         status[0x8];
5435         u8         reserved_at_8[0x18];
5436
5437         u8         syndrome[0x20];
5438
5439         u8         reserved_at_40[0x40];
5440 };
5441
5442 struct mlx5_ifc_rmp_bitmask_bits {
5443         u8         reserved_at_0[0x20];
5444
5445         u8         reserved_at_20[0x1f];
5446         u8         lwm[0x1];
5447 };
5448
5449 struct mlx5_ifc_modify_rmp_in_bits {
5450         u8         opcode[0x10];
5451         u8         reserved_at_10[0x10];
5452
5453         u8         reserved_at_20[0x10];
5454         u8         op_mod[0x10];
5455
5456         u8         rmp_state[0x4];
5457         u8         reserved_at_44[0x4];
5458         u8         rmpn[0x18];
5459
5460         u8         reserved_at_60[0x20];
5461
5462         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5463
5464         u8         reserved_at_c0[0x40];
5465
5466         struct mlx5_ifc_rmpc_bits ctx;
5467 };
5468
5469 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5470         u8         status[0x8];
5471         u8         reserved_at_8[0x18];
5472
5473         u8         syndrome[0x20];
5474
5475         u8         reserved_at_40[0x40];
5476 };
5477
5478 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5479         u8         reserved_at_0[0x12];
5480         u8         affiliation[0x1];
5481         u8         reserved_at_e[0x1];
5482         u8         disable_uc_local_lb[0x1];
5483         u8         disable_mc_local_lb[0x1];
5484         u8         node_guid[0x1];
5485         u8         port_guid[0x1];
5486         u8         min_inline[0x1];
5487         u8         mtu[0x1];
5488         u8         change_event[0x1];
5489         u8         promisc[0x1];
5490         u8         permanent_address[0x1];
5491         u8         addresses_list[0x1];
5492         u8         roce_en[0x1];
5493         u8         reserved_at_1f[0x1];
5494 };
5495
5496 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5497         u8         opcode[0x10];
5498         u8         reserved_at_10[0x10];
5499
5500         u8         reserved_at_20[0x10];
5501         u8         op_mod[0x10];
5502
5503         u8         other_vport[0x1];
5504         u8         reserved_at_41[0xf];
5505         u8         vport_number[0x10];
5506
5507         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5508
5509         u8         reserved_at_80[0x780];
5510
5511         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5512 };
5513
5514 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5515         u8         status[0x8];
5516         u8         reserved_at_8[0x18];
5517
5518         u8         syndrome[0x20];
5519
5520         u8         reserved_at_40[0x40];
5521 };
5522
5523 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5524         u8         opcode[0x10];
5525         u8         reserved_at_10[0x10];
5526
5527         u8         reserved_at_20[0x10];
5528         u8         op_mod[0x10];
5529
5530         u8         other_vport[0x1];
5531         u8         reserved_at_41[0xb];
5532         u8         port_num[0x4];
5533         u8         vport_number[0x10];
5534
5535         u8         reserved_at_60[0x20];
5536
5537         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5538 };
5539
5540 struct mlx5_ifc_modify_cq_out_bits {
5541         u8         status[0x8];
5542         u8         reserved_at_8[0x18];
5543
5544         u8         syndrome[0x20];
5545
5546         u8         reserved_at_40[0x40];
5547 };
5548
5549 enum {
5550         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5551         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5552 };
5553
5554 struct mlx5_ifc_modify_cq_in_bits {
5555         u8         opcode[0x10];
5556         u8         reserved_at_10[0x10];
5557
5558         u8         reserved_at_20[0x10];
5559         u8         op_mod[0x10];
5560
5561         u8         reserved_at_40[0x8];
5562         u8         cqn[0x18];
5563
5564         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5565
5566         struct mlx5_ifc_cqc_bits cq_context;
5567
5568         u8         reserved_at_280[0x600];
5569
5570         u8         pas[0][0x40];
5571 };
5572
5573 struct mlx5_ifc_modify_cong_status_out_bits {
5574         u8         status[0x8];
5575         u8         reserved_at_8[0x18];
5576
5577         u8         syndrome[0x20];
5578
5579         u8         reserved_at_40[0x40];
5580 };
5581
5582 struct mlx5_ifc_modify_cong_status_in_bits {
5583         u8         opcode[0x10];
5584         u8         reserved_at_10[0x10];
5585
5586         u8         reserved_at_20[0x10];
5587         u8         op_mod[0x10];
5588
5589         u8         reserved_at_40[0x18];
5590         u8         priority[0x4];
5591         u8         cong_protocol[0x4];
5592
5593         u8         enable[0x1];
5594         u8         tag_enable[0x1];
5595         u8         reserved_at_62[0x1e];
5596 };
5597
5598 struct mlx5_ifc_modify_cong_params_out_bits {
5599         u8         status[0x8];
5600         u8         reserved_at_8[0x18];
5601
5602         u8         syndrome[0x20];
5603
5604         u8         reserved_at_40[0x40];
5605 };
5606
5607 struct mlx5_ifc_modify_cong_params_in_bits {
5608         u8         opcode[0x10];
5609         u8         reserved_at_10[0x10];
5610
5611         u8         reserved_at_20[0x10];
5612         u8         op_mod[0x10];
5613
5614         u8         reserved_at_40[0x1c];
5615         u8         cong_protocol[0x4];
5616
5617         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5618
5619         u8         reserved_at_80[0x80];
5620
5621         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5622 };
5623
5624 struct mlx5_ifc_manage_pages_out_bits {
5625         u8         status[0x8];
5626         u8         reserved_at_8[0x18];
5627
5628         u8         syndrome[0x20];
5629
5630         u8         output_num_entries[0x20];
5631
5632         u8         reserved_at_60[0x20];
5633
5634         u8         pas[0][0x40];
5635 };
5636
5637 enum {
5638         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5639         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5640         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5641 };
5642
5643 struct mlx5_ifc_manage_pages_in_bits {
5644         u8         opcode[0x10];
5645         u8         reserved_at_10[0x10];
5646
5647         u8         reserved_at_20[0x10];
5648         u8         op_mod[0x10];
5649
5650         u8         reserved_at_40[0x10];
5651         u8         function_id[0x10];
5652
5653         u8         input_num_entries[0x20];
5654
5655         u8         pas[0][0x40];
5656 };
5657
5658 struct mlx5_ifc_mad_ifc_out_bits {
5659         u8         status[0x8];
5660         u8         reserved_at_8[0x18];
5661
5662         u8         syndrome[0x20];
5663
5664         u8         reserved_at_40[0x40];
5665
5666         u8         response_mad_packet[256][0x8];
5667 };
5668
5669 struct mlx5_ifc_mad_ifc_in_bits {
5670         u8         opcode[0x10];
5671         u8         reserved_at_10[0x10];
5672
5673         u8         reserved_at_20[0x10];
5674         u8         op_mod[0x10];
5675
5676         u8         remote_lid[0x10];
5677         u8         reserved_at_50[0x8];
5678         u8         port[0x8];
5679
5680         u8         reserved_at_60[0x20];
5681
5682         u8         mad[256][0x8];
5683 };
5684
5685 struct mlx5_ifc_init_hca_out_bits {
5686         u8         status[0x8];
5687         u8         reserved_at_8[0x18];
5688
5689         u8         syndrome[0x20];
5690
5691         u8         reserved_at_40[0x40];
5692 };
5693
5694 struct mlx5_ifc_init_hca_in_bits {
5695         u8         opcode[0x10];
5696         u8         reserved_at_10[0x10];
5697
5698         u8         reserved_at_20[0x10];
5699         u8         op_mod[0x10];
5700
5701         u8         reserved_at_40[0x40];
5702         u8         sw_owner_id[4][0x20];
5703 };
5704
5705 struct mlx5_ifc_init2rtr_qp_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708
5709         u8         syndrome[0x20];
5710
5711         u8         reserved_at_40[0x40];
5712 };
5713
5714 struct mlx5_ifc_init2rtr_qp_in_bits {
5715         u8         opcode[0x10];
5716         u8         reserved_at_10[0x10];
5717
5718         u8         reserved_at_20[0x10];
5719         u8         op_mod[0x10];
5720
5721         u8         reserved_at_40[0x8];
5722         u8         qpn[0x18];
5723
5724         u8         reserved_at_60[0x20];
5725
5726         u8         opt_param_mask[0x20];
5727
5728         u8         reserved_at_a0[0x20];
5729
5730         struct mlx5_ifc_qpc_bits qpc;
5731
5732         u8         reserved_at_800[0x80];
5733 };
5734
5735 struct mlx5_ifc_init2init_qp_out_bits {
5736         u8         status[0x8];
5737         u8         reserved_at_8[0x18];
5738
5739         u8         syndrome[0x20];
5740
5741         u8         reserved_at_40[0x40];
5742 };
5743
5744 struct mlx5_ifc_init2init_qp_in_bits {
5745         u8         opcode[0x10];
5746         u8         reserved_at_10[0x10];
5747
5748         u8         reserved_at_20[0x10];
5749         u8         op_mod[0x10];
5750
5751         u8         reserved_at_40[0x8];
5752         u8         qpn[0x18];
5753
5754         u8         reserved_at_60[0x20];
5755
5756         u8         opt_param_mask[0x20];
5757
5758         u8         reserved_at_a0[0x20];
5759
5760         struct mlx5_ifc_qpc_bits qpc;
5761
5762         u8         reserved_at_800[0x80];
5763 };
5764
5765 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5766         u8         status[0x8];
5767         u8         reserved_at_8[0x18];
5768
5769         u8         syndrome[0x20];
5770
5771         u8         reserved_at_40[0x40];
5772
5773         u8         packet_headers_log[128][0x8];
5774
5775         u8         packet_syndrome[64][0x8];
5776 };
5777
5778 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5779         u8         opcode[0x10];
5780         u8         reserved_at_10[0x10];
5781
5782         u8         reserved_at_20[0x10];
5783         u8         op_mod[0x10];
5784
5785         u8         reserved_at_40[0x40];
5786 };
5787
5788 struct mlx5_ifc_gen_eqe_in_bits {
5789         u8         opcode[0x10];
5790         u8         reserved_at_10[0x10];
5791
5792         u8         reserved_at_20[0x10];
5793         u8         op_mod[0x10];
5794
5795         u8         reserved_at_40[0x18];
5796         u8         eq_number[0x8];
5797
5798         u8         reserved_at_60[0x20];
5799
5800         u8         eqe[64][0x8];
5801 };
5802
5803 struct mlx5_ifc_gen_eq_out_bits {
5804         u8         status[0x8];
5805         u8         reserved_at_8[0x18];
5806
5807         u8         syndrome[0x20];
5808
5809         u8         reserved_at_40[0x40];
5810 };
5811
5812 struct mlx5_ifc_enable_hca_out_bits {
5813         u8         status[0x8];
5814         u8         reserved_at_8[0x18];
5815
5816         u8         syndrome[0x20];
5817
5818         u8         reserved_at_40[0x20];
5819 };
5820
5821 struct mlx5_ifc_enable_hca_in_bits {
5822         u8         opcode[0x10];
5823         u8         reserved_at_10[0x10];
5824
5825         u8         reserved_at_20[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         reserved_at_40[0x10];
5829         u8         function_id[0x10];
5830
5831         u8         reserved_at_60[0x20];
5832 };
5833
5834 struct mlx5_ifc_drain_dct_out_bits {
5835         u8         status[0x8];
5836         u8         reserved_at_8[0x18];
5837
5838         u8         syndrome[0x20];
5839
5840         u8         reserved_at_40[0x40];
5841 };
5842
5843 struct mlx5_ifc_drain_dct_in_bits {
5844         u8         opcode[0x10];
5845         u8         reserved_at_10[0x10];
5846
5847         u8         reserved_at_20[0x10];
5848         u8         op_mod[0x10];
5849
5850         u8         reserved_at_40[0x8];
5851         u8         dctn[0x18];
5852
5853         u8         reserved_at_60[0x20];
5854 };
5855
5856 struct mlx5_ifc_disable_hca_out_bits {
5857         u8         status[0x8];
5858         u8         reserved_at_8[0x18];
5859
5860         u8         syndrome[0x20];
5861
5862         u8         reserved_at_40[0x20];
5863 };
5864
5865 struct mlx5_ifc_disable_hca_in_bits {
5866         u8         opcode[0x10];
5867         u8         reserved_at_10[0x10];
5868
5869         u8         reserved_at_20[0x10];
5870         u8         op_mod[0x10];
5871
5872         u8         reserved_at_40[0x10];
5873         u8         function_id[0x10];
5874
5875         u8         reserved_at_60[0x20];
5876 };
5877
5878 struct mlx5_ifc_detach_from_mcg_out_bits {
5879         u8         status[0x8];
5880         u8         reserved_at_8[0x18];
5881
5882         u8         syndrome[0x20];
5883
5884         u8         reserved_at_40[0x40];
5885 };
5886
5887 struct mlx5_ifc_detach_from_mcg_in_bits {
5888         u8         opcode[0x10];
5889         u8         reserved_at_10[0x10];
5890
5891         u8         reserved_at_20[0x10];
5892         u8         op_mod[0x10];
5893
5894         u8         reserved_at_40[0x8];
5895         u8         qpn[0x18];
5896
5897         u8         reserved_at_60[0x20];
5898
5899         u8         multicast_gid[16][0x8];
5900 };
5901
5902 struct mlx5_ifc_destroy_xrq_out_bits {
5903         u8         status[0x8];
5904         u8         reserved_at_8[0x18];
5905
5906         u8         syndrome[0x20];
5907
5908         u8         reserved_at_40[0x40];
5909 };
5910
5911 struct mlx5_ifc_destroy_xrq_in_bits {
5912         u8         opcode[0x10];
5913         u8         reserved_at_10[0x10];
5914
5915         u8         reserved_at_20[0x10];
5916         u8         op_mod[0x10];
5917
5918         u8         reserved_at_40[0x8];
5919         u8         xrqn[0x18];
5920
5921         u8         reserved_at_60[0x20];
5922 };
5923
5924 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5925         u8         status[0x8];
5926         u8         reserved_at_8[0x18];
5927
5928         u8         syndrome[0x20];
5929
5930         u8         reserved_at_40[0x40];
5931 };
5932
5933 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x8];
5941         u8         xrc_srqn[0x18];
5942
5943         u8         reserved_at_60[0x20];
5944 };
5945
5946 struct mlx5_ifc_destroy_tis_out_bits {
5947         u8         status[0x8];
5948         u8         reserved_at_8[0x18];
5949
5950         u8         syndrome[0x20];
5951
5952         u8         reserved_at_40[0x40];
5953 };
5954
5955 struct mlx5_ifc_destroy_tis_in_bits {
5956         u8         opcode[0x10];
5957         u8         reserved_at_10[0x10];
5958
5959         u8         reserved_at_20[0x10];
5960         u8         op_mod[0x10];
5961
5962         u8         reserved_at_40[0x8];
5963         u8         tisn[0x18];
5964
5965         u8         reserved_at_60[0x20];
5966 };
5967
5968 struct mlx5_ifc_destroy_tir_out_bits {
5969         u8         status[0x8];
5970         u8         reserved_at_8[0x18];
5971
5972         u8         syndrome[0x20];
5973
5974         u8         reserved_at_40[0x40];
5975 };
5976
5977 struct mlx5_ifc_destroy_tir_in_bits {
5978         u8         opcode[0x10];
5979         u8         reserved_at_10[0x10];
5980
5981         u8         reserved_at_20[0x10];
5982         u8         op_mod[0x10];
5983
5984         u8         reserved_at_40[0x8];
5985         u8         tirn[0x18];
5986
5987         u8         reserved_at_60[0x20];
5988 };
5989
5990 struct mlx5_ifc_destroy_srq_out_bits {
5991         u8         status[0x8];
5992         u8         reserved_at_8[0x18];
5993
5994         u8         syndrome[0x20];
5995
5996         u8         reserved_at_40[0x40];
5997 };
5998
5999 struct mlx5_ifc_destroy_srq_in_bits {
6000         u8         opcode[0x10];
6001         u8         reserved_at_10[0x10];
6002
6003         u8         reserved_at_20[0x10];
6004         u8         op_mod[0x10];
6005
6006         u8         reserved_at_40[0x8];
6007         u8         srqn[0x18];
6008
6009         u8         reserved_at_60[0x20];
6010 };
6011
6012 struct mlx5_ifc_destroy_sq_out_bits {
6013         u8         status[0x8];
6014         u8         reserved_at_8[0x18];
6015
6016         u8         syndrome[0x20];
6017
6018         u8         reserved_at_40[0x40];
6019 };
6020
6021 struct mlx5_ifc_destroy_sq_in_bits {
6022         u8         opcode[0x10];
6023         u8         reserved_at_10[0x10];
6024
6025         u8         reserved_at_20[0x10];
6026         u8         op_mod[0x10];
6027
6028         u8         reserved_at_40[0x8];
6029         u8         sqn[0x18];
6030
6031         u8         reserved_at_60[0x20];
6032 };
6033
6034 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6035         u8         status[0x8];
6036         u8         reserved_at_8[0x18];
6037
6038         u8         syndrome[0x20];
6039
6040         u8         reserved_at_40[0x1c0];
6041 };
6042
6043 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6044         u8         opcode[0x10];
6045         u8         reserved_at_10[0x10];
6046
6047         u8         reserved_at_20[0x10];
6048         u8         op_mod[0x10];
6049
6050         u8         scheduling_hierarchy[0x8];
6051         u8         reserved_at_48[0x18];
6052
6053         u8         scheduling_element_id[0x20];
6054
6055         u8         reserved_at_80[0x180];
6056 };
6057
6058 struct mlx5_ifc_destroy_rqt_out_bits {
6059         u8         status[0x8];
6060         u8         reserved_at_8[0x18];
6061
6062         u8         syndrome[0x20];
6063
6064         u8         reserved_at_40[0x40];
6065 };
6066
6067 struct mlx5_ifc_destroy_rqt_in_bits {
6068         u8         opcode[0x10];
6069         u8         reserved_at_10[0x10];
6070
6071         u8         reserved_at_20[0x10];
6072         u8         op_mod[0x10];
6073
6074         u8         reserved_at_40[0x8];
6075         u8         rqtn[0x18];
6076
6077         u8         reserved_at_60[0x20];
6078 };
6079
6080 struct mlx5_ifc_destroy_rq_out_bits {
6081         u8         status[0x8];
6082         u8         reserved_at_8[0x18];
6083
6084         u8         syndrome[0x20];
6085
6086         u8         reserved_at_40[0x40];
6087 };
6088
6089 struct mlx5_ifc_destroy_rq_in_bits {
6090         u8         opcode[0x10];
6091         u8         reserved_at_10[0x10];
6092
6093         u8         reserved_at_20[0x10];
6094         u8         op_mod[0x10];
6095
6096         u8         reserved_at_40[0x8];
6097         u8         rqn[0x18];
6098
6099         u8         reserved_at_60[0x20];
6100 };
6101
6102 struct mlx5_ifc_set_delay_drop_params_in_bits {
6103         u8         opcode[0x10];
6104         u8         reserved_at_10[0x10];
6105
6106         u8         reserved_at_20[0x10];
6107         u8         op_mod[0x10];
6108
6109         u8         reserved_at_40[0x20];
6110
6111         u8         reserved_at_60[0x10];
6112         u8         delay_drop_timeout[0x10];
6113 };
6114
6115 struct mlx5_ifc_set_delay_drop_params_out_bits {
6116         u8         status[0x8];
6117         u8         reserved_at_8[0x18];
6118
6119         u8         syndrome[0x20];
6120
6121         u8         reserved_at_40[0x40];
6122 };
6123
6124 struct mlx5_ifc_destroy_rmp_out_bits {
6125         u8         status[0x8];
6126         u8         reserved_at_8[0x18];
6127
6128         u8         syndrome[0x20];
6129
6130         u8         reserved_at_40[0x40];
6131 };
6132
6133 struct mlx5_ifc_destroy_rmp_in_bits {
6134         u8         opcode[0x10];
6135         u8         reserved_at_10[0x10];
6136
6137         u8         reserved_at_20[0x10];
6138         u8         op_mod[0x10];
6139
6140         u8         reserved_at_40[0x8];
6141         u8         rmpn[0x18];
6142
6143         u8         reserved_at_60[0x20];
6144 };
6145
6146 struct mlx5_ifc_destroy_qp_out_bits {
6147         u8         status[0x8];
6148         u8         reserved_at_8[0x18];
6149
6150         u8         syndrome[0x20];
6151
6152         u8         reserved_at_40[0x40];
6153 };
6154
6155 struct mlx5_ifc_destroy_qp_in_bits {
6156         u8         opcode[0x10];
6157         u8         reserved_at_10[0x10];
6158
6159         u8         reserved_at_20[0x10];
6160         u8         op_mod[0x10];
6161
6162         u8         reserved_at_40[0x8];
6163         u8         qpn[0x18];
6164
6165         u8         reserved_at_60[0x20];
6166 };
6167
6168 struct mlx5_ifc_destroy_psv_out_bits {
6169         u8         status[0x8];
6170         u8         reserved_at_8[0x18];
6171
6172         u8         syndrome[0x20];
6173
6174         u8         reserved_at_40[0x40];
6175 };
6176
6177 struct mlx5_ifc_destroy_psv_in_bits {
6178         u8         opcode[0x10];
6179         u8         reserved_at_10[0x10];
6180
6181         u8         reserved_at_20[0x10];
6182         u8         op_mod[0x10];
6183
6184         u8         reserved_at_40[0x8];
6185         u8         psvn[0x18];
6186
6187         u8         reserved_at_60[0x20];
6188 };
6189
6190 struct mlx5_ifc_destroy_mkey_out_bits {
6191         u8         status[0x8];
6192         u8         reserved_at_8[0x18];
6193
6194         u8         syndrome[0x20];
6195
6196         u8         reserved_at_40[0x40];
6197 };
6198
6199 struct mlx5_ifc_destroy_mkey_in_bits {
6200         u8         opcode[0x10];
6201         u8         reserved_at_10[0x10];
6202
6203         u8         reserved_at_20[0x10];
6204         u8         op_mod[0x10];
6205
6206         u8         reserved_at_40[0x8];
6207         u8         mkey_index[0x18];
6208
6209         u8         reserved_at_60[0x20];
6210 };
6211
6212 struct mlx5_ifc_destroy_flow_table_out_bits {
6213         u8         status[0x8];
6214         u8         reserved_at_8[0x18];
6215
6216         u8         syndrome[0x20];
6217
6218         u8         reserved_at_40[0x40];
6219 };
6220
6221 struct mlx5_ifc_destroy_flow_table_in_bits {
6222         u8         opcode[0x10];
6223         u8         reserved_at_10[0x10];
6224
6225         u8         reserved_at_20[0x10];
6226         u8         op_mod[0x10];
6227
6228         u8         other_vport[0x1];
6229         u8         reserved_at_41[0xf];
6230         u8         vport_number[0x10];
6231
6232         u8         reserved_at_60[0x20];
6233
6234         u8         table_type[0x8];
6235         u8         reserved_at_88[0x18];
6236
6237         u8         reserved_at_a0[0x8];
6238         u8         table_id[0x18];
6239
6240         u8         reserved_at_c0[0x140];
6241 };
6242
6243 struct mlx5_ifc_destroy_flow_group_out_bits {
6244         u8         status[0x8];
6245         u8         reserved_at_8[0x18];
6246
6247         u8         syndrome[0x20];
6248
6249         u8         reserved_at_40[0x40];
6250 };
6251
6252 struct mlx5_ifc_destroy_flow_group_in_bits {
6253         u8         opcode[0x10];
6254         u8         reserved_at_10[0x10];
6255
6256         u8         reserved_at_20[0x10];
6257         u8         op_mod[0x10];
6258
6259         u8         other_vport[0x1];
6260         u8         reserved_at_41[0xf];
6261         u8         vport_number[0x10];
6262
6263         u8         reserved_at_60[0x20];
6264
6265         u8         table_type[0x8];
6266         u8         reserved_at_88[0x18];
6267
6268         u8         reserved_at_a0[0x8];
6269         u8         table_id[0x18];
6270
6271         u8         group_id[0x20];
6272
6273         u8         reserved_at_e0[0x120];
6274 };
6275
6276 struct mlx5_ifc_destroy_eq_out_bits {
6277         u8         status[0x8];
6278         u8         reserved_at_8[0x18];
6279
6280         u8         syndrome[0x20];
6281
6282         u8         reserved_at_40[0x40];
6283 };
6284
6285 struct mlx5_ifc_destroy_eq_in_bits {
6286         u8         opcode[0x10];
6287         u8         reserved_at_10[0x10];
6288
6289         u8         reserved_at_20[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         reserved_at_40[0x18];
6293         u8         eq_number[0x8];
6294
6295         u8         reserved_at_60[0x20];
6296 };
6297
6298 struct mlx5_ifc_destroy_dct_out_bits {
6299         u8         status[0x8];
6300         u8         reserved_at_8[0x18];
6301
6302         u8         syndrome[0x20];
6303
6304         u8         reserved_at_40[0x40];
6305 };
6306
6307 struct mlx5_ifc_destroy_dct_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_at_10[0x10];
6310
6311         u8         reserved_at_20[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         reserved_at_40[0x8];
6315         u8         dctn[0x18];
6316
6317         u8         reserved_at_60[0x20];
6318 };
6319
6320 struct mlx5_ifc_destroy_cq_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_at_8[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_at_40[0x40];
6327 };
6328
6329 struct mlx5_ifc_destroy_cq_in_bits {
6330         u8         opcode[0x10];
6331         u8         reserved_at_10[0x10];
6332
6333         u8         reserved_at_20[0x10];
6334         u8         op_mod[0x10];
6335
6336         u8         reserved_at_40[0x8];
6337         u8         cqn[0x18];
6338
6339         u8         reserved_at_60[0x20];
6340 };
6341
6342 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6343         u8         status[0x8];
6344         u8         reserved_at_8[0x18];
6345
6346         u8         syndrome[0x20];
6347
6348         u8         reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6352         u8         opcode[0x10];
6353         u8         reserved_at_10[0x10];
6354
6355         u8         reserved_at_20[0x10];
6356         u8         op_mod[0x10];
6357
6358         u8         reserved_at_40[0x20];
6359
6360         u8         reserved_at_60[0x10];
6361         u8         vxlan_udp_port[0x10];
6362 };
6363
6364 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6365         u8         status[0x8];
6366         u8         reserved_at_8[0x18];
6367
6368         u8         syndrome[0x20];
6369
6370         u8         reserved_at_40[0x40];
6371 };
6372
6373 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6374         u8         opcode[0x10];
6375         u8         reserved_at_10[0x10];
6376
6377         u8         reserved_at_20[0x10];
6378         u8         op_mod[0x10];
6379
6380         u8         reserved_at_40[0x60];
6381
6382         u8         reserved_at_a0[0x8];
6383         u8         table_index[0x18];
6384
6385         u8         reserved_at_c0[0x140];
6386 };
6387
6388 struct mlx5_ifc_delete_fte_out_bits {
6389         u8         status[0x8];
6390         u8         reserved_at_8[0x18];
6391
6392         u8         syndrome[0x20];
6393
6394         u8         reserved_at_40[0x40];
6395 };
6396
6397 struct mlx5_ifc_delete_fte_in_bits {
6398         u8         opcode[0x10];
6399         u8         reserved_at_10[0x10];
6400
6401         u8         reserved_at_20[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         other_vport[0x1];
6405         u8         reserved_at_41[0xf];
6406         u8         vport_number[0x10];
6407
6408         u8         reserved_at_60[0x20];
6409
6410         u8         table_type[0x8];
6411         u8         reserved_at_88[0x18];
6412
6413         u8         reserved_at_a0[0x8];
6414         u8         table_id[0x18];
6415
6416         u8         reserved_at_c0[0x40];
6417
6418         u8         flow_index[0x20];
6419
6420         u8         reserved_at_120[0xe0];
6421 };
6422
6423 struct mlx5_ifc_dealloc_xrcd_out_bits {
6424         u8         status[0x8];
6425         u8         reserved_at_8[0x18];
6426
6427         u8         syndrome[0x20];
6428
6429         u8         reserved_at_40[0x40];
6430 };
6431
6432 struct mlx5_ifc_dealloc_xrcd_in_bits {
6433         u8         opcode[0x10];
6434         u8         reserved_at_10[0x10];
6435
6436         u8         reserved_at_20[0x10];
6437         u8         op_mod[0x10];
6438
6439         u8         reserved_at_40[0x8];
6440         u8         xrcd[0x18];
6441
6442         u8         reserved_at_60[0x20];
6443 };
6444
6445 struct mlx5_ifc_dealloc_uar_out_bits {
6446         u8         status[0x8];
6447         u8         reserved_at_8[0x18];
6448
6449         u8         syndrome[0x20];
6450
6451         u8         reserved_at_40[0x40];
6452 };
6453
6454 struct mlx5_ifc_dealloc_uar_in_bits {
6455         u8         opcode[0x10];
6456         u8         reserved_at_10[0x10];
6457
6458         u8         reserved_at_20[0x10];
6459         u8         op_mod[0x10];
6460
6461         u8         reserved_at_40[0x8];
6462         u8         uar[0x18];
6463
6464         u8         reserved_at_60[0x20];
6465 };
6466
6467 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6468         u8         status[0x8];
6469         u8         reserved_at_8[0x18];
6470
6471         u8         syndrome[0x20];
6472
6473         u8         reserved_at_40[0x40];
6474 };
6475
6476 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6477         u8         opcode[0x10];
6478         u8         reserved_at_10[0x10];
6479
6480         u8         reserved_at_20[0x10];
6481         u8         op_mod[0x10];
6482
6483         u8         reserved_at_40[0x8];
6484         u8         transport_domain[0x18];
6485
6486         u8         reserved_at_60[0x20];
6487 };
6488
6489 struct mlx5_ifc_dealloc_q_counter_out_bits {
6490         u8         status[0x8];
6491         u8         reserved_at_8[0x18];
6492
6493         u8         syndrome[0x20];
6494
6495         u8         reserved_at_40[0x40];
6496 };
6497
6498 struct mlx5_ifc_dealloc_q_counter_in_bits {
6499         u8         opcode[0x10];
6500         u8         reserved_at_10[0x10];
6501
6502         u8         reserved_at_20[0x10];
6503         u8         op_mod[0x10];
6504
6505         u8         reserved_at_40[0x18];
6506         u8         counter_set_id[0x8];
6507
6508         u8         reserved_at_60[0x20];
6509 };
6510
6511 struct mlx5_ifc_dealloc_pd_out_bits {
6512         u8         status[0x8];
6513         u8         reserved_at_8[0x18];
6514
6515         u8         syndrome[0x20];
6516
6517         u8         reserved_at_40[0x40];
6518 };
6519
6520 struct mlx5_ifc_dealloc_pd_in_bits {
6521         u8         opcode[0x10];
6522         u8         reserved_at_10[0x10];
6523
6524         u8         reserved_at_20[0x10];
6525         u8         op_mod[0x10];
6526
6527         u8         reserved_at_40[0x8];
6528         u8         pd[0x18];
6529
6530         u8         reserved_at_60[0x20];
6531 };
6532
6533 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6534         u8         status[0x8];
6535         u8         reserved_at_8[0x18];
6536
6537         u8         syndrome[0x20];
6538
6539         u8         reserved_at_40[0x40];
6540 };
6541
6542 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6543         u8         opcode[0x10];
6544         u8         reserved_at_10[0x10];
6545
6546         u8         reserved_at_20[0x10];
6547         u8         op_mod[0x10];
6548
6549         u8         flow_counter_id[0x20];
6550
6551         u8         reserved_at_60[0x20];
6552 };
6553
6554 struct mlx5_ifc_create_xrq_out_bits {
6555         u8         status[0x8];
6556         u8         reserved_at_8[0x18];
6557
6558         u8         syndrome[0x20];
6559
6560         u8         reserved_at_40[0x8];
6561         u8         xrqn[0x18];
6562
6563         u8         reserved_at_60[0x20];
6564 };
6565
6566 struct mlx5_ifc_create_xrq_in_bits {
6567         u8         opcode[0x10];
6568         u8         reserved_at_10[0x10];
6569
6570         u8         reserved_at_20[0x10];
6571         u8         op_mod[0x10];
6572
6573         u8         reserved_at_40[0x40];
6574
6575         struct mlx5_ifc_xrqc_bits xrq_context;
6576 };
6577
6578 struct mlx5_ifc_create_xrc_srq_out_bits {
6579         u8         status[0x8];
6580         u8         reserved_at_8[0x18];
6581
6582         u8         syndrome[0x20];
6583
6584         u8         reserved_at_40[0x8];
6585         u8         xrc_srqn[0x18];
6586
6587         u8         reserved_at_60[0x20];
6588 };
6589
6590 struct mlx5_ifc_create_xrc_srq_in_bits {
6591         u8         opcode[0x10];
6592         u8         reserved_at_10[0x10];
6593
6594         u8         reserved_at_20[0x10];
6595         u8         op_mod[0x10];
6596
6597         u8         reserved_at_40[0x40];
6598
6599         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6600
6601         u8         reserved_at_280[0x600];
6602
6603         u8         pas[0][0x40];
6604 };
6605
6606 struct mlx5_ifc_create_tis_out_bits {
6607         u8         status[0x8];
6608         u8         reserved_at_8[0x18];
6609
6610         u8         syndrome[0x20];
6611
6612         u8         reserved_at_40[0x8];
6613         u8         tisn[0x18];
6614
6615         u8         reserved_at_60[0x20];
6616 };
6617
6618 struct mlx5_ifc_create_tis_in_bits {
6619         u8         opcode[0x10];
6620         u8         reserved_at_10[0x10];
6621
6622         u8         reserved_at_20[0x10];
6623         u8         op_mod[0x10];
6624
6625         u8         reserved_at_40[0xc0];
6626
6627         struct mlx5_ifc_tisc_bits ctx;
6628 };
6629
6630 struct mlx5_ifc_create_tir_out_bits {
6631         u8         status[0x8];
6632         u8         reserved_at_8[0x18];
6633
6634         u8         syndrome[0x20];
6635
6636         u8         reserved_at_40[0x8];
6637         u8         tirn[0x18];
6638
6639         u8         reserved_at_60[0x20];
6640 };
6641
6642 struct mlx5_ifc_create_tir_in_bits {
6643         u8         opcode[0x10];
6644         u8         reserved_at_10[0x10];
6645
6646         u8         reserved_at_20[0x10];
6647         u8         op_mod[0x10];
6648
6649         u8         reserved_at_40[0xc0];
6650
6651         struct mlx5_ifc_tirc_bits ctx;
6652 };
6653
6654 struct mlx5_ifc_create_srq_out_bits {
6655         u8         status[0x8];
6656         u8         reserved_at_8[0x18];
6657
6658         u8         syndrome[0x20];
6659
6660         u8         reserved_at_40[0x8];
6661         u8         srqn[0x18];
6662
6663         u8         reserved_at_60[0x20];
6664 };
6665
6666 struct mlx5_ifc_create_srq_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         reserved_at_40[0x40];
6674
6675         struct mlx5_ifc_srqc_bits srq_context_entry;
6676
6677         u8         reserved_at_280[0x600];
6678
6679         u8         pas[0][0x40];
6680 };
6681
6682 struct mlx5_ifc_create_sq_out_bits {
6683         u8         status[0x8];
6684         u8         reserved_at_8[0x18];
6685
6686         u8         syndrome[0x20];
6687
6688         u8         reserved_at_40[0x8];
6689         u8         sqn[0x18];
6690
6691         u8         reserved_at_60[0x20];
6692 };
6693
6694 struct mlx5_ifc_create_sq_in_bits {
6695         u8         opcode[0x10];
6696         u8         reserved_at_10[0x10];
6697
6698         u8         reserved_at_20[0x10];
6699         u8         op_mod[0x10];
6700
6701         u8         reserved_at_40[0xc0];
6702
6703         struct mlx5_ifc_sqc_bits ctx;
6704 };
6705
6706 struct mlx5_ifc_create_scheduling_element_out_bits {
6707         u8         status[0x8];
6708         u8         reserved_at_8[0x18];
6709
6710         u8         syndrome[0x20];
6711
6712         u8         reserved_at_40[0x40];
6713
6714         u8         scheduling_element_id[0x20];
6715
6716         u8         reserved_at_a0[0x160];
6717 };
6718
6719 struct mlx5_ifc_create_scheduling_element_in_bits {
6720         u8         opcode[0x10];
6721         u8         reserved_at_10[0x10];
6722
6723         u8         reserved_at_20[0x10];
6724         u8         op_mod[0x10];
6725
6726         u8         scheduling_hierarchy[0x8];
6727         u8         reserved_at_48[0x18];
6728
6729         u8         reserved_at_60[0xa0];
6730
6731         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6732
6733         u8         reserved_at_300[0x100];
6734 };
6735
6736 struct mlx5_ifc_create_rqt_out_bits {
6737         u8         status[0x8];
6738         u8         reserved_at_8[0x18];
6739
6740         u8         syndrome[0x20];
6741
6742         u8         reserved_at_40[0x8];
6743         u8         rqtn[0x18];
6744
6745         u8         reserved_at_60[0x20];
6746 };
6747
6748 struct mlx5_ifc_create_rqt_in_bits {
6749         u8         opcode[0x10];
6750         u8         reserved_at_10[0x10];
6751
6752         u8         reserved_at_20[0x10];
6753         u8         op_mod[0x10];
6754
6755         u8         reserved_at_40[0xc0];
6756
6757         struct mlx5_ifc_rqtc_bits rqt_context;
6758 };
6759
6760 struct mlx5_ifc_create_rq_out_bits {
6761         u8         status[0x8];
6762         u8         reserved_at_8[0x18];
6763
6764         u8         syndrome[0x20];
6765
6766         u8         reserved_at_40[0x8];
6767         u8         rqn[0x18];
6768
6769         u8         reserved_at_60[0x20];
6770 };
6771
6772 struct mlx5_ifc_create_rq_in_bits {
6773         u8         opcode[0x10];
6774         u8         reserved_at_10[0x10];
6775
6776         u8         reserved_at_20[0x10];
6777         u8         op_mod[0x10];
6778
6779         u8         reserved_at_40[0xc0];
6780
6781         struct mlx5_ifc_rqc_bits ctx;
6782 };
6783
6784 struct mlx5_ifc_create_rmp_out_bits {
6785         u8         status[0x8];
6786         u8         reserved_at_8[0x18];
6787
6788         u8         syndrome[0x20];
6789
6790         u8         reserved_at_40[0x8];
6791         u8         rmpn[0x18];
6792
6793         u8         reserved_at_60[0x20];
6794 };
6795
6796 struct mlx5_ifc_create_rmp_in_bits {
6797         u8         opcode[0x10];
6798         u8         reserved_at_10[0x10];
6799
6800         u8         reserved_at_20[0x10];
6801         u8         op_mod[0x10];
6802
6803         u8         reserved_at_40[0xc0];
6804
6805         struct mlx5_ifc_rmpc_bits ctx;
6806 };
6807
6808 struct mlx5_ifc_create_qp_out_bits {
6809         u8         status[0x8];
6810         u8         reserved_at_8[0x18];
6811
6812         u8         syndrome[0x20];
6813
6814         u8         reserved_at_40[0x8];
6815         u8         qpn[0x18];
6816
6817         u8         reserved_at_60[0x20];
6818 };
6819
6820 struct mlx5_ifc_create_qp_in_bits {
6821         u8         opcode[0x10];
6822         u8         reserved_at_10[0x10];
6823
6824         u8         reserved_at_20[0x10];
6825         u8         op_mod[0x10];
6826
6827         u8         reserved_at_40[0x40];
6828
6829         u8         opt_param_mask[0x20];
6830
6831         u8         reserved_at_a0[0x20];
6832
6833         struct mlx5_ifc_qpc_bits qpc;
6834
6835         u8         reserved_at_800[0x80];
6836
6837         u8         pas[0][0x40];
6838 };
6839
6840 struct mlx5_ifc_create_psv_out_bits {
6841         u8         status[0x8];
6842         u8         reserved_at_8[0x18];
6843
6844         u8         syndrome[0x20];
6845
6846         u8         reserved_at_40[0x40];
6847
6848         u8         reserved_at_80[0x8];
6849         u8         psv0_index[0x18];
6850
6851         u8         reserved_at_a0[0x8];
6852         u8         psv1_index[0x18];
6853
6854         u8         reserved_at_c0[0x8];
6855         u8         psv2_index[0x18];
6856
6857         u8         reserved_at_e0[0x8];
6858         u8         psv3_index[0x18];
6859 };
6860
6861 struct mlx5_ifc_create_psv_in_bits {
6862         u8         opcode[0x10];
6863         u8         reserved_at_10[0x10];
6864
6865         u8         reserved_at_20[0x10];
6866         u8         op_mod[0x10];
6867
6868         u8         num_psv[0x4];
6869         u8         reserved_at_44[0x4];
6870         u8         pd[0x18];
6871
6872         u8         reserved_at_60[0x20];
6873 };
6874
6875 struct mlx5_ifc_create_mkey_out_bits {
6876         u8         status[0x8];
6877         u8         reserved_at_8[0x18];
6878
6879         u8         syndrome[0x20];
6880
6881         u8         reserved_at_40[0x8];
6882         u8         mkey_index[0x18];
6883
6884         u8         reserved_at_60[0x20];
6885 };
6886
6887 struct mlx5_ifc_create_mkey_in_bits {
6888         u8         opcode[0x10];
6889         u8         reserved_at_10[0x10];
6890
6891         u8         reserved_at_20[0x10];
6892         u8         op_mod[0x10];
6893
6894         u8         reserved_at_40[0x20];
6895
6896         u8         pg_access[0x1];
6897         u8         reserved_at_61[0x1f];
6898
6899         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6900
6901         u8         reserved_at_280[0x80];
6902
6903         u8         translations_octword_actual_size[0x20];
6904
6905         u8         reserved_at_320[0x560];
6906
6907         u8         klm_pas_mtt[0][0x20];
6908 };
6909
6910 struct mlx5_ifc_create_flow_table_out_bits {
6911         u8         status[0x8];
6912         u8         reserved_at_8[0x18];
6913
6914         u8         syndrome[0x20];
6915
6916         u8         reserved_at_40[0x8];
6917         u8         table_id[0x18];
6918
6919         u8         reserved_at_60[0x20];
6920 };
6921
6922 struct mlx5_ifc_flow_table_context_bits {
6923         u8         encap_en[0x1];
6924         u8         decap_en[0x1];
6925         u8         reserved_at_2[0x2];
6926         u8         table_miss_action[0x4];
6927         u8         level[0x8];
6928         u8         reserved_at_10[0x8];
6929         u8         log_size[0x8];
6930
6931         u8         reserved_at_20[0x8];
6932         u8         table_miss_id[0x18];
6933
6934         u8         reserved_at_40[0x8];
6935         u8         lag_master_next_table_id[0x18];
6936
6937         u8         reserved_at_60[0xe0];
6938 };
6939
6940 struct mlx5_ifc_create_flow_table_in_bits {
6941         u8         opcode[0x10];
6942         u8         reserved_at_10[0x10];
6943
6944         u8         reserved_at_20[0x10];
6945         u8         op_mod[0x10];
6946
6947         u8         other_vport[0x1];
6948         u8         reserved_at_41[0xf];
6949         u8         vport_number[0x10];
6950
6951         u8         reserved_at_60[0x20];
6952
6953         u8         table_type[0x8];
6954         u8         reserved_at_88[0x18];
6955
6956         u8         reserved_at_a0[0x20];
6957
6958         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6959 };
6960
6961 struct mlx5_ifc_create_flow_group_out_bits {
6962         u8         status[0x8];
6963         u8         reserved_at_8[0x18];
6964
6965         u8         syndrome[0x20];
6966
6967         u8         reserved_at_40[0x8];
6968         u8         group_id[0x18];
6969
6970         u8         reserved_at_60[0x20];
6971 };
6972
6973 enum {
6974         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6975         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6976         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6977 };
6978
6979 struct mlx5_ifc_create_flow_group_in_bits {
6980         u8         opcode[0x10];
6981         u8         reserved_at_10[0x10];
6982
6983         u8         reserved_at_20[0x10];
6984         u8         op_mod[0x10];
6985
6986         u8         other_vport[0x1];
6987         u8         reserved_at_41[0xf];
6988         u8         vport_number[0x10];
6989
6990         u8         reserved_at_60[0x20];
6991
6992         u8         table_type[0x8];
6993         u8         reserved_at_88[0x18];
6994
6995         u8         reserved_at_a0[0x8];
6996         u8         table_id[0x18];
6997
6998         u8         reserved_at_c0[0x20];
6999
7000         u8         start_flow_index[0x20];
7001
7002         u8         reserved_at_100[0x20];
7003
7004         u8         end_flow_index[0x20];
7005
7006         u8         reserved_at_140[0xa0];
7007
7008         u8         reserved_at_1e0[0x18];
7009         u8         match_criteria_enable[0x8];
7010
7011         struct mlx5_ifc_fte_match_param_bits match_criteria;
7012
7013         u8         reserved_at_1200[0xe00];
7014 };
7015
7016 struct mlx5_ifc_create_eq_out_bits {
7017         u8         status[0x8];
7018         u8         reserved_at_8[0x18];
7019
7020         u8         syndrome[0x20];
7021
7022         u8         reserved_at_40[0x18];
7023         u8         eq_number[0x8];
7024
7025         u8         reserved_at_60[0x20];
7026 };
7027
7028 struct mlx5_ifc_create_eq_in_bits {
7029         u8         opcode[0x10];
7030         u8         reserved_at_10[0x10];
7031
7032         u8         reserved_at_20[0x10];
7033         u8         op_mod[0x10];
7034
7035         u8         reserved_at_40[0x40];
7036
7037         struct mlx5_ifc_eqc_bits eq_context_entry;
7038
7039         u8         reserved_at_280[0x40];
7040
7041         u8         event_bitmask[0x40];
7042
7043         u8         reserved_at_300[0x580];
7044
7045         u8         pas[0][0x40];
7046 };
7047
7048 struct mlx5_ifc_create_dct_out_bits {
7049         u8         status[0x8];
7050         u8         reserved_at_8[0x18];
7051
7052         u8         syndrome[0x20];
7053
7054         u8         reserved_at_40[0x8];
7055         u8         dctn[0x18];
7056
7057         u8         reserved_at_60[0x20];
7058 };
7059
7060 struct mlx5_ifc_create_dct_in_bits {
7061         u8         opcode[0x10];
7062         u8         reserved_at_10[0x10];
7063
7064         u8         reserved_at_20[0x10];
7065         u8         op_mod[0x10];
7066
7067         u8         reserved_at_40[0x40];
7068
7069         struct mlx5_ifc_dctc_bits dct_context_entry;
7070
7071         u8         reserved_at_280[0x180];
7072 };
7073
7074 struct mlx5_ifc_create_cq_out_bits {
7075         u8         status[0x8];
7076         u8         reserved_at_8[0x18];
7077
7078         u8         syndrome[0x20];
7079
7080         u8         reserved_at_40[0x8];
7081         u8         cqn[0x18];
7082
7083         u8         reserved_at_60[0x20];
7084 };
7085
7086 struct mlx5_ifc_create_cq_in_bits {
7087         u8         opcode[0x10];
7088         u8         reserved_at_10[0x10];
7089
7090         u8         reserved_at_20[0x10];
7091         u8         op_mod[0x10];
7092
7093         u8         reserved_at_40[0x40];
7094
7095         struct mlx5_ifc_cqc_bits cq_context;
7096
7097         u8         reserved_at_280[0x600];
7098
7099         u8         pas[0][0x40];
7100 };
7101
7102 struct mlx5_ifc_config_int_moderation_out_bits {
7103         u8         status[0x8];
7104         u8         reserved_at_8[0x18];
7105
7106         u8         syndrome[0x20];
7107
7108         u8         reserved_at_40[0x4];
7109         u8         min_delay[0xc];
7110         u8         int_vector[0x10];
7111
7112         u8         reserved_at_60[0x20];
7113 };
7114
7115 enum {
7116         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7117         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7118 };
7119
7120 struct mlx5_ifc_config_int_moderation_in_bits {
7121         u8         opcode[0x10];
7122         u8         reserved_at_10[0x10];
7123
7124         u8         reserved_at_20[0x10];
7125         u8         op_mod[0x10];
7126
7127         u8         reserved_at_40[0x4];
7128         u8         min_delay[0xc];
7129         u8         int_vector[0x10];
7130
7131         u8         reserved_at_60[0x20];
7132 };
7133
7134 struct mlx5_ifc_attach_to_mcg_out_bits {
7135         u8         status[0x8];
7136         u8         reserved_at_8[0x18];
7137
7138         u8         syndrome[0x20];
7139
7140         u8         reserved_at_40[0x40];
7141 };
7142
7143 struct mlx5_ifc_attach_to_mcg_in_bits {
7144         u8         opcode[0x10];
7145         u8         reserved_at_10[0x10];
7146
7147         u8         reserved_at_20[0x10];
7148         u8         op_mod[0x10];
7149
7150         u8         reserved_at_40[0x8];
7151         u8         qpn[0x18];
7152
7153         u8         reserved_at_60[0x20];
7154
7155         u8         multicast_gid[16][0x8];
7156 };
7157
7158 struct mlx5_ifc_arm_xrq_out_bits {
7159         u8         status[0x8];
7160         u8         reserved_at_8[0x18];
7161
7162         u8         syndrome[0x20];
7163
7164         u8         reserved_at_40[0x40];
7165 };
7166
7167 struct mlx5_ifc_arm_xrq_in_bits {
7168         u8         opcode[0x10];
7169         u8         reserved_at_10[0x10];
7170
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173
7174         u8         reserved_at_40[0x8];
7175         u8         xrqn[0x18];
7176
7177         u8         reserved_at_60[0x10];
7178         u8         lwm[0x10];
7179 };
7180
7181 struct mlx5_ifc_arm_xrc_srq_out_bits {
7182         u8         status[0x8];
7183         u8         reserved_at_8[0x18];
7184
7185         u8         syndrome[0x20];
7186
7187         u8         reserved_at_40[0x40];
7188 };
7189
7190 enum {
7191         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7192 };
7193
7194 struct mlx5_ifc_arm_xrc_srq_in_bits {
7195         u8         opcode[0x10];
7196         u8         reserved_at_10[0x10];
7197
7198         u8         reserved_at_20[0x10];
7199         u8         op_mod[0x10];
7200
7201         u8         reserved_at_40[0x8];
7202         u8         xrc_srqn[0x18];
7203
7204         u8         reserved_at_60[0x10];
7205         u8         lwm[0x10];
7206 };
7207
7208 struct mlx5_ifc_arm_rq_out_bits {
7209         u8         status[0x8];
7210         u8         reserved_at_8[0x18];
7211
7212         u8         syndrome[0x20];
7213
7214         u8         reserved_at_40[0x40];
7215 };
7216
7217 enum {
7218         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7219         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7220 };
7221
7222 struct mlx5_ifc_arm_rq_in_bits {
7223         u8         opcode[0x10];
7224         u8         reserved_at_10[0x10];
7225
7226         u8         reserved_at_20[0x10];
7227         u8         op_mod[0x10];
7228
7229         u8         reserved_at_40[0x8];
7230         u8         srq_number[0x18];
7231
7232         u8         reserved_at_60[0x10];
7233         u8         lwm[0x10];
7234 };
7235
7236 struct mlx5_ifc_arm_dct_out_bits {
7237         u8         status[0x8];
7238         u8         reserved_at_8[0x18];
7239
7240         u8         syndrome[0x20];
7241
7242         u8         reserved_at_40[0x40];
7243 };
7244
7245 struct mlx5_ifc_arm_dct_in_bits {
7246         u8         opcode[0x10];
7247         u8         reserved_at_10[0x10];
7248
7249         u8         reserved_at_20[0x10];
7250         u8         op_mod[0x10];
7251
7252         u8         reserved_at_40[0x8];
7253         u8         dct_number[0x18];
7254
7255         u8         reserved_at_60[0x20];
7256 };
7257
7258 struct mlx5_ifc_alloc_xrcd_out_bits {
7259         u8         status[0x8];
7260         u8         reserved_at_8[0x18];
7261
7262         u8         syndrome[0x20];
7263
7264         u8         reserved_at_40[0x8];
7265         u8         xrcd[0x18];
7266
7267         u8         reserved_at_60[0x20];
7268 };
7269
7270 struct mlx5_ifc_alloc_xrcd_in_bits {
7271         u8         opcode[0x10];
7272         u8         reserved_at_10[0x10];
7273
7274         u8         reserved_at_20[0x10];
7275         u8         op_mod[0x10];
7276
7277         u8         reserved_at_40[0x40];
7278 };
7279
7280 struct mlx5_ifc_alloc_uar_out_bits {
7281         u8         status[0x8];
7282         u8         reserved_at_8[0x18];
7283
7284         u8         syndrome[0x20];
7285
7286         u8         reserved_at_40[0x8];
7287         u8         uar[0x18];
7288
7289         u8         reserved_at_60[0x20];
7290 };
7291
7292 struct mlx5_ifc_alloc_uar_in_bits {
7293         u8         opcode[0x10];
7294         u8         reserved_at_10[0x10];
7295
7296         u8         reserved_at_20[0x10];
7297         u8         op_mod[0x10];
7298
7299         u8         reserved_at_40[0x40];
7300 };
7301
7302 struct mlx5_ifc_alloc_transport_domain_out_bits {
7303         u8         status[0x8];
7304         u8         reserved_at_8[0x18];
7305
7306         u8         syndrome[0x20];
7307
7308         u8         reserved_at_40[0x8];
7309         u8         transport_domain[0x18];
7310
7311         u8         reserved_at_60[0x20];
7312 };
7313
7314 struct mlx5_ifc_alloc_transport_domain_in_bits {
7315         u8         opcode[0x10];
7316         u8         reserved_at_10[0x10];
7317
7318         u8         reserved_at_20[0x10];
7319         u8         op_mod[0x10];
7320
7321         u8         reserved_at_40[0x40];
7322 };
7323
7324 struct mlx5_ifc_alloc_q_counter_out_bits {
7325         u8         status[0x8];
7326         u8         reserved_at_8[0x18];
7327
7328         u8         syndrome[0x20];
7329
7330         u8         reserved_at_40[0x18];
7331         u8         counter_set_id[0x8];
7332
7333         u8         reserved_at_60[0x20];
7334 };
7335
7336 struct mlx5_ifc_alloc_q_counter_in_bits {
7337         u8         opcode[0x10];
7338         u8         reserved_at_10[0x10];
7339
7340         u8         reserved_at_20[0x10];
7341         u8         op_mod[0x10];
7342
7343         u8         reserved_at_40[0x40];
7344 };
7345
7346 struct mlx5_ifc_alloc_pd_out_bits {
7347         u8         status[0x8];
7348         u8         reserved_at_8[0x18];
7349
7350         u8         syndrome[0x20];
7351
7352         u8         reserved_at_40[0x8];
7353         u8         pd[0x18];
7354
7355         u8         reserved_at_60[0x20];
7356 };
7357
7358 struct mlx5_ifc_alloc_pd_in_bits {
7359         u8         opcode[0x10];
7360         u8         reserved_at_10[0x10];
7361
7362         u8         reserved_at_20[0x10];
7363         u8         op_mod[0x10];
7364
7365         u8         reserved_at_40[0x40];
7366 };
7367
7368 struct mlx5_ifc_alloc_flow_counter_out_bits {
7369         u8         status[0x8];
7370         u8         reserved_at_8[0x18];
7371
7372         u8         syndrome[0x20];
7373
7374         u8         flow_counter_id[0x20];
7375
7376         u8         reserved_at_60[0x20];
7377 };
7378
7379 struct mlx5_ifc_alloc_flow_counter_in_bits {
7380         u8         opcode[0x10];
7381         u8         reserved_at_10[0x10];
7382
7383         u8         reserved_at_20[0x10];
7384         u8         op_mod[0x10];
7385
7386         u8         reserved_at_40[0x40];
7387 };
7388
7389 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7390         u8         status[0x8];
7391         u8         reserved_at_8[0x18];
7392
7393         u8         syndrome[0x20];
7394
7395         u8         reserved_at_40[0x40];
7396 };
7397
7398 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7399         u8         opcode[0x10];
7400         u8         reserved_at_10[0x10];
7401
7402         u8         reserved_at_20[0x10];
7403         u8         op_mod[0x10];
7404
7405         u8         reserved_at_40[0x20];
7406
7407         u8         reserved_at_60[0x10];
7408         u8         vxlan_udp_port[0x10];
7409 };
7410
7411 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7412         u8         status[0x8];
7413         u8         reserved_at_8[0x18];
7414
7415         u8         syndrome[0x20];
7416
7417         u8         reserved_at_40[0x40];
7418 };
7419
7420 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7421         u8         opcode[0x10];
7422         u8         reserved_at_10[0x10];
7423
7424         u8         reserved_at_20[0x10];
7425         u8         op_mod[0x10];
7426
7427         u8         reserved_at_40[0x10];
7428         u8         rate_limit_index[0x10];
7429
7430         u8         reserved_at_60[0x20];
7431
7432         u8         rate_limit[0x20];
7433
7434         u8         burst_upper_bound[0x20];
7435
7436         u8         reserved_at_c0[0x10];
7437         u8         typical_packet_size[0x10];
7438
7439         u8         reserved_at_e0[0x120];
7440 };
7441
7442 struct mlx5_ifc_access_register_out_bits {
7443         u8         status[0x8];
7444         u8         reserved_at_8[0x18];
7445
7446         u8         syndrome[0x20];
7447
7448         u8         reserved_at_40[0x40];
7449
7450         u8         register_data[0][0x20];
7451 };
7452
7453 enum {
7454         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7455         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7456 };
7457
7458 struct mlx5_ifc_access_register_in_bits {
7459         u8         opcode[0x10];
7460         u8         reserved_at_10[0x10];
7461
7462         u8         reserved_at_20[0x10];
7463         u8         op_mod[0x10];
7464
7465         u8         reserved_at_40[0x10];
7466         u8         register_id[0x10];
7467
7468         u8         argument[0x20];
7469
7470         u8         register_data[0][0x20];
7471 };
7472
7473 struct mlx5_ifc_sltp_reg_bits {
7474         u8         status[0x4];
7475         u8         version[0x4];
7476         u8         local_port[0x8];
7477         u8         pnat[0x2];
7478         u8         reserved_at_12[0x2];
7479         u8         lane[0x4];
7480         u8         reserved_at_18[0x8];
7481
7482         u8         reserved_at_20[0x20];
7483
7484         u8         reserved_at_40[0x7];
7485         u8         polarity[0x1];
7486         u8         ob_tap0[0x8];
7487         u8         ob_tap1[0x8];
7488         u8         ob_tap2[0x8];
7489
7490         u8         reserved_at_60[0xc];
7491         u8         ob_preemp_mode[0x4];
7492         u8         ob_reg[0x8];
7493         u8         ob_bias[0x8];
7494
7495         u8         reserved_at_80[0x20];
7496 };
7497
7498 struct mlx5_ifc_slrg_reg_bits {
7499         u8         status[0x4];
7500         u8         version[0x4];
7501         u8         local_port[0x8];
7502         u8         pnat[0x2];
7503         u8         reserved_at_12[0x2];
7504         u8         lane[0x4];
7505         u8         reserved_at_18[0x8];
7506
7507         u8         time_to_link_up[0x10];
7508         u8         reserved_at_30[0xc];
7509         u8         grade_lane_speed[0x4];
7510
7511         u8         grade_version[0x8];
7512         u8         grade[0x18];
7513
7514         u8         reserved_at_60[0x4];
7515         u8         height_grade_type[0x4];
7516         u8         height_grade[0x18];
7517
7518         u8         height_dz[0x10];
7519         u8         height_dv[0x10];
7520
7521         u8         reserved_at_a0[0x10];
7522         u8         height_sigma[0x10];
7523
7524         u8         reserved_at_c0[0x20];
7525
7526         u8         reserved_at_e0[0x4];
7527         u8         phase_grade_type[0x4];
7528         u8         phase_grade[0x18];
7529
7530         u8         reserved_at_100[0x8];
7531         u8         phase_eo_pos[0x8];
7532         u8         reserved_at_110[0x8];
7533         u8         phase_eo_neg[0x8];
7534
7535         u8         ffe_set_tested[0x10];
7536         u8         test_errors_per_lane[0x10];
7537 };
7538
7539 struct mlx5_ifc_pvlc_reg_bits {
7540         u8         reserved_at_0[0x8];
7541         u8         local_port[0x8];
7542         u8         reserved_at_10[0x10];
7543
7544         u8         reserved_at_20[0x1c];
7545         u8         vl_hw_cap[0x4];
7546
7547         u8         reserved_at_40[0x1c];
7548         u8         vl_admin[0x4];
7549
7550         u8         reserved_at_60[0x1c];
7551         u8         vl_operational[0x4];
7552 };
7553
7554 struct mlx5_ifc_pude_reg_bits {
7555         u8         swid[0x8];
7556         u8         local_port[0x8];
7557         u8         reserved_at_10[0x4];
7558         u8         admin_status[0x4];
7559         u8         reserved_at_18[0x4];
7560         u8         oper_status[0x4];
7561
7562         u8         reserved_at_20[0x60];
7563 };
7564
7565 struct mlx5_ifc_ptys_reg_bits {
7566         u8         reserved_at_0[0x1];
7567         u8         an_disable_admin[0x1];
7568         u8         an_disable_cap[0x1];
7569         u8         reserved_at_3[0x5];
7570         u8         local_port[0x8];
7571         u8         reserved_at_10[0xd];
7572         u8         proto_mask[0x3];
7573
7574         u8         an_status[0x4];
7575         u8         reserved_at_24[0x3c];
7576
7577         u8         eth_proto_capability[0x20];
7578
7579         u8         ib_link_width_capability[0x10];
7580         u8         ib_proto_capability[0x10];
7581
7582         u8         reserved_at_a0[0x20];
7583
7584         u8         eth_proto_admin[0x20];
7585
7586         u8         ib_link_width_admin[0x10];
7587         u8         ib_proto_admin[0x10];
7588
7589         u8         reserved_at_100[0x20];
7590
7591         u8         eth_proto_oper[0x20];
7592
7593         u8         ib_link_width_oper[0x10];
7594         u8         ib_proto_oper[0x10];
7595
7596         u8         reserved_at_160[0x1c];
7597         u8         connector_type[0x4];
7598
7599         u8         eth_proto_lp_advertise[0x20];
7600
7601         u8         reserved_at_1a0[0x60];
7602 };
7603
7604 struct mlx5_ifc_mlcr_reg_bits {
7605         u8         reserved_at_0[0x8];
7606         u8         local_port[0x8];
7607         u8         reserved_at_10[0x20];
7608
7609         u8         beacon_duration[0x10];
7610         u8         reserved_at_40[0x10];
7611
7612         u8         beacon_remain[0x10];
7613 };
7614
7615 struct mlx5_ifc_ptas_reg_bits {
7616         u8         reserved_at_0[0x20];
7617
7618         u8         algorithm_options[0x10];
7619         u8         reserved_at_30[0x4];
7620         u8         repetitions_mode[0x4];
7621         u8         num_of_repetitions[0x8];
7622
7623         u8         grade_version[0x8];
7624         u8         height_grade_type[0x4];
7625         u8         phase_grade_type[0x4];
7626         u8         height_grade_weight[0x8];
7627         u8         phase_grade_weight[0x8];
7628
7629         u8         gisim_measure_bits[0x10];
7630         u8         adaptive_tap_measure_bits[0x10];
7631
7632         u8         ber_bath_high_error_threshold[0x10];
7633         u8         ber_bath_mid_error_threshold[0x10];
7634
7635         u8         ber_bath_low_error_threshold[0x10];
7636         u8         one_ratio_high_threshold[0x10];
7637
7638         u8         one_ratio_high_mid_threshold[0x10];
7639         u8         one_ratio_low_mid_threshold[0x10];
7640
7641         u8         one_ratio_low_threshold[0x10];
7642         u8         ndeo_error_threshold[0x10];
7643
7644         u8         mixer_offset_step_size[0x10];
7645         u8         reserved_at_110[0x8];
7646         u8         mix90_phase_for_voltage_bath[0x8];
7647
7648         u8         mixer_offset_start[0x10];
7649         u8         mixer_offset_end[0x10];
7650
7651         u8         reserved_at_140[0x15];
7652         u8         ber_test_time[0xb];
7653 };
7654
7655 struct mlx5_ifc_pspa_reg_bits {
7656         u8         swid[0x8];
7657         u8         local_port[0x8];
7658         u8         sub_port[0x8];
7659         u8         reserved_at_18[0x8];
7660
7661         u8         reserved_at_20[0x20];
7662 };
7663
7664 struct mlx5_ifc_pqdr_reg_bits {
7665         u8         reserved_at_0[0x8];
7666         u8         local_port[0x8];
7667         u8         reserved_at_10[0x5];
7668         u8         prio[0x3];
7669         u8         reserved_at_18[0x6];
7670         u8         mode[0x2];
7671
7672         u8         reserved_at_20[0x20];
7673
7674         u8         reserved_at_40[0x10];
7675         u8         min_threshold[0x10];
7676
7677         u8         reserved_at_60[0x10];
7678         u8         max_threshold[0x10];
7679
7680         u8         reserved_at_80[0x10];
7681         u8         mark_probability_denominator[0x10];
7682
7683         u8         reserved_at_a0[0x60];
7684 };
7685
7686 struct mlx5_ifc_ppsc_reg_bits {
7687         u8         reserved_at_0[0x8];
7688         u8         local_port[0x8];
7689         u8         reserved_at_10[0x10];
7690
7691         u8         reserved_at_20[0x60];
7692
7693         u8         reserved_at_80[0x1c];
7694         u8         wrps_admin[0x4];
7695
7696         u8         reserved_at_a0[0x1c];
7697         u8         wrps_status[0x4];
7698
7699         u8         reserved_at_c0[0x8];
7700         u8         up_threshold[0x8];
7701         u8         reserved_at_d0[0x8];
7702         u8         down_threshold[0x8];
7703
7704         u8         reserved_at_e0[0x20];
7705
7706         u8         reserved_at_100[0x1c];
7707         u8         srps_admin[0x4];
7708
7709         u8         reserved_at_120[0x1c];
7710         u8         srps_status[0x4];
7711
7712         u8         reserved_at_140[0x40];
7713 };
7714
7715 struct mlx5_ifc_pplr_reg_bits {
7716         u8         reserved_at_0[0x8];
7717         u8         local_port[0x8];
7718         u8         reserved_at_10[0x10];
7719
7720         u8         reserved_at_20[0x8];
7721         u8         lb_cap[0x8];
7722         u8         reserved_at_30[0x8];
7723         u8         lb_en[0x8];
7724 };
7725
7726 struct mlx5_ifc_pplm_reg_bits {
7727         u8         reserved_at_0[0x8];
7728         u8         local_port[0x8];
7729         u8         reserved_at_10[0x10];
7730
7731         u8         reserved_at_20[0x20];
7732
7733         u8         port_profile_mode[0x8];
7734         u8         static_port_profile[0x8];
7735         u8         active_port_profile[0x8];
7736         u8         reserved_at_58[0x8];
7737
7738         u8         retransmission_active[0x8];
7739         u8         fec_mode_active[0x18];
7740
7741         u8         reserved_at_80[0x20];
7742 };
7743
7744 struct mlx5_ifc_ppcnt_reg_bits {
7745         u8         swid[0x8];
7746         u8         local_port[0x8];
7747         u8         pnat[0x2];
7748         u8         reserved_at_12[0x8];
7749         u8         grp[0x6];
7750
7751         u8         clr[0x1];
7752         u8         reserved_at_21[0x1c];
7753         u8         prio_tc[0x3];
7754
7755         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7756 };
7757
7758 struct mlx5_ifc_mpcnt_reg_bits {
7759         u8         reserved_at_0[0x8];
7760         u8         pcie_index[0x8];
7761         u8         reserved_at_10[0xa];
7762         u8         grp[0x6];
7763
7764         u8         clr[0x1];
7765         u8         reserved_at_21[0x1f];
7766
7767         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7768 };
7769
7770 struct mlx5_ifc_ppad_reg_bits {
7771         u8         reserved_at_0[0x3];
7772         u8         single_mac[0x1];
7773         u8         reserved_at_4[0x4];
7774         u8         local_port[0x8];
7775         u8         mac_47_32[0x10];
7776
7777         u8         mac_31_0[0x20];
7778
7779         u8         reserved_at_40[0x40];
7780 };
7781
7782 struct mlx5_ifc_pmtu_reg_bits {
7783         u8         reserved_at_0[0x8];
7784         u8         local_port[0x8];
7785         u8         reserved_at_10[0x10];
7786
7787         u8         max_mtu[0x10];
7788         u8         reserved_at_30[0x10];
7789
7790         u8         admin_mtu[0x10];
7791         u8         reserved_at_50[0x10];
7792
7793         u8         oper_mtu[0x10];
7794         u8         reserved_at_70[0x10];
7795 };
7796
7797 struct mlx5_ifc_pmpr_reg_bits {
7798         u8         reserved_at_0[0x8];
7799         u8         module[0x8];
7800         u8         reserved_at_10[0x10];
7801
7802         u8         reserved_at_20[0x18];
7803         u8         attenuation_5g[0x8];
7804
7805         u8         reserved_at_40[0x18];
7806         u8         attenuation_7g[0x8];
7807
7808         u8         reserved_at_60[0x18];
7809         u8         attenuation_12g[0x8];
7810 };
7811
7812 struct mlx5_ifc_pmpe_reg_bits {
7813         u8         reserved_at_0[0x8];
7814         u8         module[0x8];
7815         u8         reserved_at_10[0xc];
7816         u8         module_status[0x4];
7817
7818         u8         reserved_at_20[0x60];
7819 };
7820
7821 struct mlx5_ifc_pmpc_reg_bits {
7822         u8         module_state_updated[32][0x8];
7823 };
7824
7825 struct mlx5_ifc_pmlpn_reg_bits {
7826         u8         reserved_at_0[0x4];
7827         u8         mlpn_status[0x4];
7828         u8         local_port[0x8];
7829         u8         reserved_at_10[0x10];
7830
7831         u8         e[0x1];
7832         u8         reserved_at_21[0x1f];
7833 };
7834
7835 struct mlx5_ifc_pmlp_reg_bits {
7836         u8         rxtx[0x1];
7837         u8         reserved_at_1[0x7];
7838         u8         local_port[0x8];
7839         u8         reserved_at_10[0x8];
7840         u8         width[0x8];
7841
7842         u8         lane0_module_mapping[0x20];
7843
7844         u8         lane1_module_mapping[0x20];
7845
7846         u8         lane2_module_mapping[0x20];
7847
7848         u8         lane3_module_mapping[0x20];
7849
7850         u8         reserved_at_a0[0x160];
7851 };
7852
7853 struct mlx5_ifc_pmaos_reg_bits {
7854         u8         reserved_at_0[0x8];
7855         u8         module[0x8];
7856         u8         reserved_at_10[0x4];
7857         u8         admin_status[0x4];
7858         u8         reserved_at_18[0x4];
7859         u8         oper_status[0x4];
7860
7861         u8         ase[0x1];
7862         u8         ee[0x1];
7863         u8         reserved_at_22[0x1c];
7864         u8         e[0x2];
7865
7866         u8         reserved_at_40[0x40];
7867 };
7868
7869 struct mlx5_ifc_plpc_reg_bits {
7870         u8         reserved_at_0[0x4];
7871         u8         profile_id[0xc];
7872         u8         reserved_at_10[0x4];
7873         u8         proto_mask[0x4];
7874         u8         reserved_at_18[0x8];
7875
7876         u8         reserved_at_20[0x10];
7877         u8         lane_speed[0x10];
7878
7879         u8         reserved_at_40[0x17];
7880         u8         lpbf[0x1];
7881         u8         fec_mode_policy[0x8];
7882
7883         u8         retransmission_capability[0x8];
7884         u8         fec_mode_capability[0x18];
7885
7886         u8         retransmission_support_admin[0x8];
7887         u8         fec_mode_support_admin[0x18];
7888
7889         u8         retransmission_request_admin[0x8];
7890         u8         fec_mode_request_admin[0x18];
7891
7892         u8         reserved_at_c0[0x80];
7893 };
7894
7895 struct mlx5_ifc_plib_reg_bits {
7896         u8         reserved_at_0[0x8];
7897         u8         local_port[0x8];
7898         u8         reserved_at_10[0x8];
7899         u8         ib_port[0x8];
7900
7901         u8         reserved_at_20[0x60];
7902 };
7903
7904 struct mlx5_ifc_plbf_reg_bits {
7905         u8         reserved_at_0[0x8];
7906         u8         local_port[0x8];
7907         u8         reserved_at_10[0xd];
7908         u8         lbf_mode[0x3];
7909
7910         u8         reserved_at_20[0x20];
7911 };
7912
7913 struct mlx5_ifc_pipg_reg_bits {
7914         u8         reserved_at_0[0x8];
7915         u8         local_port[0x8];
7916         u8         reserved_at_10[0x10];
7917
7918         u8         dic[0x1];
7919         u8         reserved_at_21[0x19];
7920         u8         ipg[0x4];
7921         u8         reserved_at_3e[0x2];
7922 };
7923
7924 struct mlx5_ifc_pifr_reg_bits {
7925         u8         reserved_at_0[0x8];
7926         u8         local_port[0x8];
7927         u8         reserved_at_10[0x10];
7928
7929         u8         reserved_at_20[0xe0];
7930
7931         u8         port_filter[8][0x20];
7932
7933         u8         port_filter_update_en[8][0x20];
7934 };
7935
7936 struct mlx5_ifc_pfcc_reg_bits {
7937         u8         reserved_at_0[0x8];
7938         u8         local_port[0x8];
7939         u8         reserved_at_10[0xb];
7940         u8         ppan_mask_n[0x1];
7941         u8         minor_stall_mask[0x1];
7942         u8         critical_stall_mask[0x1];
7943         u8         reserved_at_1e[0x2];
7944
7945         u8         ppan[0x4];
7946         u8         reserved_at_24[0x4];
7947         u8         prio_mask_tx[0x8];
7948         u8         reserved_at_30[0x8];
7949         u8         prio_mask_rx[0x8];
7950
7951         u8         pptx[0x1];
7952         u8         aptx[0x1];
7953         u8         pptx_mask_n[0x1];
7954         u8         reserved_at_43[0x5];
7955         u8         pfctx[0x8];
7956         u8         reserved_at_50[0x10];
7957
7958         u8         pprx[0x1];
7959         u8         aprx[0x1];
7960         u8         pprx_mask_n[0x1];
7961         u8         reserved_at_63[0x5];
7962         u8         pfcrx[0x8];
7963         u8         reserved_at_70[0x10];
7964
7965         u8         device_stall_minor_watermark[0x10];
7966         u8         device_stall_critical_watermark[0x10];
7967
7968         u8         reserved_at_a0[0x60];
7969 };
7970
7971 struct mlx5_ifc_pelc_reg_bits {
7972         u8         op[0x4];
7973         u8         reserved_at_4[0x4];
7974         u8         local_port[0x8];
7975         u8         reserved_at_10[0x10];
7976
7977         u8         op_admin[0x8];
7978         u8         op_capability[0x8];
7979         u8         op_request[0x8];
7980         u8         op_active[0x8];
7981
7982         u8         admin[0x40];
7983
7984         u8         capability[0x40];
7985
7986         u8         request[0x40];
7987
7988         u8         active[0x40];
7989
7990         u8         reserved_at_140[0x80];
7991 };
7992
7993 struct mlx5_ifc_peir_reg_bits {
7994         u8         reserved_at_0[0x8];
7995         u8         local_port[0x8];
7996         u8         reserved_at_10[0x10];
7997
7998         u8         reserved_at_20[0xc];
7999         u8         error_count[0x4];
8000         u8         reserved_at_30[0x10];
8001
8002         u8         reserved_at_40[0xc];
8003         u8         lane[0x4];
8004         u8         reserved_at_50[0x8];
8005         u8         error_type[0x8];
8006 };
8007
8008 struct mlx5_ifc_pcam_enhanced_features_bits {
8009         u8         reserved_at_0[0x76];
8010
8011         u8         pfcc_mask[0x1];
8012         u8         reserved_at_77[0x4];
8013         u8         rx_buffer_fullness_counters[0x1];
8014         u8         ptys_connector_type[0x1];
8015         u8         reserved_at_7d[0x1];
8016         u8         ppcnt_discard_group[0x1];
8017         u8         ppcnt_statistical_group[0x1];
8018 };
8019
8020 struct mlx5_ifc_pcam_reg_bits {
8021         u8         reserved_at_0[0x8];
8022         u8         feature_group[0x8];
8023         u8         reserved_at_10[0x8];
8024         u8         access_reg_group[0x8];
8025
8026         u8         reserved_at_20[0x20];
8027
8028         union {
8029                 u8         reserved_at_0[0x80];
8030         } port_access_reg_cap_mask;
8031
8032         u8         reserved_at_c0[0x80];
8033
8034         union {
8035                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8036                 u8         reserved_at_0[0x80];
8037         } feature_cap_mask;
8038
8039         u8         reserved_at_1c0[0xc0];
8040 };
8041
8042 struct mlx5_ifc_mcam_enhanced_features_bits {
8043         u8         reserved_at_0[0x7b];
8044         u8         pcie_outbound_stalled[0x1];
8045         u8         tx_overflow_buffer_pkt[0x1];
8046         u8         mtpps_enh_out_per_adj[0x1];
8047         u8         mtpps_fs[0x1];
8048         u8         pcie_performance_group[0x1];
8049 };
8050
8051 struct mlx5_ifc_mcam_access_reg_bits {
8052         u8         reserved_at_0[0x1c];
8053         u8         mcda[0x1];
8054         u8         mcc[0x1];
8055         u8         mcqi[0x1];
8056         u8         reserved_at_1f[0x1];
8057
8058         u8         regs_95_to_64[0x20];
8059         u8         regs_63_to_32[0x20];
8060         u8         regs_31_to_0[0x20];
8061 };
8062
8063 struct mlx5_ifc_mcam_reg_bits {
8064         u8         reserved_at_0[0x8];
8065         u8         feature_group[0x8];
8066         u8         reserved_at_10[0x8];
8067         u8         access_reg_group[0x8];
8068
8069         u8         reserved_at_20[0x20];
8070
8071         union {
8072                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8073                 u8         reserved_at_0[0x80];
8074         } mng_access_reg_cap_mask;
8075
8076         u8         reserved_at_c0[0x80];
8077
8078         union {
8079                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8080                 u8         reserved_at_0[0x80];
8081         } mng_feature_cap_mask;
8082
8083         u8         reserved_at_1c0[0x80];
8084 };
8085
8086 struct mlx5_ifc_qcam_access_reg_cap_mask {
8087         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8088         u8         qpdpm[0x1];
8089         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8090         u8         qdpm[0x1];
8091         u8         qpts[0x1];
8092         u8         qcap[0x1];
8093         u8         qcam_access_reg_cap_mask_0[0x1];
8094 };
8095
8096 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8097         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8098         u8         qpts_trust_both[0x1];
8099 };
8100
8101 struct mlx5_ifc_qcam_reg_bits {
8102         u8         reserved_at_0[0x8];
8103         u8         feature_group[0x8];
8104         u8         reserved_at_10[0x8];
8105         u8         access_reg_group[0x8];
8106         u8         reserved_at_20[0x20];
8107
8108         union {
8109                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8110                 u8  reserved_at_0[0x80];
8111         } qos_access_reg_cap_mask;
8112
8113         u8         reserved_at_c0[0x80];
8114
8115         union {
8116                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8117                 u8  reserved_at_0[0x80];
8118         } qos_feature_cap_mask;
8119
8120         u8         reserved_at_1c0[0x80];
8121 };
8122
8123 struct mlx5_ifc_pcap_reg_bits {
8124         u8         reserved_at_0[0x8];
8125         u8         local_port[0x8];
8126         u8         reserved_at_10[0x10];
8127
8128         u8         port_capability_mask[4][0x20];
8129 };
8130
8131 struct mlx5_ifc_paos_reg_bits {
8132         u8         swid[0x8];
8133         u8         local_port[0x8];
8134         u8         reserved_at_10[0x4];
8135         u8         admin_status[0x4];
8136         u8         reserved_at_18[0x4];
8137         u8         oper_status[0x4];
8138
8139         u8         ase[0x1];
8140         u8         ee[0x1];
8141         u8         reserved_at_22[0x1c];
8142         u8         e[0x2];
8143
8144         u8         reserved_at_40[0x40];
8145 };
8146
8147 struct mlx5_ifc_pamp_reg_bits {
8148         u8         reserved_at_0[0x8];
8149         u8         opamp_group[0x8];
8150         u8         reserved_at_10[0xc];
8151         u8         opamp_group_type[0x4];
8152
8153         u8         start_index[0x10];
8154         u8         reserved_at_30[0x4];
8155         u8         num_of_indices[0xc];
8156
8157         u8         index_data[18][0x10];
8158 };
8159
8160 struct mlx5_ifc_pcmr_reg_bits {
8161         u8         reserved_at_0[0x8];
8162         u8         local_port[0x8];
8163         u8         reserved_at_10[0x2e];
8164         u8         fcs_cap[0x1];
8165         u8         reserved_at_3f[0x1f];
8166         u8         fcs_chk[0x1];
8167         u8         reserved_at_5f[0x1];
8168 };
8169
8170 struct mlx5_ifc_lane_2_module_mapping_bits {
8171         u8         reserved_at_0[0x6];
8172         u8         rx_lane[0x2];
8173         u8         reserved_at_8[0x6];
8174         u8         tx_lane[0x2];
8175         u8         reserved_at_10[0x8];
8176         u8         module[0x8];
8177 };
8178
8179 struct mlx5_ifc_bufferx_reg_bits {
8180         u8         reserved_at_0[0x6];
8181         u8         lossy[0x1];
8182         u8         epsb[0x1];
8183         u8         reserved_at_8[0xc];
8184         u8         size[0xc];
8185
8186         u8         xoff_threshold[0x10];
8187         u8         xon_threshold[0x10];
8188 };
8189
8190 struct mlx5_ifc_set_node_in_bits {
8191         u8         node_description[64][0x8];
8192 };
8193
8194 struct mlx5_ifc_register_power_settings_bits {
8195         u8         reserved_at_0[0x18];
8196         u8         power_settings_level[0x8];
8197
8198         u8         reserved_at_20[0x60];
8199 };
8200
8201 struct mlx5_ifc_register_host_endianness_bits {
8202         u8         he[0x1];
8203         u8         reserved_at_1[0x1f];
8204
8205         u8         reserved_at_20[0x60];
8206 };
8207
8208 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8209         u8         reserved_at_0[0x20];
8210
8211         u8         mkey[0x20];
8212
8213         u8         addressh_63_32[0x20];
8214
8215         u8         addressl_31_0[0x20];
8216 };
8217
8218 struct mlx5_ifc_ud_adrs_vector_bits {
8219         u8         dc_key[0x40];
8220
8221         u8         ext[0x1];
8222         u8         reserved_at_41[0x7];
8223         u8         destination_qp_dct[0x18];
8224
8225         u8         static_rate[0x4];
8226         u8         sl_eth_prio[0x4];
8227         u8         fl[0x1];
8228         u8         mlid[0x7];
8229         u8         rlid_udp_sport[0x10];
8230
8231         u8         reserved_at_80[0x20];
8232
8233         u8         rmac_47_16[0x20];
8234
8235         u8         rmac_15_0[0x10];
8236         u8         tclass[0x8];
8237         u8         hop_limit[0x8];
8238
8239         u8         reserved_at_e0[0x1];
8240         u8         grh[0x1];
8241         u8         reserved_at_e2[0x2];
8242         u8         src_addr_index[0x8];
8243         u8         flow_label[0x14];
8244
8245         u8         rgid_rip[16][0x8];
8246 };
8247
8248 struct mlx5_ifc_pages_req_event_bits {
8249         u8         reserved_at_0[0x10];
8250         u8         function_id[0x10];
8251
8252         u8         num_pages[0x20];
8253
8254         u8         reserved_at_40[0xa0];
8255 };
8256
8257 struct mlx5_ifc_eqe_bits {
8258         u8         reserved_at_0[0x8];
8259         u8         event_type[0x8];
8260         u8         reserved_at_10[0x8];
8261         u8         event_sub_type[0x8];
8262
8263         u8         reserved_at_20[0xe0];
8264
8265         union mlx5_ifc_event_auto_bits event_data;
8266
8267         u8         reserved_at_1e0[0x10];
8268         u8         signature[0x8];
8269         u8         reserved_at_1f8[0x7];
8270         u8         owner[0x1];
8271 };
8272
8273 enum {
8274         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8275 };
8276
8277 struct mlx5_ifc_cmd_queue_entry_bits {
8278         u8         type[0x8];
8279         u8         reserved_at_8[0x18];
8280
8281         u8         input_length[0x20];
8282
8283         u8         input_mailbox_pointer_63_32[0x20];
8284
8285         u8         input_mailbox_pointer_31_9[0x17];
8286         u8         reserved_at_77[0x9];
8287
8288         u8         command_input_inline_data[16][0x8];
8289
8290         u8         command_output_inline_data[16][0x8];
8291
8292         u8         output_mailbox_pointer_63_32[0x20];
8293
8294         u8         output_mailbox_pointer_31_9[0x17];
8295         u8         reserved_at_1b7[0x9];
8296
8297         u8         output_length[0x20];
8298
8299         u8         token[0x8];
8300         u8         signature[0x8];
8301         u8         reserved_at_1f0[0x8];
8302         u8         status[0x7];
8303         u8         ownership[0x1];
8304 };
8305
8306 struct mlx5_ifc_cmd_out_bits {
8307         u8         status[0x8];
8308         u8         reserved_at_8[0x18];
8309
8310         u8         syndrome[0x20];
8311
8312         u8         command_output[0x20];
8313 };
8314
8315 struct mlx5_ifc_cmd_in_bits {
8316         u8         opcode[0x10];
8317         u8         reserved_at_10[0x10];
8318
8319         u8         reserved_at_20[0x10];
8320         u8         op_mod[0x10];
8321
8322         u8         command[0][0x20];
8323 };
8324
8325 struct mlx5_ifc_cmd_if_box_bits {
8326         u8         mailbox_data[512][0x8];
8327
8328         u8         reserved_at_1000[0x180];
8329
8330         u8         next_pointer_63_32[0x20];
8331
8332         u8         next_pointer_31_10[0x16];
8333         u8         reserved_at_11b6[0xa];
8334
8335         u8         block_number[0x20];
8336
8337         u8         reserved_at_11e0[0x8];
8338         u8         token[0x8];
8339         u8         ctrl_signature[0x8];
8340         u8         signature[0x8];
8341 };
8342
8343 struct mlx5_ifc_mtt_bits {
8344         u8         ptag_63_32[0x20];
8345
8346         u8         ptag_31_8[0x18];
8347         u8         reserved_at_38[0x6];
8348         u8         wr_en[0x1];
8349         u8         rd_en[0x1];
8350 };
8351
8352 struct mlx5_ifc_query_wol_rol_out_bits {
8353         u8         status[0x8];
8354         u8         reserved_at_8[0x18];
8355
8356         u8         syndrome[0x20];
8357
8358         u8         reserved_at_40[0x10];
8359         u8         rol_mode[0x8];
8360         u8         wol_mode[0x8];
8361
8362         u8         reserved_at_60[0x20];
8363 };
8364
8365 struct mlx5_ifc_query_wol_rol_in_bits {
8366         u8         opcode[0x10];
8367         u8         reserved_at_10[0x10];
8368
8369         u8         reserved_at_20[0x10];
8370         u8         op_mod[0x10];
8371
8372         u8         reserved_at_40[0x40];
8373 };
8374
8375 struct mlx5_ifc_set_wol_rol_out_bits {
8376         u8         status[0x8];
8377         u8         reserved_at_8[0x18];
8378
8379         u8         syndrome[0x20];
8380
8381         u8         reserved_at_40[0x40];
8382 };
8383
8384 struct mlx5_ifc_set_wol_rol_in_bits {
8385         u8         opcode[0x10];
8386         u8         reserved_at_10[0x10];
8387
8388         u8         reserved_at_20[0x10];
8389         u8         op_mod[0x10];
8390
8391         u8         rol_mode_valid[0x1];
8392         u8         wol_mode_valid[0x1];
8393         u8         reserved_at_42[0xe];
8394         u8         rol_mode[0x8];
8395         u8         wol_mode[0x8];
8396
8397         u8         reserved_at_60[0x20];
8398 };
8399
8400 enum {
8401         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8402         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8403         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8404 };
8405
8406 enum {
8407         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8408         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8409         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8410 };
8411
8412 enum {
8413         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8414         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8415         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8416         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8417         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8418         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8419         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8420         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8421         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8422         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8423         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8424 };
8425
8426 struct mlx5_ifc_initial_seg_bits {
8427         u8         fw_rev_minor[0x10];
8428         u8         fw_rev_major[0x10];
8429
8430         u8         cmd_interface_rev[0x10];
8431         u8         fw_rev_subminor[0x10];
8432
8433         u8         reserved_at_40[0x40];
8434
8435         u8         cmdq_phy_addr_63_32[0x20];
8436
8437         u8         cmdq_phy_addr_31_12[0x14];
8438         u8         reserved_at_b4[0x2];
8439         u8         nic_interface[0x2];
8440         u8         log_cmdq_size[0x4];
8441         u8         log_cmdq_stride[0x4];
8442
8443         u8         command_doorbell_vector[0x20];
8444
8445         u8         reserved_at_e0[0xf00];
8446
8447         u8         initializing[0x1];
8448         u8         reserved_at_fe1[0x4];
8449         u8         nic_interface_supported[0x3];
8450         u8         reserved_at_fe8[0x18];
8451
8452         struct mlx5_ifc_health_buffer_bits health_buffer;
8453
8454         u8         no_dram_nic_offset[0x20];
8455
8456         u8         reserved_at_1220[0x6e40];
8457
8458         u8         reserved_at_8060[0x1f];
8459         u8         clear_int[0x1];
8460
8461         u8         health_syndrome[0x8];
8462         u8         health_counter[0x18];
8463
8464         u8         reserved_at_80a0[0x17fc0];
8465 };
8466
8467 struct mlx5_ifc_mtpps_reg_bits {
8468         u8         reserved_at_0[0xc];
8469         u8         cap_number_of_pps_pins[0x4];
8470         u8         reserved_at_10[0x4];
8471         u8         cap_max_num_of_pps_in_pins[0x4];
8472         u8         reserved_at_18[0x4];
8473         u8         cap_max_num_of_pps_out_pins[0x4];
8474
8475         u8         reserved_at_20[0x24];
8476         u8         cap_pin_3_mode[0x4];
8477         u8         reserved_at_48[0x4];
8478         u8         cap_pin_2_mode[0x4];
8479         u8         reserved_at_50[0x4];
8480         u8         cap_pin_1_mode[0x4];
8481         u8         reserved_at_58[0x4];
8482         u8         cap_pin_0_mode[0x4];
8483
8484         u8         reserved_at_60[0x4];
8485         u8         cap_pin_7_mode[0x4];
8486         u8         reserved_at_68[0x4];
8487         u8         cap_pin_6_mode[0x4];
8488         u8         reserved_at_70[0x4];
8489         u8         cap_pin_5_mode[0x4];
8490         u8         reserved_at_78[0x4];
8491         u8         cap_pin_4_mode[0x4];
8492
8493         u8         field_select[0x20];
8494         u8         reserved_at_a0[0x60];
8495
8496         u8         enable[0x1];
8497         u8         reserved_at_101[0xb];
8498         u8         pattern[0x4];
8499         u8         reserved_at_110[0x4];
8500         u8         pin_mode[0x4];
8501         u8         pin[0x8];
8502
8503         u8         reserved_at_120[0x20];
8504
8505         u8         time_stamp[0x40];
8506
8507         u8         out_pulse_duration[0x10];
8508         u8         out_periodic_adjustment[0x10];
8509         u8         enhanced_out_periodic_adjustment[0x20];
8510
8511         u8         reserved_at_1c0[0x20];
8512 };
8513
8514 struct mlx5_ifc_mtppse_reg_bits {
8515         u8         reserved_at_0[0x18];
8516         u8         pin[0x8];
8517         u8         event_arm[0x1];
8518         u8         reserved_at_21[0x1b];
8519         u8         event_generation_mode[0x4];
8520         u8         reserved_at_40[0x40];
8521 };
8522
8523 struct mlx5_ifc_mcqi_cap_bits {
8524         u8         supported_info_bitmask[0x20];
8525
8526         u8         component_size[0x20];
8527
8528         u8         max_component_size[0x20];
8529
8530         u8         log_mcda_word_size[0x4];
8531         u8         reserved_at_64[0xc];
8532         u8         mcda_max_write_size[0x10];
8533
8534         u8         rd_en[0x1];
8535         u8         reserved_at_81[0x1];
8536         u8         match_chip_id[0x1];
8537         u8         match_psid[0x1];
8538         u8         check_user_timestamp[0x1];
8539         u8         match_base_guid_mac[0x1];
8540         u8         reserved_at_86[0x1a];
8541 };
8542
8543 struct mlx5_ifc_mcqi_reg_bits {
8544         u8         read_pending_component[0x1];
8545         u8         reserved_at_1[0xf];
8546         u8         component_index[0x10];
8547
8548         u8         reserved_at_20[0x20];
8549
8550         u8         reserved_at_40[0x1b];
8551         u8         info_type[0x5];
8552
8553         u8         info_size[0x20];
8554
8555         u8         offset[0x20];
8556
8557         u8         reserved_at_a0[0x10];
8558         u8         data_size[0x10];
8559
8560         u8         data[0][0x20];
8561 };
8562
8563 struct mlx5_ifc_mcc_reg_bits {
8564         u8         reserved_at_0[0x4];
8565         u8         time_elapsed_since_last_cmd[0xc];
8566         u8         reserved_at_10[0x8];
8567         u8         instruction[0x8];
8568
8569         u8         reserved_at_20[0x10];
8570         u8         component_index[0x10];
8571
8572         u8         reserved_at_40[0x8];
8573         u8         update_handle[0x18];
8574
8575         u8         handle_owner_type[0x4];
8576         u8         handle_owner_host_id[0x4];
8577         u8         reserved_at_68[0x1];
8578         u8         control_progress[0x7];
8579         u8         error_code[0x8];
8580         u8         reserved_at_78[0x4];
8581         u8         control_state[0x4];
8582
8583         u8         component_size[0x20];
8584
8585         u8         reserved_at_a0[0x60];
8586 };
8587
8588 struct mlx5_ifc_mcda_reg_bits {
8589         u8         reserved_at_0[0x8];
8590         u8         update_handle[0x18];
8591
8592         u8         offset[0x20];
8593
8594         u8         reserved_at_40[0x10];
8595         u8         size[0x10];
8596
8597         u8         reserved_at_60[0x20];
8598
8599         u8         data[0][0x20];
8600 };
8601
8602 union mlx5_ifc_ports_control_registers_document_bits {
8603         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8604         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8605         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8606         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8607         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8608         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8609         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8610         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8611         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8612         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8613         struct mlx5_ifc_paos_reg_bits paos_reg;
8614         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8615         struct mlx5_ifc_peir_reg_bits peir_reg;
8616         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8617         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8618         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8619         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8620         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8621         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8622         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8623         struct mlx5_ifc_plib_reg_bits plib_reg;
8624         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8625         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8626         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8627         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8628         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8629         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8630         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8631         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8632         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8633         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8634         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8635         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8636         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8637         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8638         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8639         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8640         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8641         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8642         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8643         struct mlx5_ifc_pude_reg_bits pude_reg;
8644         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8645         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8646         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8647         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8648         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8649         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8650         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8651         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8652         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8653         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8654         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8655         u8         reserved_at_0[0x60e0];
8656 };
8657
8658 union mlx5_ifc_debug_enhancements_document_bits {
8659         struct mlx5_ifc_health_buffer_bits health_buffer;
8660         u8         reserved_at_0[0x200];
8661 };
8662
8663 union mlx5_ifc_uplink_pci_interface_document_bits {
8664         struct mlx5_ifc_initial_seg_bits initial_seg;
8665         u8         reserved_at_0[0x20060];
8666 };
8667
8668 struct mlx5_ifc_set_flow_table_root_out_bits {
8669         u8         status[0x8];
8670         u8         reserved_at_8[0x18];
8671
8672         u8         syndrome[0x20];
8673
8674         u8         reserved_at_40[0x40];
8675 };
8676
8677 struct mlx5_ifc_set_flow_table_root_in_bits {
8678         u8         opcode[0x10];
8679         u8         reserved_at_10[0x10];
8680
8681         u8         reserved_at_20[0x10];
8682         u8         op_mod[0x10];
8683
8684         u8         other_vport[0x1];
8685         u8         reserved_at_41[0xf];
8686         u8         vport_number[0x10];
8687
8688         u8         reserved_at_60[0x20];
8689
8690         u8         table_type[0x8];
8691         u8         reserved_at_88[0x18];
8692
8693         u8         reserved_at_a0[0x8];
8694         u8         table_id[0x18];
8695
8696         u8         reserved_at_c0[0x8];
8697         u8         underlay_qpn[0x18];
8698         u8         reserved_at_e0[0x120];
8699 };
8700
8701 enum {
8702         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8703         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8704 };
8705
8706 struct mlx5_ifc_modify_flow_table_out_bits {
8707         u8         status[0x8];
8708         u8         reserved_at_8[0x18];
8709
8710         u8         syndrome[0x20];
8711
8712         u8         reserved_at_40[0x40];
8713 };
8714
8715 struct mlx5_ifc_modify_flow_table_in_bits {
8716         u8         opcode[0x10];
8717         u8         reserved_at_10[0x10];
8718
8719         u8         reserved_at_20[0x10];
8720         u8         op_mod[0x10];
8721
8722         u8         other_vport[0x1];
8723         u8         reserved_at_41[0xf];
8724         u8         vport_number[0x10];
8725
8726         u8         reserved_at_60[0x10];
8727         u8         modify_field_select[0x10];
8728
8729         u8         table_type[0x8];
8730         u8         reserved_at_88[0x18];
8731
8732         u8         reserved_at_a0[0x8];
8733         u8         table_id[0x18];
8734
8735         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8736 };
8737
8738 struct mlx5_ifc_ets_tcn_config_reg_bits {
8739         u8         g[0x1];
8740         u8         b[0x1];
8741         u8         r[0x1];
8742         u8         reserved_at_3[0x9];
8743         u8         group[0x4];
8744         u8         reserved_at_10[0x9];
8745         u8         bw_allocation[0x7];
8746
8747         u8         reserved_at_20[0xc];
8748         u8         max_bw_units[0x4];
8749         u8         reserved_at_30[0x8];
8750         u8         max_bw_value[0x8];
8751 };
8752
8753 struct mlx5_ifc_ets_global_config_reg_bits {
8754         u8         reserved_at_0[0x2];
8755         u8         r[0x1];
8756         u8         reserved_at_3[0x1d];
8757
8758         u8         reserved_at_20[0xc];
8759         u8         max_bw_units[0x4];
8760         u8         reserved_at_30[0x8];
8761         u8         max_bw_value[0x8];
8762 };
8763
8764 struct mlx5_ifc_qetc_reg_bits {
8765         u8                                         reserved_at_0[0x8];
8766         u8                                         port_number[0x8];
8767         u8                                         reserved_at_10[0x30];
8768
8769         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8770         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8771 };
8772
8773 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8774         u8         e[0x1];
8775         u8         reserved_at_01[0x0b];
8776         u8         prio[0x04];
8777 };
8778
8779 struct mlx5_ifc_qpdpm_reg_bits {
8780         u8                                     reserved_at_0[0x8];
8781         u8                                     local_port[0x8];
8782         u8                                     reserved_at_10[0x10];
8783         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8784 };
8785
8786 struct mlx5_ifc_qpts_reg_bits {
8787         u8         reserved_at_0[0x8];
8788         u8         local_port[0x8];
8789         u8         reserved_at_10[0x2d];
8790         u8         trust_state[0x3];
8791 };
8792
8793 struct mlx5_ifc_qtct_reg_bits {
8794         u8         reserved_at_0[0x8];
8795         u8         port_number[0x8];
8796         u8         reserved_at_10[0xd];
8797         u8         prio[0x3];
8798
8799         u8         reserved_at_20[0x1d];
8800         u8         tclass[0x3];
8801 };
8802
8803 struct mlx5_ifc_mcia_reg_bits {
8804         u8         l[0x1];
8805         u8         reserved_at_1[0x7];
8806         u8         module[0x8];
8807         u8         reserved_at_10[0x8];
8808         u8         status[0x8];
8809
8810         u8         i2c_device_address[0x8];
8811         u8         page_number[0x8];
8812         u8         device_address[0x10];
8813
8814         u8         reserved_at_40[0x10];
8815         u8         size[0x10];
8816
8817         u8         reserved_at_60[0x20];
8818
8819         u8         dword_0[0x20];
8820         u8         dword_1[0x20];
8821         u8         dword_2[0x20];
8822         u8         dword_3[0x20];
8823         u8         dword_4[0x20];
8824         u8         dword_5[0x20];
8825         u8         dword_6[0x20];
8826         u8         dword_7[0x20];
8827         u8         dword_8[0x20];
8828         u8         dword_9[0x20];
8829         u8         dword_10[0x20];
8830         u8         dword_11[0x20];
8831 };
8832
8833 struct mlx5_ifc_dcbx_param_bits {
8834         u8         dcbx_cee_cap[0x1];
8835         u8         dcbx_ieee_cap[0x1];
8836         u8         dcbx_standby_cap[0x1];
8837         u8         reserved_at_0[0x5];
8838         u8         port_number[0x8];
8839         u8         reserved_at_10[0xa];
8840         u8         max_application_table_size[6];
8841         u8         reserved_at_20[0x15];
8842         u8         version_oper[0x3];
8843         u8         reserved_at_38[5];
8844         u8         version_admin[0x3];
8845         u8         willing_admin[0x1];
8846         u8         reserved_at_41[0x3];
8847         u8         pfc_cap_oper[0x4];
8848         u8         reserved_at_48[0x4];
8849         u8         pfc_cap_admin[0x4];
8850         u8         reserved_at_50[0x4];
8851         u8         num_of_tc_oper[0x4];
8852         u8         reserved_at_58[0x4];
8853         u8         num_of_tc_admin[0x4];
8854         u8         remote_willing[0x1];
8855         u8         reserved_at_61[3];
8856         u8         remote_pfc_cap[4];
8857         u8         reserved_at_68[0x14];
8858         u8         remote_num_of_tc[0x4];
8859         u8         reserved_at_80[0x18];
8860         u8         error[0x8];
8861         u8         reserved_at_a0[0x160];
8862 };
8863
8864 struct mlx5_ifc_lagc_bits {
8865         u8         reserved_at_0[0x1d];
8866         u8         lag_state[0x3];
8867
8868         u8         reserved_at_20[0x14];
8869         u8         tx_remap_affinity_2[0x4];
8870         u8         reserved_at_38[0x4];
8871         u8         tx_remap_affinity_1[0x4];
8872 };
8873
8874 struct mlx5_ifc_create_lag_out_bits {
8875         u8         status[0x8];
8876         u8         reserved_at_8[0x18];
8877
8878         u8         syndrome[0x20];
8879
8880         u8         reserved_at_40[0x40];
8881 };
8882
8883 struct mlx5_ifc_create_lag_in_bits {
8884         u8         opcode[0x10];
8885         u8         reserved_at_10[0x10];
8886
8887         u8         reserved_at_20[0x10];
8888         u8         op_mod[0x10];
8889
8890         struct mlx5_ifc_lagc_bits ctx;
8891 };
8892
8893 struct mlx5_ifc_modify_lag_out_bits {
8894         u8         status[0x8];
8895         u8         reserved_at_8[0x18];
8896
8897         u8         syndrome[0x20];
8898
8899         u8         reserved_at_40[0x40];
8900 };
8901
8902 struct mlx5_ifc_modify_lag_in_bits {
8903         u8         opcode[0x10];
8904         u8         reserved_at_10[0x10];
8905
8906         u8         reserved_at_20[0x10];
8907         u8         op_mod[0x10];
8908
8909         u8         reserved_at_40[0x20];
8910         u8         field_select[0x20];
8911
8912         struct mlx5_ifc_lagc_bits ctx;
8913 };
8914
8915 struct mlx5_ifc_query_lag_out_bits {
8916         u8         status[0x8];
8917         u8         reserved_at_8[0x18];
8918
8919         u8         syndrome[0x20];
8920
8921         u8         reserved_at_40[0x40];
8922
8923         struct mlx5_ifc_lagc_bits ctx;
8924 };
8925
8926 struct mlx5_ifc_query_lag_in_bits {
8927         u8         opcode[0x10];
8928         u8         reserved_at_10[0x10];
8929
8930         u8         reserved_at_20[0x10];
8931         u8         op_mod[0x10];
8932
8933         u8         reserved_at_40[0x40];
8934 };
8935
8936 struct mlx5_ifc_destroy_lag_out_bits {
8937         u8         status[0x8];
8938         u8         reserved_at_8[0x18];
8939
8940         u8         syndrome[0x20];
8941
8942         u8         reserved_at_40[0x40];
8943 };
8944
8945 struct mlx5_ifc_destroy_lag_in_bits {
8946         u8         opcode[0x10];
8947         u8         reserved_at_10[0x10];
8948
8949         u8         reserved_at_20[0x10];
8950         u8         op_mod[0x10];
8951
8952         u8         reserved_at_40[0x40];
8953 };
8954
8955 struct mlx5_ifc_create_vport_lag_out_bits {
8956         u8         status[0x8];
8957         u8         reserved_at_8[0x18];
8958
8959         u8         syndrome[0x20];
8960
8961         u8         reserved_at_40[0x40];
8962 };
8963
8964 struct mlx5_ifc_create_vport_lag_in_bits {
8965         u8         opcode[0x10];
8966         u8         reserved_at_10[0x10];
8967
8968         u8         reserved_at_20[0x10];
8969         u8         op_mod[0x10];
8970
8971         u8         reserved_at_40[0x40];
8972 };
8973
8974 struct mlx5_ifc_destroy_vport_lag_out_bits {
8975         u8         status[0x8];
8976         u8         reserved_at_8[0x18];
8977
8978         u8         syndrome[0x20];
8979
8980         u8         reserved_at_40[0x40];
8981 };
8982
8983 struct mlx5_ifc_destroy_vport_lag_in_bits {
8984         u8         opcode[0x10];
8985         u8         reserved_at_10[0x10];
8986
8987         u8         reserved_at_20[0x10];
8988         u8         op_mod[0x10];
8989
8990         u8         reserved_at_40[0x40];
8991 };
8992
8993 struct mlx5_ifc_alloc_memic_in_bits {
8994         u8         opcode[0x10];
8995         u8         reserved_at_10[0x10];
8996
8997         u8         reserved_at_20[0x10];
8998         u8         op_mod[0x10];
8999
9000         u8         reserved_at_30[0x20];
9001
9002         u8         reserved_at_40[0x18];
9003         u8         log_memic_addr_alignment[0x8];
9004
9005         u8         range_start_addr[0x40];
9006
9007         u8         range_size[0x20];
9008
9009         u8         memic_size[0x20];
9010 };
9011
9012 struct mlx5_ifc_alloc_memic_out_bits {
9013         u8         status[0x8];
9014         u8         reserved_at_8[0x18];
9015
9016         u8         syndrome[0x20];
9017
9018         u8         memic_start_addr[0x40];
9019 };
9020
9021 struct mlx5_ifc_dealloc_memic_in_bits {
9022         u8         opcode[0x10];
9023         u8         reserved_at_10[0x10];
9024
9025         u8         reserved_at_20[0x10];
9026         u8         op_mod[0x10];
9027
9028         u8         reserved_at_40[0x40];
9029
9030         u8         memic_start_addr[0x40];
9031
9032         u8         memic_size[0x20];
9033
9034         u8         reserved_at_e0[0x20];
9035 };
9036
9037 struct mlx5_ifc_dealloc_memic_out_bits {
9038         u8         status[0x8];
9039         u8         reserved_at_8[0x18];
9040
9041         u8         syndrome[0x20];
9042
9043         u8         reserved_at_40[0x40];
9044 };
9045
9046 #endif /* MLX5_IFC_H */