include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  80         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  81         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  82         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  83         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  84         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  85         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  86         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  87         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  88         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  89         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  90         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  91         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  92         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  93         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  94         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  95         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  96         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
  97         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
  98         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  99         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 100         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 101         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 102         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 103         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 104         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 105         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 106         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 107         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 108         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 109         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 110         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 111         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 112         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 113         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 114         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 115         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 116         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 117         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 118         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 119         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 120         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 121         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 122         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 123         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 124         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 125         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 126         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 127         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 128         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 129         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 130         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 131         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 132         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 133         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 134         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 135         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 136         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 137         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 138         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 139         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 140         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 141         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 142         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 143         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 144         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 146         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 147         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 148         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 149         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 150         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 151         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 152         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 153         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 154         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 155         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 156         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 157         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 158         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 159         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 160         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 161         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 162         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 163         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 164         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 165         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 166         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 167         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 168         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 169         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 170         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 171         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 172         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 173         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 174         MLX5_CMD_OP_NOP                           = 0x80d,
 175         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 176         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 177         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 178         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 179         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 180         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 181         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 182         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 183         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 184         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 185         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 186         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 187         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 188         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 189         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 190         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 191         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 192         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 193         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 194         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 195         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 196         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 197         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 198         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 199         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 200         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 201         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 202         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 203         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 204         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 205         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 206         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 207         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 208         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 209         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 210         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 211         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 212         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 213         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 214         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 215         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 216         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 217         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 218         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 219         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 220         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 221         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 222         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 223         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 224         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 225         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 226         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 227         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 228         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 229         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 230         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 231         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 232         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 233         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 234         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 235         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 236         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 237         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 238         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 239         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 240         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 241         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 242         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 243         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 244         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 245         MLX5_CMD_OP_MAX
 246 };
 247
 248 struct mlx5_ifc_flow_table_fields_supported_bits {
 249         u8         outer_dmac[0x1];
 250         u8         outer_smac[0x1];
 251         u8         outer_ether_type[0x1];
 252         u8         outer_ip_version[0x1];
 253         u8         outer_first_prio[0x1];
 254         u8         outer_first_cfi[0x1];
 255         u8         outer_first_vid[0x1];
 256         u8         outer_ipv4_ttl[0x1];
 257         u8         outer_second_prio[0x1];
 258         u8         outer_second_cfi[0x1];
 259         u8         outer_second_vid[0x1];
 260         u8         reserved_at_b[0x1];
 261         u8         outer_sip[0x1];
 262         u8         outer_dip[0x1];
 263         u8         outer_frag[0x1];
 264         u8         outer_ip_protocol[0x1];
 265         u8         outer_ip_ecn[0x1];
 266         u8         outer_ip_dscp[0x1];
 267         u8         outer_udp_sport[0x1];
 268         u8         outer_udp_dport[0x1];
 269         u8         outer_tcp_sport[0x1];
 270         u8         outer_tcp_dport[0x1];
 271         u8         outer_tcp_flags[0x1];
 272         u8         outer_gre_protocol[0x1];
 273         u8         outer_gre_key[0x1];
 274         u8         outer_vxlan_vni[0x1];
 275         u8         reserved_at_1a[0x5];
 276         u8         source_eswitch_port[0x1];
 277
 278         u8         inner_dmac[0x1];
 279         u8         inner_smac[0x1];
 280         u8         inner_ether_type[0x1];
 281         u8         inner_ip_version[0x1];
 282         u8         inner_first_prio[0x1];
 283         u8         inner_first_cfi[0x1];
 284         u8         inner_first_vid[0x1];
 285         u8         reserved_at_27[0x1];
 286         u8         inner_second_prio[0x1];
 287         u8         inner_second_cfi[0x1];
 288         u8         inner_second_vid[0x1];
 289         u8         reserved_at_2b[0x1];
 290         u8         inner_sip[0x1];
 291         u8         inner_dip[0x1];
 292         u8         inner_frag[0x1];
 293         u8         inner_ip_protocol[0x1];
 294         u8         inner_ip_ecn[0x1];
 295         u8         inner_ip_dscp[0x1];
 296         u8         inner_udp_sport[0x1];
 297         u8         inner_udp_dport[0x1];
 298         u8         inner_tcp_sport[0x1];
 299         u8         inner_tcp_dport[0x1];
 300         u8         inner_tcp_flags[0x1];
 301         u8         reserved_at_37[0x9];
 302
 303         u8         reserved_at_40[0x5];
 304         u8         outer_first_mpls_over_udp[0x4];
 305         u8         outer_first_mpls_over_gre[0x4];
 306         u8         inner_first_mpls[0x4];
 307         u8         outer_first_mpls[0x4];
 308         u8         reserved_at_55[0x2];
 309         u8         outer_esp_spi[0x1];
 310         u8         reserved_at_58[0x2];
 311         u8         bth_dst_qp[0x1];
 312
 313         u8         reserved_at_5b[0x25];
 314 };
 315
 316 struct mlx5_ifc_flow_table_prop_layout_bits {
 317         u8         ft_support[0x1];
 318         u8         reserved_at_1[0x1];
 319         u8         flow_counter[0x1];
 320         u8         flow_modify_en[0x1];
 321         u8         modify_root[0x1];
 322         u8         identified_miss_table_mode[0x1];
 323         u8         flow_table_modify[0x1];
 324         u8         encap[0x1];
 325         u8         decap[0x1];
 326         u8         reserved_at_9[0x1];
 327         u8         pop_vlan[0x1];
 328         u8         push_vlan[0x1];
 329         u8         reserved_at_c[0x14];
 330
 331         u8         reserved_at_20[0x2];
 332         u8         log_max_ft_size[0x6];
 333         u8         log_max_modify_header_context[0x8];
 334         u8         max_modify_header_actions[0x8];
 335         u8         max_ft_level[0x8];
 336
 337         u8         reserved_at_40[0x20];
 338
 339         u8         reserved_at_60[0x18];
 340         u8         log_max_ft_num[0x8];
 341
 342         u8         reserved_at_80[0x18];
 343         u8         log_max_destination[0x8];
 344
 345         u8         log_max_flow_counter[0x8];
 346         u8         reserved_at_a8[0x10];
 347         u8         log_max_flow[0x8];
 348
 349         u8         reserved_at_c0[0x40];
 350
 351         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 352
 353         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 354 };
 355
 356 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 357         u8         send[0x1];
 358         u8         receive[0x1];
 359         u8         write[0x1];
 360         u8         read[0x1];
 361         u8         atomic[0x1];
 362         u8         srq_receive[0x1];
 363         u8         reserved_at_6[0x1a];
 364 };
 365
 366 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 367         u8         smac_47_16[0x20];
 368
 369         u8         smac_15_0[0x10];
 370         u8         ethertype[0x10];
 371
 372         u8         dmac_47_16[0x20];
 373
 374         u8         dmac_15_0[0x10];
 375         u8         first_prio[0x3];
 376         u8         first_cfi[0x1];
 377         u8         first_vid[0xc];
 378
 379         u8         ip_protocol[0x8];
 380         u8         ip_dscp[0x6];
 381         u8         ip_ecn[0x2];
 382         u8         cvlan_tag[0x1];
 383         u8         svlan_tag[0x1];
 384         u8         frag[0x1];
 385         u8         ip_version[0x4];
 386         u8         tcp_flags[0x9];
 387
 388         u8         tcp_sport[0x10];
 389         u8         tcp_dport[0x10];
 390
 391         u8         reserved_at_c0[0x18];
 392         u8         ttl_hoplimit[0x8];
 393
 394         u8         udp_sport[0x10];
 395         u8         udp_dport[0x10];
 396
 397         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 398
 399         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 400 };
 401
 402 struct mlx5_ifc_fte_match_set_misc_bits {
 403         u8         reserved_at_0[0x8];
 404         u8         source_sqn[0x18];
 405
 406         u8         source_eswitch_owner_vhca_id[0x10];
 407         u8         source_port[0x10];
 408
 409         u8         outer_second_prio[0x3];
 410         u8         outer_second_cfi[0x1];
 411         u8         outer_second_vid[0xc];
 412         u8         inner_second_prio[0x3];
 413         u8         inner_second_cfi[0x1];
 414         u8         inner_second_vid[0xc];
 415
 416         u8         outer_second_cvlan_tag[0x1];
 417         u8         inner_second_cvlan_tag[0x1];
 418         u8         outer_second_svlan_tag[0x1];
 419         u8         inner_second_svlan_tag[0x1];
 420         u8         reserved_at_64[0xc];
 421         u8         gre_protocol[0x10];
 422
 423         u8         gre_key_h[0x18];
 424         u8         gre_key_l[0x8];
 425
 426         u8         vxlan_vni[0x18];
 427         u8         reserved_at_b8[0x8];
 428
 429         u8         reserved_at_c0[0x20];
 430
 431         u8         reserved_at_e0[0xc];
 432         u8         outer_ipv6_flow_label[0x14];
 433
 434         u8         reserved_at_100[0xc];
 435         u8         inner_ipv6_flow_label[0x14];
 436
 437         u8         reserved_at_120[0x28];
 438         u8         bth_dst_qp[0x18];
 439         u8         reserved_at_160[0x20];
 440         u8         outer_esp_spi[0x20];
 441         u8         reserved_at_1a0[0x60];
 442 };
 443
 444 struct mlx5_ifc_fte_match_mpls_bits {
 445         u8         mpls_label[0x14];
 446         u8         mpls_exp[0x3];
 447         u8         mpls_s_bos[0x1];
 448         u8         mpls_ttl[0x8];
 449 };
 450
 451 struct mlx5_ifc_fte_match_set_misc2_bits {
 452         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 453
 454         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 455
 456         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 457
 458         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 459
 460         u8         reserved_at_80[0x100];
 461
 462         u8         metadata_reg_a[0x20];
 463
 464         u8         reserved_at_1a0[0x60];
 465 };
 466
 467 struct mlx5_ifc_cmd_pas_bits {
 468         u8         pa_h[0x20];
 469
 470         u8         pa_l[0x14];
 471         u8         reserved_at_34[0xc];
 472 };
 473
 474 struct mlx5_ifc_uint64_bits {
 475         u8         hi[0x20];
 476
 477         u8         lo[0x20];
 478 };
 479
 480 enum {
 481         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 482         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 483         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 484         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 485         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 486         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 487         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 488         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 489         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 490         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 491 };
 492
 493 struct mlx5_ifc_ads_bits {
 494         u8         fl[0x1];
 495         u8         free_ar[0x1];
 496         u8         reserved_at_2[0xe];
 497         u8         pkey_index[0x10];
 498
 499         u8         reserved_at_20[0x8];
 500         u8         grh[0x1];
 501         u8         mlid[0x7];
 502         u8         rlid[0x10];
 503
 504         u8         ack_timeout[0x5];
 505         u8         reserved_at_45[0x3];
 506         u8         src_addr_index[0x8];
 507         u8         reserved_at_50[0x4];
 508         u8         stat_rate[0x4];
 509         u8         hop_limit[0x8];
 510
 511         u8         reserved_at_60[0x4];
 512         u8         tclass[0x8];
 513         u8         flow_label[0x14];
 514
 515         u8         rgid_rip[16][0x8];
 516
 517         u8         reserved_at_100[0x4];
 518         u8         f_dscp[0x1];
 519         u8         f_ecn[0x1];
 520         u8         reserved_at_106[0x1];
 521         u8         f_eth_prio[0x1];
 522         u8         ecn[0x2];
 523         u8         dscp[0x6];
 524         u8         udp_sport[0x10];
 525
 526         u8         dei_cfi[0x1];
 527         u8         eth_prio[0x3];
 528         u8         sl[0x4];
 529         u8         vhca_port_num[0x8];
 530         u8         rmac_47_32[0x10];
 531
 532         u8         rmac_31_0[0x20];
 533 };
 534
 535 struct mlx5_ifc_flow_table_nic_cap_bits {
 536         u8         nic_rx_multi_path_tirs[0x1];
 537         u8         nic_rx_multi_path_tirs_fts[0x1];
 538         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 539         u8         reserved_at_3[0x1fd];
 540
 541         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 542
 543         u8         reserved_at_400[0x200];
 544
 545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 546
 547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 548
 549         u8         reserved_at_a00[0x200];
 550
 551         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 552
 553         u8         reserved_at_e00[0x7200];
 554 };
 555
 556 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 557         u8      reserved_at_0[0x1c];
 558         u8      fdb_multi_path_to_table[0x1];
 559         u8      reserved_at_1d[0x1e3];
 560
 561         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 562
 563         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 564
 565         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 566
 567         u8      reserved_at_800[0x7800];
 568 };
 569
 570 struct mlx5_ifc_e_switch_cap_bits {
 571         u8         vport_svlan_strip[0x1];
 572         u8         vport_cvlan_strip[0x1];
 573         u8         vport_svlan_insert[0x1];
 574         u8         vport_cvlan_insert_if_not_exist[0x1];
 575         u8         vport_cvlan_insert_overwrite[0x1];
 576         u8         reserved_at_5[0x18];
 577         u8         merged_eswitch[0x1];
 578         u8         nic_vport_node_guid_modify[0x1];
 579         u8         nic_vport_port_guid_modify[0x1];
 580
 581         u8         vxlan_encap_decap[0x1];
 582         u8         nvgre_encap_decap[0x1];
 583         u8         reserved_at_22[0x9];
 584         u8         log_max_encap_headers[0x5];
 585         u8         reserved_2b[0x6];
 586         u8         max_encap_header_size[0xa];
 587
 588         u8         reserved_40[0x7c0];
 589
 590 };
 591
 592 struct mlx5_ifc_qos_cap_bits {
 593         u8         packet_pacing[0x1];
 594         u8         esw_scheduling[0x1];
 595         u8         esw_bw_share[0x1];
 596         u8         esw_rate_limit[0x1];
 597         u8         reserved_at_4[0x1];
 598         u8         packet_pacing_burst_bound[0x1];
 599         u8         packet_pacing_typical_size[0x1];
 600         u8         reserved_at_7[0x19];
 601
 602         u8         reserved_at_20[0x20];
 603
 604         u8         packet_pacing_max_rate[0x20];
 605
 606         u8         packet_pacing_min_rate[0x20];
 607
 608         u8         reserved_at_80[0x10];
 609         u8         packet_pacing_rate_table_size[0x10];
 610
 611         u8         esw_element_type[0x10];
 612         u8         esw_tsar_type[0x10];
 613
 614         u8         reserved_at_c0[0x10];
 615         u8         max_qos_para_vport[0x10];
 616
 617         u8         max_tsar_bw_share[0x20];
 618
 619         u8         reserved_at_100[0x700];
 620 };
 621
 622 struct mlx5_ifc_debug_cap_bits {
 623         u8         reserved_at_0[0x20];
 624
 625         u8         reserved_at_20[0x2];
 626         u8         stall_detect[0x1];
 627         u8         reserved_at_23[0x1d];
 628
 629         u8         reserved_at_40[0x7c0];
 630 };
 631
 632 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 633         u8         csum_cap[0x1];
 634         u8         vlan_cap[0x1];
 635         u8         lro_cap[0x1];
 636         u8         lro_psh_flag[0x1];
 637         u8         lro_time_stamp[0x1];
 638         u8         reserved_at_5[0x2];
 639         u8         wqe_vlan_insert[0x1];
 640         u8         self_lb_en_modifiable[0x1];
 641         u8         reserved_at_9[0x2];
 642         u8         max_lso_cap[0x5];
 643         u8         multi_pkt_send_wqe[0x2];
 644         u8         wqe_inline_mode[0x2];
 645         u8         rss_ind_tbl_cap[0x4];
 646         u8         reg_umr_sq[0x1];
 647         u8         scatter_fcs[0x1];
 648         u8         enhanced_multi_pkt_send_wqe[0x1];
 649         u8         tunnel_lso_const_out_ip_id[0x1];
 650         u8         reserved_at_1c[0x2];
 651         u8         tunnel_stateless_gre[0x1];
 652         u8         tunnel_stateless_vxlan[0x1];
 653
 654         u8         swp[0x1];
 655         u8         swp_csum[0x1];
 656         u8         swp_lso[0x1];
 657         u8         reserved_at_23[0x1b];
 658         u8         max_geneve_opt_len[0x1];
 659         u8         tunnel_stateless_geneve_rx[0x1];
 660
 661         u8         reserved_at_40[0x10];
 662         u8         lro_min_mss_size[0x10];
 663
 664         u8         reserved_at_60[0x120];
 665
 666         u8         lro_timer_supported_periods[4][0x20];
 667
 668         u8         reserved_at_200[0x600];
 669 };
 670
 671 struct mlx5_ifc_roce_cap_bits {
 672         u8         roce_apm[0x1];
 673         u8         reserved_at_1[0x1f];
 674
 675         u8         reserved_at_20[0x60];
 676
 677         u8         reserved_at_80[0xc];
 678         u8         l3_type[0x4];
 679         u8         reserved_at_90[0x8];
 680         u8         roce_version[0x8];
 681
 682         u8         reserved_at_a0[0x10];
 683         u8         r_roce_dest_udp_port[0x10];
 684
 685         u8         r_roce_max_src_udp_port[0x10];
 686         u8         r_roce_min_src_udp_port[0x10];
 687
 688         u8         reserved_at_e0[0x10];
 689         u8         roce_address_table_size[0x10];
 690
 691         u8         reserved_at_100[0x700];
 692 };
 693
 694 struct mlx5_ifc_device_mem_cap_bits {
 695         u8         memic[0x1];
 696         u8         reserved_at_1[0x1f];
 697
 698         u8         reserved_at_20[0xb];
 699         u8         log_min_memic_alloc_size[0x5];
 700         u8         reserved_at_30[0x8];
 701         u8         log_max_memic_addr_alignment[0x8];
 702
 703         u8         memic_bar_start_addr[0x40];
 704
 705         u8         memic_bar_size[0x20];
 706
 707         u8         max_memic_size[0x20];
 708
 709         u8         reserved_at_c0[0x740];
 710 };
 711
 712 enum {
 713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 717         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 718         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 719         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 720         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 721         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 722 };
 723
 724 enum {
 725         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 726         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 727         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 728         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 729         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 730         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 733         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 734 };
 735
 736 struct mlx5_ifc_atomic_caps_bits {
 737         u8         reserved_at_0[0x40];
 738
 739         u8         atomic_req_8B_endianness_mode[0x2];
 740         u8         reserved_at_42[0x4];
 741         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 742
 743         u8         reserved_at_47[0x19];
 744
 745         u8         reserved_at_60[0x20];
 746
 747         u8         reserved_at_80[0x10];
 748         u8         atomic_operations[0x10];
 749
 750         u8         reserved_at_a0[0x10];
 751         u8         atomic_size_qp[0x10];
 752
 753         u8         reserved_at_c0[0x10];
 754         u8         atomic_size_dc[0x10];
 755
 756         u8         reserved_at_e0[0x720];
 757 };
 758
 759 struct mlx5_ifc_odp_cap_bits {
 760         u8         reserved_at_0[0x40];
 761
 762         u8         sig[0x1];
 763         u8         reserved_at_41[0x1f];
 764
 765         u8         reserved_at_60[0x20];
 766
 767         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 768
 769         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 770
 771         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 772
 773         u8         reserved_at_e0[0x720];
 774 };
 775
 776 struct mlx5_ifc_calc_op {
 777         u8        reserved_at_0[0x10];
 778         u8        reserved_at_10[0x9];
 779         u8        op_swap_endianness[0x1];
 780         u8        op_min[0x1];
 781         u8        op_xor[0x1];
 782         u8        op_or[0x1];
 783         u8        op_and[0x1];
 784         u8        op_max[0x1];
 785         u8        op_add[0x1];
 786 };
 787
 788 struct mlx5_ifc_vector_calc_cap_bits {
 789         u8         calc_matrix[0x1];
 790         u8         reserved_at_1[0x1f];
 791         u8         reserved_at_20[0x8];
 792         u8         max_vec_count[0x8];
 793         u8         reserved_at_30[0xd];
 794         u8         max_chunk_size[0x3];
 795         struct mlx5_ifc_calc_op calc0;
 796         struct mlx5_ifc_calc_op calc1;
 797         struct mlx5_ifc_calc_op calc2;
 798         struct mlx5_ifc_calc_op calc3;
 799
 800         u8         reserved_at_e0[0x720];
 801 };
 802
 803 enum {
 804         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 805         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 806         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 807         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 808 };
 809
 810 enum {
 811         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 812         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 813 };
 814
 815 enum {
 816         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 817         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 818         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 819         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 820         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 821 };
 822
 823 enum {
 824         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 825         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 826         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 827         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 828         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 829         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 830 };
 831
 832 enum {
 833         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 834         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 835 };
 836
 837 enum {
 838         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 839         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 840         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 841 };
 842
 843 enum {
 844         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 845         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 846 };
 847
 848 enum {
 849         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 850         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 851         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 852 };
 853
 854 struct mlx5_ifc_cmd_hca_cap_bits {
 855         u8         reserved_at_0[0x30];
 856         u8         vhca_id[0x10];
 857
 858         u8         reserved_at_40[0x40];
 859
 860         u8         log_max_srq_sz[0x8];
 861         u8         log_max_qp_sz[0x8];
 862         u8         reserved_at_90[0xb];
 863         u8         log_max_qp[0x5];
 864
 865         u8         reserved_at_a0[0xb];
 866         u8         log_max_srq[0x5];
 867         u8         reserved_at_b0[0x10];
 868
 869         u8         reserved_at_c0[0x8];
 870         u8         log_max_cq_sz[0x8];
 871         u8         reserved_at_d0[0xb];
 872         u8         log_max_cq[0x5];
 873
 874         u8         log_max_eq_sz[0x8];
 875         u8         reserved_at_e8[0x2];
 876         u8         log_max_mkey[0x6];
 877         u8         reserved_at_f0[0xc];
 878         u8         log_max_eq[0x4];
 879
 880         u8         max_indirection[0x8];
 881         u8         fixed_buffer_size[0x1];
 882         u8         log_max_mrw_sz[0x7];
 883         u8         force_teardown[0x1];
 884         u8         reserved_at_111[0x1];
 885         u8         log_max_bsf_list_size[0x6];
 886         u8         umr_extended_translation_offset[0x1];
 887         u8         null_mkey[0x1];
 888         u8         log_max_klm_list_size[0x6];
 889
 890         u8         reserved_at_120[0xa];
 891         u8         log_max_ra_req_dc[0x6];
 892         u8         reserved_at_130[0xa];
 893         u8         log_max_ra_res_dc[0x6];
 894
 895         u8         reserved_at_140[0xa];
 896         u8         log_max_ra_req_qp[0x6];
 897         u8         reserved_at_150[0xa];
 898         u8         log_max_ra_res_qp[0x6];
 899
 900         u8         end_pad[0x1];
 901         u8         cc_query_allowed[0x1];
 902         u8         cc_modify_allowed[0x1];
 903         u8         start_pad[0x1];
 904         u8         cache_line_128byte[0x1];
 905         u8         reserved_at_165[0xa];
 906         u8         qcam_reg[0x1];
 907         u8         gid_table_size[0x10];
 908
 909         u8         out_of_seq_cnt[0x1];
 910         u8         vport_counters[0x1];
 911         u8         retransmission_q_counters[0x1];
 912         u8         debug[0x1];
 913         u8         modify_rq_counter_set_id[0x1];
 914         u8         rq_delay_drop[0x1];
 915         u8         max_qp_cnt[0xa];
 916         u8         pkey_table_size[0x10];
 917
 918         u8         vport_group_manager[0x1];
 919         u8         vhca_group_manager[0x1];
 920         u8         ib_virt[0x1];
 921         u8         eth_virt[0x1];
 922         u8         vnic_env_queue_counters[0x1];
 923         u8         ets[0x1];
 924         u8         nic_flow_table[0x1];
 925         u8         eswitch_flow_table[0x1];
 926         u8         device_memory[0x1];
 927         u8         mcam_reg[0x1];
 928         u8         pcam_reg[0x1];
 929         u8         local_ca_ack_delay[0x5];
 930         u8         port_module_event[0x1];
 931         u8         enhanced_error_q_counters[0x1];
 932         u8         ports_check[0x1];
 933         u8         reserved_at_1b3[0x1];
 934         u8         disable_link_up[0x1];
 935         u8         beacon_led[0x1];
 936         u8         port_type[0x2];
 937         u8         num_ports[0x8];
 938
 939         u8         reserved_at_1c0[0x1];
 940         u8         pps[0x1];
 941         u8         pps_modify[0x1];
 942         u8         log_max_msg[0x5];
 943         u8         reserved_at_1c8[0x4];
 944         u8         max_tc[0x4];
 945         u8         temp_warn_event[0x1];
 946         u8         dcbx[0x1];
 947         u8         general_notification_event[0x1];
 948         u8         reserved_at_1d3[0x2];
 949         u8         fpga[0x1];
 950         u8         rol_s[0x1];
 951         u8         rol_g[0x1];
 952         u8         reserved_at_1d8[0x1];
 953         u8         wol_s[0x1];
 954         u8         wol_g[0x1];
 955         u8         wol_a[0x1];
 956         u8         wol_b[0x1];
 957         u8         wol_m[0x1];
 958         u8         wol_u[0x1];
 959         u8         wol_p[0x1];
 960
 961         u8         stat_rate_support[0x10];
 962         u8         reserved_at_1f0[0xc];
 963         u8         cqe_version[0x4];
 964
 965         u8         compact_address_vector[0x1];
 966         u8         striding_rq[0x1];
 967         u8         reserved_at_202[0x1];
 968         u8         ipoib_enhanced_offloads[0x1];
 969         u8         ipoib_basic_offloads[0x1];
 970         u8         reserved_at_205[0x1];
 971         u8         repeated_block_disabled[0x1];
 972         u8         umr_modify_entity_size_disabled[0x1];
 973         u8         umr_modify_atomic_disabled[0x1];
 974         u8         umr_indirect_mkey_disabled[0x1];
 975         u8         umr_fence[0x2];
 976         u8         reserved_at_20c[0x3];
 977         u8         drain_sigerr[0x1];
 978         u8         cmdif_checksum[0x2];
 979         u8         sigerr_cqe[0x1];
 980         u8         reserved_at_213[0x1];
 981         u8         wq_signature[0x1];
 982         u8         sctr_data_cqe[0x1];
 983         u8         reserved_at_216[0x1];
 984         u8         sho[0x1];
 985         u8         tph[0x1];
 986         u8         rf[0x1];
 987         u8         dct[0x1];
 988         u8         qos[0x1];
 989         u8         eth_net_offloads[0x1];
 990         u8         roce[0x1];
 991         u8         atomic[0x1];
 992         u8         reserved_at_21f[0x1];
 993
 994         u8         cq_oi[0x1];
 995         u8         cq_resize[0x1];
 996         u8         cq_moderation[0x1];
 997         u8         reserved_at_223[0x3];
 998         u8         cq_eq_remap[0x1];
 999         u8         pg[0x1];
1000         u8         block_lb_mc[0x1];
1001         u8         reserved_at_229[0x1];
1002         u8         scqe_break_moderation[0x1];
1003         u8         cq_period_start_from_cqe[0x1];
1004         u8         cd[0x1];
1005         u8         reserved_at_22d[0x1];
1006         u8         apm[0x1];
1007         u8         vector_calc[0x1];
1008         u8         umr_ptr_rlky[0x1];
1009         u8         imaicl[0x1];
1010         u8         reserved_at_232[0x4];
1011         u8         qkv[0x1];
1012         u8         pkv[0x1];
1013         u8         set_deth_sqpn[0x1];
1014         u8         reserved_at_239[0x3];
1015         u8         xrc[0x1];
1016         u8         ud[0x1];
1017         u8         uc[0x1];
1018         u8         rc[0x1];
1019
1020         u8         uar_4k[0x1];
1021         u8         reserved_at_241[0x9];
1022         u8         uar_sz[0x6];
1023         u8         reserved_at_250[0x8];
1024         u8         log_pg_sz[0x8];
1025
1026         u8         bf[0x1];
1027         u8         driver_version[0x1];
1028         u8         pad_tx_eth_packet[0x1];
1029         u8         reserved_at_263[0x8];
1030         u8         log_bf_reg_size[0x5];
1031
1032         u8         reserved_at_270[0xb];
1033         u8         lag_master[0x1];
1034         u8         num_lag_ports[0x4];
1035
1036         u8         reserved_at_280[0x10];
1037         u8         max_wqe_sz_sq[0x10];
1038
1039         u8         reserved_at_2a0[0x10];
1040         u8         max_wqe_sz_rq[0x10];
1041
1042         u8         max_flow_counter_31_16[0x10];
1043         u8         max_wqe_sz_sq_dc[0x10];
1044
1045         u8         reserved_at_2e0[0x7];
1046         u8         max_qp_mcg[0x19];
1047
1048         u8         reserved_at_300[0x18];
1049         u8         log_max_mcg[0x8];
1050
1051         u8         reserved_at_320[0x3];
1052         u8         log_max_transport_domain[0x5];
1053         u8         reserved_at_328[0x3];
1054         u8         log_max_pd[0x5];
1055         u8         reserved_at_330[0xb];
1056         u8         log_max_xrcd[0x5];
1057
1058         u8         nic_receive_steering_discard[0x1];
1059         u8         receive_discard_vport_down[0x1];
1060         u8         transmit_discard_vport_down[0x1];
1061         u8         reserved_at_343[0x5];
1062         u8         log_max_flow_counter_bulk[0x8];
1063         u8         max_flow_counter_15_0[0x10];
1064
1065
1066         u8         reserved_at_360[0x3];
1067         u8         log_max_rq[0x5];
1068         u8         reserved_at_368[0x3];
1069         u8         log_max_sq[0x5];
1070         u8         reserved_at_370[0x3];
1071         u8         log_max_tir[0x5];
1072         u8         reserved_at_378[0x3];
1073         u8         log_max_tis[0x5];
1074
1075         u8         basic_cyclic_rcv_wqe[0x1];
1076         u8         reserved_at_381[0x2];
1077         u8         log_max_rmp[0x5];
1078         u8         reserved_at_388[0x3];
1079         u8         log_max_rqt[0x5];
1080         u8         reserved_at_390[0x3];
1081         u8         log_max_rqt_size[0x5];
1082         u8         reserved_at_398[0x3];
1083         u8         log_max_tis_per_sq[0x5];
1084
1085         u8         ext_stride_num_range[0x1];
1086         u8         reserved_at_3a1[0x2];
1087         u8         log_max_stride_sz_rq[0x5];
1088         u8         reserved_at_3a8[0x3];
1089         u8         log_min_stride_sz_rq[0x5];
1090         u8         reserved_at_3b0[0x3];
1091         u8         log_max_stride_sz_sq[0x5];
1092         u8         reserved_at_3b8[0x3];
1093         u8         log_min_stride_sz_sq[0x5];
1094
1095         u8         hairpin[0x1];
1096         u8         reserved_at_3c1[0x2];
1097         u8         log_max_hairpin_queues[0x5];
1098         u8         reserved_at_3c8[0x3];
1099         u8         log_max_hairpin_wq_data_sz[0x5];
1100         u8         reserved_at_3d0[0x3];
1101         u8         log_max_hairpin_num_packets[0x5];
1102         u8         reserved_at_3d8[0x3];
1103         u8         log_max_wq_sz[0x5];
1104
1105         u8         nic_vport_change_event[0x1];
1106         u8         disable_local_lb_uc[0x1];
1107         u8         disable_local_lb_mc[0x1];
1108         u8         log_min_hairpin_wq_data_sz[0x5];
1109         u8         reserved_at_3e8[0x3];
1110         u8         log_max_vlan_list[0x5];
1111         u8         reserved_at_3f0[0x3];
1112         u8         log_max_current_mc_list[0x5];
1113         u8         reserved_at_3f8[0x3];
1114         u8         log_max_current_uc_list[0x5];
1115
1116         u8         reserved_at_400[0x80];
1117
1118         u8         reserved_at_480[0x3];
1119         u8         log_max_l2_table[0x5];
1120         u8         reserved_at_488[0x8];
1121         u8         log_uar_page_sz[0x10];
1122
1123         u8         reserved_at_4a0[0x20];
1124         u8         device_frequency_mhz[0x20];
1125         u8         device_frequency_khz[0x20];
1126
1127         u8         reserved_at_500[0x20];
1128         u8         num_of_uars_per_page[0x20];
1129
1130         u8         flex_parser_protocols[0x20];
1131         u8         reserved_at_560[0x20];
1132
1133         u8         reserved_at_580[0x3c];
1134         u8         mini_cqe_resp_stride_index[0x1];
1135         u8         cqe_128_always[0x1];
1136         u8         cqe_compression_128[0x1];
1137         u8         cqe_compression[0x1];
1138
1139         u8         cqe_compression_timeout[0x10];
1140         u8         cqe_compression_max_num[0x10];
1141
1142         u8         reserved_at_5e0[0x10];
1143         u8         tag_matching[0x1];
1144         u8         rndv_offload_rc[0x1];
1145         u8         rndv_offload_dc[0x1];
1146         u8         log_tag_matching_list_sz[0x5];
1147         u8         reserved_at_5f8[0x3];
1148         u8         log_max_xrq[0x5];
1149
1150         u8         affiliate_nic_vport_criteria[0x8];
1151         u8         native_port_num[0x8];
1152         u8         num_vhca_ports[0x8];
1153         u8         reserved_at_618[0x6];
1154         u8         sw_owner_id[0x1];
1155         u8         reserved_at_61f[0x1e1];
1156 };
1157
1158 enum mlx5_flow_destination_type {
1159         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1160         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1161         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1162
1163         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1164         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1165 };
1166
1167 struct mlx5_ifc_dest_format_struct_bits {
1168         u8         destination_type[0x8];
1169         u8         destination_id[0x18];
1170         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1171         u8         reserved_at_21[0xf];
1172         u8         destination_eswitch_owner_vhca_id[0x10];
1173 };
1174
1175 struct mlx5_ifc_flow_counter_list_bits {
1176         u8         flow_counter_id[0x20];
1177
1178         u8         reserved_at_20[0x20];
1179 };
1180
1181 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1182         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1183         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1184         u8         reserved_at_0[0x40];
1185 };
1186
1187 struct mlx5_ifc_fte_match_param_bits {
1188         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1189
1190         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1191
1192         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1193
1194         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1195
1196         u8         reserved_at_800[0x800];
1197 };
1198
1199 enum {
1200         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1201         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1202         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1203         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1204         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1205 };
1206
1207 struct mlx5_ifc_rx_hash_field_select_bits {
1208         u8         l3_prot_type[0x1];
1209         u8         l4_prot_type[0x1];
1210         u8         selected_fields[0x1e];
1211 };
1212
1213 enum {
1214         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1215         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1216 };
1217
1218 enum {
1219         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1220         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1221 };
1222
1223 struct mlx5_ifc_wq_bits {
1224         u8         wq_type[0x4];
1225         u8         wq_signature[0x1];
1226         u8         end_padding_mode[0x2];
1227         u8         cd_slave[0x1];
1228         u8         reserved_at_8[0x18];
1229
1230         u8         hds_skip_first_sge[0x1];
1231         u8         log2_hds_buf_size[0x3];
1232         u8         reserved_at_24[0x7];
1233         u8         page_offset[0x5];
1234         u8         lwm[0x10];
1235
1236         u8         reserved_at_40[0x8];
1237         u8         pd[0x18];
1238
1239         u8         reserved_at_60[0x8];
1240         u8         uar_page[0x18];
1241
1242         u8         dbr_addr[0x40];
1243
1244         u8         hw_counter[0x20];
1245
1246         u8         sw_counter[0x20];
1247
1248         u8         reserved_at_100[0xc];
1249         u8         log_wq_stride[0x4];
1250         u8         reserved_at_110[0x3];
1251         u8         log_wq_pg_sz[0x5];
1252         u8         reserved_at_118[0x3];
1253         u8         log_wq_sz[0x5];
1254
1255         u8         reserved_at_120[0x3];
1256         u8         log_hairpin_num_packets[0x5];
1257         u8         reserved_at_128[0x3];
1258         u8         log_hairpin_data_sz[0x5];
1259
1260         u8         reserved_at_130[0x4];
1261         u8         log_wqe_num_of_strides[0x4];
1262         u8         two_byte_shift_en[0x1];
1263         u8         reserved_at_139[0x4];
1264         u8         log_wqe_stride_size[0x3];
1265
1266         u8         reserved_at_140[0x4c0];
1267
1268         struct mlx5_ifc_cmd_pas_bits pas[0];
1269 };
1270
1271 struct mlx5_ifc_rq_num_bits {
1272         u8         reserved_at_0[0x8];
1273         u8         rq_num[0x18];
1274 };
1275
1276 struct mlx5_ifc_mac_address_layout_bits {
1277         u8         reserved_at_0[0x10];
1278         u8         mac_addr_47_32[0x10];
1279
1280         u8         mac_addr_31_0[0x20];
1281 };
1282
1283 struct mlx5_ifc_vlan_layout_bits {
1284         u8         reserved_at_0[0x14];
1285         u8         vlan[0x0c];
1286
1287         u8         reserved_at_20[0x20];
1288 };
1289
1290 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1291         u8         reserved_at_0[0xa0];
1292
1293         u8         min_time_between_cnps[0x20];
1294
1295         u8         reserved_at_c0[0x12];
1296         u8         cnp_dscp[0x6];
1297         u8         reserved_at_d8[0x4];
1298         u8         cnp_prio_mode[0x1];
1299         u8         cnp_802p_prio[0x3];
1300
1301         u8         reserved_at_e0[0x720];
1302 };
1303
1304 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1305         u8         reserved_at_0[0x60];
1306
1307         u8         reserved_at_60[0x4];
1308         u8         clamp_tgt_rate[0x1];
1309         u8         reserved_at_65[0x3];
1310         u8         clamp_tgt_rate_after_time_inc[0x1];
1311         u8         reserved_at_69[0x17];
1312
1313         u8         reserved_at_80[0x20];
1314
1315         u8         rpg_time_reset[0x20];
1316
1317         u8         rpg_byte_reset[0x20];
1318
1319         u8         rpg_threshold[0x20];
1320
1321         u8         rpg_max_rate[0x20];
1322
1323         u8         rpg_ai_rate[0x20];
1324
1325         u8         rpg_hai_rate[0x20];
1326
1327         u8         rpg_gd[0x20];
1328
1329         u8         rpg_min_dec_fac[0x20];
1330
1331         u8         rpg_min_rate[0x20];
1332
1333         u8         reserved_at_1c0[0xe0];
1334
1335         u8         rate_to_set_on_first_cnp[0x20];
1336
1337         u8         dce_tcp_g[0x20];
1338
1339         u8         dce_tcp_rtt[0x20];
1340
1341         u8         rate_reduce_monitor_period[0x20];
1342
1343         u8         reserved_at_320[0x20];
1344
1345         u8         initial_alpha_value[0x20];
1346
1347         u8         reserved_at_360[0x4a0];
1348 };
1349
1350 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1351         u8         reserved_at_0[0x80];
1352
1353         u8         rppp_max_rps[0x20];
1354
1355         u8         rpg_time_reset[0x20];
1356
1357         u8         rpg_byte_reset[0x20];
1358
1359         u8         rpg_threshold[0x20];
1360
1361         u8         rpg_max_rate[0x20];
1362
1363         u8         rpg_ai_rate[0x20];
1364
1365         u8         rpg_hai_rate[0x20];
1366
1367         u8         rpg_gd[0x20];
1368
1369         u8         rpg_min_dec_fac[0x20];
1370
1371         u8         rpg_min_rate[0x20];
1372
1373         u8         reserved_at_1c0[0x640];
1374 };
1375
1376 enum {
1377         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1378         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1379         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1380 };
1381
1382 struct mlx5_ifc_resize_field_select_bits {
1383         u8         resize_field_select[0x20];
1384 };
1385
1386 enum {
1387         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1388         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1389         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1390         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1391 };
1392
1393 struct mlx5_ifc_modify_field_select_bits {
1394         u8         modify_field_select[0x20];
1395 };
1396
1397 struct mlx5_ifc_field_select_r_roce_np_bits {
1398         u8         field_select_r_roce_np[0x20];
1399 };
1400
1401 struct mlx5_ifc_field_select_r_roce_rp_bits {
1402         u8         field_select_r_roce_rp[0x20];
1403 };
1404
1405 enum {
1406         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1407         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1408         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1409         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1410         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1411         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1412         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1413         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1414         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1415         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1416 };
1417
1418 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1419         u8         field_select_8021qaurp[0x20];
1420 };
1421
1422 struct mlx5_ifc_phys_layer_cntrs_bits {
1423         u8         time_since_last_clear_high[0x20];
1424
1425         u8         time_since_last_clear_low[0x20];
1426
1427         u8         symbol_errors_high[0x20];
1428
1429         u8         symbol_errors_low[0x20];
1430
1431         u8         sync_headers_errors_high[0x20];
1432
1433         u8         sync_headers_errors_low[0x20];
1434
1435         u8         edpl_bip_errors_lane0_high[0x20];
1436
1437         u8         edpl_bip_errors_lane0_low[0x20];
1438
1439         u8         edpl_bip_errors_lane1_high[0x20];
1440
1441         u8         edpl_bip_errors_lane1_low[0x20];
1442
1443         u8         edpl_bip_errors_lane2_high[0x20];
1444
1445         u8         edpl_bip_errors_lane2_low[0x20];
1446
1447         u8         edpl_bip_errors_lane3_high[0x20];
1448
1449         u8         edpl_bip_errors_lane3_low[0x20];
1450
1451         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1452
1453         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1454
1455         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1456
1457         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1458
1459         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1460
1461         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1462
1463         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1464
1465         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1466
1467         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1468
1469         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1470
1471         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1472
1473         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1474
1475         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1476
1477         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1478
1479         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1480
1481         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1482
1483         u8         rs_fec_corrected_blocks_high[0x20];
1484
1485         u8         rs_fec_corrected_blocks_low[0x20];
1486
1487         u8         rs_fec_uncorrectable_blocks_high[0x20];
1488
1489         u8         rs_fec_uncorrectable_blocks_low[0x20];
1490
1491         u8         rs_fec_no_errors_blocks_high[0x20];
1492
1493         u8         rs_fec_no_errors_blocks_low[0x20];
1494
1495         u8         rs_fec_single_error_blocks_high[0x20];
1496
1497         u8         rs_fec_single_error_blocks_low[0x20];
1498
1499         u8         rs_fec_corrected_symbols_total_high[0x20];
1500
1501         u8         rs_fec_corrected_symbols_total_low[0x20];
1502
1503         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1504
1505         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1506
1507         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1508
1509         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1510
1511         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1512
1513         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1514
1515         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1516
1517         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1518
1519         u8         link_down_events[0x20];
1520
1521         u8         successful_recovery_events[0x20];
1522
1523         u8         reserved_at_640[0x180];
1524 };
1525
1526 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1527         u8         time_since_last_clear_high[0x20];
1528
1529         u8         time_since_last_clear_low[0x20];
1530
1531         u8         phy_received_bits_high[0x20];
1532
1533         u8         phy_received_bits_low[0x20];
1534
1535         u8         phy_symbol_errors_high[0x20];
1536
1537         u8         phy_symbol_errors_low[0x20];
1538
1539         u8         phy_corrected_bits_high[0x20];
1540
1541         u8         phy_corrected_bits_low[0x20];
1542
1543         u8         phy_corrected_bits_lane0_high[0x20];
1544
1545         u8         phy_corrected_bits_lane0_low[0x20];
1546
1547         u8         phy_corrected_bits_lane1_high[0x20];
1548
1549         u8         phy_corrected_bits_lane1_low[0x20];
1550
1551         u8         phy_corrected_bits_lane2_high[0x20];
1552
1553         u8         phy_corrected_bits_lane2_low[0x20];
1554
1555         u8         phy_corrected_bits_lane3_high[0x20];
1556
1557         u8         phy_corrected_bits_lane3_low[0x20];
1558
1559         u8         reserved_at_200[0x5c0];
1560 };
1561
1562 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1563         u8         symbol_error_counter[0x10];
1564
1565         u8         link_error_recovery_counter[0x8];
1566
1567         u8         link_downed_counter[0x8];
1568
1569         u8         port_rcv_errors[0x10];
1570
1571         u8         port_rcv_remote_physical_errors[0x10];
1572
1573         u8         port_rcv_switch_relay_errors[0x10];
1574
1575         u8         port_xmit_discards[0x10];
1576
1577         u8         port_xmit_constraint_errors[0x8];
1578
1579         u8         port_rcv_constraint_errors[0x8];
1580
1581         u8         reserved_at_70[0x8];
1582
1583         u8         link_overrun_errors[0x8];
1584
1585         u8         reserved_at_80[0x10];
1586
1587         u8         vl_15_dropped[0x10];
1588
1589         u8         reserved_at_a0[0x80];
1590
1591         u8         port_xmit_wait[0x20];
1592 };
1593
1594 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1595         u8         transmit_queue_high[0x20];
1596
1597         u8         transmit_queue_low[0x20];
1598
1599         u8         reserved_at_40[0x780];
1600 };
1601
1602 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1603         u8         rx_octets_high[0x20];
1604
1605         u8         rx_octets_low[0x20];
1606
1607         u8         reserved_at_40[0xc0];
1608
1609         u8         rx_frames_high[0x20];
1610
1611         u8         rx_frames_low[0x20];
1612
1613         u8         tx_octets_high[0x20];
1614
1615         u8         tx_octets_low[0x20];
1616
1617         u8         reserved_at_180[0xc0];
1618
1619         u8         tx_frames_high[0x20];
1620
1621         u8         tx_frames_low[0x20];
1622
1623         u8         rx_pause_high[0x20];
1624
1625         u8         rx_pause_low[0x20];
1626
1627         u8         rx_pause_duration_high[0x20];
1628
1629         u8         rx_pause_duration_low[0x20];
1630
1631         u8         tx_pause_high[0x20];
1632
1633         u8         tx_pause_low[0x20];
1634
1635         u8         tx_pause_duration_high[0x20];
1636
1637         u8         tx_pause_duration_low[0x20];
1638
1639         u8         rx_pause_transition_high[0x20];
1640
1641         u8         rx_pause_transition_low[0x20];
1642
1643         u8         reserved_at_3c0[0x40];
1644
1645         u8         device_stall_minor_watermark_cnt_high[0x20];
1646
1647         u8         device_stall_minor_watermark_cnt_low[0x20];
1648
1649         u8         device_stall_critical_watermark_cnt_high[0x20];
1650
1651         u8         device_stall_critical_watermark_cnt_low[0x20];
1652
1653         u8         reserved_at_480[0x340];
1654 };
1655
1656 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1657         u8         port_transmit_wait_high[0x20];
1658
1659         u8         port_transmit_wait_low[0x20];
1660
1661         u8         reserved_at_40[0x100];
1662
1663         u8         rx_buffer_almost_full_high[0x20];
1664
1665         u8         rx_buffer_almost_full_low[0x20];
1666
1667         u8         rx_buffer_full_high[0x20];
1668
1669         u8         rx_buffer_full_low[0x20];
1670
1671         u8         reserved_at_1c0[0x600];
1672 };
1673
1674 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1675         u8         dot3stats_alignment_errors_high[0x20];
1676
1677         u8         dot3stats_alignment_errors_low[0x20];
1678
1679         u8         dot3stats_fcs_errors_high[0x20];
1680
1681         u8         dot3stats_fcs_errors_low[0x20];
1682
1683         u8         dot3stats_single_collision_frames_high[0x20];
1684
1685         u8         dot3stats_single_collision_frames_low[0x20];
1686
1687         u8         dot3stats_multiple_collision_frames_high[0x20];
1688
1689         u8         dot3stats_multiple_collision_frames_low[0x20];
1690
1691         u8         dot3stats_sqe_test_errors_high[0x20];
1692
1693         u8         dot3stats_sqe_test_errors_low[0x20];
1694
1695         u8         dot3stats_deferred_transmissions_high[0x20];
1696
1697         u8         dot3stats_deferred_transmissions_low[0x20];
1698
1699         u8         dot3stats_late_collisions_high[0x20];
1700
1701         u8         dot3stats_late_collisions_low[0x20];
1702
1703         u8         dot3stats_excessive_collisions_high[0x20];
1704
1705         u8         dot3stats_excessive_collisions_low[0x20];
1706
1707         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1708
1709         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1710
1711         u8         dot3stats_carrier_sense_errors_high[0x20];
1712
1713         u8         dot3stats_carrier_sense_errors_low[0x20];
1714
1715         u8         dot3stats_frame_too_longs_high[0x20];
1716
1717         u8         dot3stats_frame_too_longs_low[0x20];
1718
1719         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1720
1721         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1722
1723         u8         dot3stats_symbol_errors_high[0x20];
1724
1725         u8         dot3stats_symbol_errors_low[0x20];
1726
1727         u8         dot3control_in_unknown_opcodes_high[0x20];
1728
1729         u8         dot3control_in_unknown_opcodes_low[0x20];
1730
1731         u8         dot3in_pause_frames_high[0x20];
1732
1733         u8         dot3in_pause_frames_low[0x20];
1734
1735         u8         dot3out_pause_frames_high[0x20];
1736
1737         u8         dot3out_pause_frames_low[0x20];
1738
1739         u8         reserved_at_400[0x3c0];
1740 };
1741
1742 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1743         u8         ether_stats_drop_events_high[0x20];
1744
1745         u8         ether_stats_drop_events_low[0x20];
1746
1747         u8         ether_stats_octets_high[0x20];
1748
1749         u8         ether_stats_octets_low[0x20];
1750
1751         u8         ether_stats_pkts_high[0x20];
1752
1753         u8         ether_stats_pkts_low[0x20];
1754
1755         u8         ether_stats_broadcast_pkts_high[0x20];
1756
1757         u8         ether_stats_broadcast_pkts_low[0x20];
1758
1759         u8         ether_stats_multicast_pkts_high[0x20];
1760
1761         u8         ether_stats_multicast_pkts_low[0x20];
1762
1763         u8         ether_stats_crc_align_errors_high[0x20];
1764
1765         u8         ether_stats_crc_align_errors_low[0x20];
1766
1767         u8         ether_stats_undersize_pkts_high[0x20];
1768
1769         u8         ether_stats_undersize_pkts_low[0x20];
1770
1771         u8         ether_stats_oversize_pkts_high[0x20];
1772
1773         u8         ether_stats_oversize_pkts_low[0x20];
1774
1775         u8         ether_stats_fragments_high[0x20];
1776
1777         u8         ether_stats_fragments_low[0x20];
1778
1779         u8         ether_stats_jabbers_high[0x20];
1780
1781         u8         ether_stats_jabbers_low[0x20];
1782
1783         u8         ether_stats_collisions_high[0x20];
1784
1785         u8         ether_stats_collisions_low[0x20];
1786
1787         u8         ether_stats_pkts64octets_high[0x20];
1788
1789         u8         ether_stats_pkts64octets_low[0x20];
1790
1791         u8         ether_stats_pkts65to127octets_high[0x20];
1792
1793         u8         ether_stats_pkts65to127octets_low[0x20];
1794
1795         u8         ether_stats_pkts128to255octets_high[0x20];
1796
1797         u8         ether_stats_pkts128to255octets_low[0x20];
1798
1799         u8         ether_stats_pkts256to511octets_high[0x20];
1800
1801         u8         ether_stats_pkts256to511octets_low[0x20];
1802
1803         u8         ether_stats_pkts512to1023octets_high[0x20];
1804
1805         u8         ether_stats_pkts512to1023octets_low[0x20];
1806
1807         u8         ether_stats_pkts1024to1518octets_high[0x20];
1808
1809         u8         ether_stats_pkts1024to1518octets_low[0x20];
1810
1811         u8         ether_stats_pkts1519to2047octets_high[0x20];
1812
1813         u8         ether_stats_pkts1519to2047octets_low[0x20];
1814
1815         u8         ether_stats_pkts2048to4095octets_high[0x20];
1816
1817         u8         ether_stats_pkts2048to4095octets_low[0x20];
1818
1819         u8         ether_stats_pkts4096to8191octets_high[0x20];
1820
1821         u8         ether_stats_pkts4096to8191octets_low[0x20];
1822
1823         u8         ether_stats_pkts8192to10239octets_high[0x20];
1824
1825         u8         ether_stats_pkts8192to10239octets_low[0x20];
1826
1827         u8         reserved_at_540[0x280];
1828 };
1829
1830 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1831         u8         if_in_octets_high[0x20];
1832
1833         u8         if_in_octets_low[0x20];
1834
1835         u8         if_in_ucast_pkts_high[0x20];
1836
1837         u8         if_in_ucast_pkts_low[0x20];
1838
1839         u8         if_in_discards_high[0x20];
1840
1841         u8         if_in_discards_low[0x20];
1842
1843         u8         if_in_errors_high[0x20];
1844
1845         u8         if_in_errors_low[0x20];
1846
1847         u8         if_in_unknown_protos_high[0x20];
1848
1849         u8         if_in_unknown_protos_low[0x20];
1850
1851         u8         if_out_octets_high[0x20];
1852
1853         u8         if_out_octets_low[0x20];
1854
1855         u8         if_out_ucast_pkts_high[0x20];
1856
1857         u8         if_out_ucast_pkts_low[0x20];
1858
1859         u8         if_out_discards_high[0x20];
1860
1861         u8         if_out_discards_low[0x20];
1862
1863         u8         if_out_errors_high[0x20];
1864
1865         u8         if_out_errors_low[0x20];
1866
1867         u8         if_in_multicast_pkts_high[0x20];
1868
1869         u8         if_in_multicast_pkts_low[0x20];
1870
1871         u8         if_in_broadcast_pkts_high[0x20];
1872
1873         u8         if_in_broadcast_pkts_low[0x20];
1874
1875         u8         if_out_multicast_pkts_high[0x20];
1876
1877         u8         if_out_multicast_pkts_low[0x20];
1878
1879         u8         if_out_broadcast_pkts_high[0x20];
1880
1881         u8         if_out_broadcast_pkts_low[0x20];
1882
1883         u8         reserved_at_340[0x480];
1884 };
1885
1886 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1887         u8         a_frames_transmitted_ok_high[0x20];
1888
1889         u8         a_frames_transmitted_ok_low[0x20];
1890
1891         u8         a_frames_received_ok_high[0x20];
1892
1893         u8         a_frames_received_ok_low[0x20];
1894
1895         u8         a_frame_check_sequence_errors_high[0x20];
1896
1897         u8         a_frame_check_sequence_errors_low[0x20];
1898
1899         u8         a_alignment_errors_high[0x20];
1900
1901         u8         a_alignment_errors_low[0x20];
1902
1903         u8         a_octets_transmitted_ok_high[0x20];
1904
1905         u8         a_octets_transmitted_ok_low[0x20];
1906
1907         u8         a_octets_received_ok_high[0x20];
1908
1909         u8         a_octets_received_ok_low[0x20];
1910
1911         u8         a_multicast_frames_xmitted_ok_high[0x20];
1912
1913         u8         a_multicast_frames_xmitted_ok_low[0x20];
1914
1915         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1916
1917         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1918
1919         u8         a_multicast_frames_received_ok_high[0x20];
1920
1921         u8         a_multicast_frames_received_ok_low[0x20];
1922
1923         u8         a_broadcast_frames_received_ok_high[0x20];
1924
1925         u8         a_broadcast_frames_received_ok_low[0x20];
1926
1927         u8         a_in_range_length_errors_high[0x20];
1928
1929         u8         a_in_range_length_errors_low[0x20];
1930
1931         u8         a_out_of_range_length_field_high[0x20];
1932
1933         u8         a_out_of_range_length_field_low[0x20];
1934
1935         u8         a_frame_too_long_errors_high[0x20];
1936
1937         u8         a_frame_too_long_errors_low[0x20];
1938
1939         u8         a_symbol_error_during_carrier_high[0x20];
1940
1941         u8         a_symbol_error_during_carrier_low[0x20];
1942
1943         u8         a_mac_control_frames_transmitted_high[0x20];
1944
1945         u8         a_mac_control_frames_transmitted_low[0x20];
1946
1947         u8         a_mac_control_frames_received_high[0x20];
1948
1949         u8         a_mac_control_frames_received_low[0x20];
1950
1951         u8         a_unsupported_opcodes_received_high[0x20];
1952
1953         u8         a_unsupported_opcodes_received_low[0x20];
1954
1955         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1956
1957         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1958
1959         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1960
1961         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1962
1963         u8         reserved_at_4c0[0x300];
1964 };
1965
1966 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1967         u8         life_time_counter_high[0x20];
1968
1969         u8         life_time_counter_low[0x20];
1970
1971         u8         rx_errors[0x20];
1972
1973         u8         tx_errors[0x20];
1974
1975         u8         l0_to_recovery_eieos[0x20];
1976
1977         u8         l0_to_recovery_ts[0x20];
1978
1979         u8         l0_to_recovery_framing[0x20];
1980
1981         u8         l0_to_recovery_retrain[0x20];
1982
1983         u8         crc_error_dllp[0x20];
1984
1985         u8         crc_error_tlp[0x20];
1986
1987         u8         tx_overflow_buffer_pkt_high[0x20];
1988
1989         u8         tx_overflow_buffer_pkt_low[0x20];
1990
1991         u8         outbound_stalled_reads[0x20];
1992
1993         u8         outbound_stalled_writes[0x20];
1994
1995         u8         outbound_stalled_reads_events[0x20];
1996
1997         u8         outbound_stalled_writes_events[0x20];
1998
1999         u8         reserved_at_200[0x5c0];
2000 };
2001
2002 struct mlx5_ifc_cmd_inter_comp_event_bits {
2003         u8         command_completion_vector[0x20];
2004
2005         u8         reserved_at_20[0xc0];
2006 };
2007
2008 struct mlx5_ifc_stall_vl_event_bits {
2009         u8         reserved_at_0[0x18];
2010         u8         port_num[0x1];
2011         u8         reserved_at_19[0x3];
2012         u8         vl[0x4];
2013
2014         u8         reserved_at_20[0xa0];
2015 };
2016
2017 struct mlx5_ifc_db_bf_congestion_event_bits {
2018         u8         event_subtype[0x8];
2019         u8         reserved_at_8[0x8];
2020         u8         congestion_level[0x8];
2021         u8         reserved_at_18[0x8];
2022
2023         u8         reserved_at_20[0xa0];
2024 };
2025
2026 struct mlx5_ifc_gpio_event_bits {
2027         u8         reserved_at_0[0x60];
2028
2029         u8         gpio_event_hi[0x20];
2030
2031         u8         gpio_event_lo[0x20];
2032
2033         u8         reserved_at_a0[0x40];
2034 };
2035
2036 struct mlx5_ifc_port_state_change_event_bits {
2037         u8         reserved_at_0[0x40];
2038
2039         u8         port_num[0x4];
2040         u8         reserved_at_44[0x1c];
2041
2042         u8         reserved_at_60[0x80];
2043 };
2044
2045 struct mlx5_ifc_dropped_packet_logged_bits {
2046         u8         reserved_at_0[0xe0];
2047 };
2048
2049 enum {
2050         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2051         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2052 };
2053
2054 struct mlx5_ifc_cq_error_bits {
2055         u8         reserved_at_0[0x8];
2056         u8         cqn[0x18];
2057
2058         u8         reserved_at_20[0x20];
2059
2060         u8         reserved_at_40[0x18];
2061         u8         syndrome[0x8];
2062
2063         u8         reserved_at_60[0x80];
2064 };
2065
2066 struct mlx5_ifc_rdma_page_fault_event_bits {
2067         u8         bytes_committed[0x20];
2068
2069         u8         r_key[0x20];
2070
2071         u8         reserved_at_40[0x10];
2072         u8         packet_len[0x10];
2073
2074         u8         rdma_op_len[0x20];
2075
2076         u8         rdma_va[0x40];
2077
2078         u8         reserved_at_c0[0x5];
2079         u8         rdma[0x1];
2080         u8         write[0x1];
2081         u8         requestor[0x1];
2082         u8         qp_number[0x18];
2083 };
2084
2085 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2086         u8         bytes_committed[0x20];
2087
2088         u8         reserved_at_20[0x10];
2089         u8         wqe_index[0x10];
2090
2091         u8         reserved_at_40[0x10];
2092         u8         len[0x10];
2093
2094         u8         reserved_at_60[0x60];
2095
2096         u8         reserved_at_c0[0x5];
2097         u8         rdma[0x1];
2098         u8         write_read[0x1];
2099         u8         requestor[0x1];
2100         u8         qpn[0x18];
2101 };
2102
2103 struct mlx5_ifc_qp_events_bits {
2104         u8         reserved_at_0[0xa0];
2105
2106         u8         type[0x8];
2107         u8         reserved_at_a8[0x18];
2108
2109         u8         reserved_at_c0[0x8];
2110         u8         qpn_rqn_sqn[0x18];
2111 };
2112
2113 struct mlx5_ifc_dct_events_bits {
2114         u8         reserved_at_0[0xc0];
2115
2116         u8         reserved_at_c0[0x8];
2117         u8         dct_number[0x18];
2118 };
2119
2120 struct mlx5_ifc_comp_event_bits {
2121         u8         reserved_at_0[0xc0];
2122
2123         u8         reserved_at_c0[0x8];
2124         u8         cq_number[0x18];
2125 };
2126
2127 enum {
2128         MLX5_QPC_STATE_RST        = 0x0,
2129         MLX5_QPC_STATE_INIT       = 0x1,
2130         MLX5_QPC_STATE_RTR        = 0x2,
2131         MLX5_QPC_STATE_RTS        = 0x3,
2132         MLX5_QPC_STATE_SQER       = 0x4,
2133         MLX5_QPC_STATE_ERR        = 0x6,
2134         MLX5_QPC_STATE_SQD        = 0x7,
2135         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2136 };
2137
2138 enum {
2139         MLX5_QPC_ST_RC            = 0x0,
2140         MLX5_QPC_ST_UC            = 0x1,
2141         MLX5_QPC_ST_UD            = 0x2,
2142         MLX5_QPC_ST_XRC           = 0x3,
2143         MLX5_QPC_ST_DCI           = 0x5,
2144         MLX5_QPC_ST_QP0           = 0x7,
2145         MLX5_QPC_ST_QP1           = 0x8,
2146         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2147         MLX5_QPC_ST_REG_UMR       = 0xc,
2148 };
2149
2150 enum {
2151         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2152         MLX5_QPC_PM_STATE_REARM     = 0x1,
2153         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2154         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2155 };
2156
2157 enum {
2158         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2159 };
2160
2161 enum {
2162         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2163         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2164 };
2165
2166 enum {
2167         MLX5_QPC_MTU_256_BYTES        = 0x1,
2168         MLX5_QPC_MTU_512_BYTES        = 0x2,
2169         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2170         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2171         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2172         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2173 };
2174
2175 enum {
2176         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2177         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2178         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2179         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2180         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2181         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2182         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2183         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2184 };
2185
2186 enum {
2187         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2188         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2189         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2190 };
2191
2192 enum {
2193         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2194         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2195         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2196 };
2197
2198 struct mlx5_ifc_qpc_bits {
2199         u8         state[0x4];
2200         u8         lag_tx_port_affinity[0x4];
2201         u8         st[0x8];
2202         u8         reserved_at_10[0x3];
2203         u8         pm_state[0x2];
2204         u8         reserved_at_15[0x3];
2205         u8         offload_type[0x4];
2206         u8         end_padding_mode[0x2];
2207         u8         reserved_at_1e[0x2];
2208
2209         u8         wq_signature[0x1];
2210         u8         block_lb_mc[0x1];
2211         u8         atomic_like_write_en[0x1];
2212         u8         latency_sensitive[0x1];
2213         u8         reserved_at_24[0x1];
2214         u8         drain_sigerr[0x1];
2215         u8         reserved_at_26[0x2];
2216         u8         pd[0x18];
2217
2218         u8         mtu[0x3];
2219         u8         log_msg_max[0x5];
2220         u8         reserved_at_48[0x1];
2221         u8         log_rq_size[0x4];
2222         u8         log_rq_stride[0x3];
2223         u8         no_sq[0x1];
2224         u8         log_sq_size[0x4];
2225         u8         reserved_at_55[0x6];
2226         u8         rlky[0x1];
2227         u8         ulp_stateless_offload_mode[0x4];
2228
2229         u8         counter_set_id[0x8];
2230         u8         uar_page[0x18];
2231
2232         u8         reserved_at_80[0x8];
2233         u8         user_index[0x18];
2234
2235         u8         reserved_at_a0[0x3];
2236         u8         log_page_size[0x5];
2237         u8         remote_qpn[0x18];
2238
2239         struct mlx5_ifc_ads_bits primary_address_path;
2240
2241         struct mlx5_ifc_ads_bits secondary_address_path;
2242
2243         u8         log_ack_req_freq[0x4];
2244         u8         reserved_at_384[0x4];
2245         u8         log_sra_max[0x3];
2246         u8         reserved_at_38b[0x2];
2247         u8         retry_count[0x3];
2248         u8         rnr_retry[0x3];
2249         u8         reserved_at_393[0x1];
2250         u8         fre[0x1];
2251         u8         cur_rnr_retry[0x3];
2252         u8         cur_retry_count[0x3];
2253         u8         reserved_at_39b[0x5];
2254
2255         u8         reserved_at_3a0[0x20];
2256
2257         u8         reserved_at_3c0[0x8];
2258         u8         next_send_psn[0x18];
2259
2260         u8         reserved_at_3e0[0x8];
2261         u8         cqn_snd[0x18];
2262
2263         u8         reserved_at_400[0x8];
2264         u8         deth_sqpn[0x18];
2265
2266         u8         reserved_at_420[0x20];
2267
2268         u8         reserved_at_440[0x8];
2269         u8         last_acked_psn[0x18];
2270
2271         u8         reserved_at_460[0x8];
2272         u8         ssn[0x18];
2273
2274         u8         reserved_at_480[0x8];
2275         u8         log_rra_max[0x3];
2276         u8         reserved_at_48b[0x1];
2277         u8         atomic_mode[0x4];
2278         u8         rre[0x1];
2279         u8         rwe[0x1];
2280         u8         rae[0x1];
2281         u8         reserved_at_493[0x1];
2282         u8         page_offset[0x6];
2283         u8         reserved_at_49a[0x3];
2284         u8         cd_slave_receive[0x1];
2285         u8         cd_slave_send[0x1];
2286         u8         cd_master[0x1];
2287
2288         u8         reserved_at_4a0[0x3];
2289         u8         min_rnr_nak[0x5];
2290         u8         next_rcv_psn[0x18];
2291
2292         u8         reserved_at_4c0[0x8];
2293         u8         xrcd[0x18];
2294
2295         u8         reserved_at_4e0[0x8];
2296         u8         cqn_rcv[0x18];
2297
2298         u8         dbr_addr[0x40];
2299
2300         u8         q_key[0x20];
2301
2302         u8         reserved_at_560[0x5];
2303         u8         rq_type[0x3];
2304         u8         srqn_rmpn_xrqn[0x18];
2305
2306         u8         reserved_at_580[0x8];
2307         u8         rmsn[0x18];
2308
2309         u8         hw_sq_wqebb_counter[0x10];
2310         u8         sw_sq_wqebb_counter[0x10];
2311
2312         u8         hw_rq_counter[0x20];
2313
2314         u8         sw_rq_counter[0x20];
2315
2316         u8         reserved_at_600[0x20];
2317
2318         u8         reserved_at_620[0xf];
2319         u8         cgs[0x1];
2320         u8         cs_req[0x8];
2321         u8         cs_res[0x8];
2322
2323         u8         dc_access_key[0x40];
2324
2325         u8         reserved_at_680[0xc0];
2326 };
2327
2328 struct mlx5_ifc_roce_addr_layout_bits {
2329         u8         source_l3_address[16][0x8];
2330
2331         u8         reserved_at_80[0x3];
2332         u8         vlan_valid[0x1];
2333         u8         vlan_id[0xc];
2334         u8         source_mac_47_32[0x10];
2335
2336         u8         source_mac_31_0[0x20];
2337
2338         u8         reserved_at_c0[0x14];
2339         u8         roce_l3_type[0x4];
2340         u8         roce_version[0x8];
2341
2342         u8         reserved_at_e0[0x20];
2343 };
2344
2345 union mlx5_ifc_hca_cap_union_bits {
2346         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2347         struct mlx5_ifc_odp_cap_bits odp_cap;
2348         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2349         struct mlx5_ifc_roce_cap_bits roce_cap;
2350         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2351         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2352         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2353         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2354         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2355         struct mlx5_ifc_qos_cap_bits qos_cap;
2356         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2357         u8         reserved_at_0[0x8000];
2358 };
2359
2360 enum {
2361         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2362         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2363         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2364         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2365         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2366         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2367         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2368         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2369         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2370 };
2371
2372 struct mlx5_ifc_vlan_bits {
2373         u8         ethtype[0x10];
2374         u8         prio[0x3];
2375         u8         cfi[0x1];
2376         u8         vid[0xc];
2377 };
2378
2379 struct mlx5_ifc_flow_context_bits {
2380         struct mlx5_ifc_vlan_bits push_vlan;
2381
2382         u8         group_id[0x20];
2383
2384         u8         reserved_at_40[0x8];
2385         u8         flow_tag[0x18];
2386
2387         u8         reserved_at_60[0x10];
2388         u8         action[0x10];
2389
2390         u8         reserved_at_80[0x8];
2391         u8         destination_list_size[0x18];
2392
2393         u8         reserved_at_a0[0x8];
2394         u8         flow_counter_list_size[0x18];
2395
2396         u8         encap_id[0x20];
2397
2398         u8         modify_header_id[0x20];
2399
2400         u8         reserved_at_100[0x100];
2401
2402         struct mlx5_ifc_fte_match_param_bits match_value;
2403
2404         u8         reserved_at_1200[0x600];
2405
2406         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2407 };
2408
2409 enum {
2410         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2411         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2412 };
2413
2414 struct mlx5_ifc_xrc_srqc_bits {
2415         u8         state[0x4];
2416         u8         log_xrc_srq_size[0x4];
2417         u8         reserved_at_8[0x18];
2418
2419         u8         wq_signature[0x1];
2420         u8         cont_srq[0x1];
2421         u8         reserved_at_22[0x1];
2422         u8         rlky[0x1];
2423         u8         basic_cyclic_rcv_wqe[0x1];
2424         u8         log_rq_stride[0x3];
2425         u8         xrcd[0x18];
2426
2427         u8         page_offset[0x6];
2428         u8         reserved_at_46[0x2];
2429         u8         cqn[0x18];
2430
2431         u8         reserved_at_60[0x20];
2432
2433         u8         user_index_equal_xrc_srqn[0x1];
2434         u8         reserved_at_81[0x1];
2435         u8         log_page_size[0x6];
2436         u8         user_index[0x18];
2437
2438         u8         reserved_at_a0[0x20];
2439
2440         u8         reserved_at_c0[0x8];
2441         u8         pd[0x18];
2442
2443         u8         lwm[0x10];
2444         u8         wqe_cnt[0x10];
2445
2446         u8         reserved_at_100[0x40];
2447
2448         u8         db_record_addr_h[0x20];
2449
2450         u8         db_record_addr_l[0x1e];
2451         u8         reserved_at_17e[0x2];
2452
2453         u8         reserved_at_180[0x80];
2454 };
2455
2456 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2457         u8         counter_error_queues[0x20];
2458
2459         u8         total_error_queues[0x20];
2460
2461         u8         send_queue_priority_update_flow[0x20];
2462
2463         u8         reserved_at_60[0x20];
2464
2465         u8         nic_receive_steering_discard[0x40];
2466
2467         u8         receive_discard_vport_down[0x40];
2468
2469         u8         transmit_discard_vport_down[0x40];
2470
2471         u8         reserved_at_140[0xec0];
2472 };
2473
2474 struct mlx5_ifc_traffic_counter_bits {
2475         u8         packets[0x40];
2476
2477         u8         octets[0x40];
2478 };
2479
2480 struct mlx5_ifc_tisc_bits {
2481         u8         strict_lag_tx_port_affinity[0x1];
2482         u8         reserved_at_1[0x3];
2483         u8         lag_tx_port_affinity[0x04];
2484
2485         u8         reserved_at_8[0x4];
2486         u8         prio[0x4];
2487         u8         reserved_at_10[0x10];
2488
2489         u8         reserved_at_20[0x100];
2490
2491         u8         reserved_at_120[0x8];
2492         u8         transport_domain[0x18];
2493
2494         u8         reserved_at_140[0x8];
2495         u8         underlay_qpn[0x18];
2496         u8         reserved_at_160[0x3a0];
2497 };
2498
2499 enum {
2500         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2501         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2502 };
2503
2504 enum {
2505         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2506         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2507 };
2508
2509 enum {
2510         MLX5_RX_HASH_FN_NONE           = 0x0,
2511         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2512         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2513 };
2514
2515 enum {
2516         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2517         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2518 };
2519
2520 struct mlx5_ifc_tirc_bits {
2521         u8         reserved_at_0[0x20];
2522
2523         u8         disp_type[0x4];
2524         u8         reserved_at_24[0x1c];
2525
2526         u8         reserved_at_40[0x40];
2527
2528         u8         reserved_at_80[0x4];
2529         u8         lro_timeout_period_usecs[0x10];
2530         u8         lro_enable_mask[0x4];
2531         u8         lro_max_ip_payload_size[0x8];
2532
2533         u8         reserved_at_a0[0x40];
2534
2535         u8         reserved_at_e0[0x8];
2536         u8         inline_rqn[0x18];
2537
2538         u8         rx_hash_symmetric[0x1];
2539         u8         reserved_at_101[0x1];
2540         u8         tunneled_offload_en[0x1];
2541         u8         reserved_at_103[0x5];
2542         u8         indirect_table[0x18];
2543
2544         u8         rx_hash_fn[0x4];
2545         u8         reserved_at_124[0x2];
2546         u8         self_lb_block[0x2];
2547         u8         transport_domain[0x18];
2548
2549         u8         rx_hash_toeplitz_key[10][0x20];
2550
2551         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2552
2553         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2554
2555         u8         reserved_at_2c0[0x4c0];
2556 };
2557
2558 enum {
2559         MLX5_SRQC_STATE_GOOD   = 0x0,
2560         MLX5_SRQC_STATE_ERROR  = 0x1,
2561 };
2562
2563 struct mlx5_ifc_srqc_bits {
2564         u8         state[0x4];
2565         u8         log_srq_size[0x4];
2566         u8         reserved_at_8[0x18];
2567
2568         u8         wq_signature[0x1];
2569         u8         cont_srq[0x1];
2570         u8         reserved_at_22[0x1];
2571         u8         rlky[0x1];
2572         u8         reserved_at_24[0x1];
2573         u8         log_rq_stride[0x3];
2574         u8         xrcd[0x18];
2575
2576         u8         page_offset[0x6];
2577         u8         reserved_at_46[0x2];
2578         u8         cqn[0x18];
2579
2580         u8         reserved_at_60[0x20];
2581
2582         u8         reserved_at_80[0x2];
2583         u8         log_page_size[0x6];
2584         u8         reserved_at_88[0x18];
2585
2586         u8         reserved_at_a0[0x20];
2587
2588         u8         reserved_at_c0[0x8];
2589         u8         pd[0x18];
2590
2591         u8         lwm[0x10];
2592         u8         wqe_cnt[0x10];
2593
2594         u8         reserved_at_100[0x40];
2595
2596         u8         dbr_addr[0x40];
2597
2598         u8         reserved_at_180[0x80];
2599 };
2600
2601 enum {
2602         MLX5_SQC_STATE_RST  = 0x0,
2603         MLX5_SQC_STATE_RDY  = 0x1,
2604         MLX5_SQC_STATE_ERR  = 0x3,
2605 };
2606
2607 struct mlx5_ifc_sqc_bits {
2608         u8         rlky[0x1];
2609         u8         cd_master[0x1];
2610         u8         fre[0x1];
2611         u8         flush_in_error_en[0x1];
2612         u8         allow_multi_pkt_send_wqe[0x1];
2613         u8         min_wqe_inline_mode[0x3];
2614         u8         state[0x4];
2615         u8         reg_umr[0x1];
2616         u8         allow_swp[0x1];
2617         u8         hairpin[0x1];
2618         u8         reserved_at_f[0x11];
2619
2620         u8         reserved_at_20[0x8];
2621         u8         user_index[0x18];
2622
2623         u8         reserved_at_40[0x8];
2624         u8         cqn[0x18];
2625
2626         u8         reserved_at_60[0x8];
2627         u8         hairpin_peer_rq[0x18];
2628
2629         u8         reserved_at_80[0x10];
2630         u8         hairpin_peer_vhca[0x10];
2631
2632         u8         reserved_at_a0[0x50];
2633
2634         u8         packet_pacing_rate_limit_index[0x10];
2635         u8         tis_lst_sz[0x10];
2636         u8         reserved_at_110[0x10];
2637
2638         u8         reserved_at_120[0x40];
2639
2640         u8         reserved_at_160[0x8];
2641         u8         tis_num_0[0x18];
2642
2643         struct mlx5_ifc_wq_bits wq;
2644 };
2645
2646 enum {
2647         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2648         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2649         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2650         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2651 };
2652
2653 struct mlx5_ifc_scheduling_context_bits {
2654         u8         element_type[0x8];
2655         u8         reserved_at_8[0x18];
2656
2657         u8         element_attributes[0x20];
2658
2659         u8         parent_element_id[0x20];
2660
2661         u8         reserved_at_60[0x40];
2662
2663         u8         bw_share[0x20];
2664
2665         u8         max_average_bw[0x20];
2666
2667         u8         reserved_at_e0[0x120];
2668 };
2669
2670 struct mlx5_ifc_rqtc_bits {
2671         u8         reserved_at_0[0xa0];
2672
2673         u8         reserved_at_a0[0x10];
2674         u8         rqt_max_size[0x10];
2675
2676         u8         reserved_at_c0[0x10];
2677         u8         rqt_actual_size[0x10];
2678
2679         u8         reserved_at_e0[0x6a0];
2680
2681         struct mlx5_ifc_rq_num_bits rq_num[0];
2682 };
2683
2684 enum {
2685         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2686         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2687 };
2688
2689 enum {
2690         MLX5_RQC_STATE_RST  = 0x0,
2691         MLX5_RQC_STATE_RDY  = 0x1,
2692         MLX5_RQC_STATE_ERR  = 0x3,
2693 };
2694
2695 struct mlx5_ifc_rqc_bits {
2696         u8         rlky[0x1];
2697         u8         delay_drop_en[0x1];
2698         u8         scatter_fcs[0x1];
2699         u8         vsd[0x1];
2700         u8         mem_rq_type[0x4];
2701         u8         state[0x4];
2702         u8         reserved_at_c[0x1];
2703         u8         flush_in_error_en[0x1];
2704         u8         hairpin[0x1];
2705         u8         reserved_at_f[0x11];
2706
2707         u8         reserved_at_20[0x8];
2708         u8         user_index[0x18];
2709
2710         u8         reserved_at_40[0x8];
2711         u8         cqn[0x18];
2712
2713         u8         counter_set_id[0x8];
2714         u8         reserved_at_68[0x18];
2715
2716         u8         reserved_at_80[0x8];
2717         u8         rmpn[0x18];
2718
2719         u8         reserved_at_a0[0x8];
2720         u8         hairpin_peer_sq[0x18];
2721
2722         u8         reserved_at_c0[0x10];
2723         u8         hairpin_peer_vhca[0x10];
2724
2725         u8         reserved_at_e0[0xa0];
2726
2727         struct mlx5_ifc_wq_bits wq;
2728 };
2729
2730 enum {
2731         MLX5_RMPC_STATE_RDY  = 0x1,
2732         MLX5_RMPC_STATE_ERR  = 0x3,
2733 };
2734
2735 struct mlx5_ifc_rmpc_bits {
2736         u8         reserved_at_0[0x8];
2737         u8         state[0x4];
2738         u8         reserved_at_c[0x14];
2739
2740         u8         basic_cyclic_rcv_wqe[0x1];
2741         u8         reserved_at_21[0x1f];
2742
2743         u8         reserved_at_40[0x140];
2744
2745         struct mlx5_ifc_wq_bits wq;
2746 };
2747
2748 struct mlx5_ifc_nic_vport_context_bits {
2749         u8         reserved_at_0[0x5];
2750         u8         min_wqe_inline_mode[0x3];
2751         u8         reserved_at_8[0x15];
2752         u8         disable_mc_local_lb[0x1];
2753         u8         disable_uc_local_lb[0x1];
2754         u8         roce_en[0x1];
2755
2756         u8         arm_change_event[0x1];
2757         u8         reserved_at_21[0x1a];
2758         u8         event_on_mtu[0x1];
2759         u8         event_on_promisc_change[0x1];
2760         u8         event_on_vlan_change[0x1];
2761         u8         event_on_mc_address_change[0x1];
2762         u8         event_on_uc_address_change[0x1];
2763
2764         u8         reserved_at_40[0xc];
2765
2766         u8         affiliation_criteria[0x4];
2767         u8         affiliated_vhca_id[0x10];
2768
2769         u8         reserved_at_60[0xd0];
2770
2771         u8         mtu[0x10];
2772
2773         u8         system_image_guid[0x40];
2774         u8         port_guid[0x40];
2775         u8         node_guid[0x40];
2776
2777         u8         reserved_at_200[0x140];
2778         u8         qkey_violation_counter[0x10];
2779         u8         reserved_at_350[0x430];
2780
2781         u8         promisc_uc[0x1];
2782         u8         promisc_mc[0x1];
2783         u8         promisc_all[0x1];
2784         u8         reserved_at_783[0x2];
2785         u8         allowed_list_type[0x3];
2786         u8         reserved_at_788[0xc];
2787         u8         allowed_list_size[0xc];
2788
2789         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2790
2791         u8         reserved_at_7e0[0x20];
2792
2793         u8         current_uc_mac_address[0][0x40];
2794 };
2795
2796 enum {
2797         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2798         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2799         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2800         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2801         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2802 };
2803
2804 struct mlx5_ifc_mkc_bits {
2805         u8         reserved_at_0[0x1];
2806         u8         free[0x1];
2807         u8         reserved_at_2[0x1];
2808         u8         access_mode_4_2[0x3];
2809         u8         reserved_at_6[0x7];
2810         u8         relaxed_ordering_write[0x1];
2811         u8         reserved_at_e[0x1];
2812         u8         small_fence_on_rdma_read_response[0x1];
2813         u8         umr_en[0x1];
2814         u8         a[0x1];
2815         u8         rw[0x1];
2816         u8         rr[0x1];
2817         u8         lw[0x1];
2818         u8         lr[0x1];
2819         u8         access_mode_1_0[0x2];
2820         u8         reserved_at_18[0x8];
2821
2822         u8         qpn[0x18];
2823         u8         mkey_7_0[0x8];
2824
2825         u8         reserved_at_40[0x20];
2826
2827         u8         length64[0x1];
2828         u8         bsf_en[0x1];
2829         u8         sync_umr[0x1];
2830         u8         reserved_at_63[0x2];
2831         u8         expected_sigerr_count[0x1];
2832         u8         reserved_at_66[0x1];
2833         u8         en_rinval[0x1];
2834         u8         pd[0x18];
2835
2836         u8         start_addr[0x40];
2837
2838         u8         len[0x40];
2839
2840         u8         bsf_octword_size[0x20];
2841
2842         u8         reserved_at_120[0x80];
2843
2844         u8         translations_octword_size[0x20];
2845
2846         u8         reserved_at_1c0[0x1b];
2847         u8         log_page_size[0x5];
2848
2849         u8         reserved_at_1e0[0x20];
2850 };
2851
2852 struct mlx5_ifc_pkey_bits {
2853         u8         reserved_at_0[0x10];
2854         u8         pkey[0x10];
2855 };
2856
2857 struct mlx5_ifc_array128_auto_bits {
2858         u8         array128_auto[16][0x8];
2859 };
2860
2861 struct mlx5_ifc_hca_vport_context_bits {
2862         u8         field_select[0x20];
2863
2864         u8         reserved_at_20[0xe0];
2865
2866         u8         sm_virt_aware[0x1];
2867         u8         has_smi[0x1];
2868         u8         has_raw[0x1];
2869         u8         grh_required[0x1];
2870         u8         reserved_at_104[0xc];
2871         u8         port_physical_state[0x4];
2872         u8         vport_state_policy[0x4];
2873         u8         port_state[0x4];
2874         u8         vport_state[0x4];
2875
2876         u8         reserved_at_120[0x20];
2877
2878         u8         system_image_guid[0x40];
2879
2880         u8         port_guid[0x40];
2881
2882         u8         node_guid[0x40];
2883
2884         u8         cap_mask1[0x20];
2885
2886         u8         cap_mask1_field_select[0x20];
2887
2888         u8         cap_mask2[0x20];
2889
2890         u8         cap_mask2_field_select[0x20];
2891
2892         u8         reserved_at_280[0x80];
2893
2894         u8         lid[0x10];
2895         u8         reserved_at_310[0x4];
2896         u8         init_type_reply[0x4];
2897         u8         lmc[0x3];
2898         u8         subnet_timeout[0x5];
2899
2900         u8         sm_lid[0x10];
2901         u8         sm_sl[0x4];
2902         u8         reserved_at_334[0xc];
2903
2904         u8         qkey_violation_counter[0x10];
2905         u8         pkey_violation_counter[0x10];
2906
2907         u8         reserved_at_360[0xca0];
2908 };
2909
2910 struct mlx5_ifc_esw_vport_context_bits {
2911         u8         reserved_at_0[0x3];
2912         u8         vport_svlan_strip[0x1];
2913         u8         vport_cvlan_strip[0x1];
2914         u8         vport_svlan_insert[0x1];
2915         u8         vport_cvlan_insert[0x2];
2916         u8         reserved_at_8[0x18];
2917
2918         u8         reserved_at_20[0x20];
2919
2920         u8         svlan_cfi[0x1];
2921         u8         svlan_pcp[0x3];
2922         u8         svlan_id[0xc];
2923         u8         cvlan_cfi[0x1];
2924         u8         cvlan_pcp[0x3];
2925         u8         cvlan_id[0xc];
2926
2927         u8         reserved_at_60[0x7a0];
2928 };
2929
2930 enum {
2931         MLX5_EQC_STATUS_OK                = 0x0,
2932         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2933 };
2934
2935 enum {
2936         MLX5_EQC_ST_ARMED  = 0x9,
2937         MLX5_EQC_ST_FIRED  = 0xa,
2938 };
2939
2940 struct mlx5_ifc_eqc_bits {
2941         u8         status[0x4];
2942         u8         reserved_at_4[0x9];
2943         u8         ec[0x1];
2944         u8         oi[0x1];
2945         u8         reserved_at_f[0x5];
2946         u8         st[0x4];
2947         u8         reserved_at_18[0x8];
2948
2949         u8         reserved_at_20[0x20];
2950
2951         u8         reserved_at_40[0x14];
2952         u8         page_offset[0x6];
2953         u8         reserved_at_5a[0x6];
2954
2955         u8         reserved_at_60[0x3];
2956         u8         log_eq_size[0x5];
2957         u8         uar_page[0x18];
2958
2959         u8         reserved_at_80[0x20];
2960
2961         u8         reserved_at_a0[0x18];
2962         u8         intr[0x8];
2963
2964         u8         reserved_at_c0[0x3];
2965         u8         log_page_size[0x5];
2966         u8         reserved_at_c8[0x18];
2967
2968         u8         reserved_at_e0[0x60];
2969
2970         u8         reserved_at_140[0x8];
2971         u8         consumer_counter[0x18];
2972
2973         u8         reserved_at_160[0x8];
2974         u8         producer_counter[0x18];
2975
2976         u8         reserved_at_180[0x80];
2977 };
2978
2979 enum {
2980         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2981         MLX5_DCTC_STATE_DRAINING  = 0x1,
2982         MLX5_DCTC_STATE_DRAINED   = 0x2,
2983 };
2984
2985 enum {
2986         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2987         MLX5_DCTC_CS_RES_NA         = 0x1,
2988         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2989 };
2990
2991 enum {
2992         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2993         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2994         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2995         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2996         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2997 };
2998
2999 struct mlx5_ifc_dctc_bits {
3000         u8         reserved_at_0[0x4];
3001         u8         state[0x4];
3002         u8         reserved_at_8[0x18];
3003
3004         u8         reserved_at_20[0x8];
3005         u8         user_index[0x18];
3006
3007         u8         reserved_at_40[0x8];
3008         u8         cqn[0x18];
3009
3010         u8         counter_set_id[0x8];
3011         u8         atomic_mode[0x4];
3012         u8         rre[0x1];
3013         u8         rwe[0x1];
3014         u8         rae[0x1];
3015         u8         atomic_like_write_en[0x1];
3016         u8         latency_sensitive[0x1];
3017         u8         rlky[0x1];
3018         u8         free_ar[0x1];
3019         u8         reserved_at_73[0xd];
3020
3021         u8         reserved_at_80[0x8];
3022         u8         cs_res[0x8];
3023         u8         reserved_at_90[0x3];
3024         u8         min_rnr_nak[0x5];
3025         u8         reserved_at_98[0x8];
3026
3027         u8         reserved_at_a0[0x8];
3028         u8         srqn_xrqn[0x18];
3029
3030         u8         reserved_at_c0[0x8];
3031         u8         pd[0x18];
3032
3033         u8         tclass[0x8];
3034         u8         reserved_at_e8[0x4];
3035         u8         flow_label[0x14];
3036
3037         u8         dc_access_key[0x40];
3038
3039         u8         reserved_at_140[0x5];
3040         u8         mtu[0x3];
3041         u8         port[0x8];
3042         u8         pkey_index[0x10];
3043
3044         u8         reserved_at_160[0x8];
3045         u8         my_addr_index[0x8];
3046         u8         reserved_at_170[0x8];
3047         u8         hop_limit[0x8];
3048
3049         u8         dc_access_key_violation_count[0x20];
3050
3051         u8         reserved_at_1a0[0x14];
3052         u8         dei_cfi[0x1];
3053         u8         eth_prio[0x3];
3054         u8         ecn[0x2];
3055         u8         dscp[0x6];
3056
3057         u8         reserved_at_1c0[0x40];
3058 };
3059
3060 enum {
3061         MLX5_CQC_STATUS_OK             = 0x0,
3062         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3063         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3064 };
3065
3066 enum {
3067         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3068         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3069 };
3070
3071 enum {
3072         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3073         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3074         MLX5_CQC_ST_FIRED                                 = 0xa,
3075 };
3076
3077 enum {
3078         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3079         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3080         MLX5_CQ_PERIOD_NUM_MODES
3081 };
3082
3083 struct mlx5_ifc_cqc_bits {
3084         u8         status[0x4];
3085         u8         reserved_at_4[0x4];
3086         u8         cqe_sz[0x3];
3087         u8         cc[0x1];
3088         u8         reserved_at_c[0x1];
3089         u8         scqe_break_moderation_en[0x1];
3090         u8         oi[0x1];
3091         u8         cq_period_mode[0x2];
3092         u8         cqe_comp_en[0x1];
3093         u8         mini_cqe_res_format[0x2];
3094         u8         st[0x4];
3095         u8         reserved_at_18[0x8];
3096
3097         u8         reserved_at_20[0x20];
3098
3099         u8         reserved_at_40[0x14];
3100         u8         page_offset[0x6];
3101         u8         reserved_at_5a[0x6];
3102
3103         u8         reserved_at_60[0x3];
3104         u8         log_cq_size[0x5];
3105         u8         uar_page[0x18];
3106
3107         u8         reserved_at_80[0x4];
3108         u8         cq_period[0xc];
3109         u8         cq_max_count[0x10];
3110
3111         u8         reserved_at_a0[0x18];
3112         u8         c_eqn[0x8];
3113
3114         u8         reserved_at_c0[0x3];
3115         u8         log_page_size[0x5];
3116         u8         reserved_at_c8[0x18];
3117
3118         u8         reserved_at_e0[0x20];
3119
3120         u8         reserved_at_100[0x8];
3121         u8         last_notified_index[0x18];
3122
3123         u8         reserved_at_120[0x8];
3124         u8         last_solicit_index[0x18];
3125
3126         u8         reserved_at_140[0x8];
3127         u8         consumer_counter[0x18];
3128
3129         u8         reserved_at_160[0x8];
3130         u8         producer_counter[0x18];
3131
3132         u8         reserved_at_180[0x40];
3133
3134         u8         dbr_addr[0x40];
3135 };
3136
3137 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3138         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3139         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3140         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3141         u8         reserved_at_0[0x800];
3142 };
3143
3144 struct mlx5_ifc_query_adapter_param_block_bits {
3145         u8         reserved_at_0[0xc0];
3146
3147         u8         reserved_at_c0[0x8];
3148         u8         ieee_vendor_id[0x18];
3149
3150         u8         reserved_at_e0[0x10];
3151         u8         vsd_vendor_id[0x10];
3152
3153         u8         vsd[208][0x8];
3154
3155         u8         vsd_contd_psid[16][0x8];
3156 };
3157
3158 enum {
3159         MLX5_XRQC_STATE_GOOD   = 0x0,
3160         MLX5_XRQC_STATE_ERROR  = 0x1,
3161 };
3162
3163 enum {
3164         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3165         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3166 };
3167
3168 enum {
3169         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3170 };
3171
3172 struct mlx5_ifc_tag_matching_topology_context_bits {
3173         u8         log_matching_list_sz[0x4];
3174         u8         reserved_at_4[0xc];
3175         u8         append_next_index[0x10];
3176
3177         u8         sw_phase_cnt[0x10];
3178         u8         hw_phase_cnt[0x10];
3179
3180         u8         reserved_at_40[0x40];
3181 };
3182
3183 struct mlx5_ifc_xrqc_bits {
3184         u8         state[0x4];
3185         u8         rlkey[0x1];
3186         u8         reserved_at_5[0xf];
3187         u8         topology[0x4];
3188         u8         reserved_at_18[0x4];
3189         u8         offload[0x4];
3190
3191         u8         reserved_at_20[0x8];
3192         u8         user_index[0x18];
3193
3194         u8         reserved_at_40[0x8];
3195         u8         cqn[0x18];
3196
3197         u8         reserved_at_60[0xa0];
3198
3199         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3200
3201         u8         reserved_at_180[0x280];
3202
3203         struct mlx5_ifc_wq_bits wq;
3204 };
3205
3206 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3207         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3208         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3209         u8         reserved_at_0[0x20];
3210 };
3211
3212 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3213         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3214         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3215         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3216         u8         reserved_at_0[0x20];
3217 };
3218
3219 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3220         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3221         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3222         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3223         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3224         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3225         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3226         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3227         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3228         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3229         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3230         u8         reserved_at_0[0x7c0];
3231 };
3232
3233 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3234         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3235         u8         reserved_at_0[0x7c0];
3236 };
3237
3238 union mlx5_ifc_event_auto_bits {
3239         struct mlx5_ifc_comp_event_bits comp_event;
3240         struct mlx5_ifc_dct_events_bits dct_events;
3241         struct mlx5_ifc_qp_events_bits qp_events;
3242         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3243         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3244         struct mlx5_ifc_cq_error_bits cq_error;
3245         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3246         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3247         struct mlx5_ifc_gpio_event_bits gpio_event;
3248         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3249         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3250         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3251         u8         reserved_at_0[0xe0];
3252 };
3253
3254 struct mlx5_ifc_health_buffer_bits {
3255         u8         reserved_at_0[0x100];
3256
3257         u8         assert_existptr[0x20];
3258
3259         u8         assert_callra[0x20];
3260
3261         u8         reserved_at_140[0x40];
3262
3263         u8         fw_version[0x20];
3264
3265         u8         hw_id[0x20];
3266
3267         u8         reserved_at_1c0[0x20];
3268
3269         u8         irisc_index[0x8];
3270         u8         synd[0x8];
3271         u8         ext_synd[0x10];
3272 };
3273
3274 struct mlx5_ifc_register_loopback_control_bits {
3275         u8         no_lb[0x1];
3276         u8         reserved_at_1[0x7];
3277         u8         port[0x8];
3278         u8         reserved_at_10[0x10];
3279
3280         u8         reserved_at_20[0x60];
3281 };
3282
3283 struct mlx5_ifc_vport_tc_element_bits {
3284         u8         traffic_class[0x4];
3285         u8         reserved_at_4[0xc];
3286         u8         vport_number[0x10];
3287 };
3288
3289 struct mlx5_ifc_vport_element_bits {
3290         u8         reserved_at_0[0x10];
3291         u8         vport_number[0x10];
3292 };
3293
3294 enum {
3295         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3296         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3297         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3298 };
3299
3300 struct mlx5_ifc_tsar_element_bits {
3301         u8         reserved_at_0[0x8];
3302         u8         tsar_type[0x8];
3303         u8         reserved_at_10[0x10];
3304 };
3305
3306 enum {
3307         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3308         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3309 };
3310
3311 struct mlx5_ifc_teardown_hca_out_bits {
3312         u8         status[0x8];
3313         u8         reserved_at_8[0x18];
3314
3315         u8         syndrome[0x20];
3316
3317         u8         reserved_at_40[0x3f];
3318
3319         u8         force_state[0x1];
3320 };
3321
3322 enum {
3323         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3324         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3325 };
3326
3327 struct mlx5_ifc_teardown_hca_in_bits {
3328         u8         opcode[0x10];
3329         u8         reserved_at_10[0x10];
3330
3331         u8         reserved_at_20[0x10];
3332         u8         op_mod[0x10];
3333
3334         u8         reserved_at_40[0x10];
3335         u8         profile[0x10];
3336
3337         u8         reserved_at_60[0x20];
3338 };
3339
3340 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3341         u8         status[0x8];
3342         u8         reserved_at_8[0x18];
3343
3344         u8         syndrome[0x20];
3345
3346         u8         reserved_at_40[0x40];
3347 };
3348
3349 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3350         u8         opcode[0x10];
3351         u8         reserved_at_10[0x10];
3352
3353         u8         reserved_at_20[0x10];
3354         u8         op_mod[0x10];
3355
3356         u8         reserved_at_40[0x8];
3357         u8         qpn[0x18];
3358
3359         u8         reserved_at_60[0x20];
3360
3361         u8         opt_param_mask[0x20];
3362
3363         u8         reserved_at_a0[0x20];
3364
3365         struct mlx5_ifc_qpc_bits qpc;
3366
3367         u8         reserved_at_800[0x80];
3368 };
3369
3370 struct mlx5_ifc_sqd2rts_qp_out_bits {
3371         u8         status[0x8];
3372         u8         reserved_at_8[0x18];
3373
3374         u8         syndrome[0x20];
3375
3376         u8         reserved_at_40[0x40];
3377 };
3378
3379 struct mlx5_ifc_sqd2rts_qp_in_bits {
3380         u8         opcode[0x10];
3381         u8         reserved_at_10[0x10];
3382
3383         u8         reserved_at_20[0x10];
3384         u8         op_mod[0x10];
3385
3386         u8         reserved_at_40[0x8];
3387         u8         qpn[0x18];
3388
3389         u8         reserved_at_60[0x20];
3390
3391         u8         opt_param_mask[0x20];
3392
3393         u8         reserved_at_a0[0x20];
3394
3395         struct mlx5_ifc_qpc_bits qpc;
3396
3397         u8         reserved_at_800[0x80];
3398 };
3399
3400 struct mlx5_ifc_set_roce_address_out_bits {
3401         u8         status[0x8];
3402         u8         reserved_at_8[0x18];
3403
3404         u8         syndrome[0x20];
3405
3406         u8         reserved_at_40[0x40];
3407 };
3408
3409 struct mlx5_ifc_set_roce_address_in_bits {
3410         u8         opcode[0x10];
3411         u8         reserved_at_10[0x10];
3412
3413         u8         reserved_at_20[0x10];
3414         u8         op_mod[0x10];
3415
3416         u8         roce_address_index[0x10];
3417         u8         reserved_at_50[0xc];
3418         u8         vhca_port_num[0x4];
3419
3420         u8         reserved_at_60[0x20];
3421
3422         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3423 };
3424
3425 struct mlx5_ifc_set_mad_demux_out_bits {
3426         u8         status[0x8];
3427         u8         reserved_at_8[0x18];
3428
3429         u8         syndrome[0x20];
3430
3431         u8         reserved_at_40[0x40];
3432 };
3433
3434 enum {
3435         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3436         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3437 };
3438
3439 struct mlx5_ifc_set_mad_demux_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_at_10[0x10];
3442
3443         u8         reserved_at_20[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         reserved_at_40[0x20];
3447
3448         u8         reserved_at_60[0x6];
3449         u8         demux_mode[0x2];
3450         u8         reserved_at_68[0x18];
3451 };
3452
3453 struct mlx5_ifc_set_l2_table_entry_out_bits {
3454         u8         status[0x8];
3455         u8         reserved_at_8[0x18];
3456
3457         u8         syndrome[0x20];
3458
3459         u8         reserved_at_40[0x40];
3460 };
3461
3462 struct mlx5_ifc_set_l2_table_entry_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_at_40[0x60];
3470
3471         u8         reserved_at_a0[0x8];
3472         u8         table_index[0x18];
3473
3474         u8         reserved_at_c0[0x20];
3475
3476         u8         reserved_at_e0[0x13];
3477         u8         vlan_valid[0x1];
3478         u8         vlan[0xc];
3479
3480         struct mlx5_ifc_mac_address_layout_bits mac_address;
3481
3482         u8         reserved_at_140[0xc0];
3483 };
3484
3485 struct mlx5_ifc_set_issi_out_bits {
3486         u8         status[0x8];
3487         u8         reserved_at_8[0x18];
3488
3489         u8         syndrome[0x20];
3490
3491         u8         reserved_at_40[0x40];
3492 };
3493
3494 struct mlx5_ifc_set_issi_in_bits {
3495         u8         opcode[0x10];
3496         u8         reserved_at_10[0x10];
3497
3498         u8         reserved_at_20[0x10];
3499         u8         op_mod[0x10];
3500
3501         u8         reserved_at_40[0x10];
3502         u8         current_issi[0x10];
3503
3504         u8         reserved_at_60[0x20];
3505 };
3506
3507 struct mlx5_ifc_set_hca_cap_out_bits {
3508         u8         status[0x8];
3509         u8         reserved_at_8[0x18];
3510
3511         u8         syndrome[0x20];
3512
3513         u8         reserved_at_40[0x40];
3514 };
3515
3516 struct mlx5_ifc_set_hca_cap_in_bits {
3517         u8         opcode[0x10];
3518         u8         reserved_at_10[0x10];
3519
3520         u8         reserved_at_20[0x10];
3521         u8         op_mod[0x10];
3522
3523         u8         reserved_at_40[0x40];
3524
3525         union mlx5_ifc_hca_cap_union_bits capability;
3526 };
3527
3528 enum {
3529         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3530         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3531         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3532         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3533 };
3534
3535 struct mlx5_ifc_set_fte_out_bits {
3536         u8         status[0x8];
3537         u8         reserved_at_8[0x18];
3538
3539         u8         syndrome[0x20];
3540
3541         u8         reserved_at_40[0x40];
3542 };
3543
3544 struct mlx5_ifc_set_fte_in_bits {
3545         u8         opcode[0x10];
3546         u8         reserved_at_10[0x10];
3547
3548         u8         reserved_at_20[0x10];
3549         u8         op_mod[0x10];
3550
3551         u8         other_vport[0x1];
3552         u8         reserved_at_41[0xf];
3553         u8         vport_number[0x10];
3554
3555         u8         reserved_at_60[0x20];
3556
3557         u8         table_type[0x8];
3558         u8         reserved_at_88[0x18];
3559
3560         u8         reserved_at_a0[0x8];
3561         u8         table_id[0x18];
3562
3563         u8         reserved_at_c0[0x18];
3564         u8         modify_enable_mask[0x8];
3565
3566         u8         reserved_at_e0[0x20];
3567
3568         u8         flow_index[0x20];
3569
3570         u8         reserved_at_120[0xe0];
3571
3572         struct mlx5_ifc_flow_context_bits flow_context;
3573 };
3574
3575 struct mlx5_ifc_rts2rts_qp_out_bits {
3576         u8         status[0x8];
3577         u8         reserved_at_8[0x18];
3578
3579         u8         syndrome[0x20];
3580
3581         u8         reserved_at_40[0x40];
3582 };
3583
3584 struct mlx5_ifc_rts2rts_qp_in_bits {
3585         u8         opcode[0x10];
3586         u8         reserved_at_10[0x10];
3587
3588         u8         reserved_at_20[0x10];
3589         u8         op_mod[0x10];
3590
3591         u8         reserved_at_40[0x8];
3592         u8         qpn[0x18];
3593
3594         u8         reserved_at_60[0x20];
3595
3596         u8         opt_param_mask[0x20];
3597
3598         u8         reserved_at_a0[0x20];
3599
3600         struct mlx5_ifc_qpc_bits qpc;
3601
3602         u8         reserved_at_800[0x80];
3603 };
3604
3605 struct mlx5_ifc_rtr2rts_qp_out_bits {
3606         u8         status[0x8];
3607         u8         reserved_at_8[0x18];
3608
3609         u8         syndrome[0x20];
3610
3611         u8         reserved_at_40[0x40];
3612 };
3613
3614 struct mlx5_ifc_rtr2rts_qp_in_bits {
3615         u8         opcode[0x10];
3616         u8         reserved_at_10[0x10];
3617
3618         u8         reserved_at_20[0x10];
3619         u8         op_mod[0x10];
3620
3621         u8         reserved_at_40[0x8];
3622         u8         qpn[0x18];
3623
3624         u8         reserved_at_60[0x20];
3625
3626         u8         opt_param_mask[0x20];
3627
3628         u8         reserved_at_a0[0x20];
3629
3630         struct mlx5_ifc_qpc_bits qpc;
3631
3632         u8         reserved_at_800[0x80];
3633 };
3634
3635 struct mlx5_ifc_rst2init_qp_out_bits {
3636         u8         status[0x8];
3637         u8         reserved_at_8[0x18];
3638
3639         u8         syndrome[0x20];
3640
3641         u8         reserved_at_40[0x40];
3642 };
3643
3644 struct mlx5_ifc_rst2init_qp_in_bits {
3645         u8         opcode[0x10];
3646         u8         reserved_at_10[0x10];
3647
3648         u8         reserved_at_20[0x10];
3649         u8         op_mod[0x10];
3650
3651         u8         reserved_at_40[0x8];
3652         u8         qpn[0x18];
3653
3654         u8         reserved_at_60[0x20];
3655
3656         u8         opt_param_mask[0x20];
3657
3658         u8         reserved_at_a0[0x20];
3659
3660         struct mlx5_ifc_qpc_bits qpc;
3661
3662         u8         reserved_at_800[0x80];
3663 };
3664
3665 struct mlx5_ifc_query_xrq_out_bits {
3666         u8         status[0x8];
3667         u8         reserved_at_8[0x18];
3668
3669         u8         syndrome[0x20];
3670
3671         u8         reserved_at_40[0x40];
3672
3673         struct mlx5_ifc_xrqc_bits xrq_context;
3674 };
3675
3676 struct mlx5_ifc_query_xrq_in_bits {
3677         u8         opcode[0x10];
3678         u8         reserved_at_10[0x10];
3679
3680         u8         reserved_at_20[0x10];
3681         u8         op_mod[0x10];
3682
3683         u8         reserved_at_40[0x8];
3684         u8         xrqn[0x18];
3685
3686         u8         reserved_at_60[0x20];
3687 };
3688
3689 struct mlx5_ifc_query_xrc_srq_out_bits {
3690         u8         status[0x8];
3691         u8         reserved_at_8[0x18];
3692
3693         u8         syndrome[0x20];
3694
3695         u8         reserved_at_40[0x40];
3696
3697         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3698
3699         u8         reserved_at_280[0x600];
3700
3701         u8         pas[0][0x40];
3702 };
3703
3704 struct mlx5_ifc_query_xrc_srq_in_bits {
3705         u8         opcode[0x10];
3706         u8         reserved_at_10[0x10];
3707
3708         u8         reserved_at_20[0x10];
3709         u8         op_mod[0x10];
3710
3711         u8         reserved_at_40[0x8];
3712         u8         xrc_srqn[0x18];
3713
3714         u8         reserved_at_60[0x20];
3715 };
3716
3717 enum {
3718         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3719         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3720 };
3721
3722 struct mlx5_ifc_query_vport_state_out_bits {
3723         u8         status[0x8];
3724         u8         reserved_at_8[0x18];
3725
3726         u8         syndrome[0x20];
3727
3728         u8         reserved_at_40[0x20];
3729
3730         u8         reserved_at_60[0x18];
3731         u8         admin_state[0x4];
3732         u8         state[0x4];
3733 };
3734
3735 enum {
3736         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3737         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3738 };
3739
3740 struct mlx5_ifc_query_vport_state_in_bits {
3741         u8         opcode[0x10];
3742         u8         reserved_at_10[0x10];
3743
3744         u8         reserved_at_20[0x10];
3745         u8         op_mod[0x10];
3746
3747         u8         other_vport[0x1];
3748         u8         reserved_at_41[0xf];
3749         u8         vport_number[0x10];
3750
3751         u8         reserved_at_60[0x20];
3752 };
3753
3754 struct mlx5_ifc_query_vnic_env_out_bits {
3755         u8         status[0x8];
3756         u8         reserved_at_8[0x18];
3757
3758         u8         syndrome[0x20];
3759
3760         u8         reserved_at_40[0x40];
3761
3762         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3763 };
3764
3765 enum {
3766         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3767 };
3768
3769 struct mlx5_ifc_query_vnic_env_in_bits {
3770         u8         opcode[0x10];
3771         u8         reserved_at_10[0x10];
3772
3773         u8         reserved_at_20[0x10];
3774         u8         op_mod[0x10];
3775
3776         u8         other_vport[0x1];
3777         u8         reserved_at_41[0xf];
3778         u8         vport_number[0x10];
3779
3780         u8         reserved_at_60[0x20];
3781 };
3782
3783 struct mlx5_ifc_query_vport_counter_out_bits {
3784         u8         status[0x8];
3785         u8         reserved_at_8[0x18];
3786
3787         u8         syndrome[0x20];
3788
3789         u8         reserved_at_40[0x40];
3790
3791         struct mlx5_ifc_traffic_counter_bits received_errors;
3792
3793         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3794
3795         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3796
3797         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3798
3799         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3800
3801         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3802
3803         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3804
3805         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3806
3807         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3808
3809         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3810
3811         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3812
3813         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3814
3815         u8         reserved_at_680[0xa00];
3816 };
3817
3818 enum {
3819         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3820 };
3821
3822 struct mlx5_ifc_query_vport_counter_in_bits {
3823         u8         opcode[0x10];
3824         u8         reserved_at_10[0x10];
3825
3826         u8         reserved_at_20[0x10];
3827         u8         op_mod[0x10];
3828
3829         u8         other_vport[0x1];
3830         u8         reserved_at_41[0xb];
3831         u8         port_num[0x4];
3832         u8         vport_number[0x10];
3833
3834         u8         reserved_at_60[0x60];
3835
3836         u8         clear[0x1];
3837         u8         reserved_at_c1[0x1f];
3838
3839         u8         reserved_at_e0[0x20];
3840 };
3841
3842 struct mlx5_ifc_query_tis_out_bits {
3843         u8         status[0x8];
3844         u8         reserved_at_8[0x18];
3845
3846         u8         syndrome[0x20];
3847
3848         u8         reserved_at_40[0x40];
3849
3850         struct mlx5_ifc_tisc_bits tis_context;
3851 };
3852
3853 struct mlx5_ifc_query_tis_in_bits {
3854         u8         opcode[0x10];
3855         u8         reserved_at_10[0x10];
3856
3857         u8         reserved_at_20[0x10];
3858         u8         op_mod[0x10];
3859
3860         u8         reserved_at_40[0x8];
3861         u8         tisn[0x18];
3862
3863         u8         reserved_at_60[0x20];
3864 };
3865
3866 struct mlx5_ifc_query_tir_out_bits {
3867         u8         status[0x8];
3868         u8         reserved_at_8[0x18];
3869
3870         u8         syndrome[0x20];
3871
3872         u8         reserved_at_40[0xc0];
3873
3874         struct mlx5_ifc_tirc_bits tir_context;
3875 };
3876
3877 struct mlx5_ifc_query_tir_in_bits {
3878         u8         opcode[0x10];
3879         u8         reserved_at_10[0x10];
3880
3881         u8         reserved_at_20[0x10];
3882         u8         op_mod[0x10];
3883
3884         u8         reserved_at_40[0x8];
3885         u8         tirn[0x18];
3886
3887         u8         reserved_at_60[0x20];
3888 };
3889
3890 struct mlx5_ifc_query_srq_out_bits {
3891         u8         status[0x8];
3892         u8         reserved_at_8[0x18];
3893
3894         u8         syndrome[0x20];
3895
3896         u8         reserved_at_40[0x40];
3897
3898         struct mlx5_ifc_srqc_bits srq_context_entry;
3899
3900         u8         reserved_at_280[0x600];
3901
3902         u8         pas[0][0x40];
3903 };
3904
3905 struct mlx5_ifc_query_srq_in_bits {
3906         u8         opcode[0x10];
3907         u8         reserved_at_10[0x10];
3908
3909         u8         reserved_at_20[0x10];
3910         u8         op_mod[0x10];
3911
3912         u8         reserved_at_40[0x8];
3913         u8         srqn[0x18];
3914
3915         u8         reserved_at_60[0x20];
3916 };
3917
3918 struct mlx5_ifc_query_sq_out_bits {
3919         u8         status[0x8];
3920         u8         reserved_at_8[0x18];
3921
3922         u8         syndrome[0x20];
3923
3924         u8         reserved_at_40[0xc0];
3925
3926         struct mlx5_ifc_sqc_bits sq_context;
3927 };
3928
3929 struct mlx5_ifc_query_sq_in_bits {
3930         u8         opcode[0x10];
3931         u8         reserved_at_10[0x10];
3932
3933         u8         reserved_at_20[0x10];
3934         u8         op_mod[0x10];
3935
3936         u8         reserved_at_40[0x8];
3937         u8         sqn[0x18];
3938
3939         u8         reserved_at_60[0x20];
3940 };
3941
3942 struct mlx5_ifc_query_special_contexts_out_bits {
3943         u8         status[0x8];
3944         u8         reserved_at_8[0x18];
3945
3946         u8         syndrome[0x20];
3947
3948         u8         dump_fill_mkey[0x20];
3949
3950         u8         resd_lkey[0x20];
3951
3952         u8         null_mkey[0x20];
3953
3954         u8         reserved_at_a0[0x60];
3955 };
3956
3957 struct mlx5_ifc_query_special_contexts_in_bits {
3958         u8         opcode[0x10];
3959         u8         reserved_at_10[0x10];
3960
3961         u8         reserved_at_20[0x10];
3962         u8         op_mod[0x10];
3963
3964         u8         reserved_at_40[0x40];
3965 };
3966
3967 struct mlx5_ifc_query_scheduling_element_out_bits {
3968         u8         opcode[0x10];
3969         u8         reserved_at_10[0x10];
3970
3971         u8         reserved_at_20[0x10];
3972         u8         op_mod[0x10];
3973
3974         u8         reserved_at_40[0xc0];
3975
3976         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3977
3978         u8         reserved_at_300[0x100];
3979 };
3980
3981 enum {
3982         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3983 };
3984
3985 struct mlx5_ifc_query_scheduling_element_in_bits {
3986         u8         opcode[0x10];
3987         u8         reserved_at_10[0x10];
3988
3989         u8         reserved_at_20[0x10];
3990         u8         op_mod[0x10];
3991
3992         u8         scheduling_hierarchy[0x8];
3993         u8         reserved_at_48[0x18];
3994
3995         u8         scheduling_element_id[0x20];
3996
3997         u8         reserved_at_80[0x180];
3998 };
3999
4000 struct mlx5_ifc_query_rqt_out_bits {
4001         u8         status[0x8];
4002         u8         reserved_at_8[0x18];
4003
4004         u8         syndrome[0x20];
4005
4006         u8         reserved_at_40[0xc0];
4007
4008         struct mlx5_ifc_rqtc_bits rqt_context;
4009 };
4010
4011 struct mlx5_ifc_query_rqt_in_bits {
4012         u8         opcode[0x10];
4013         u8         reserved_at_10[0x10];
4014
4015         u8         reserved_at_20[0x10];
4016         u8         op_mod[0x10];
4017
4018         u8         reserved_at_40[0x8];
4019         u8         rqtn[0x18];
4020
4021         u8         reserved_at_60[0x20];
4022 };
4023
4024 struct mlx5_ifc_query_rq_out_bits {
4025         u8         status[0x8];
4026         u8         reserved_at_8[0x18];
4027
4028         u8         syndrome[0x20];
4029
4030         u8         reserved_at_40[0xc0];
4031
4032         struct mlx5_ifc_rqc_bits rq_context;
4033 };
4034
4035 struct mlx5_ifc_query_rq_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_at_10[0x10];
4038
4039         u8         reserved_at_20[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_at_40[0x8];
4043         u8         rqn[0x18];
4044
4045         u8         reserved_at_60[0x20];
4046 };
4047
4048 struct mlx5_ifc_query_roce_address_out_bits {
4049         u8         status[0x8];
4050         u8         reserved_at_8[0x18];
4051
4052         u8         syndrome[0x20];
4053
4054         u8         reserved_at_40[0x40];
4055
4056         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4057 };
4058
4059 struct mlx5_ifc_query_roce_address_in_bits {
4060         u8         opcode[0x10];
4061         u8         reserved_at_10[0x10];
4062
4063         u8         reserved_at_20[0x10];
4064         u8         op_mod[0x10];
4065
4066         u8         roce_address_index[0x10];
4067         u8         reserved_at_50[0xc];
4068         u8         vhca_port_num[0x4];
4069
4070         u8         reserved_at_60[0x20];
4071 };
4072
4073 struct mlx5_ifc_query_rmp_out_bits {
4074         u8         status[0x8];
4075         u8         reserved_at_8[0x18];
4076
4077         u8         syndrome[0x20];
4078
4079         u8         reserved_at_40[0xc0];
4080
4081         struct mlx5_ifc_rmpc_bits rmp_context;
4082 };
4083
4084 struct mlx5_ifc_query_rmp_in_bits {
4085         u8         opcode[0x10];
4086         u8         reserved_at_10[0x10];
4087
4088         u8         reserved_at_20[0x10];
4089         u8         op_mod[0x10];
4090
4091         u8         reserved_at_40[0x8];
4092         u8         rmpn[0x18];
4093
4094         u8         reserved_at_60[0x20];
4095 };
4096
4097 struct mlx5_ifc_query_qp_out_bits {
4098         u8         status[0x8];
4099         u8         reserved_at_8[0x18];
4100
4101         u8         syndrome[0x20];
4102
4103         u8         reserved_at_40[0x40];
4104
4105         u8         opt_param_mask[0x20];
4106
4107         u8         reserved_at_a0[0x20];
4108
4109         struct mlx5_ifc_qpc_bits qpc;
4110
4111         u8         reserved_at_800[0x80];
4112
4113         u8         pas[0][0x40];
4114 };
4115
4116 struct mlx5_ifc_query_qp_in_bits {
4117         u8         opcode[0x10];
4118         u8         reserved_at_10[0x10];
4119
4120         u8         reserved_at_20[0x10];
4121         u8         op_mod[0x10];
4122
4123         u8         reserved_at_40[0x8];
4124         u8         qpn[0x18];
4125
4126         u8         reserved_at_60[0x20];
4127 };
4128
4129 struct mlx5_ifc_query_q_counter_out_bits {
4130         u8         status[0x8];
4131         u8         reserved_at_8[0x18];
4132
4133         u8         syndrome[0x20];
4134
4135         u8         reserved_at_40[0x40];
4136
4137         u8         rx_write_requests[0x20];
4138
4139         u8         reserved_at_a0[0x20];
4140
4141         u8         rx_read_requests[0x20];
4142
4143         u8         reserved_at_e0[0x20];
4144
4145         u8         rx_atomic_requests[0x20];
4146
4147         u8         reserved_at_120[0x20];
4148
4149         u8         rx_dct_connect[0x20];
4150
4151         u8         reserved_at_160[0x20];
4152
4153         u8         out_of_buffer[0x20];
4154
4155         u8         reserved_at_1a0[0x20];
4156
4157         u8         out_of_sequence[0x20];
4158
4159         u8         reserved_at_1e0[0x20];
4160
4161         u8         duplicate_request[0x20];
4162
4163         u8         reserved_at_220[0x20];
4164
4165         u8         rnr_nak_retry_err[0x20];
4166
4167         u8         reserved_at_260[0x20];
4168
4169         u8         packet_seq_err[0x20];
4170
4171         u8         reserved_at_2a0[0x20];
4172
4173         u8         implied_nak_seq_err[0x20];
4174
4175         u8         reserved_at_2e0[0x20];
4176
4177         u8         local_ack_timeout_err[0x20];
4178
4179         u8         reserved_at_320[0xa0];
4180
4181         u8         resp_local_length_error[0x20];
4182
4183         u8         req_local_length_error[0x20];
4184
4185         u8         resp_local_qp_error[0x20];
4186
4187         u8         local_operation_error[0x20];
4188
4189         u8         resp_local_protection[0x20];
4190
4191         u8         req_local_protection[0x20];
4192
4193         u8         resp_cqe_error[0x20];
4194
4195         u8         req_cqe_error[0x20];
4196
4197         u8         req_mw_binding[0x20];
4198
4199         u8         req_bad_response[0x20];
4200
4201         u8         req_remote_invalid_request[0x20];
4202
4203         u8         resp_remote_invalid_request[0x20];
4204
4205         u8         req_remote_access_errors[0x20];
4206
4207         u8         resp_remote_access_errors[0x20];
4208
4209         u8         req_remote_operation_errors[0x20];
4210
4211         u8         req_transport_retries_exceeded[0x20];
4212
4213         u8         cq_overflow[0x20];
4214
4215         u8         resp_cqe_flush_error[0x20];
4216
4217         u8         req_cqe_flush_error[0x20];
4218
4219         u8         reserved_at_620[0x1e0];
4220 };
4221
4222 struct mlx5_ifc_query_q_counter_in_bits {
4223         u8         opcode[0x10];
4224         u8         reserved_at_10[0x10];
4225
4226         u8         reserved_at_20[0x10];
4227         u8         op_mod[0x10];
4228
4229         u8         reserved_at_40[0x80];
4230
4231         u8         clear[0x1];
4232         u8         reserved_at_c1[0x1f];
4233
4234         u8         reserved_at_e0[0x18];
4235         u8         counter_set_id[0x8];
4236 };
4237
4238 struct mlx5_ifc_query_pages_out_bits {
4239         u8         status[0x8];
4240         u8         reserved_at_8[0x18];
4241
4242         u8         syndrome[0x20];
4243
4244         u8         reserved_at_40[0x10];
4245         u8         function_id[0x10];
4246
4247         u8         num_pages[0x20];
4248 };
4249
4250 enum {
4251         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4252         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4253         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4254 };
4255
4256 struct mlx5_ifc_query_pages_in_bits {
4257         u8         opcode[0x10];
4258         u8         reserved_at_10[0x10];
4259
4260         u8         reserved_at_20[0x10];
4261         u8         op_mod[0x10];
4262
4263         u8         reserved_at_40[0x10];
4264         u8         function_id[0x10];
4265
4266         u8         reserved_at_60[0x20];
4267 };
4268
4269 struct mlx5_ifc_query_nic_vport_context_out_bits {
4270         u8         status[0x8];
4271         u8         reserved_at_8[0x18];
4272
4273         u8         syndrome[0x20];
4274
4275         u8         reserved_at_40[0x40];
4276
4277         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4278 };
4279
4280 struct mlx5_ifc_query_nic_vport_context_in_bits {
4281         u8         opcode[0x10];
4282         u8         reserved_at_10[0x10];
4283
4284         u8         reserved_at_20[0x10];
4285         u8         op_mod[0x10];
4286
4287         u8         other_vport[0x1];
4288         u8         reserved_at_41[0xf];
4289         u8         vport_number[0x10];
4290
4291         u8         reserved_at_60[0x5];
4292         u8         allowed_list_type[0x3];
4293         u8         reserved_at_68[0x18];
4294 };
4295
4296 struct mlx5_ifc_query_mkey_out_bits {
4297         u8         status[0x8];
4298         u8         reserved_at_8[0x18];
4299
4300         u8         syndrome[0x20];
4301
4302         u8         reserved_at_40[0x40];
4303
4304         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4305
4306         u8         reserved_at_280[0x600];
4307
4308         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4309
4310         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4311 };
4312
4313 struct mlx5_ifc_query_mkey_in_bits {
4314         u8         opcode[0x10];
4315         u8         reserved_at_10[0x10];
4316
4317         u8         reserved_at_20[0x10];
4318         u8         op_mod[0x10];
4319
4320         u8         reserved_at_40[0x8];
4321         u8         mkey_index[0x18];
4322
4323         u8         pg_access[0x1];
4324         u8         reserved_at_61[0x1f];
4325 };
4326
4327 struct mlx5_ifc_query_mad_demux_out_bits {
4328         u8         status[0x8];
4329         u8         reserved_at_8[0x18];
4330
4331         u8         syndrome[0x20];
4332
4333         u8         reserved_at_40[0x40];
4334
4335         u8         mad_dumux_parameters_block[0x20];
4336 };
4337
4338 struct mlx5_ifc_query_mad_demux_in_bits {
4339         u8         opcode[0x10];
4340         u8         reserved_at_10[0x10];
4341
4342         u8         reserved_at_20[0x10];
4343         u8         op_mod[0x10];
4344
4345         u8         reserved_at_40[0x40];
4346 };
4347
4348 struct mlx5_ifc_query_l2_table_entry_out_bits {
4349         u8         status[0x8];
4350         u8         reserved_at_8[0x18];
4351
4352         u8         syndrome[0x20];
4353
4354         u8         reserved_at_40[0xa0];
4355
4356         u8         reserved_at_e0[0x13];
4357         u8         vlan_valid[0x1];
4358         u8         vlan[0xc];
4359
4360         struct mlx5_ifc_mac_address_layout_bits mac_address;
4361
4362         u8         reserved_at_140[0xc0];
4363 };
4364
4365 struct mlx5_ifc_query_l2_table_entry_in_bits {
4366         u8         opcode[0x10];
4367         u8         reserved_at_10[0x10];
4368
4369         u8         reserved_at_20[0x10];
4370         u8         op_mod[0x10];
4371
4372         u8         reserved_at_40[0x60];
4373
4374         u8         reserved_at_a0[0x8];
4375         u8         table_index[0x18];
4376
4377         u8         reserved_at_c0[0x140];
4378 };
4379
4380 struct mlx5_ifc_query_issi_out_bits {
4381         u8         status[0x8];
4382         u8         reserved_at_8[0x18];
4383
4384         u8         syndrome[0x20];
4385
4386         u8         reserved_at_40[0x10];
4387         u8         current_issi[0x10];
4388
4389         u8         reserved_at_60[0xa0];
4390
4391         u8         reserved_at_100[76][0x8];
4392         u8         supported_issi_dw0[0x20];
4393 };
4394
4395 struct mlx5_ifc_query_issi_in_bits {
4396         u8         opcode[0x10];
4397         u8         reserved_at_10[0x10];
4398
4399         u8         reserved_at_20[0x10];
4400         u8         op_mod[0x10];
4401
4402         u8         reserved_at_40[0x40];
4403 };
4404
4405 struct mlx5_ifc_set_driver_version_out_bits {
4406         u8         status[0x8];
4407         u8         reserved_0[0x18];
4408
4409         u8         syndrome[0x20];
4410         u8         reserved_1[0x40];
4411 };
4412
4413 struct mlx5_ifc_set_driver_version_in_bits {
4414         u8         opcode[0x10];
4415         u8         reserved_0[0x10];
4416
4417         u8         reserved_1[0x10];
4418         u8         op_mod[0x10];
4419
4420         u8         reserved_2[0x40];
4421         u8         driver_version[64][0x8];
4422 };
4423
4424 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4425         u8         status[0x8];
4426         u8         reserved_at_8[0x18];
4427
4428         u8         syndrome[0x20];
4429
4430         u8         reserved_at_40[0x40];
4431
4432         struct mlx5_ifc_pkey_bits pkey[0];
4433 };
4434
4435 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4436         u8         opcode[0x10];
4437         u8         reserved_at_10[0x10];
4438
4439         u8         reserved_at_20[0x10];
4440         u8         op_mod[0x10];
4441
4442         u8         other_vport[0x1];
4443         u8         reserved_at_41[0xb];
4444         u8         port_num[0x4];
4445         u8         vport_number[0x10];
4446
4447         u8         reserved_at_60[0x10];
4448         u8         pkey_index[0x10];
4449 };
4450
4451 enum {
4452         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4453         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4454         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4455 };
4456
4457 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4458         u8         status[0x8];
4459         u8         reserved_at_8[0x18];
4460
4461         u8         syndrome[0x20];
4462
4463         u8         reserved_at_40[0x20];
4464
4465         u8         gids_num[0x10];
4466         u8         reserved_at_70[0x10];
4467
4468         struct mlx5_ifc_array128_auto_bits gid[0];
4469 };
4470
4471 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4472         u8         opcode[0x10];
4473         u8         reserved_at_10[0x10];
4474
4475         u8         reserved_at_20[0x10];
4476         u8         op_mod[0x10];
4477
4478         u8         other_vport[0x1];
4479         u8         reserved_at_41[0xb];
4480         u8         port_num[0x4];
4481         u8         vport_number[0x10];
4482
4483         u8         reserved_at_60[0x10];
4484         u8         gid_index[0x10];
4485 };
4486
4487 struct mlx5_ifc_query_hca_vport_context_out_bits {
4488         u8         status[0x8];
4489         u8         reserved_at_8[0x18];
4490
4491         u8         syndrome[0x20];
4492
4493         u8         reserved_at_40[0x40];
4494
4495         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4496 };
4497
4498 struct mlx5_ifc_query_hca_vport_context_in_bits {
4499         u8         opcode[0x10];
4500         u8         reserved_at_10[0x10];
4501
4502         u8         reserved_at_20[0x10];
4503         u8         op_mod[0x10];
4504
4505         u8         other_vport[0x1];
4506         u8         reserved_at_41[0xb];
4507         u8         port_num[0x4];
4508         u8         vport_number[0x10];
4509
4510         u8         reserved_at_60[0x20];
4511 };
4512
4513 struct mlx5_ifc_query_hca_cap_out_bits {
4514         u8         status[0x8];
4515         u8         reserved_at_8[0x18];
4516
4517         u8         syndrome[0x20];
4518
4519         u8         reserved_at_40[0x40];
4520
4521         union mlx5_ifc_hca_cap_union_bits capability;
4522 };
4523
4524 struct mlx5_ifc_query_hca_cap_in_bits {
4525         u8         opcode[0x10];
4526         u8         reserved_at_10[0x10];
4527
4528         u8         reserved_at_20[0x10];
4529         u8         op_mod[0x10];
4530
4531         u8         reserved_at_40[0x40];
4532 };
4533
4534 struct mlx5_ifc_query_flow_table_out_bits {
4535         u8         status[0x8];
4536         u8         reserved_at_8[0x18];
4537
4538         u8         syndrome[0x20];
4539
4540         u8         reserved_at_40[0x80];
4541
4542         u8         reserved_at_c0[0x8];
4543         u8         level[0x8];
4544         u8         reserved_at_d0[0x8];
4545         u8         log_size[0x8];
4546
4547         u8         reserved_at_e0[0x120];
4548 };
4549
4550 struct mlx5_ifc_query_flow_table_in_bits {
4551         u8         opcode[0x10];
4552         u8         reserved_at_10[0x10];
4553
4554         u8         reserved_at_20[0x10];
4555         u8         op_mod[0x10];
4556
4557         u8         reserved_at_40[0x40];
4558
4559         u8         table_type[0x8];
4560         u8         reserved_at_88[0x18];
4561
4562         u8         reserved_at_a0[0x8];
4563         u8         table_id[0x18];
4564
4565         u8         reserved_at_c0[0x140];
4566 };
4567
4568 struct mlx5_ifc_query_fte_out_bits {
4569         u8         status[0x8];
4570         u8         reserved_at_8[0x18];
4571
4572         u8         syndrome[0x20];
4573
4574         u8         reserved_at_40[0x1c0];
4575
4576         struct mlx5_ifc_flow_context_bits flow_context;
4577 };
4578
4579 struct mlx5_ifc_query_fte_in_bits {
4580         u8         opcode[0x10];
4581         u8         reserved_at_10[0x10];
4582
4583         u8         reserved_at_20[0x10];
4584         u8         op_mod[0x10];
4585
4586         u8         reserved_at_40[0x40];
4587
4588         u8         table_type[0x8];
4589         u8         reserved_at_88[0x18];
4590
4591         u8         reserved_at_a0[0x8];
4592         u8         table_id[0x18];
4593
4594         u8         reserved_at_c0[0x40];
4595
4596         u8         flow_index[0x20];
4597
4598         u8         reserved_at_120[0xe0];
4599 };
4600
4601 enum {
4602         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4603         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4604         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4605         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4606 };
4607
4608 struct mlx5_ifc_query_flow_group_out_bits {
4609         u8         status[0x8];
4610         u8         reserved_at_8[0x18];
4611
4612         u8         syndrome[0x20];
4613
4614         u8         reserved_at_40[0xa0];
4615
4616         u8         start_flow_index[0x20];
4617
4618         u8         reserved_at_100[0x20];
4619
4620         u8         end_flow_index[0x20];
4621
4622         u8         reserved_at_140[0xa0];
4623
4624         u8         reserved_at_1e0[0x18];
4625         u8         match_criteria_enable[0x8];
4626
4627         struct mlx5_ifc_fte_match_param_bits match_criteria;
4628
4629         u8         reserved_at_1200[0xe00];
4630 };
4631
4632 struct mlx5_ifc_query_flow_group_in_bits {
4633         u8         opcode[0x10];
4634         u8         reserved_at_10[0x10];
4635
4636         u8         reserved_at_20[0x10];
4637         u8         op_mod[0x10];
4638
4639         u8         reserved_at_40[0x40];
4640
4641         u8         table_type[0x8];
4642         u8         reserved_at_88[0x18];
4643
4644         u8         reserved_at_a0[0x8];
4645         u8         table_id[0x18];
4646
4647         u8         group_id[0x20];
4648
4649         u8         reserved_at_e0[0x120];
4650 };
4651
4652 struct mlx5_ifc_query_flow_counter_out_bits {
4653         u8         status[0x8];
4654         u8         reserved_at_8[0x18];
4655
4656         u8         syndrome[0x20];
4657
4658         u8         reserved_at_40[0x40];
4659
4660         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4661 };
4662
4663 struct mlx5_ifc_query_flow_counter_in_bits {
4664         u8         opcode[0x10];
4665         u8         reserved_at_10[0x10];
4666
4667         u8         reserved_at_20[0x10];
4668         u8         op_mod[0x10];
4669
4670         u8         reserved_at_40[0x80];
4671
4672         u8         clear[0x1];
4673         u8         reserved_at_c1[0xf];
4674         u8         num_of_counters[0x10];
4675
4676         u8         flow_counter_id[0x20];
4677 };
4678
4679 struct mlx5_ifc_query_esw_vport_context_out_bits {
4680         u8         status[0x8];
4681         u8         reserved_at_8[0x18];
4682
4683         u8         syndrome[0x20];
4684
4685         u8         reserved_at_40[0x40];
4686
4687         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4688 };
4689
4690 struct mlx5_ifc_query_esw_vport_context_in_bits {
4691         u8         opcode[0x10];
4692         u8         reserved_at_10[0x10];
4693
4694         u8         reserved_at_20[0x10];
4695         u8         op_mod[0x10];
4696
4697         u8         other_vport[0x1];
4698         u8         reserved_at_41[0xf];
4699         u8         vport_number[0x10];
4700
4701         u8         reserved_at_60[0x20];
4702 };
4703
4704 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4705         u8         status[0x8];
4706         u8         reserved_at_8[0x18];
4707
4708         u8         syndrome[0x20];
4709
4710         u8         reserved_at_40[0x40];
4711 };
4712
4713 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4714         u8         reserved_at_0[0x1c];
4715         u8         vport_cvlan_insert[0x1];
4716         u8         vport_svlan_insert[0x1];
4717         u8         vport_cvlan_strip[0x1];
4718         u8         vport_svlan_strip[0x1];
4719 };
4720
4721 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4722         u8         opcode[0x10];
4723         u8         reserved_at_10[0x10];
4724
4725         u8         reserved_at_20[0x10];
4726         u8         op_mod[0x10];
4727
4728         u8         other_vport[0x1];
4729         u8         reserved_at_41[0xf];
4730         u8         vport_number[0x10];
4731
4732         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4733
4734         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4735 };
4736
4737 struct mlx5_ifc_query_eq_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x40];
4744
4745         struct mlx5_ifc_eqc_bits eq_context_entry;
4746
4747         u8         reserved_at_280[0x40];
4748
4749         u8         event_bitmask[0x40];
4750
4751         u8         reserved_at_300[0x580];
4752
4753         u8         pas[0][0x40];
4754 };
4755
4756 struct mlx5_ifc_query_eq_in_bits {
4757         u8         opcode[0x10];
4758         u8         reserved_at_10[0x10];
4759
4760         u8         reserved_at_20[0x10];
4761         u8         op_mod[0x10];
4762
4763         u8         reserved_at_40[0x18];
4764         u8         eq_number[0x8];
4765
4766         u8         reserved_at_60[0x20];
4767 };
4768
4769 struct mlx5_ifc_encap_header_in_bits {
4770         u8         reserved_at_0[0x5];
4771         u8         header_type[0x3];
4772         u8         reserved_at_8[0xe];
4773         u8         encap_header_size[0xa];
4774
4775         u8         reserved_at_20[0x10];
4776         u8         encap_header[2][0x8];
4777
4778         u8         more_encap_header[0][0x8];
4779 };
4780
4781 struct mlx5_ifc_query_encap_header_out_bits {
4782         u8         status[0x8];
4783         u8         reserved_at_8[0x18];
4784
4785         u8         syndrome[0x20];
4786
4787         u8         reserved_at_40[0xa0];
4788
4789         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4790 };
4791
4792 struct mlx5_ifc_query_encap_header_in_bits {
4793         u8         opcode[0x10];
4794         u8         reserved_at_10[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         encap_id[0x20];
4800
4801         u8         reserved_at_60[0xa0];
4802 };
4803
4804 struct mlx5_ifc_alloc_encap_header_out_bits {
4805         u8         status[0x8];
4806         u8         reserved_at_8[0x18];
4807
4808         u8         syndrome[0x20];
4809
4810         u8         encap_id[0x20];
4811
4812         u8         reserved_at_60[0x20];
4813 };
4814
4815 struct mlx5_ifc_alloc_encap_header_in_bits {
4816         u8         opcode[0x10];
4817         u8         reserved_at_10[0x10];
4818
4819         u8         reserved_at_20[0x10];
4820         u8         op_mod[0x10];
4821
4822         u8         reserved_at_40[0xa0];
4823
4824         struct mlx5_ifc_encap_header_in_bits encap_header;
4825 };
4826
4827 struct mlx5_ifc_dealloc_encap_header_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_at_8[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_at_40[0x40];
4834 };
4835
4836 struct mlx5_ifc_dealloc_encap_header_in_bits {
4837         u8         opcode[0x10];
4838         u8         reserved_at_10[0x10];
4839
4840         u8         reserved_20[0x10];
4841         u8         op_mod[0x10];
4842
4843         u8         encap_id[0x20];
4844
4845         u8         reserved_60[0x20];
4846 };
4847
4848 struct mlx5_ifc_set_action_in_bits {
4849         u8         action_type[0x4];
4850         u8         field[0xc];
4851         u8         reserved_at_10[0x3];
4852         u8         offset[0x5];
4853         u8         reserved_at_18[0x3];
4854         u8         length[0x5];
4855
4856         u8         data[0x20];
4857 };
4858
4859 struct mlx5_ifc_add_action_in_bits {
4860         u8         action_type[0x4];
4861         u8         field[0xc];
4862         u8         reserved_at_10[0x10];
4863
4864         u8         data[0x20];
4865 };
4866
4867 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4868         struct mlx5_ifc_set_action_in_bits set_action_in;
4869         struct mlx5_ifc_add_action_in_bits add_action_in;
4870         u8         reserved_at_0[0x40];
4871 };
4872
4873 enum {
4874         MLX5_ACTION_TYPE_SET   = 0x1,
4875         MLX5_ACTION_TYPE_ADD   = 0x2,
4876 };
4877
4878 enum {
4879         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4880         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4881         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4882         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4883         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4884         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4885         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4886         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4887         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4888         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4889         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4890         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4891         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4892         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4893         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4894         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4895         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4896         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4897         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4898         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4899         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4900         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4901         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4902 };
4903
4904 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4905         u8         status[0x8];
4906         u8         reserved_at_8[0x18];
4907
4908         u8         syndrome[0x20];
4909
4910         u8         modify_header_id[0x20];
4911
4912         u8         reserved_at_60[0x20];
4913 };
4914
4915 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4916         u8         opcode[0x10];
4917         u8         reserved_at_10[0x10];
4918
4919         u8         reserved_at_20[0x10];
4920         u8         op_mod[0x10];
4921
4922         u8         reserved_at_40[0x20];
4923
4924         u8         table_type[0x8];
4925         u8         reserved_at_68[0x10];
4926         u8         num_of_actions[0x8];
4927
4928         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4929 };
4930
4931 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4932         u8         status[0x8];
4933         u8         reserved_at_8[0x18];
4934
4935         u8         syndrome[0x20];
4936
4937         u8         reserved_at_40[0x40];
4938 };
4939
4940 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4941         u8         opcode[0x10];
4942         u8         reserved_at_10[0x10];
4943
4944         u8         reserved_at_20[0x10];
4945         u8         op_mod[0x10];
4946
4947         u8         modify_header_id[0x20];
4948
4949         u8         reserved_at_60[0x20];
4950 };
4951
4952 struct mlx5_ifc_query_dct_out_bits {
4953         u8         status[0x8];
4954         u8         reserved_at_8[0x18];
4955
4956         u8         syndrome[0x20];
4957
4958         u8         reserved_at_40[0x40];
4959
4960         struct mlx5_ifc_dctc_bits dct_context_entry;
4961
4962         u8         reserved_at_280[0x180];
4963 };
4964
4965 struct mlx5_ifc_query_dct_in_bits {
4966         u8         opcode[0x10];
4967         u8         reserved_at_10[0x10];
4968
4969         u8         reserved_at_20[0x10];
4970         u8         op_mod[0x10];
4971
4972         u8         reserved_at_40[0x8];
4973         u8         dctn[0x18];
4974
4975         u8         reserved_at_60[0x20];
4976 };
4977
4978 struct mlx5_ifc_query_cq_out_bits {
4979         u8         status[0x8];
4980         u8         reserved_at_8[0x18];
4981
4982         u8         syndrome[0x20];
4983
4984         u8         reserved_at_40[0x40];
4985
4986         struct mlx5_ifc_cqc_bits cq_context;
4987
4988         u8         reserved_at_280[0x600];
4989
4990         u8         pas[0][0x40];
4991 };
4992
4993 struct mlx5_ifc_query_cq_in_bits {
4994         u8         opcode[0x10];
4995         u8         reserved_at_10[0x10];
4996
4997         u8         reserved_at_20[0x10];
4998         u8         op_mod[0x10];
4999
5000         u8         reserved_at_40[0x8];
5001         u8         cqn[0x18];
5002
5003         u8         reserved_at_60[0x20];
5004 };
5005
5006 struct mlx5_ifc_query_cong_status_out_bits {
5007         u8         status[0x8];
5008         u8         reserved_at_8[0x18];
5009
5010         u8         syndrome[0x20];
5011
5012         u8         reserved_at_40[0x20];
5013
5014         u8         enable[0x1];
5015         u8         tag_enable[0x1];
5016         u8         reserved_at_62[0x1e];
5017 };
5018
5019 struct mlx5_ifc_query_cong_status_in_bits {
5020         u8         opcode[0x10];
5021         u8         reserved_at_10[0x10];
5022
5023         u8         reserved_at_20[0x10];
5024         u8         op_mod[0x10];
5025
5026         u8         reserved_at_40[0x18];
5027         u8         priority[0x4];
5028         u8         cong_protocol[0x4];
5029
5030         u8         reserved_at_60[0x20];
5031 };
5032
5033 struct mlx5_ifc_query_cong_statistics_out_bits {
5034         u8         status[0x8];
5035         u8         reserved_at_8[0x18];
5036
5037         u8         syndrome[0x20];
5038
5039         u8         reserved_at_40[0x40];
5040
5041         u8         rp_cur_flows[0x20];
5042
5043         u8         sum_flows[0x20];
5044
5045         u8         rp_cnp_ignored_high[0x20];
5046
5047         u8         rp_cnp_ignored_low[0x20];
5048
5049         u8         rp_cnp_handled_high[0x20];
5050
5051         u8         rp_cnp_handled_low[0x20];
5052
5053         u8         reserved_at_140[0x100];
5054
5055         u8         time_stamp_high[0x20];
5056
5057         u8         time_stamp_low[0x20];
5058
5059         u8         accumulators_period[0x20];
5060
5061         u8         np_ecn_marked_roce_packets_high[0x20];
5062
5063         u8         np_ecn_marked_roce_packets_low[0x20];
5064
5065         u8         np_cnp_sent_high[0x20];
5066
5067         u8         np_cnp_sent_low[0x20];
5068
5069         u8         reserved_at_320[0x560];
5070 };
5071
5072 struct mlx5_ifc_query_cong_statistics_in_bits {
5073         u8         opcode[0x10];
5074         u8         reserved_at_10[0x10];
5075
5076         u8         reserved_at_20[0x10];
5077         u8         op_mod[0x10];
5078
5079         u8         clear[0x1];
5080         u8         reserved_at_41[0x1f];
5081
5082         u8         reserved_at_60[0x20];
5083 };
5084
5085 struct mlx5_ifc_query_cong_params_out_bits {
5086         u8         status[0x8];
5087         u8         reserved_at_8[0x18];
5088
5089         u8         syndrome[0x20];
5090
5091         u8         reserved_at_40[0x40];
5092
5093         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5094 };
5095
5096 struct mlx5_ifc_query_cong_params_in_bits {
5097         u8         opcode[0x10];
5098         u8         reserved_at_10[0x10];
5099
5100         u8         reserved_at_20[0x10];
5101         u8         op_mod[0x10];
5102
5103         u8         reserved_at_40[0x1c];
5104         u8         cong_protocol[0x4];
5105
5106         u8         reserved_at_60[0x20];
5107 };
5108
5109 struct mlx5_ifc_query_adapter_out_bits {
5110         u8         status[0x8];
5111         u8         reserved_at_8[0x18];
5112
5113         u8         syndrome[0x20];
5114
5115         u8         reserved_at_40[0x40];
5116
5117         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5118 };
5119
5120 struct mlx5_ifc_query_adapter_in_bits {
5121         u8         opcode[0x10];
5122         u8         reserved_at_10[0x10];
5123
5124         u8         reserved_at_20[0x10];
5125         u8         op_mod[0x10];
5126
5127         u8         reserved_at_40[0x40];
5128 };
5129
5130 struct mlx5_ifc_qp_2rst_out_bits {
5131         u8         status[0x8];
5132         u8         reserved_at_8[0x18];
5133
5134         u8         syndrome[0x20];
5135
5136         u8         reserved_at_40[0x40];
5137 };
5138
5139 struct mlx5_ifc_qp_2rst_in_bits {
5140         u8         opcode[0x10];
5141         u8         reserved_at_10[0x10];
5142
5143         u8         reserved_at_20[0x10];
5144         u8         op_mod[0x10];
5145
5146         u8         reserved_at_40[0x8];
5147         u8         qpn[0x18];
5148
5149         u8         reserved_at_60[0x20];
5150 };
5151
5152 struct mlx5_ifc_qp_2err_out_bits {
5153         u8         status[0x8];
5154         u8         reserved_at_8[0x18];
5155
5156         u8         syndrome[0x20];
5157
5158         u8         reserved_at_40[0x40];
5159 };
5160
5161 struct mlx5_ifc_qp_2err_in_bits {
5162         u8         opcode[0x10];
5163         u8         reserved_at_10[0x10];
5164
5165         u8         reserved_at_20[0x10];
5166         u8         op_mod[0x10];
5167
5168         u8         reserved_at_40[0x8];
5169         u8         qpn[0x18];
5170
5171         u8         reserved_at_60[0x20];
5172 };
5173
5174 struct mlx5_ifc_page_fault_resume_out_bits {
5175         u8         status[0x8];
5176         u8         reserved_at_8[0x18];
5177
5178         u8         syndrome[0x20];
5179
5180         u8         reserved_at_40[0x40];
5181 };
5182
5183 struct mlx5_ifc_page_fault_resume_in_bits {
5184         u8         opcode[0x10];
5185         u8         reserved_at_10[0x10];
5186
5187         u8         reserved_at_20[0x10];
5188         u8         op_mod[0x10];
5189
5190         u8         error[0x1];
5191         u8         reserved_at_41[0x4];
5192         u8         page_fault_type[0x3];
5193         u8         wq_number[0x18];
5194
5195         u8         reserved_at_60[0x8];
5196         u8         token[0x18];
5197 };
5198
5199 struct mlx5_ifc_nop_out_bits {
5200         u8         status[0x8];
5201         u8         reserved_at_8[0x18];
5202
5203         u8         syndrome[0x20];
5204
5205         u8         reserved_at_40[0x40];
5206 };
5207
5208 struct mlx5_ifc_nop_in_bits {
5209         u8         opcode[0x10];
5210         u8         reserved_at_10[0x10];
5211
5212         u8         reserved_at_20[0x10];
5213         u8         op_mod[0x10];
5214
5215         u8         reserved_at_40[0x40];
5216 };
5217
5218 struct mlx5_ifc_modify_vport_state_out_bits {
5219         u8         status[0x8];
5220         u8         reserved_at_8[0x18];
5221
5222         u8         syndrome[0x20];
5223
5224         u8         reserved_at_40[0x40];
5225 };
5226
5227 struct mlx5_ifc_modify_vport_state_in_bits {
5228         u8         opcode[0x10];
5229         u8         reserved_at_10[0x10];
5230
5231         u8         reserved_at_20[0x10];
5232         u8         op_mod[0x10];
5233
5234         u8         other_vport[0x1];
5235         u8         reserved_at_41[0xf];
5236         u8         vport_number[0x10];
5237
5238         u8         reserved_at_60[0x18];
5239         u8         admin_state[0x4];
5240         u8         reserved_at_7c[0x4];
5241 };
5242
5243 struct mlx5_ifc_modify_tis_out_bits {
5244         u8         status[0x8];
5245         u8         reserved_at_8[0x18];
5246
5247         u8         syndrome[0x20];
5248
5249         u8         reserved_at_40[0x40];
5250 };
5251
5252 struct mlx5_ifc_modify_tis_bitmask_bits {
5253         u8         reserved_at_0[0x20];
5254
5255         u8         reserved_at_20[0x1d];
5256         u8         lag_tx_port_affinity[0x1];
5257         u8         strict_lag_tx_port_affinity[0x1];
5258         u8         prio[0x1];
5259 };
5260
5261 struct mlx5_ifc_modify_tis_in_bits {
5262         u8         opcode[0x10];
5263         u8         reserved_at_10[0x10];
5264
5265         u8         reserved_at_20[0x10];
5266         u8         op_mod[0x10];
5267
5268         u8         reserved_at_40[0x8];
5269         u8         tisn[0x18];
5270
5271         u8         reserved_at_60[0x20];
5272
5273         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5274
5275         u8         reserved_at_c0[0x40];
5276
5277         struct mlx5_ifc_tisc_bits ctx;
5278 };
5279
5280 struct mlx5_ifc_modify_tir_bitmask_bits {
5281         u8         reserved_at_0[0x20];
5282
5283         u8         reserved_at_20[0x1b];
5284         u8         self_lb_en[0x1];
5285         u8         reserved_at_3c[0x1];
5286         u8         hash[0x1];
5287         u8         reserved_at_3e[0x1];
5288         u8         lro[0x1];
5289 };
5290
5291 struct mlx5_ifc_modify_tir_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_at_8[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_at_40[0x40];
5298 };
5299
5300 struct mlx5_ifc_modify_tir_in_bits {
5301         u8         opcode[0x10];
5302         u8         reserved_at_10[0x10];
5303
5304         u8         reserved_at_20[0x10];
5305         u8         op_mod[0x10];
5306
5307         u8         reserved_at_40[0x8];
5308         u8         tirn[0x18];
5309
5310         u8         reserved_at_60[0x20];
5311
5312         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5313
5314         u8         reserved_at_c0[0x40];
5315
5316         struct mlx5_ifc_tirc_bits ctx;
5317 };
5318
5319 struct mlx5_ifc_modify_sq_out_bits {
5320         u8         status[0x8];
5321         u8         reserved_at_8[0x18];
5322
5323         u8         syndrome[0x20];
5324
5325         u8         reserved_at_40[0x40];
5326 };
5327
5328 struct mlx5_ifc_modify_sq_in_bits {
5329         u8         opcode[0x10];
5330         u8         reserved_at_10[0x10];
5331
5332         u8         reserved_at_20[0x10];
5333         u8         op_mod[0x10];
5334
5335         u8         sq_state[0x4];
5336         u8         reserved_at_44[0x4];
5337         u8         sqn[0x18];
5338
5339         u8         reserved_at_60[0x20];
5340
5341         u8         modify_bitmask[0x40];
5342
5343         u8         reserved_at_c0[0x40];
5344
5345         struct mlx5_ifc_sqc_bits ctx;
5346 };
5347
5348 struct mlx5_ifc_modify_scheduling_element_out_bits {
5349         u8         status[0x8];
5350         u8         reserved_at_8[0x18];
5351
5352         u8         syndrome[0x20];
5353
5354         u8         reserved_at_40[0x1c0];
5355 };
5356
5357 enum {
5358         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5359         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5360 };
5361
5362 struct mlx5_ifc_modify_scheduling_element_in_bits {
5363         u8         opcode[0x10];
5364         u8         reserved_at_10[0x10];
5365
5366         u8         reserved_at_20[0x10];
5367         u8         op_mod[0x10];
5368
5369         u8         scheduling_hierarchy[0x8];
5370         u8         reserved_at_48[0x18];
5371
5372         u8         scheduling_element_id[0x20];
5373
5374         u8         reserved_at_80[0x20];
5375
5376         u8         modify_bitmask[0x20];
5377
5378         u8         reserved_at_c0[0x40];
5379
5380         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5381
5382         u8         reserved_at_300[0x100];
5383 };
5384
5385 struct mlx5_ifc_modify_rqt_out_bits {
5386         u8         status[0x8];
5387         u8         reserved_at_8[0x18];
5388
5389         u8         syndrome[0x20];
5390
5391         u8         reserved_at_40[0x40];
5392 };
5393
5394 struct mlx5_ifc_rqt_bitmask_bits {
5395         u8         reserved_at_0[0x20];
5396
5397         u8         reserved_at_20[0x1f];
5398         u8         rqn_list[0x1];
5399 };
5400
5401 struct mlx5_ifc_modify_rqt_in_bits {
5402         u8         opcode[0x10];
5403         u8         reserved_at_10[0x10];
5404
5405         u8         reserved_at_20[0x10];
5406         u8         op_mod[0x10];
5407
5408         u8         reserved_at_40[0x8];
5409         u8         rqtn[0x18];
5410
5411         u8         reserved_at_60[0x20];
5412
5413         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5414
5415         u8         reserved_at_c0[0x40];
5416
5417         struct mlx5_ifc_rqtc_bits ctx;
5418 };
5419
5420 struct mlx5_ifc_modify_rq_out_bits {
5421         u8         status[0x8];
5422         u8         reserved_at_8[0x18];
5423
5424         u8         syndrome[0x20];
5425
5426         u8         reserved_at_40[0x40];
5427 };
5428
5429 enum {
5430         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5431         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5432         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5433 };
5434
5435 struct mlx5_ifc_modify_rq_in_bits {
5436         u8         opcode[0x10];
5437         u8         reserved_at_10[0x10];
5438
5439         u8         reserved_at_20[0x10];
5440         u8         op_mod[0x10];
5441
5442         u8         rq_state[0x4];
5443         u8         reserved_at_44[0x4];
5444         u8         rqn[0x18];
5445
5446         u8         reserved_at_60[0x20];
5447
5448         u8         modify_bitmask[0x40];
5449
5450         u8         reserved_at_c0[0x40];
5451
5452         struct mlx5_ifc_rqc_bits ctx;
5453 };
5454
5455 struct mlx5_ifc_modify_rmp_out_bits {
5456         u8         status[0x8];
5457         u8         reserved_at_8[0x18];
5458
5459         u8         syndrome[0x20];
5460
5461         u8         reserved_at_40[0x40];
5462 };
5463
5464 struct mlx5_ifc_rmp_bitmask_bits {
5465         u8         reserved_at_0[0x20];
5466
5467         u8         reserved_at_20[0x1f];
5468         u8         lwm[0x1];
5469 };
5470
5471 struct mlx5_ifc_modify_rmp_in_bits {
5472         u8         opcode[0x10];
5473         u8         reserved_at_10[0x10];
5474
5475         u8         reserved_at_20[0x10];
5476         u8         op_mod[0x10];
5477
5478         u8         rmp_state[0x4];
5479         u8         reserved_at_44[0x4];
5480         u8         rmpn[0x18];
5481
5482         u8         reserved_at_60[0x20];
5483
5484         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5485
5486         u8         reserved_at_c0[0x40];
5487
5488         struct mlx5_ifc_rmpc_bits ctx;
5489 };
5490
5491 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498 };
5499
5500 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5501         u8         reserved_at_0[0x12];
5502         u8         affiliation[0x1];
5503         u8         reserved_at_e[0x1];
5504         u8         disable_uc_local_lb[0x1];
5505         u8         disable_mc_local_lb[0x1];
5506         u8         node_guid[0x1];
5507         u8         port_guid[0x1];
5508         u8         min_inline[0x1];
5509         u8         mtu[0x1];
5510         u8         change_event[0x1];
5511         u8         promisc[0x1];
5512         u8         permanent_address[0x1];
5513         u8         addresses_list[0x1];
5514         u8         roce_en[0x1];
5515         u8         reserved_at_1f[0x1];
5516 };
5517
5518 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5519         u8         opcode[0x10];
5520         u8         reserved_at_10[0x10];
5521
5522         u8         reserved_at_20[0x10];
5523         u8         op_mod[0x10];
5524
5525         u8         other_vport[0x1];
5526         u8         reserved_at_41[0xf];
5527         u8         vport_number[0x10];
5528
5529         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5530
5531         u8         reserved_at_80[0x780];
5532
5533         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5534 };
5535
5536 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5537         u8         status[0x8];
5538         u8         reserved_at_8[0x18];
5539
5540         u8         syndrome[0x20];
5541
5542         u8         reserved_at_40[0x40];
5543 };
5544
5545 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5546         u8         opcode[0x10];
5547         u8         reserved_at_10[0x10];
5548
5549         u8         reserved_at_20[0x10];
5550         u8         op_mod[0x10];
5551
5552         u8         other_vport[0x1];
5553         u8         reserved_at_41[0xb];
5554         u8         port_num[0x4];
5555         u8         vport_number[0x10];
5556
5557         u8         reserved_at_60[0x20];
5558
5559         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5560 };
5561
5562 struct mlx5_ifc_modify_cq_out_bits {
5563         u8         status[0x8];
5564         u8         reserved_at_8[0x18];
5565
5566         u8         syndrome[0x20];
5567
5568         u8         reserved_at_40[0x40];
5569 };
5570
5571 enum {
5572         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5573         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5574 };
5575
5576 struct mlx5_ifc_modify_cq_in_bits {
5577         u8         opcode[0x10];
5578         u8         reserved_at_10[0x10];
5579
5580         u8         reserved_at_20[0x10];
5581         u8         op_mod[0x10];
5582
5583         u8         reserved_at_40[0x8];
5584         u8         cqn[0x18];
5585
5586         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5587
5588         struct mlx5_ifc_cqc_bits cq_context;
5589
5590         u8         reserved_at_280[0x600];
5591
5592         u8         pas[0][0x40];
5593 };
5594
5595 struct mlx5_ifc_modify_cong_status_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_at_8[0x18];
5598
5599         u8         syndrome[0x20];
5600
5601         u8         reserved_at_40[0x40];
5602 };
5603
5604 struct mlx5_ifc_modify_cong_status_in_bits {
5605         u8         opcode[0x10];
5606         u8         reserved_at_10[0x10];
5607
5608         u8         reserved_at_20[0x10];
5609         u8         op_mod[0x10];
5610
5611         u8         reserved_at_40[0x18];
5612         u8         priority[0x4];
5613         u8         cong_protocol[0x4];
5614
5615         u8         enable[0x1];
5616         u8         tag_enable[0x1];
5617         u8         reserved_at_62[0x1e];
5618 };
5619
5620 struct mlx5_ifc_modify_cong_params_out_bits {
5621         u8         status[0x8];
5622         u8         reserved_at_8[0x18];
5623
5624         u8         syndrome[0x20];
5625
5626         u8         reserved_at_40[0x40];
5627 };
5628
5629 struct mlx5_ifc_modify_cong_params_in_bits {
5630         u8         opcode[0x10];
5631         u8         reserved_at_10[0x10];
5632
5633         u8         reserved_at_20[0x10];
5634         u8         op_mod[0x10];
5635
5636         u8         reserved_at_40[0x1c];
5637         u8         cong_protocol[0x4];
5638
5639         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5640
5641         u8         reserved_at_80[0x80];
5642
5643         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5644 };
5645
5646 struct mlx5_ifc_manage_pages_out_bits {
5647         u8         status[0x8];
5648         u8         reserved_at_8[0x18];
5649
5650         u8         syndrome[0x20];
5651
5652         u8         output_num_entries[0x20];
5653
5654         u8         reserved_at_60[0x20];
5655
5656         u8         pas[0][0x40];
5657 };
5658
5659 enum {
5660         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5661         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5662         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5663 };
5664
5665 struct mlx5_ifc_manage_pages_in_bits {
5666         u8         opcode[0x10];
5667         u8         reserved_at_10[0x10];
5668
5669         u8         reserved_at_20[0x10];
5670         u8         op_mod[0x10];
5671
5672         u8         reserved_at_40[0x10];
5673         u8         function_id[0x10];
5674
5675         u8         input_num_entries[0x20];
5676
5677         u8         pas[0][0x40];
5678 };
5679
5680 struct mlx5_ifc_mad_ifc_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_at_8[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_at_40[0x40];
5687
5688         u8         response_mad_packet[256][0x8];
5689 };
5690
5691 struct mlx5_ifc_mad_ifc_in_bits {
5692         u8         opcode[0x10];
5693         u8         reserved_at_10[0x10];
5694
5695         u8         reserved_at_20[0x10];
5696         u8         op_mod[0x10];
5697
5698         u8         remote_lid[0x10];
5699         u8         reserved_at_50[0x8];
5700         u8         port[0x8];
5701
5702         u8         reserved_at_60[0x20];
5703
5704         u8         mad[256][0x8];
5705 };
5706
5707 struct mlx5_ifc_init_hca_out_bits {
5708         u8         status[0x8];
5709         u8         reserved_at_8[0x18];
5710
5711         u8         syndrome[0x20];
5712
5713         u8         reserved_at_40[0x40];
5714 };
5715
5716 struct mlx5_ifc_init_hca_in_bits {
5717         u8         opcode[0x10];
5718         u8         reserved_at_10[0x10];
5719
5720         u8         reserved_at_20[0x10];
5721         u8         op_mod[0x10];
5722
5723         u8         reserved_at_40[0x40];
5724         u8         sw_owner_id[4][0x20];
5725 };
5726
5727 struct mlx5_ifc_init2rtr_qp_out_bits {
5728         u8         status[0x8];
5729         u8         reserved_at_8[0x18];
5730
5731         u8         syndrome[0x20];
5732
5733         u8         reserved_at_40[0x40];
5734 };
5735
5736 struct mlx5_ifc_init2rtr_qp_in_bits {
5737         u8         opcode[0x10];
5738         u8         reserved_at_10[0x10];
5739
5740         u8         reserved_at_20[0x10];
5741         u8         op_mod[0x10];
5742
5743         u8         reserved_at_40[0x8];
5744         u8         qpn[0x18];
5745
5746         u8         reserved_at_60[0x20];
5747
5748         u8         opt_param_mask[0x20];
5749
5750         u8         reserved_at_a0[0x20];
5751
5752         struct mlx5_ifc_qpc_bits qpc;
5753
5754         u8         reserved_at_800[0x80];
5755 };
5756
5757 struct mlx5_ifc_init2init_qp_out_bits {
5758         u8         status[0x8];
5759         u8         reserved_at_8[0x18];
5760
5761         u8         syndrome[0x20];
5762
5763         u8         reserved_at_40[0x40];
5764 };
5765
5766 struct mlx5_ifc_init2init_qp_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_at_10[0x10];
5769
5770         u8         reserved_at_20[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         reserved_at_40[0x8];
5774         u8         qpn[0x18];
5775
5776         u8         reserved_at_60[0x20];
5777
5778         u8         opt_param_mask[0x20];
5779
5780         u8         reserved_at_a0[0x20];
5781
5782         struct mlx5_ifc_qpc_bits qpc;
5783
5784         u8         reserved_at_800[0x80];
5785 };
5786
5787 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5788         u8         status[0x8];
5789         u8         reserved_at_8[0x18];
5790
5791         u8         syndrome[0x20];
5792
5793         u8         reserved_at_40[0x40];
5794
5795         u8         packet_headers_log[128][0x8];
5796
5797         u8         packet_syndrome[64][0x8];
5798 };
5799
5800 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5801         u8         opcode[0x10];
5802         u8         reserved_at_10[0x10];
5803
5804         u8         reserved_at_20[0x10];
5805         u8         op_mod[0x10];
5806
5807         u8         reserved_at_40[0x40];
5808 };
5809
5810 struct mlx5_ifc_gen_eqe_in_bits {
5811         u8         opcode[0x10];
5812         u8         reserved_at_10[0x10];
5813
5814         u8         reserved_at_20[0x10];
5815         u8         op_mod[0x10];
5816
5817         u8         reserved_at_40[0x18];
5818         u8         eq_number[0x8];
5819
5820         u8         reserved_at_60[0x20];
5821
5822         u8         eqe[64][0x8];
5823 };
5824
5825 struct mlx5_ifc_gen_eq_out_bits {
5826         u8         status[0x8];
5827         u8         reserved_at_8[0x18];
5828
5829         u8         syndrome[0x20];
5830
5831         u8         reserved_at_40[0x40];
5832 };
5833
5834 struct mlx5_ifc_enable_hca_out_bits {
5835         u8         status[0x8];
5836         u8         reserved_at_8[0x18];
5837
5838         u8         syndrome[0x20];
5839
5840         u8         reserved_at_40[0x20];
5841 };
5842
5843 struct mlx5_ifc_enable_hca_in_bits {
5844         u8         opcode[0x10];
5845         u8         reserved_at_10[0x10];
5846
5847         u8         reserved_at_20[0x10];
5848         u8         op_mod[0x10];
5849
5850         u8         reserved_at_40[0x10];
5851         u8         function_id[0x10];
5852
5853         u8         reserved_at_60[0x20];
5854 };
5855
5856 struct mlx5_ifc_drain_dct_out_bits {
5857         u8         status[0x8];
5858         u8         reserved_at_8[0x18];
5859
5860         u8         syndrome[0x20];
5861
5862         u8         reserved_at_40[0x40];
5863 };
5864
5865 struct mlx5_ifc_drain_dct_in_bits {
5866         u8         opcode[0x10];
5867         u8         reserved_at_10[0x10];
5868
5869         u8         reserved_at_20[0x10];
5870         u8         op_mod[0x10];
5871
5872         u8         reserved_at_40[0x8];
5873         u8         dctn[0x18];
5874
5875         u8         reserved_at_60[0x20];
5876 };
5877
5878 struct mlx5_ifc_disable_hca_out_bits {
5879         u8         status[0x8];
5880         u8         reserved_at_8[0x18];
5881
5882         u8         syndrome[0x20];
5883
5884         u8         reserved_at_40[0x20];
5885 };
5886
5887 struct mlx5_ifc_disable_hca_in_bits {
5888         u8         opcode[0x10];
5889         u8         reserved_at_10[0x10];
5890
5891         u8         reserved_at_20[0x10];
5892         u8         op_mod[0x10];
5893
5894         u8         reserved_at_40[0x10];
5895         u8         function_id[0x10];
5896
5897         u8         reserved_at_60[0x20];
5898 };
5899
5900 struct mlx5_ifc_detach_from_mcg_out_bits {
5901         u8         status[0x8];
5902         u8         reserved_at_8[0x18];
5903
5904         u8         syndrome[0x20];
5905
5906         u8         reserved_at_40[0x40];
5907 };
5908
5909 struct mlx5_ifc_detach_from_mcg_in_bits {
5910         u8         opcode[0x10];
5911         u8         reserved_at_10[0x10];
5912
5913         u8         reserved_at_20[0x10];
5914         u8         op_mod[0x10];
5915
5916         u8         reserved_at_40[0x8];
5917         u8         qpn[0x18];
5918
5919         u8         reserved_at_60[0x20];
5920
5921         u8         multicast_gid[16][0x8];
5922 };
5923
5924 struct mlx5_ifc_destroy_xrq_out_bits {
5925         u8         status[0x8];
5926         u8         reserved_at_8[0x18];
5927
5928         u8         syndrome[0x20];
5929
5930         u8         reserved_at_40[0x40];
5931 };
5932
5933 struct mlx5_ifc_destroy_xrq_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x8];
5941         u8         xrqn[0x18];
5942
5943         u8         reserved_at_60[0x20];
5944 };
5945
5946 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5947         u8         status[0x8];
5948         u8         reserved_at_8[0x18];
5949
5950         u8         syndrome[0x20];
5951
5952         u8         reserved_at_40[0x40];
5953 };
5954
5955 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5956         u8         opcode[0x10];
5957         u8         reserved_at_10[0x10];
5958
5959         u8         reserved_at_20[0x10];
5960         u8         op_mod[0x10];
5961
5962         u8         reserved_at_40[0x8];
5963         u8         xrc_srqn[0x18];
5964
5965         u8         reserved_at_60[0x20];
5966 };
5967
5968 struct mlx5_ifc_destroy_tis_out_bits {
5969         u8         status[0x8];
5970         u8         reserved_at_8[0x18];
5971
5972         u8         syndrome[0x20];
5973
5974         u8         reserved_at_40[0x40];
5975 };
5976
5977 struct mlx5_ifc_destroy_tis_in_bits {
5978         u8         opcode[0x10];
5979         u8         reserved_at_10[0x10];
5980
5981         u8         reserved_at_20[0x10];
5982         u8         op_mod[0x10];
5983
5984         u8         reserved_at_40[0x8];
5985         u8         tisn[0x18];
5986
5987         u8         reserved_at_60[0x20];
5988 };
5989
5990 struct mlx5_ifc_destroy_tir_out_bits {
5991         u8         status[0x8];
5992         u8         reserved_at_8[0x18];
5993
5994         u8         syndrome[0x20];
5995
5996         u8         reserved_at_40[0x40];
5997 };
5998
5999 struct mlx5_ifc_destroy_tir_in_bits {
6000         u8         opcode[0x10];
6001         u8         reserved_at_10[0x10];
6002
6003         u8         reserved_at_20[0x10];
6004         u8         op_mod[0x10];
6005
6006         u8         reserved_at_40[0x8];
6007         u8         tirn[0x18];
6008
6009         u8         reserved_at_60[0x20];
6010 };
6011
6012 struct mlx5_ifc_destroy_srq_out_bits {
6013         u8         status[0x8];
6014         u8         reserved_at_8[0x18];
6015
6016         u8         syndrome[0x20];
6017
6018         u8         reserved_at_40[0x40];
6019 };
6020
6021 struct mlx5_ifc_destroy_srq_in_bits {
6022         u8         opcode[0x10];
6023         u8         reserved_at_10[0x10];
6024
6025         u8         reserved_at_20[0x10];
6026         u8         op_mod[0x10];
6027
6028         u8         reserved_at_40[0x8];
6029         u8         srqn[0x18];
6030
6031         u8         reserved_at_60[0x20];
6032 };
6033
6034 struct mlx5_ifc_destroy_sq_out_bits {
6035         u8         status[0x8];
6036         u8         reserved_at_8[0x18];
6037
6038         u8         syndrome[0x20];
6039
6040         u8         reserved_at_40[0x40];
6041 };
6042
6043 struct mlx5_ifc_destroy_sq_in_bits {
6044         u8         opcode[0x10];
6045         u8         reserved_at_10[0x10];
6046
6047         u8         reserved_at_20[0x10];
6048         u8         op_mod[0x10];
6049
6050         u8         reserved_at_40[0x8];
6051         u8         sqn[0x18];
6052
6053         u8         reserved_at_60[0x20];
6054 };
6055
6056 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6057         u8         status[0x8];
6058         u8         reserved_at_8[0x18];
6059
6060         u8         syndrome[0x20];
6061
6062         u8         reserved_at_40[0x1c0];
6063 };
6064
6065 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6066         u8         opcode[0x10];
6067         u8         reserved_at_10[0x10];
6068
6069         u8         reserved_at_20[0x10];
6070         u8         op_mod[0x10];
6071
6072         u8         scheduling_hierarchy[0x8];
6073         u8         reserved_at_48[0x18];
6074
6075         u8         scheduling_element_id[0x20];
6076
6077         u8         reserved_at_80[0x180];
6078 };
6079
6080 struct mlx5_ifc_destroy_rqt_out_bits {
6081         u8         status[0x8];
6082         u8         reserved_at_8[0x18];
6083
6084         u8         syndrome[0x20];
6085
6086         u8         reserved_at_40[0x40];
6087 };
6088
6089 struct mlx5_ifc_destroy_rqt_in_bits {
6090         u8         opcode[0x10];
6091         u8         reserved_at_10[0x10];
6092
6093         u8         reserved_at_20[0x10];
6094         u8         op_mod[0x10];
6095
6096         u8         reserved_at_40[0x8];
6097         u8         rqtn[0x18];
6098
6099         u8         reserved_at_60[0x20];
6100 };
6101
6102 struct mlx5_ifc_destroy_rq_out_bits {
6103         u8         status[0x8];
6104         u8         reserved_at_8[0x18];
6105
6106         u8         syndrome[0x20];
6107
6108         u8         reserved_at_40[0x40];
6109 };
6110
6111 struct mlx5_ifc_destroy_rq_in_bits {
6112         u8         opcode[0x10];
6113         u8         reserved_at_10[0x10];
6114
6115         u8         reserved_at_20[0x10];
6116         u8         op_mod[0x10];
6117
6118         u8         reserved_at_40[0x8];
6119         u8         rqn[0x18];
6120
6121         u8         reserved_at_60[0x20];
6122 };
6123
6124 struct mlx5_ifc_set_delay_drop_params_in_bits {
6125         u8         opcode[0x10];
6126         u8         reserved_at_10[0x10];
6127
6128         u8         reserved_at_20[0x10];
6129         u8         op_mod[0x10];
6130
6131         u8         reserved_at_40[0x20];
6132
6133         u8         reserved_at_60[0x10];
6134         u8         delay_drop_timeout[0x10];
6135 };
6136
6137 struct mlx5_ifc_set_delay_drop_params_out_bits {
6138         u8         status[0x8];
6139         u8         reserved_at_8[0x18];
6140
6141         u8         syndrome[0x20];
6142
6143         u8         reserved_at_40[0x40];
6144 };
6145
6146 struct mlx5_ifc_destroy_rmp_out_bits {
6147         u8         status[0x8];
6148         u8         reserved_at_8[0x18];
6149
6150         u8         syndrome[0x20];
6151
6152         u8         reserved_at_40[0x40];
6153 };
6154
6155 struct mlx5_ifc_destroy_rmp_in_bits {
6156         u8         opcode[0x10];
6157         u8         reserved_at_10[0x10];
6158
6159         u8         reserved_at_20[0x10];
6160         u8         op_mod[0x10];
6161
6162         u8         reserved_at_40[0x8];
6163         u8         rmpn[0x18];
6164
6165         u8         reserved_at_60[0x20];
6166 };
6167
6168 struct mlx5_ifc_destroy_qp_out_bits {
6169         u8         status[0x8];
6170         u8         reserved_at_8[0x18];
6171
6172         u8         syndrome[0x20];
6173
6174         u8         reserved_at_40[0x40];
6175 };
6176
6177 struct mlx5_ifc_destroy_qp_in_bits {
6178         u8         opcode[0x10];
6179         u8         reserved_at_10[0x10];
6180
6181         u8         reserved_at_20[0x10];
6182         u8         op_mod[0x10];
6183
6184         u8         reserved_at_40[0x8];
6185         u8         qpn[0x18];
6186
6187         u8         reserved_at_60[0x20];
6188 };
6189
6190 struct mlx5_ifc_destroy_psv_out_bits {
6191         u8         status[0x8];
6192         u8         reserved_at_8[0x18];
6193
6194         u8         syndrome[0x20];
6195
6196         u8         reserved_at_40[0x40];
6197 };
6198
6199 struct mlx5_ifc_destroy_psv_in_bits {
6200         u8         opcode[0x10];
6201         u8         reserved_at_10[0x10];
6202
6203         u8         reserved_at_20[0x10];
6204         u8         op_mod[0x10];
6205
6206         u8         reserved_at_40[0x8];
6207         u8         psvn[0x18];
6208
6209         u8         reserved_at_60[0x20];
6210 };
6211
6212 struct mlx5_ifc_destroy_mkey_out_bits {
6213         u8         status[0x8];
6214         u8         reserved_at_8[0x18];
6215
6216         u8         syndrome[0x20];
6217
6218         u8         reserved_at_40[0x40];
6219 };
6220
6221 struct mlx5_ifc_destroy_mkey_in_bits {
6222         u8         opcode[0x10];
6223         u8         reserved_at_10[0x10];
6224
6225         u8         reserved_at_20[0x10];
6226         u8         op_mod[0x10];
6227
6228         u8         reserved_at_40[0x8];
6229         u8         mkey_index[0x18];
6230
6231         u8         reserved_at_60[0x20];
6232 };
6233
6234 struct mlx5_ifc_destroy_flow_table_out_bits {
6235         u8         status[0x8];
6236         u8         reserved_at_8[0x18];
6237
6238         u8         syndrome[0x20];
6239
6240         u8         reserved_at_40[0x40];
6241 };
6242
6243 struct mlx5_ifc_destroy_flow_table_in_bits {
6244         u8         opcode[0x10];
6245         u8         reserved_at_10[0x10];
6246
6247         u8         reserved_at_20[0x10];
6248         u8         op_mod[0x10];
6249
6250         u8         other_vport[0x1];
6251         u8         reserved_at_41[0xf];
6252         u8         vport_number[0x10];
6253
6254         u8         reserved_at_60[0x20];
6255
6256         u8         table_type[0x8];
6257         u8         reserved_at_88[0x18];
6258
6259         u8         reserved_at_a0[0x8];
6260         u8         table_id[0x18];
6261
6262         u8         reserved_at_c0[0x140];
6263 };
6264
6265 struct mlx5_ifc_destroy_flow_group_out_bits {
6266         u8         status[0x8];
6267         u8         reserved_at_8[0x18];
6268
6269         u8         syndrome[0x20];
6270
6271         u8         reserved_at_40[0x40];
6272 };
6273
6274 struct mlx5_ifc_destroy_flow_group_in_bits {
6275         u8         opcode[0x10];
6276         u8         reserved_at_10[0x10];
6277
6278         u8         reserved_at_20[0x10];
6279         u8         op_mod[0x10];
6280
6281         u8         other_vport[0x1];
6282         u8         reserved_at_41[0xf];
6283         u8         vport_number[0x10];
6284
6285         u8         reserved_at_60[0x20];
6286
6287         u8         table_type[0x8];
6288         u8         reserved_at_88[0x18];
6289
6290         u8         reserved_at_a0[0x8];
6291         u8         table_id[0x18];
6292
6293         u8         group_id[0x20];
6294
6295         u8         reserved_at_e0[0x120];
6296 };
6297
6298 struct mlx5_ifc_destroy_eq_out_bits {
6299         u8         status[0x8];
6300         u8         reserved_at_8[0x18];
6301
6302         u8         syndrome[0x20];
6303
6304         u8         reserved_at_40[0x40];
6305 };
6306
6307 struct mlx5_ifc_destroy_eq_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_at_10[0x10];
6310
6311         u8         reserved_at_20[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         reserved_at_40[0x18];
6315         u8         eq_number[0x8];
6316
6317         u8         reserved_at_60[0x20];
6318 };
6319
6320 struct mlx5_ifc_destroy_dct_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_at_8[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_at_40[0x40];
6327 };
6328
6329 struct mlx5_ifc_destroy_dct_in_bits {
6330         u8         opcode[0x10];
6331         u8         reserved_at_10[0x10];
6332
6333         u8         reserved_at_20[0x10];
6334         u8         op_mod[0x10];
6335
6336         u8         reserved_at_40[0x8];
6337         u8         dctn[0x18];
6338
6339         u8         reserved_at_60[0x20];
6340 };
6341
6342 struct mlx5_ifc_destroy_cq_out_bits {
6343         u8         status[0x8];
6344         u8         reserved_at_8[0x18];
6345
6346         u8         syndrome[0x20];
6347
6348         u8         reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_destroy_cq_in_bits {
6352         u8         opcode[0x10];
6353         u8         reserved_at_10[0x10];
6354
6355         u8         reserved_at_20[0x10];
6356         u8         op_mod[0x10];
6357
6358         u8         reserved_at_40[0x8];
6359         u8         cqn[0x18];
6360
6361         u8         reserved_at_60[0x20];
6362 };
6363
6364 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6365         u8         status[0x8];
6366         u8         reserved_at_8[0x18];
6367
6368         u8         syndrome[0x20];
6369
6370         u8         reserved_at_40[0x40];
6371 };
6372
6373 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6374         u8         opcode[0x10];
6375         u8         reserved_at_10[0x10];
6376
6377         u8         reserved_at_20[0x10];
6378         u8         op_mod[0x10];
6379
6380         u8         reserved_at_40[0x20];
6381
6382         u8         reserved_at_60[0x10];
6383         u8         vxlan_udp_port[0x10];
6384 };
6385
6386 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6387         u8         status[0x8];
6388         u8         reserved_at_8[0x18];
6389
6390         u8         syndrome[0x20];
6391
6392         u8         reserved_at_40[0x40];
6393 };
6394
6395 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6396         u8         opcode[0x10];
6397         u8         reserved_at_10[0x10];
6398
6399         u8         reserved_at_20[0x10];
6400         u8         op_mod[0x10];
6401
6402         u8         reserved_at_40[0x60];
6403
6404         u8         reserved_at_a0[0x8];
6405         u8         table_index[0x18];
6406
6407         u8         reserved_at_c0[0x140];
6408 };
6409
6410 struct mlx5_ifc_delete_fte_out_bits {
6411         u8         status[0x8];
6412         u8         reserved_at_8[0x18];
6413
6414         u8         syndrome[0x20];
6415
6416         u8         reserved_at_40[0x40];
6417 };
6418
6419 struct mlx5_ifc_delete_fte_in_bits {
6420         u8         opcode[0x10];
6421         u8         reserved_at_10[0x10];
6422
6423         u8         reserved_at_20[0x10];
6424         u8         op_mod[0x10];
6425
6426         u8         other_vport[0x1];
6427         u8         reserved_at_41[0xf];
6428         u8         vport_number[0x10];
6429
6430         u8         reserved_at_60[0x20];
6431
6432         u8         table_type[0x8];
6433         u8         reserved_at_88[0x18];
6434
6435         u8         reserved_at_a0[0x8];
6436         u8         table_id[0x18];
6437
6438         u8         reserved_at_c0[0x40];
6439
6440         u8         flow_index[0x20];
6441
6442         u8         reserved_at_120[0xe0];
6443 };
6444
6445 struct mlx5_ifc_dealloc_xrcd_out_bits {
6446         u8         status[0x8];
6447         u8         reserved_at_8[0x18];
6448
6449         u8         syndrome[0x20];
6450
6451         u8         reserved_at_40[0x40];
6452 };
6453
6454 struct mlx5_ifc_dealloc_xrcd_in_bits {
6455         u8         opcode[0x10];
6456         u8         reserved_at_10[0x10];
6457
6458         u8         reserved_at_20[0x10];
6459         u8         op_mod[0x10];
6460
6461         u8         reserved_at_40[0x8];
6462         u8         xrcd[0x18];
6463
6464         u8         reserved_at_60[0x20];
6465 };
6466
6467 struct mlx5_ifc_dealloc_uar_out_bits {
6468         u8         status[0x8];
6469         u8         reserved_at_8[0x18];
6470
6471         u8         syndrome[0x20];
6472
6473         u8         reserved_at_40[0x40];
6474 };
6475
6476 struct mlx5_ifc_dealloc_uar_in_bits {
6477         u8         opcode[0x10];
6478         u8         reserved_at_10[0x10];
6479
6480         u8         reserved_at_20[0x10];
6481         u8         op_mod[0x10];
6482
6483         u8         reserved_at_40[0x8];
6484         u8         uar[0x18];
6485
6486         u8         reserved_at_60[0x20];
6487 };
6488
6489 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6490         u8         status[0x8];
6491         u8         reserved_at_8[0x18];
6492
6493         u8         syndrome[0x20];
6494
6495         u8         reserved_at_40[0x40];
6496 };
6497
6498 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6499         u8         opcode[0x10];
6500         u8         reserved_at_10[0x10];
6501
6502         u8         reserved_at_20[0x10];
6503         u8         op_mod[0x10];
6504
6505         u8         reserved_at_40[0x8];
6506         u8         transport_domain[0x18];
6507
6508         u8         reserved_at_60[0x20];
6509 };
6510
6511 struct mlx5_ifc_dealloc_q_counter_out_bits {
6512         u8         status[0x8];
6513         u8         reserved_at_8[0x18];
6514
6515         u8         syndrome[0x20];
6516
6517         u8         reserved_at_40[0x40];
6518 };
6519
6520 struct mlx5_ifc_dealloc_q_counter_in_bits {
6521         u8         opcode[0x10];
6522         u8         reserved_at_10[0x10];
6523
6524         u8         reserved_at_20[0x10];
6525         u8         op_mod[0x10];
6526
6527         u8         reserved_at_40[0x18];
6528         u8         counter_set_id[0x8];
6529
6530         u8         reserved_at_60[0x20];
6531 };
6532
6533 struct mlx5_ifc_dealloc_pd_out_bits {
6534         u8         status[0x8];
6535         u8         reserved_at_8[0x18];
6536
6537         u8         syndrome[0x20];
6538
6539         u8         reserved_at_40[0x40];
6540 };
6541
6542 struct mlx5_ifc_dealloc_pd_in_bits {
6543         u8         opcode[0x10];
6544         u8         reserved_at_10[0x10];
6545
6546         u8         reserved_at_20[0x10];
6547         u8         op_mod[0x10];
6548
6549         u8         reserved_at_40[0x8];
6550         u8         pd[0x18];
6551
6552         u8         reserved_at_60[0x20];
6553 };
6554
6555 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6556         u8         status[0x8];
6557         u8         reserved_at_8[0x18];
6558
6559         u8         syndrome[0x20];
6560
6561         u8         reserved_at_40[0x40];
6562 };
6563
6564 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6565         u8         opcode[0x10];
6566         u8         reserved_at_10[0x10];
6567
6568         u8         reserved_at_20[0x10];
6569         u8         op_mod[0x10];
6570
6571         u8         flow_counter_id[0x20];
6572
6573         u8         reserved_at_60[0x20];
6574 };
6575
6576 struct mlx5_ifc_create_xrq_out_bits {
6577         u8         status[0x8];
6578         u8         reserved_at_8[0x18];
6579
6580         u8         syndrome[0x20];
6581
6582         u8         reserved_at_40[0x8];
6583         u8         xrqn[0x18];
6584
6585         u8         reserved_at_60[0x20];
6586 };
6587
6588 struct mlx5_ifc_create_xrq_in_bits {
6589         u8         opcode[0x10];
6590         u8         reserved_at_10[0x10];
6591
6592         u8         reserved_at_20[0x10];
6593         u8         op_mod[0x10];
6594
6595         u8         reserved_at_40[0x40];
6596
6597         struct mlx5_ifc_xrqc_bits xrq_context;
6598 };
6599
6600 struct mlx5_ifc_create_xrc_srq_out_bits {
6601         u8         status[0x8];
6602         u8         reserved_at_8[0x18];
6603
6604         u8         syndrome[0x20];
6605
6606         u8         reserved_at_40[0x8];
6607         u8         xrc_srqn[0x18];
6608
6609         u8         reserved_at_60[0x20];
6610 };
6611
6612 struct mlx5_ifc_create_xrc_srq_in_bits {
6613         u8         opcode[0x10];
6614         u8         reserved_at_10[0x10];
6615
6616         u8         reserved_at_20[0x10];
6617         u8         op_mod[0x10];
6618
6619         u8         reserved_at_40[0x40];
6620
6621         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6622
6623         u8         reserved_at_280[0x600];
6624
6625         u8         pas[0][0x40];
6626 };
6627
6628 struct mlx5_ifc_create_tis_out_bits {
6629         u8         status[0x8];
6630         u8         reserved_at_8[0x18];
6631
6632         u8         syndrome[0x20];
6633
6634         u8         reserved_at_40[0x8];
6635         u8         tisn[0x18];
6636
6637         u8         reserved_at_60[0x20];
6638 };
6639
6640 struct mlx5_ifc_create_tis_in_bits {
6641         u8         opcode[0x10];
6642         u8         reserved_at_10[0x10];
6643
6644         u8         reserved_at_20[0x10];
6645         u8         op_mod[0x10];
6646
6647         u8         reserved_at_40[0xc0];
6648
6649         struct mlx5_ifc_tisc_bits ctx;
6650 };
6651
6652 struct mlx5_ifc_create_tir_out_bits {
6653         u8         status[0x8];
6654         u8         reserved_at_8[0x18];
6655
6656         u8         syndrome[0x20];
6657
6658         u8         reserved_at_40[0x8];
6659         u8         tirn[0x18];
6660
6661         u8         reserved_at_60[0x20];
6662 };
6663
6664 struct mlx5_ifc_create_tir_in_bits {
6665         u8         opcode[0x10];
6666         u8         reserved_at_10[0x10];
6667
6668         u8         reserved_at_20[0x10];
6669         u8         op_mod[0x10];
6670
6671         u8         reserved_at_40[0xc0];
6672
6673         struct mlx5_ifc_tirc_bits ctx;
6674 };
6675
6676 struct mlx5_ifc_create_srq_out_bits {
6677         u8         status[0x8];
6678         u8         reserved_at_8[0x18];
6679
6680         u8         syndrome[0x20];
6681
6682         u8         reserved_at_40[0x8];
6683         u8         srqn[0x18];
6684
6685         u8         reserved_at_60[0x20];
6686 };
6687
6688 struct mlx5_ifc_create_srq_in_bits {
6689         u8         opcode[0x10];
6690         u8         reserved_at_10[0x10];
6691
6692         u8         reserved_at_20[0x10];
6693         u8         op_mod[0x10];
6694
6695         u8         reserved_at_40[0x40];
6696
6697         struct mlx5_ifc_srqc_bits srq_context_entry;
6698
6699         u8         reserved_at_280[0x600];
6700
6701         u8         pas[0][0x40];
6702 };
6703
6704 struct mlx5_ifc_create_sq_out_bits {
6705         u8         status[0x8];
6706         u8         reserved_at_8[0x18];
6707
6708         u8         syndrome[0x20];
6709
6710         u8         reserved_at_40[0x8];
6711         u8         sqn[0x18];
6712
6713         u8         reserved_at_60[0x20];
6714 };
6715
6716 struct mlx5_ifc_create_sq_in_bits {
6717         u8         opcode[0x10];
6718         u8         reserved_at_10[0x10];
6719
6720         u8         reserved_at_20[0x10];
6721         u8         op_mod[0x10];
6722
6723         u8         reserved_at_40[0xc0];
6724
6725         struct mlx5_ifc_sqc_bits ctx;
6726 };
6727
6728 struct mlx5_ifc_create_scheduling_element_out_bits {
6729         u8         status[0x8];
6730         u8         reserved_at_8[0x18];
6731
6732         u8         syndrome[0x20];
6733
6734         u8         reserved_at_40[0x40];
6735
6736         u8         scheduling_element_id[0x20];
6737
6738         u8         reserved_at_a0[0x160];
6739 };
6740
6741 struct mlx5_ifc_create_scheduling_element_in_bits {
6742         u8         opcode[0x10];
6743         u8         reserved_at_10[0x10];
6744
6745         u8         reserved_at_20[0x10];
6746         u8         op_mod[0x10];
6747
6748         u8         scheduling_hierarchy[0x8];
6749         u8         reserved_at_48[0x18];
6750
6751         u8         reserved_at_60[0xa0];
6752
6753         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6754
6755         u8         reserved_at_300[0x100];
6756 };
6757
6758 struct mlx5_ifc_create_rqt_out_bits {
6759         u8         status[0x8];
6760         u8         reserved_at_8[0x18];
6761
6762         u8         syndrome[0x20];
6763
6764         u8         reserved_at_40[0x8];
6765         u8         rqtn[0x18];
6766
6767         u8         reserved_at_60[0x20];
6768 };
6769
6770 struct mlx5_ifc_create_rqt_in_bits {
6771         u8         opcode[0x10];
6772         u8         reserved_at_10[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0xc0];
6778
6779         struct mlx5_ifc_rqtc_bits rqt_context;
6780 };
6781
6782 struct mlx5_ifc_create_rq_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_at_8[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_at_40[0x8];
6789         u8         rqn[0x18];
6790
6791         u8         reserved_at_60[0x20];
6792 };
6793
6794 struct mlx5_ifc_create_rq_in_bits {
6795         u8         opcode[0x10];
6796         u8         reserved_at_10[0x10];
6797
6798         u8         reserved_at_20[0x10];
6799         u8         op_mod[0x10];
6800
6801         u8         reserved_at_40[0xc0];
6802
6803         struct mlx5_ifc_rqc_bits ctx;
6804 };
6805
6806 struct mlx5_ifc_create_rmp_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_at_8[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         reserved_at_40[0x8];
6813         u8         rmpn[0x18];
6814
6815         u8         reserved_at_60[0x20];
6816 };
6817
6818 struct mlx5_ifc_create_rmp_in_bits {
6819         u8         opcode[0x10];
6820         u8         reserved_at_10[0x10];
6821
6822         u8         reserved_at_20[0x10];
6823         u8         op_mod[0x10];
6824
6825         u8         reserved_at_40[0xc0];
6826
6827         struct mlx5_ifc_rmpc_bits ctx;
6828 };
6829
6830 struct mlx5_ifc_create_qp_out_bits {
6831         u8         status[0x8];
6832         u8         reserved_at_8[0x18];
6833
6834         u8         syndrome[0x20];
6835
6836         u8         reserved_at_40[0x8];
6837         u8         qpn[0x18];
6838
6839         u8         reserved_at_60[0x20];
6840 };
6841
6842 struct mlx5_ifc_create_qp_in_bits {
6843         u8         opcode[0x10];
6844         u8         reserved_at_10[0x10];
6845
6846         u8         reserved_at_20[0x10];
6847         u8         op_mod[0x10];
6848
6849         u8         reserved_at_40[0x40];
6850
6851         u8         opt_param_mask[0x20];
6852
6853         u8         reserved_at_a0[0x20];
6854
6855         struct mlx5_ifc_qpc_bits qpc;
6856
6857         u8         reserved_at_800[0x80];
6858
6859         u8         pas[0][0x40];
6860 };
6861
6862 struct mlx5_ifc_create_psv_out_bits {
6863         u8         status[0x8];
6864         u8         reserved_at_8[0x18];
6865
6866         u8         syndrome[0x20];
6867
6868         u8         reserved_at_40[0x40];
6869
6870         u8         reserved_at_80[0x8];
6871         u8         psv0_index[0x18];
6872
6873         u8         reserved_at_a0[0x8];
6874         u8         psv1_index[0x18];
6875
6876         u8         reserved_at_c0[0x8];
6877         u8         psv2_index[0x18];
6878
6879         u8         reserved_at_e0[0x8];
6880         u8         psv3_index[0x18];
6881 };
6882
6883 struct mlx5_ifc_create_psv_in_bits {
6884         u8         opcode[0x10];
6885         u8         reserved_at_10[0x10];
6886
6887         u8         reserved_at_20[0x10];
6888         u8         op_mod[0x10];
6889
6890         u8         num_psv[0x4];
6891         u8         reserved_at_44[0x4];
6892         u8         pd[0x18];
6893
6894         u8         reserved_at_60[0x20];
6895 };
6896
6897 struct mlx5_ifc_create_mkey_out_bits {
6898         u8         status[0x8];
6899         u8         reserved_at_8[0x18];
6900
6901         u8         syndrome[0x20];
6902
6903         u8         reserved_at_40[0x8];
6904         u8         mkey_index[0x18];
6905
6906         u8         reserved_at_60[0x20];
6907 };
6908
6909 struct mlx5_ifc_create_mkey_in_bits {
6910         u8         opcode[0x10];
6911         u8         reserved_at_10[0x10];
6912
6913         u8         reserved_at_20[0x10];
6914         u8         op_mod[0x10];
6915
6916         u8         reserved_at_40[0x20];
6917
6918         u8         pg_access[0x1];
6919         u8         reserved_at_61[0x1f];
6920
6921         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6922
6923         u8         reserved_at_280[0x80];
6924
6925         u8         translations_octword_actual_size[0x20];
6926
6927         u8         reserved_at_320[0x560];
6928
6929         u8         klm_pas_mtt[0][0x20];
6930 };
6931
6932 struct mlx5_ifc_create_flow_table_out_bits {
6933         u8         status[0x8];
6934         u8         reserved_at_8[0x18];
6935
6936         u8         syndrome[0x20];
6937
6938         u8         reserved_at_40[0x8];
6939         u8         table_id[0x18];
6940
6941         u8         reserved_at_60[0x20];
6942 };
6943
6944 struct mlx5_ifc_flow_table_context_bits {
6945         u8         encap_en[0x1];
6946         u8         decap_en[0x1];
6947         u8         reserved_at_2[0x2];
6948         u8         table_miss_action[0x4];
6949         u8         level[0x8];
6950         u8         reserved_at_10[0x8];
6951         u8         log_size[0x8];
6952
6953         u8         reserved_at_20[0x8];
6954         u8         table_miss_id[0x18];
6955
6956         u8         reserved_at_40[0x8];
6957         u8         lag_master_next_table_id[0x18];
6958
6959         u8         reserved_at_60[0xe0];
6960 };
6961
6962 struct mlx5_ifc_create_flow_table_in_bits {
6963         u8         opcode[0x10];
6964         u8         reserved_at_10[0x10];
6965
6966         u8         reserved_at_20[0x10];
6967         u8         op_mod[0x10];
6968
6969         u8         other_vport[0x1];
6970         u8         reserved_at_41[0xf];
6971         u8         vport_number[0x10];
6972
6973         u8         reserved_at_60[0x20];
6974
6975         u8         table_type[0x8];
6976         u8         reserved_at_88[0x18];
6977
6978         u8         reserved_at_a0[0x20];
6979
6980         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6981 };
6982
6983 struct mlx5_ifc_create_flow_group_out_bits {
6984         u8         status[0x8];
6985         u8         reserved_at_8[0x18];
6986
6987         u8         syndrome[0x20];
6988
6989         u8         reserved_at_40[0x8];
6990         u8         group_id[0x18];
6991
6992         u8         reserved_at_60[0x20];
6993 };
6994
6995 enum {
6996         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
6997         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
6998         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
6999         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7000 };
7001
7002 struct mlx5_ifc_create_flow_group_in_bits {
7003         u8         opcode[0x10];
7004         u8         reserved_at_10[0x10];
7005
7006         u8         reserved_at_20[0x10];
7007         u8         op_mod[0x10];
7008
7009         u8         other_vport[0x1];
7010         u8         reserved_at_41[0xf];
7011         u8         vport_number[0x10];
7012
7013         u8         reserved_at_60[0x20];
7014
7015         u8         table_type[0x8];
7016         u8         reserved_at_88[0x18];
7017
7018         u8         reserved_at_a0[0x8];
7019         u8         table_id[0x18];
7020
7021         u8         source_eswitch_owner_vhca_id_valid[0x1];
7022
7023         u8         reserved_at_c1[0x1f];
7024
7025         u8         start_flow_index[0x20];
7026
7027         u8         reserved_at_100[0x20];
7028
7029         u8         end_flow_index[0x20];
7030
7031         u8         reserved_at_140[0xa0];
7032
7033         u8         reserved_at_1e0[0x18];
7034         u8         match_criteria_enable[0x8];
7035
7036         struct mlx5_ifc_fte_match_param_bits match_criteria;
7037
7038         u8         reserved_at_1200[0xe00];
7039 };
7040
7041 struct mlx5_ifc_create_eq_out_bits {
7042         u8         status[0x8];
7043         u8         reserved_at_8[0x18];
7044
7045         u8         syndrome[0x20];
7046
7047         u8         reserved_at_40[0x18];
7048         u8         eq_number[0x8];
7049
7050         u8         reserved_at_60[0x20];
7051 };
7052
7053 struct mlx5_ifc_create_eq_in_bits {
7054         u8         opcode[0x10];
7055         u8         reserved_at_10[0x10];
7056
7057         u8         reserved_at_20[0x10];
7058         u8         op_mod[0x10];
7059
7060         u8         reserved_at_40[0x40];
7061
7062         struct mlx5_ifc_eqc_bits eq_context_entry;
7063
7064         u8         reserved_at_280[0x40];
7065
7066         u8         event_bitmask[0x40];
7067
7068         u8         reserved_at_300[0x580];
7069
7070         u8         pas[0][0x40];
7071 };
7072
7073 struct mlx5_ifc_create_dct_out_bits {
7074         u8         status[0x8];
7075         u8         reserved_at_8[0x18];
7076
7077         u8         syndrome[0x20];
7078
7079         u8         reserved_at_40[0x8];
7080         u8         dctn[0x18];
7081
7082         u8         reserved_at_60[0x20];
7083 };
7084
7085 struct mlx5_ifc_create_dct_in_bits {
7086         u8         opcode[0x10];
7087         u8         reserved_at_10[0x10];
7088
7089         u8         reserved_at_20[0x10];
7090         u8         op_mod[0x10];
7091
7092         u8         reserved_at_40[0x40];
7093
7094         struct mlx5_ifc_dctc_bits dct_context_entry;
7095
7096         u8         reserved_at_280[0x180];
7097 };
7098
7099 struct mlx5_ifc_create_cq_out_bits {
7100         u8         status[0x8];
7101         u8         reserved_at_8[0x18];
7102
7103         u8         syndrome[0x20];
7104
7105         u8         reserved_at_40[0x8];
7106         u8         cqn[0x18];
7107
7108         u8         reserved_at_60[0x20];
7109 };
7110
7111 struct mlx5_ifc_create_cq_in_bits {
7112         u8         opcode[0x10];
7113         u8         reserved_at_10[0x10];
7114
7115         u8         reserved_at_20[0x10];
7116         u8         op_mod[0x10];
7117
7118         u8         reserved_at_40[0x40];
7119
7120         struct mlx5_ifc_cqc_bits cq_context;
7121
7122         u8         reserved_at_280[0x600];
7123
7124         u8         pas[0][0x40];
7125 };
7126
7127 struct mlx5_ifc_config_int_moderation_out_bits {
7128         u8         status[0x8];
7129         u8         reserved_at_8[0x18];
7130
7131         u8         syndrome[0x20];
7132
7133         u8         reserved_at_40[0x4];
7134         u8         min_delay[0xc];
7135         u8         int_vector[0x10];
7136
7137         u8         reserved_at_60[0x20];
7138 };
7139
7140 enum {
7141         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7142         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7143 };
7144
7145 struct mlx5_ifc_config_int_moderation_in_bits {
7146         u8         opcode[0x10];
7147         u8         reserved_at_10[0x10];
7148
7149         u8         reserved_at_20[0x10];
7150         u8         op_mod[0x10];
7151
7152         u8         reserved_at_40[0x4];
7153         u8         min_delay[0xc];
7154         u8         int_vector[0x10];
7155
7156         u8         reserved_at_60[0x20];
7157 };
7158
7159 struct mlx5_ifc_attach_to_mcg_out_bits {
7160         u8         status[0x8];
7161         u8         reserved_at_8[0x18];
7162
7163         u8         syndrome[0x20];
7164
7165         u8         reserved_at_40[0x40];
7166 };
7167
7168 struct mlx5_ifc_attach_to_mcg_in_bits {
7169         u8         opcode[0x10];
7170         u8         reserved_at_10[0x10];
7171
7172         u8         reserved_at_20[0x10];
7173         u8         op_mod[0x10];
7174
7175         u8         reserved_at_40[0x8];
7176         u8         qpn[0x18];
7177
7178         u8         reserved_at_60[0x20];
7179
7180         u8         multicast_gid[16][0x8];
7181 };
7182
7183 struct mlx5_ifc_arm_xrq_out_bits {
7184         u8         status[0x8];
7185         u8         reserved_at_8[0x18];
7186
7187         u8         syndrome[0x20];
7188
7189         u8         reserved_at_40[0x40];
7190 };
7191
7192 struct mlx5_ifc_arm_xrq_in_bits {
7193         u8         opcode[0x10];
7194         u8         reserved_at_10[0x10];
7195
7196         u8         reserved_at_20[0x10];
7197         u8         op_mod[0x10];
7198
7199         u8         reserved_at_40[0x8];
7200         u8         xrqn[0x18];
7201
7202         u8         reserved_at_60[0x10];
7203         u8         lwm[0x10];
7204 };
7205
7206 struct mlx5_ifc_arm_xrc_srq_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_at_8[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_at_40[0x40];
7213 };
7214
7215 enum {
7216         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7217 };
7218
7219 struct mlx5_ifc_arm_xrc_srq_in_bits {
7220         u8         opcode[0x10];
7221         u8         reserved_at_10[0x10];
7222
7223         u8         reserved_at_20[0x10];
7224         u8         op_mod[0x10];
7225
7226         u8         reserved_at_40[0x8];
7227         u8         xrc_srqn[0x18];
7228
7229         u8         reserved_at_60[0x10];
7230         u8         lwm[0x10];
7231 };
7232
7233 struct mlx5_ifc_arm_rq_out_bits {
7234         u8         status[0x8];
7235         u8         reserved_at_8[0x18];
7236
7237         u8         syndrome[0x20];
7238
7239         u8         reserved_at_40[0x40];
7240 };
7241
7242 enum {
7243         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7244         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7245 };
7246
7247 struct mlx5_ifc_arm_rq_in_bits {
7248         u8         opcode[0x10];
7249         u8         reserved_at_10[0x10];
7250
7251         u8         reserved_at_20[0x10];
7252         u8         op_mod[0x10];
7253
7254         u8         reserved_at_40[0x8];
7255         u8         srq_number[0x18];
7256
7257         u8         reserved_at_60[0x10];
7258         u8         lwm[0x10];
7259 };
7260
7261 struct mlx5_ifc_arm_dct_out_bits {
7262         u8         status[0x8];
7263         u8         reserved_at_8[0x18];
7264
7265         u8         syndrome[0x20];
7266
7267         u8         reserved_at_40[0x40];
7268 };
7269
7270 struct mlx5_ifc_arm_dct_in_bits {
7271         u8         opcode[0x10];
7272         u8         reserved_at_10[0x10];
7273
7274         u8         reserved_at_20[0x10];
7275         u8         op_mod[0x10];
7276
7277         u8         reserved_at_40[0x8];
7278         u8         dct_number[0x18];
7279
7280         u8         reserved_at_60[0x20];
7281 };
7282
7283 struct mlx5_ifc_alloc_xrcd_out_bits {
7284         u8         status[0x8];
7285         u8         reserved_at_8[0x18];
7286
7287         u8         syndrome[0x20];
7288
7289         u8         reserved_at_40[0x8];
7290         u8         xrcd[0x18];
7291
7292         u8         reserved_at_60[0x20];
7293 };
7294
7295 struct mlx5_ifc_alloc_xrcd_in_bits {
7296         u8         opcode[0x10];
7297         u8         reserved_at_10[0x10];
7298
7299         u8         reserved_at_20[0x10];
7300         u8         op_mod[0x10];
7301
7302         u8         reserved_at_40[0x40];
7303 };
7304
7305 struct mlx5_ifc_alloc_uar_out_bits {
7306         u8         status[0x8];
7307         u8         reserved_at_8[0x18];
7308
7309         u8         syndrome[0x20];
7310
7311         u8         reserved_at_40[0x8];
7312         u8         uar[0x18];
7313
7314         u8         reserved_at_60[0x20];
7315 };
7316
7317 struct mlx5_ifc_alloc_uar_in_bits {
7318         u8         opcode[0x10];
7319         u8         reserved_at_10[0x10];
7320
7321         u8         reserved_at_20[0x10];
7322         u8         op_mod[0x10];
7323
7324         u8         reserved_at_40[0x40];
7325 };
7326
7327 struct mlx5_ifc_alloc_transport_domain_out_bits {
7328         u8         status[0x8];
7329         u8         reserved_at_8[0x18];
7330
7331         u8         syndrome[0x20];
7332
7333         u8         reserved_at_40[0x8];
7334         u8         transport_domain[0x18];
7335
7336         u8         reserved_at_60[0x20];
7337 };
7338
7339 struct mlx5_ifc_alloc_transport_domain_in_bits {
7340         u8         opcode[0x10];
7341         u8         reserved_at_10[0x10];
7342
7343         u8         reserved_at_20[0x10];
7344         u8         op_mod[0x10];
7345
7346         u8         reserved_at_40[0x40];
7347 };
7348
7349 struct mlx5_ifc_alloc_q_counter_out_bits {
7350         u8         status[0x8];
7351         u8         reserved_at_8[0x18];
7352
7353         u8         syndrome[0x20];
7354
7355         u8         reserved_at_40[0x18];
7356         u8         counter_set_id[0x8];
7357
7358         u8         reserved_at_60[0x20];
7359 };
7360
7361 struct mlx5_ifc_alloc_q_counter_in_bits {
7362         u8         opcode[0x10];
7363         u8         reserved_at_10[0x10];
7364
7365         u8         reserved_at_20[0x10];
7366         u8         op_mod[0x10];
7367
7368         u8         reserved_at_40[0x40];
7369 };
7370
7371 struct mlx5_ifc_alloc_pd_out_bits {
7372         u8         status[0x8];
7373         u8         reserved_at_8[0x18];
7374
7375         u8         syndrome[0x20];
7376
7377         u8         reserved_at_40[0x8];
7378         u8         pd[0x18];
7379
7380         u8         reserved_at_60[0x20];
7381 };
7382
7383 struct mlx5_ifc_alloc_pd_in_bits {
7384         u8         opcode[0x10];
7385         u8         reserved_at_10[0x10];
7386
7387         u8         reserved_at_20[0x10];
7388         u8         op_mod[0x10];
7389
7390         u8         reserved_at_40[0x40];
7391 };
7392
7393 struct mlx5_ifc_alloc_flow_counter_out_bits {
7394         u8         status[0x8];
7395         u8         reserved_at_8[0x18];
7396
7397         u8         syndrome[0x20];
7398
7399         u8         flow_counter_id[0x20];
7400
7401         u8         reserved_at_60[0x20];
7402 };
7403
7404 struct mlx5_ifc_alloc_flow_counter_in_bits {
7405         u8         opcode[0x10];
7406         u8         reserved_at_10[0x10];
7407
7408         u8         reserved_at_20[0x10];
7409         u8         op_mod[0x10];
7410
7411         u8         reserved_at_40[0x40];
7412 };
7413
7414 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7415         u8         status[0x8];
7416         u8         reserved_at_8[0x18];
7417
7418         u8         syndrome[0x20];
7419
7420         u8         reserved_at_40[0x40];
7421 };
7422
7423 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7424         u8         opcode[0x10];
7425         u8         reserved_at_10[0x10];
7426
7427         u8         reserved_at_20[0x10];
7428         u8         op_mod[0x10];
7429
7430         u8         reserved_at_40[0x20];
7431
7432         u8         reserved_at_60[0x10];
7433         u8         vxlan_udp_port[0x10];
7434 };
7435
7436 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7437         u8         status[0x8];
7438         u8         reserved_at_8[0x18];
7439
7440         u8         syndrome[0x20];
7441
7442         u8         reserved_at_40[0x40];
7443 };
7444
7445 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7446         u8         opcode[0x10];
7447         u8         reserved_at_10[0x10];
7448
7449         u8         reserved_at_20[0x10];
7450         u8         op_mod[0x10];
7451
7452         u8         reserved_at_40[0x10];
7453         u8         rate_limit_index[0x10];
7454
7455         u8         reserved_at_60[0x20];
7456
7457         u8         rate_limit[0x20];
7458
7459         u8         burst_upper_bound[0x20];
7460
7461         u8         reserved_at_c0[0x10];
7462         u8         typical_packet_size[0x10];
7463
7464         u8         reserved_at_e0[0x120];
7465 };
7466
7467 struct mlx5_ifc_access_register_out_bits {
7468         u8         status[0x8];
7469         u8         reserved_at_8[0x18];
7470
7471         u8         syndrome[0x20];
7472
7473         u8         reserved_at_40[0x40];
7474
7475         u8         register_data[0][0x20];
7476 };
7477
7478 enum {
7479         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7480         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7481 };
7482
7483 struct mlx5_ifc_access_register_in_bits {
7484         u8         opcode[0x10];
7485         u8         reserved_at_10[0x10];
7486
7487         u8         reserved_at_20[0x10];
7488         u8         op_mod[0x10];
7489
7490         u8         reserved_at_40[0x10];
7491         u8         register_id[0x10];
7492
7493         u8         argument[0x20];
7494
7495         u8         register_data[0][0x20];
7496 };
7497
7498 struct mlx5_ifc_sltp_reg_bits {
7499         u8         status[0x4];
7500         u8         version[0x4];
7501         u8         local_port[0x8];
7502         u8         pnat[0x2];
7503         u8         reserved_at_12[0x2];
7504         u8         lane[0x4];
7505         u8         reserved_at_18[0x8];
7506
7507         u8         reserved_at_20[0x20];
7508
7509         u8         reserved_at_40[0x7];
7510         u8         polarity[0x1];
7511         u8         ob_tap0[0x8];
7512         u8         ob_tap1[0x8];
7513         u8         ob_tap2[0x8];
7514
7515         u8         reserved_at_60[0xc];
7516         u8         ob_preemp_mode[0x4];
7517         u8         ob_reg[0x8];
7518         u8         ob_bias[0x8];
7519
7520         u8         reserved_at_80[0x20];
7521 };
7522
7523 struct mlx5_ifc_slrg_reg_bits {
7524         u8         status[0x4];
7525         u8         version[0x4];
7526         u8         local_port[0x8];
7527         u8         pnat[0x2];
7528         u8         reserved_at_12[0x2];
7529         u8         lane[0x4];
7530         u8         reserved_at_18[0x8];
7531
7532         u8         time_to_link_up[0x10];
7533         u8         reserved_at_30[0xc];
7534         u8         grade_lane_speed[0x4];
7535
7536         u8         grade_version[0x8];
7537         u8         grade[0x18];
7538
7539         u8         reserved_at_60[0x4];
7540         u8         height_grade_type[0x4];
7541         u8         height_grade[0x18];
7542
7543         u8         height_dz[0x10];
7544         u8         height_dv[0x10];
7545
7546         u8         reserved_at_a0[0x10];
7547         u8         height_sigma[0x10];
7548
7549         u8         reserved_at_c0[0x20];
7550
7551         u8         reserved_at_e0[0x4];
7552         u8         phase_grade_type[0x4];
7553         u8         phase_grade[0x18];
7554
7555         u8         reserved_at_100[0x8];
7556         u8         phase_eo_pos[0x8];
7557         u8         reserved_at_110[0x8];
7558         u8         phase_eo_neg[0x8];
7559
7560         u8         ffe_set_tested[0x10];
7561         u8         test_errors_per_lane[0x10];
7562 };
7563
7564 struct mlx5_ifc_pvlc_reg_bits {
7565         u8         reserved_at_0[0x8];
7566         u8         local_port[0x8];
7567         u8         reserved_at_10[0x10];
7568
7569         u8         reserved_at_20[0x1c];
7570         u8         vl_hw_cap[0x4];
7571
7572         u8         reserved_at_40[0x1c];
7573         u8         vl_admin[0x4];
7574
7575         u8         reserved_at_60[0x1c];
7576         u8         vl_operational[0x4];
7577 };
7578
7579 struct mlx5_ifc_pude_reg_bits {
7580         u8         swid[0x8];
7581         u8         local_port[0x8];
7582         u8         reserved_at_10[0x4];
7583         u8         admin_status[0x4];
7584         u8         reserved_at_18[0x4];
7585         u8         oper_status[0x4];
7586
7587         u8         reserved_at_20[0x60];
7588 };
7589
7590 struct mlx5_ifc_ptys_reg_bits {
7591         u8         reserved_at_0[0x1];
7592         u8         an_disable_admin[0x1];
7593         u8         an_disable_cap[0x1];
7594         u8         reserved_at_3[0x5];
7595         u8         local_port[0x8];
7596         u8         reserved_at_10[0xd];
7597         u8         proto_mask[0x3];
7598
7599         u8         an_status[0x4];
7600         u8         reserved_at_24[0x3c];
7601
7602         u8         eth_proto_capability[0x20];
7603
7604         u8         ib_link_width_capability[0x10];
7605         u8         ib_proto_capability[0x10];
7606
7607         u8         reserved_at_a0[0x20];
7608
7609         u8         eth_proto_admin[0x20];
7610
7611         u8         ib_link_width_admin[0x10];
7612         u8         ib_proto_admin[0x10];
7613
7614         u8         reserved_at_100[0x20];
7615
7616         u8         eth_proto_oper[0x20];
7617
7618         u8         ib_link_width_oper[0x10];
7619         u8         ib_proto_oper[0x10];
7620
7621         u8         reserved_at_160[0x1c];
7622         u8         connector_type[0x4];
7623
7624         u8         eth_proto_lp_advertise[0x20];
7625
7626         u8         reserved_at_1a0[0x60];
7627 };
7628
7629 struct mlx5_ifc_mlcr_reg_bits {
7630         u8         reserved_at_0[0x8];
7631         u8         local_port[0x8];
7632         u8         reserved_at_10[0x20];
7633
7634         u8         beacon_duration[0x10];
7635         u8         reserved_at_40[0x10];
7636
7637         u8         beacon_remain[0x10];
7638 };
7639
7640 struct mlx5_ifc_ptas_reg_bits {
7641         u8         reserved_at_0[0x20];
7642
7643         u8         algorithm_options[0x10];
7644         u8         reserved_at_30[0x4];
7645         u8         repetitions_mode[0x4];
7646         u8         num_of_repetitions[0x8];
7647
7648         u8         grade_version[0x8];
7649         u8         height_grade_type[0x4];
7650         u8         phase_grade_type[0x4];
7651         u8         height_grade_weight[0x8];
7652         u8         phase_grade_weight[0x8];
7653
7654         u8         gisim_measure_bits[0x10];
7655         u8         adaptive_tap_measure_bits[0x10];
7656
7657         u8         ber_bath_high_error_threshold[0x10];
7658         u8         ber_bath_mid_error_threshold[0x10];
7659
7660         u8         ber_bath_low_error_threshold[0x10];
7661         u8         one_ratio_high_threshold[0x10];
7662
7663         u8         one_ratio_high_mid_threshold[0x10];
7664         u8         one_ratio_low_mid_threshold[0x10];
7665
7666         u8         one_ratio_low_threshold[0x10];
7667         u8         ndeo_error_threshold[0x10];
7668
7669         u8         mixer_offset_step_size[0x10];
7670         u8         reserved_at_110[0x8];
7671         u8         mix90_phase_for_voltage_bath[0x8];
7672
7673         u8         mixer_offset_start[0x10];
7674         u8         mixer_offset_end[0x10];
7675
7676         u8         reserved_at_140[0x15];
7677         u8         ber_test_time[0xb];
7678 };
7679
7680 struct mlx5_ifc_pspa_reg_bits {
7681         u8         swid[0x8];
7682         u8         local_port[0x8];
7683         u8         sub_port[0x8];
7684         u8         reserved_at_18[0x8];
7685
7686         u8         reserved_at_20[0x20];
7687 };
7688
7689 struct mlx5_ifc_pqdr_reg_bits {
7690         u8         reserved_at_0[0x8];
7691         u8         local_port[0x8];
7692         u8         reserved_at_10[0x5];
7693         u8         prio[0x3];
7694         u8         reserved_at_18[0x6];
7695         u8         mode[0x2];
7696
7697         u8         reserved_at_20[0x20];
7698
7699         u8         reserved_at_40[0x10];
7700         u8         min_threshold[0x10];
7701
7702         u8         reserved_at_60[0x10];
7703         u8         max_threshold[0x10];
7704
7705         u8         reserved_at_80[0x10];
7706         u8         mark_probability_denominator[0x10];
7707
7708         u8         reserved_at_a0[0x60];
7709 };
7710
7711 struct mlx5_ifc_ppsc_reg_bits {
7712         u8         reserved_at_0[0x8];
7713         u8         local_port[0x8];
7714         u8         reserved_at_10[0x10];
7715
7716         u8         reserved_at_20[0x60];
7717
7718         u8         reserved_at_80[0x1c];
7719         u8         wrps_admin[0x4];
7720
7721         u8         reserved_at_a0[0x1c];
7722         u8         wrps_status[0x4];
7723
7724         u8         reserved_at_c0[0x8];
7725         u8         up_threshold[0x8];
7726         u8         reserved_at_d0[0x8];
7727         u8         down_threshold[0x8];
7728
7729         u8         reserved_at_e0[0x20];
7730
7731         u8         reserved_at_100[0x1c];
7732         u8         srps_admin[0x4];
7733
7734         u8         reserved_at_120[0x1c];
7735         u8         srps_status[0x4];
7736
7737         u8         reserved_at_140[0x40];
7738 };
7739
7740 struct mlx5_ifc_pplr_reg_bits {
7741         u8         reserved_at_0[0x8];
7742         u8         local_port[0x8];
7743         u8         reserved_at_10[0x10];
7744
7745         u8         reserved_at_20[0x8];
7746         u8         lb_cap[0x8];
7747         u8         reserved_at_30[0x8];
7748         u8         lb_en[0x8];
7749 };
7750
7751 struct mlx5_ifc_pplm_reg_bits {
7752         u8         reserved_at_0[0x8];
7753         u8         local_port[0x8];
7754         u8         reserved_at_10[0x10];
7755
7756         u8         reserved_at_20[0x20];
7757
7758         u8         port_profile_mode[0x8];
7759         u8         static_port_profile[0x8];
7760         u8         active_port_profile[0x8];
7761         u8         reserved_at_58[0x8];
7762
7763         u8         retransmission_active[0x8];
7764         u8         fec_mode_active[0x18];
7765
7766         u8         reserved_at_80[0x20];
7767 };
7768
7769 struct mlx5_ifc_ppcnt_reg_bits {
7770         u8         swid[0x8];
7771         u8         local_port[0x8];
7772         u8         pnat[0x2];
7773         u8         reserved_at_12[0x8];
7774         u8         grp[0x6];
7775
7776         u8         clr[0x1];
7777         u8         reserved_at_21[0x1c];
7778         u8         prio_tc[0x3];
7779
7780         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7781 };
7782
7783 struct mlx5_ifc_mpcnt_reg_bits {
7784         u8         reserved_at_0[0x8];
7785         u8         pcie_index[0x8];
7786         u8         reserved_at_10[0xa];
7787         u8         grp[0x6];
7788
7789         u8         clr[0x1];
7790         u8         reserved_at_21[0x1f];
7791
7792         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7793 };
7794
7795 struct mlx5_ifc_ppad_reg_bits {
7796         u8         reserved_at_0[0x3];
7797         u8         single_mac[0x1];
7798         u8         reserved_at_4[0x4];
7799         u8         local_port[0x8];
7800         u8         mac_47_32[0x10];
7801
7802         u8         mac_31_0[0x20];
7803
7804         u8         reserved_at_40[0x40];
7805 };
7806
7807 struct mlx5_ifc_pmtu_reg_bits {
7808         u8         reserved_at_0[0x8];
7809         u8         local_port[0x8];
7810         u8         reserved_at_10[0x10];
7811
7812         u8         max_mtu[0x10];
7813         u8         reserved_at_30[0x10];
7814
7815         u8         admin_mtu[0x10];
7816         u8         reserved_at_50[0x10];
7817
7818         u8         oper_mtu[0x10];
7819         u8         reserved_at_70[0x10];
7820 };
7821
7822 struct mlx5_ifc_pmpr_reg_bits {
7823         u8         reserved_at_0[0x8];
7824         u8         module[0x8];
7825         u8         reserved_at_10[0x10];
7826
7827         u8         reserved_at_20[0x18];
7828         u8         attenuation_5g[0x8];
7829
7830         u8         reserved_at_40[0x18];
7831         u8         attenuation_7g[0x8];
7832
7833         u8         reserved_at_60[0x18];
7834         u8         attenuation_12g[0x8];
7835 };
7836
7837 struct mlx5_ifc_pmpe_reg_bits {
7838         u8         reserved_at_0[0x8];
7839         u8         module[0x8];
7840         u8         reserved_at_10[0xc];
7841         u8         module_status[0x4];
7842
7843         u8         reserved_at_20[0x60];
7844 };
7845
7846 struct mlx5_ifc_pmpc_reg_bits {
7847         u8         module_state_updated[32][0x8];
7848 };
7849
7850 struct mlx5_ifc_pmlpn_reg_bits {
7851         u8         reserved_at_0[0x4];
7852         u8         mlpn_status[0x4];
7853         u8         local_port[0x8];
7854         u8         reserved_at_10[0x10];
7855
7856         u8         e[0x1];
7857         u8         reserved_at_21[0x1f];
7858 };
7859
7860 struct mlx5_ifc_pmlp_reg_bits {
7861         u8         rxtx[0x1];
7862         u8         reserved_at_1[0x7];
7863         u8         local_port[0x8];
7864         u8         reserved_at_10[0x8];
7865         u8         width[0x8];
7866
7867         u8         lane0_module_mapping[0x20];
7868
7869         u8         lane1_module_mapping[0x20];
7870
7871         u8         lane2_module_mapping[0x20];
7872
7873         u8         lane3_module_mapping[0x20];
7874
7875         u8         reserved_at_a0[0x160];
7876 };
7877
7878 struct mlx5_ifc_pmaos_reg_bits {
7879         u8         reserved_at_0[0x8];
7880         u8         module[0x8];
7881         u8         reserved_at_10[0x4];
7882         u8         admin_status[0x4];
7883         u8         reserved_at_18[0x4];
7884         u8         oper_status[0x4];
7885
7886         u8         ase[0x1];
7887         u8         ee[0x1];
7888         u8         reserved_at_22[0x1c];
7889         u8         e[0x2];
7890
7891         u8         reserved_at_40[0x40];
7892 };
7893
7894 struct mlx5_ifc_plpc_reg_bits {
7895         u8         reserved_at_0[0x4];
7896         u8         profile_id[0xc];
7897         u8         reserved_at_10[0x4];
7898         u8         proto_mask[0x4];
7899         u8         reserved_at_18[0x8];
7900
7901         u8         reserved_at_20[0x10];
7902         u8         lane_speed[0x10];
7903
7904         u8         reserved_at_40[0x17];
7905         u8         lpbf[0x1];
7906         u8         fec_mode_policy[0x8];
7907
7908         u8         retransmission_capability[0x8];
7909         u8         fec_mode_capability[0x18];
7910
7911         u8         retransmission_support_admin[0x8];
7912         u8         fec_mode_support_admin[0x18];
7913
7914         u8         retransmission_request_admin[0x8];
7915         u8         fec_mode_request_admin[0x18];
7916
7917         u8         reserved_at_c0[0x80];
7918 };
7919
7920 struct mlx5_ifc_plib_reg_bits {
7921         u8         reserved_at_0[0x8];
7922         u8         local_port[0x8];
7923         u8         reserved_at_10[0x8];
7924         u8         ib_port[0x8];
7925
7926         u8         reserved_at_20[0x60];
7927 };
7928
7929 struct mlx5_ifc_plbf_reg_bits {
7930         u8         reserved_at_0[0x8];
7931         u8         local_port[0x8];
7932         u8         reserved_at_10[0xd];
7933         u8         lbf_mode[0x3];
7934
7935         u8         reserved_at_20[0x20];
7936 };
7937
7938 struct mlx5_ifc_pipg_reg_bits {
7939         u8         reserved_at_0[0x8];
7940         u8         local_port[0x8];
7941         u8         reserved_at_10[0x10];
7942
7943         u8         dic[0x1];
7944         u8         reserved_at_21[0x19];
7945         u8         ipg[0x4];
7946         u8         reserved_at_3e[0x2];
7947 };
7948
7949 struct mlx5_ifc_pifr_reg_bits {
7950         u8         reserved_at_0[0x8];
7951         u8         local_port[0x8];
7952         u8         reserved_at_10[0x10];
7953
7954         u8         reserved_at_20[0xe0];
7955
7956         u8         port_filter[8][0x20];
7957
7958         u8         port_filter_update_en[8][0x20];
7959 };
7960
7961 struct mlx5_ifc_pfcc_reg_bits {
7962         u8         reserved_at_0[0x8];
7963         u8         local_port[0x8];
7964         u8         reserved_at_10[0xb];
7965         u8         ppan_mask_n[0x1];
7966         u8         minor_stall_mask[0x1];
7967         u8         critical_stall_mask[0x1];
7968         u8         reserved_at_1e[0x2];
7969
7970         u8         ppan[0x4];
7971         u8         reserved_at_24[0x4];
7972         u8         prio_mask_tx[0x8];
7973         u8         reserved_at_30[0x8];
7974         u8         prio_mask_rx[0x8];
7975
7976         u8         pptx[0x1];
7977         u8         aptx[0x1];
7978         u8         pptx_mask_n[0x1];
7979         u8         reserved_at_43[0x5];
7980         u8         pfctx[0x8];
7981         u8         reserved_at_50[0x10];
7982
7983         u8         pprx[0x1];
7984         u8         aprx[0x1];
7985         u8         pprx_mask_n[0x1];
7986         u8         reserved_at_63[0x5];
7987         u8         pfcrx[0x8];
7988         u8         reserved_at_70[0x10];
7989
7990         u8         device_stall_minor_watermark[0x10];
7991         u8         device_stall_critical_watermark[0x10];
7992
7993         u8         reserved_at_a0[0x60];
7994 };
7995
7996 struct mlx5_ifc_pelc_reg_bits {
7997         u8         op[0x4];
7998         u8         reserved_at_4[0x4];
7999         u8         local_port[0x8];
8000         u8         reserved_at_10[0x10];
8001
8002         u8         op_admin[0x8];
8003         u8         op_capability[0x8];
8004         u8         op_request[0x8];
8005         u8         op_active[0x8];
8006
8007         u8         admin[0x40];
8008
8009         u8         capability[0x40];
8010
8011         u8         request[0x40];
8012
8013         u8         active[0x40];
8014
8015         u8         reserved_at_140[0x80];
8016 };
8017
8018 struct mlx5_ifc_peir_reg_bits {
8019         u8         reserved_at_0[0x8];
8020         u8         local_port[0x8];
8021         u8         reserved_at_10[0x10];
8022
8023         u8         reserved_at_20[0xc];
8024         u8         error_count[0x4];
8025         u8         reserved_at_30[0x10];
8026
8027         u8         reserved_at_40[0xc];
8028         u8         lane[0x4];
8029         u8         reserved_at_50[0x8];
8030         u8         error_type[0x8];
8031 };
8032
8033 struct mlx5_ifc_pcam_enhanced_features_bits {
8034         u8         reserved_at_0[0x76];
8035
8036         u8         pfcc_mask[0x1];
8037         u8         reserved_at_77[0x4];
8038         u8         rx_buffer_fullness_counters[0x1];
8039         u8         ptys_connector_type[0x1];
8040         u8         reserved_at_7d[0x1];
8041         u8         ppcnt_discard_group[0x1];
8042         u8         ppcnt_statistical_group[0x1];
8043 };
8044
8045 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8046         u8         port_access_reg_cap_mask_127_to_96[0x20];
8047         u8         port_access_reg_cap_mask_95_to_64[0x20];
8048         u8         port_access_reg_cap_mask_63_to_32[0x20];
8049
8050         u8         port_access_reg_cap_mask_31_to_13[0x13];
8051         u8         pbmc[0x1];
8052         u8         pptb[0x1];
8053         u8         port_access_reg_cap_mask_10_to_0[0xb];
8054 };
8055
8056 struct mlx5_ifc_pcam_reg_bits {
8057         u8         reserved_at_0[0x8];
8058         u8         feature_group[0x8];
8059         u8         reserved_at_10[0x8];
8060         u8         access_reg_group[0x8];
8061
8062         u8         reserved_at_20[0x20];
8063
8064         union {
8065                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8066                 u8         reserved_at_0[0x80];
8067         } port_access_reg_cap_mask;
8068
8069         u8         reserved_at_c0[0x80];
8070
8071         union {
8072                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8073                 u8         reserved_at_0[0x80];
8074         } feature_cap_mask;
8075
8076         u8         reserved_at_1c0[0xc0];
8077 };
8078
8079 struct mlx5_ifc_mcam_enhanced_features_bits {
8080         u8         reserved_at_0[0x7b];
8081         u8         pcie_outbound_stalled[0x1];
8082         u8         tx_overflow_buffer_pkt[0x1];
8083         u8         mtpps_enh_out_per_adj[0x1];
8084         u8         mtpps_fs[0x1];
8085         u8         pcie_performance_group[0x1];
8086 };
8087
8088 struct mlx5_ifc_mcam_access_reg_bits {
8089         u8         reserved_at_0[0x1c];
8090         u8         mcda[0x1];
8091         u8         mcc[0x1];
8092         u8         mcqi[0x1];
8093         u8         reserved_at_1f[0x1];
8094
8095         u8         regs_95_to_64[0x20];
8096         u8         regs_63_to_32[0x20];
8097         u8         regs_31_to_0[0x20];
8098 };
8099
8100 struct mlx5_ifc_mcam_reg_bits {
8101         u8         reserved_at_0[0x8];
8102         u8         feature_group[0x8];
8103         u8         reserved_at_10[0x8];
8104         u8         access_reg_group[0x8];
8105
8106         u8         reserved_at_20[0x20];
8107
8108         union {
8109                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8110                 u8         reserved_at_0[0x80];
8111         } mng_access_reg_cap_mask;
8112
8113         u8         reserved_at_c0[0x80];
8114
8115         union {
8116                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8117                 u8         reserved_at_0[0x80];
8118         } mng_feature_cap_mask;
8119
8120         u8         reserved_at_1c0[0x80];
8121 };
8122
8123 struct mlx5_ifc_qcam_access_reg_cap_mask {
8124         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8125         u8         qpdpm[0x1];
8126         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8127         u8         qdpm[0x1];
8128         u8         qpts[0x1];
8129         u8         qcap[0x1];
8130         u8         qcam_access_reg_cap_mask_0[0x1];
8131 };
8132
8133 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8134         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8135         u8         qpts_trust_both[0x1];
8136 };
8137
8138 struct mlx5_ifc_qcam_reg_bits {
8139         u8         reserved_at_0[0x8];
8140         u8         feature_group[0x8];
8141         u8         reserved_at_10[0x8];
8142         u8         access_reg_group[0x8];
8143         u8         reserved_at_20[0x20];
8144
8145         union {
8146                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8147                 u8  reserved_at_0[0x80];
8148         } qos_access_reg_cap_mask;
8149
8150         u8         reserved_at_c0[0x80];
8151
8152         union {
8153                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8154                 u8  reserved_at_0[0x80];
8155         } qos_feature_cap_mask;
8156
8157         u8         reserved_at_1c0[0x80];
8158 };
8159
8160 struct mlx5_ifc_pcap_reg_bits {
8161         u8         reserved_at_0[0x8];
8162         u8         local_port[0x8];
8163         u8         reserved_at_10[0x10];
8164
8165         u8         port_capability_mask[4][0x20];
8166 };
8167
8168 struct mlx5_ifc_paos_reg_bits {
8169         u8         swid[0x8];
8170         u8         local_port[0x8];
8171         u8         reserved_at_10[0x4];
8172         u8         admin_status[0x4];
8173         u8         reserved_at_18[0x4];
8174         u8         oper_status[0x4];
8175
8176         u8         ase[0x1];
8177         u8         ee[0x1];
8178         u8         reserved_at_22[0x1c];
8179         u8         e[0x2];
8180
8181         u8         reserved_at_40[0x40];
8182 };
8183
8184 struct mlx5_ifc_pamp_reg_bits {
8185         u8         reserved_at_0[0x8];
8186         u8         opamp_group[0x8];
8187         u8         reserved_at_10[0xc];
8188         u8         opamp_group_type[0x4];
8189
8190         u8         start_index[0x10];
8191         u8         reserved_at_30[0x4];
8192         u8         num_of_indices[0xc];
8193
8194         u8         index_data[18][0x10];
8195 };
8196
8197 struct mlx5_ifc_pcmr_reg_bits {
8198         u8         reserved_at_0[0x8];
8199         u8         local_port[0x8];
8200         u8         reserved_at_10[0x2e];
8201         u8         fcs_cap[0x1];
8202         u8         reserved_at_3f[0x1f];
8203         u8         fcs_chk[0x1];
8204         u8         reserved_at_5f[0x1];
8205 };
8206
8207 struct mlx5_ifc_lane_2_module_mapping_bits {
8208         u8         reserved_at_0[0x6];
8209         u8         rx_lane[0x2];
8210         u8         reserved_at_8[0x6];
8211         u8         tx_lane[0x2];
8212         u8         reserved_at_10[0x8];
8213         u8         module[0x8];
8214 };
8215
8216 struct mlx5_ifc_bufferx_reg_bits {
8217         u8         reserved_at_0[0x6];
8218         u8         lossy[0x1];
8219         u8         epsb[0x1];
8220         u8         reserved_at_8[0xc];
8221         u8         size[0xc];
8222
8223         u8         xoff_threshold[0x10];
8224         u8         xon_threshold[0x10];
8225 };
8226
8227 struct mlx5_ifc_set_node_in_bits {
8228         u8         node_description[64][0x8];
8229 };
8230
8231 struct mlx5_ifc_register_power_settings_bits {
8232         u8         reserved_at_0[0x18];
8233         u8         power_settings_level[0x8];
8234
8235         u8         reserved_at_20[0x60];
8236 };
8237
8238 struct mlx5_ifc_register_host_endianness_bits {
8239         u8         he[0x1];
8240         u8         reserved_at_1[0x1f];
8241
8242         u8         reserved_at_20[0x60];
8243 };
8244
8245 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8246         u8         reserved_at_0[0x20];
8247
8248         u8         mkey[0x20];
8249
8250         u8         addressh_63_32[0x20];
8251
8252         u8         addressl_31_0[0x20];
8253 };
8254
8255 struct mlx5_ifc_ud_adrs_vector_bits {
8256         u8         dc_key[0x40];
8257
8258         u8         ext[0x1];
8259         u8         reserved_at_41[0x7];
8260         u8         destination_qp_dct[0x18];
8261
8262         u8         static_rate[0x4];
8263         u8         sl_eth_prio[0x4];
8264         u8         fl[0x1];
8265         u8         mlid[0x7];
8266         u8         rlid_udp_sport[0x10];
8267
8268         u8         reserved_at_80[0x20];
8269
8270         u8         rmac_47_16[0x20];
8271
8272         u8         rmac_15_0[0x10];
8273         u8         tclass[0x8];
8274         u8         hop_limit[0x8];
8275
8276         u8         reserved_at_e0[0x1];
8277         u8         grh[0x1];
8278         u8         reserved_at_e2[0x2];
8279         u8         src_addr_index[0x8];
8280         u8         flow_label[0x14];
8281
8282         u8         rgid_rip[16][0x8];
8283 };
8284
8285 struct mlx5_ifc_pages_req_event_bits {
8286         u8         reserved_at_0[0x10];
8287         u8         function_id[0x10];
8288
8289         u8         num_pages[0x20];
8290
8291         u8         reserved_at_40[0xa0];
8292 };
8293
8294 struct mlx5_ifc_eqe_bits {
8295         u8         reserved_at_0[0x8];
8296         u8         event_type[0x8];
8297         u8         reserved_at_10[0x8];
8298         u8         event_sub_type[0x8];
8299
8300         u8         reserved_at_20[0xe0];
8301
8302         union mlx5_ifc_event_auto_bits event_data;
8303
8304         u8         reserved_at_1e0[0x10];
8305         u8         signature[0x8];
8306         u8         reserved_at_1f8[0x7];
8307         u8         owner[0x1];
8308 };
8309
8310 enum {
8311         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8312 };
8313
8314 struct mlx5_ifc_cmd_queue_entry_bits {
8315         u8         type[0x8];
8316         u8         reserved_at_8[0x18];
8317
8318         u8         input_length[0x20];
8319
8320         u8         input_mailbox_pointer_63_32[0x20];
8321
8322         u8         input_mailbox_pointer_31_9[0x17];
8323         u8         reserved_at_77[0x9];
8324
8325         u8         command_input_inline_data[16][0x8];
8326
8327         u8         command_output_inline_data[16][0x8];
8328
8329         u8         output_mailbox_pointer_63_32[0x20];
8330
8331         u8         output_mailbox_pointer_31_9[0x17];
8332         u8         reserved_at_1b7[0x9];
8333
8334         u8         output_length[0x20];
8335
8336         u8         token[0x8];
8337         u8         signature[0x8];
8338         u8         reserved_at_1f0[0x8];
8339         u8         status[0x7];
8340         u8         ownership[0x1];
8341 };
8342
8343 struct mlx5_ifc_cmd_out_bits {
8344         u8         status[0x8];
8345         u8         reserved_at_8[0x18];
8346
8347         u8         syndrome[0x20];
8348
8349         u8         command_output[0x20];
8350 };
8351
8352 struct mlx5_ifc_cmd_in_bits {
8353         u8         opcode[0x10];
8354         u8         reserved_at_10[0x10];
8355
8356         u8         reserved_at_20[0x10];
8357         u8         op_mod[0x10];
8358
8359         u8         command[0][0x20];
8360 };
8361
8362 struct mlx5_ifc_cmd_if_box_bits {
8363         u8         mailbox_data[512][0x8];
8364
8365         u8         reserved_at_1000[0x180];
8366
8367         u8         next_pointer_63_32[0x20];
8368
8369         u8         next_pointer_31_10[0x16];
8370         u8         reserved_at_11b6[0xa];
8371
8372         u8         block_number[0x20];
8373
8374         u8         reserved_at_11e0[0x8];
8375         u8         token[0x8];
8376         u8         ctrl_signature[0x8];
8377         u8         signature[0x8];
8378 };
8379
8380 struct mlx5_ifc_mtt_bits {
8381         u8         ptag_63_32[0x20];
8382
8383         u8         ptag_31_8[0x18];
8384         u8         reserved_at_38[0x6];
8385         u8         wr_en[0x1];
8386         u8         rd_en[0x1];
8387 };
8388
8389 struct mlx5_ifc_query_wol_rol_out_bits {
8390         u8         status[0x8];
8391         u8         reserved_at_8[0x18];
8392
8393         u8         syndrome[0x20];
8394
8395         u8         reserved_at_40[0x10];
8396         u8         rol_mode[0x8];
8397         u8         wol_mode[0x8];
8398
8399         u8         reserved_at_60[0x20];
8400 };
8401
8402 struct mlx5_ifc_query_wol_rol_in_bits {
8403         u8         opcode[0x10];
8404         u8         reserved_at_10[0x10];
8405
8406         u8         reserved_at_20[0x10];
8407         u8         op_mod[0x10];
8408
8409         u8         reserved_at_40[0x40];
8410 };
8411
8412 struct mlx5_ifc_set_wol_rol_out_bits {
8413         u8         status[0x8];
8414         u8         reserved_at_8[0x18];
8415
8416         u8         syndrome[0x20];
8417
8418         u8         reserved_at_40[0x40];
8419 };
8420
8421 struct mlx5_ifc_set_wol_rol_in_bits {
8422         u8         opcode[0x10];
8423         u8         reserved_at_10[0x10];
8424
8425         u8         reserved_at_20[0x10];
8426         u8         op_mod[0x10];
8427
8428         u8         rol_mode_valid[0x1];
8429         u8         wol_mode_valid[0x1];
8430         u8         reserved_at_42[0xe];
8431         u8         rol_mode[0x8];
8432         u8         wol_mode[0x8];
8433
8434         u8         reserved_at_60[0x20];
8435 };
8436
8437 enum {
8438         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8439         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8440         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8441 };
8442
8443 enum {
8444         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8445         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8446         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8447 };
8448
8449 enum {
8450         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8451         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8452         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8453         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8454         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8455         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8456         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8457         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8458         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8459         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8460         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8461 };
8462
8463 struct mlx5_ifc_initial_seg_bits {
8464         u8         fw_rev_minor[0x10];
8465         u8         fw_rev_major[0x10];
8466
8467         u8         cmd_interface_rev[0x10];
8468         u8         fw_rev_subminor[0x10];
8469
8470         u8         reserved_at_40[0x40];
8471
8472         u8         cmdq_phy_addr_63_32[0x20];
8473
8474         u8         cmdq_phy_addr_31_12[0x14];
8475         u8         reserved_at_b4[0x2];
8476         u8         nic_interface[0x2];
8477         u8         log_cmdq_size[0x4];
8478         u8         log_cmdq_stride[0x4];
8479
8480         u8         command_doorbell_vector[0x20];
8481
8482         u8         reserved_at_e0[0xf00];
8483
8484         u8         initializing[0x1];
8485         u8         reserved_at_fe1[0x4];
8486         u8         nic_interface_supported[0x3];
8487         u8         reserved_at_fe8[0x18];
8488
8489         struct mlx5_ifc_health_buffer_bits health_buffer;
8490
8491         u8         no_dram_nic_offset[0x20];
8492
8493         u8         reserved_at_1220[0x6e40];
8494
8495         u8         reserved_at_8060[0x1f];
8496         u8         clear_int[0x1];
8497
8498         u8         health_syndrome[0x8];
8499         u8         health_counter[0x18];
8500
8501         u8         reserved_at_80a0[0x17fc0];
8502 };
8503
8504 struct mlx5_ifc_mtpps_reg_bits {
8505         u8         reserved_at_0[0xc];
8506         u8         cap_number_of_pps_pins[0x4];
8507         u8         reserved_at_10[0x4];
8508         u8         cap_max_num_of_pps_in_pins[0x4];
8509         u8         reserved_at_18[0x4];
8510         u8         cap_max_num_of_pps_out_pins[0x4];
8511
8512         u8         reserved_at_20[0x24];
8513         u8         cap_pin_3_mode[0x4];
8514         u8         reserved_at_48[0x4];
8515         u8         cap_pin_2_mode[0x4];
8516         u8         reserved_at_50[0x4];
8517         u8         cap_pin_1_mode[0x4];
8518         u8         reserved_at_58[0x4];
8519         u8         cap_pin_0_mode[0x4];
8520
8521         u8         reserved_at_60[0x4];
8522         u8         cap_pin_7_mode[0x4];
8523         u8         reserved_at_68[0x4];
8524         u8         cap_pin_6_mode[0x4];
8525         u8         reserved_at_70[0x4];
8526         u8         cap_pin_5_mode[0x4];
8527         u8         reserved_at_78[0x4];
8528         u8         cap_pin_4_mode[0x4];
8529
8530         u8         field_select[0x20];
8531         u8         reserved_at_a0[0x60];
8532
8533         u8         enable[0x1];
8534         u8         reserved_at_101[0xb];
8535         u8         pattern[0x4];
8536         u8         reserved_at_110[0x4];
8537         u8         pin_mode[0x4];
8538         u8         pin[0x8];
8539
8540         u8         reserved_at_120[0x20];
8541
8542         u8         time_stamp[0x40];
8543
8544         u8         out_pulse_duration[0x10];
8545         u8         out_periodic_adjustment[0x10];
8546         u8         enhanced_out_periodic_adjustment[0x20];
8547
8548         u8         reserved_at_1c0[0x20];
8549 };
8550
8551 struct mlx5_ifc_mtppse_reg_bits {
8552         u8         reserved_at_0[0x18];
8553         u8         pin[0x8];
8554         u8         event_arm[0x1];
8555         u8         reserved_at_21[0x1b];
8556         u8         event_generation_mode[0x4];
8557         u8         reserved_at_40[0x40];
8558 };
8559
8560 struct mlx5_ifc_mcqi_cap_bits {
8561         u8         supported_info_bitmask[0x20];
8562
8563         u8         component_size[0x20];
8564
8565         u8         max_component_size[0x20];
8566
8567         u8         log_mcda_word_size[0x4];
8568         u8         reserved_at_64[0xc];
8569         u8         mcda_max_write_size[0x10];
8570
8571         u8         rd_en[0x1];
8572         u8         reserved_at_81[0x1];
8573         u8         match_chip_id[0x1];
8574         u8         match_psid[0x1];
8575         u8         check_user_timestamp[0x1];
8576         u8         match_base_guid_mac[0x1];
8577         u8         reserved_at_86[0x1a];
8578 };
8579
8580 struct mlx5_ifc_mcqi_reg_bits {
8581         u8         read_pending_component[0x1];
8582         u8         reserved_at_1[0xf];
8583         u8         component_index[0x10];
8584
8585         u8         reserved_at_20[0x20];
8586
8587         u8         reserved_at_40[0x1b];
8588         u8         info_type[0x5];
8589
8590         u8         info_size[0x20];
8591
8592         u8         offset[0x20];
8593
8594         u8         reserved_at_a0[0x10];
8595         u8         data_size[0x10];
8596
8597         u8         data[0][0x20];
8598 };
8599
8600 struct mlx5_ifc_mcc_reg_bits {
8601         u8         reserved_at_0[0x4];
8602         u8         time_elapsed_since_last_cmd[0xc];
8603         u8         reserved_at_10[0x8];
8604         u8         instruction[0x8];
8605
8606         u8         reserved_at_20[0x10];
8607         u8         component_index[0x10];
8608
8609         u8         reserved_at_40[0x8];
8610         u8         update_handle[0x18];
8611
8612         u8         handle_owner_type[0x4];
8613         u8         handle_owner_host_id[0x4];
8614         u8         reserved_at_68[0x1];
8615         u8         control_progress[0x7];
8616         u8         error_code[0x8];
8617         u8         reserved_at_78[0x4];
8618         u8         control_state[0x4];
8619
8620         u8         component_size[0x20];
8621
8622         u8         reserved_at_a0[0x60];
8623 };
8624
8625 struct mlx5_ifc_mcda_reg_bits {
8626         u8         reserved_at_0[0x8];
8627         u8         update_handle[0x18];
8628
8629         u8         offset[0x20];
8630
8631         u8         reserved_at_40[0x10];
8632         u8         size[0x10];
8633
8634         u8         reserved_at_60[0x20];
8635
8636         u8         data[0][0x20];
8637 };
8638
8639 union mlx5_ifc_ports_control_registers_document_bits {
8640         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8641         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8642         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8643         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8644         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8645         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8646         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8647         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8648         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8649         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8650         struct mlx5_ifc_paos_reg_bits paos_reg;
8651         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8652         struct mlx5_ifc_peir_reg_bits peir_reg;
8653         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8654         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8655         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8656         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8657         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8658         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8659         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8660         struct mlx5_ifc_plib_reg_bits plib_reg;
8661         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8662         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8663         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8664         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8665         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8666         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8667         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8668         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8669         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8670         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8671         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8672         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8673         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8674         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8675         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8676         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8677         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8678         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8679         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8680         struct mlx5_ifc_pude_reg_bits pude_reg;
8681         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8682         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8683         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8684         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8685         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8686         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8687         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8688         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8689         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8690         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8691         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8692         u8         reserved_at_0[0x60e0];
8693 };
8694
8695 union mlx5_ifc_debug_enhancements_document_bits {
8696         struct mlx5_ifc_health_buffer_bits health_buffer;
8697         u8         reserved_at_0[0x200];
8698 };
8699
8700 union mlx5_ifc_uplink_pci_interface_document_bits {
8701         struct mlx5_ifc_initial_seg_bits initial_seg;
8702         u8         reserved_at_0[0x20060];
8703 };
8704
8705 struct mlx5_ifc_set_flow_table_root_out_bits {
8706         u8         status[0x8];
8707         u8         reserved_at_8[0x18];
8708
8709         u8         syndrome[0x20];
8710
8711         u8         reserved_at_40[0x40];
8712 };
8713
8714 struct mlx5_ifc_set_flow_table_root_in_bits {
8715         u8         opcode[0x10];
8716         u8         reserved_at_10[0x10];
8717
8718         u8         reserved_at_20[0x10];
8719         u8         op_mod[0x10];
8720
8721         u8         other_vport[0x1];
8722         u8         reserved_at_41[0xf];
8723         u8         vport_number[0x10];
8724
8725         u8         reserved_at_60[0x20];
8726
8727         u8         table_type[0x8];
8728         u8         reserved_at_88[0x18];
8729
8730         u8         reserved_at_a0[0x8];
8731         u8         table_id[0x18];
8732
8733         u8         reserved_at_c0[0x8];
8734         u8         underlay_qpn[0x18];
8735         u8         reserved_at_e0[0x120];
8736 };
8737
8738 enum {
8739         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8740         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8741 };
8742
8743 struct mlx5_ifc_modify_flow_table_out_bits {
8744         u8         status[0x8];
8745         u8         reserved_at_8[0x18];
8746
8747         u8         syndrome[0x20];
8748
8749         u8         reserved_at_40[0x40];
8750 };
8751
8752 struct mlx5_ifc_modify_flow_table_in_bits {
8753         u8         opcode[0x10];
8754         u8         reserved_at_10[0x10];
8755
8756         u8         reserved_at_20[0x10];
8757         u8         op_mod[0x10];
8758
8759         u8         other_vport[0x1];
8760         u8         reserved_at_41[0xf];
8761         u8         vport_number[0x10];
8762
8763         u8         reserved_at_60[0x10];
8764         u8         modify_field_select[0x10];
8765
8766         u8         table_type[0x8];
8767         u8         reserved_at_88[0x18];
8768
8769         u8         reserved_at_a0[0x8];
8770         u8         table_id[0x18];
8771
8772         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8773 };
8774
8775 struct mlx5_ifc_ets_tcn_config_reg_bits {
8776         u8         g[0x1];
8777         u8         b[0x1];
8778         u8         r[0x1];
8779         u8         reserved_at_3[0x9];
8780         u8         group[0x4];
8781         u8         reserved_at_10[0x9];
8782         u8         bw_allocation[0x7];
8783
8784         u8         reserved_at_20[0xc];
8785         u8         max_bw_units[0x4];
8786         u8         reserved_at_30[0x8];
8787         u8         max_bw_value[0x8];
8788 };
8789
8790 struct mlx5_ifc_ets_global_config_reg_bits {
8791         u8         reserved_at_0[0x2];
8792         u8         r[0x1];
8793         u8         reserved_at_3[0x1d];
8794
8795         u8         reserved_at_20[0xc];
8796         u8         max_bw_units[0x4];
8797         u8         reserved_at_30[0x8];
8798         u8         max_bw_value[0x8];
8799 };
8800
8801 struct mlx5_ifc_qetc_reg_bits {
8802         u8                                         reserved_at_0[0x8];
8803         u8                                         port_number[0x8];
8804         u8                                         reserved_at_10[0x30];
8805
8806         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8807         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8808 };
8809
8810 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8811         u8         e[0x1];
8812         u8         reserved_at_01[0x0b];
8813         u8         prio[0x04];
8814 };
8815
8816 struct mlx5_ifc_qpdpm_reg_bits {
8817         u8                                     reserved_at_0[0x8];
8818         u8                                     local_port[0x8];
8819         u8                                     reserved_at_10[0x10];
8820         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8821 };
8822
8823 struct mlx5_ifc_qpts_reg_bits {
8824         u8         reserved_at_0[0x8];
8825         u8         local_port[0x8];
8826         u8         reserved_at_10[0x2d];
8827         u8         trust_state[0x3];
8828 };
8829
8830 struct mlx5_ifc_pptb_reg_bits {
8831         u8         reserved_at_0[0x2];
8832         u8         mm[0x2];
8833         u8         reserved_at_4[0x4];
8834         u8         local_port[0x8];
8835         u8         reserved_at_10[0x6];
8836         u8         cm[0x1];
8837         u8         um[0x1];
8838         u8         pm[0x8];
8839
8840         u8         prio_x_buff[0x20];
8841
8842         u8         pm_msb[0x8];
8843         u8         reserved_at_48[0x10];
8844         u8         ctrl_buff[0x4];
8845         u8         untagged_buff[0x4];
8846 };
8847
8848 struct mlx5_ifc_pbmc_reg_bits {
8849         u8         reserved_at_0[0x8];
8850         u8         local_port[0x8];
8851         u8         reserved_at_10[0x10];
8852
8853         u8         xoff_timer_value[0x10];
8854         u8         xoff_refresh[0x10];
8855
8856         u8         reserved_at_40[0x9];
8857         u8         fullness_threshold[0x7];
8858         u8         port_buffer_size[0x10];
8859
8860         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8861
8862         u8         reserved_at_2e0[0x40];
8863 };
8864
8865 struct mlx5_ifc_qtct_reg_bits {
8866         u8         reserved_at_0[0x8];
8867         u8         port_number[0x8];
8868         u8         reserved_at_10[0xd];
8869         u8         prio[0x3];
8870
8871         u8         reserved_at_20[0x1d];
8872         u8         tclass[0x3];
8873 };
8874
8875 struct mlx5_ifc_mcia_reg_bits {
8876         u8         l[0x1];
8877         u8         reserved_at_1[0x7];
8878         u8         module[0x8];
8879         u8         reserved_at_10[0x8];
8880         u8         status[0x8];
8881
8882         u8         i2c_device_address[0x8];
8883         u8         page_number[0x8];
8884         u8         device_address[0x10];
8885
8886         u8         reserved_at_40[0x10];
8887         u8         size[0x10];
8888
8889         u8         reserved_at_60[0x20];
8890
8891         u8         dword_0[0x20];
8892         u8         dword_1[0x20];
8893         u8         dword_2[0x20];
8894         u8         dword_3[0x20];
8895         u8         dword_4[0x20];
8896         u8         dword_5[0x20];
8897         u8         dword_6[0x20];
8898         u8         dword_7[0x20];
8899         u8         dword_8[0x20];
8900         u8         dword_9[0x20];
8901         u8         dword_10[0x20];
8902         u8         dword_11[0x20];
8903 };
8904
8905 struct mlx5_ifc_dcbx_param_bits {
8906         u8         dcbx_cee_cap[0x1];
8907         u8         dcbx_ieee_cap[0x1];
8908         u8         dcbx_standby_cap[0x1];
8909         u8         reserved_at_0[0x5];
8910         u8         port_number[0x8];
8911         u8         reserved_at_10[0xa];
8912         u8         max_application_table_size[6];
8913         u8         reserved_at_20[0x15];
8914         u8         version_oper[0x3];
8915         u8         reserved_at_38[5];
8916         u8         version_admin[0x3];
8917         u8         willing_admin[0x1];
8918         u8         reserved_at_41[0x3];
8919         u8         pfc_cap_oper[0x4];
8920         u8         reserved_at_48[0x4];
8921         u8         pfc_cap_admin[0x4];
8922         u8         reserved_at_50[0x4];
8923         u8         num_of_tc_oper[0x4];
8924         u8         reserved_at_58[0x4];
8925         u8         num_of_tc_admin[0x4];
8926         u8         remote_willing[0x1];
8927         u8         reserved_at_61[3];
8928         u8         remote_pfc_cap[4];
8929         u8         reserved_at_68[0x14];
8930         u8         remote_num_of_tc[0x4];
8931         u8         reserved_at_80[0x18];
8932         u8         error[0x8];
8933         u8         reserved_at_a0[0x160];
8934 };
8935
8936 struct mlx5_ifc_lagc_bits {
8937         u8         reserved_at_0[0x1d];
8938         u8         lag_state[0x3];
8939
8940         u8         reserved_at_20[0x14];
8941         u8         tx_remap_affinity_2[0x4];
8942         u8         reserved_at_38[0x4];
8943         u8         tx_remap_affinity_1[0x4];
8944 };
8945
8946 struct mlx5_ifc_create_lag_out_bits {
8947         u8         status[0x8];
8948         u8         reserved_at_8[0x18];
8949
8950         u8         syndrome[0x20];
8951
8952         u8         reserved_at_40[0x40];
8953 };
8954
8955 struct mlx5_ifc_create_lag_in_bits {
8956         u8         opcode[0x10];
8957         u8         reserved_at_10[0x10];
8958
8959         u8         reserved_at_20[0x10];
8960         u8         op_mod[0x10];
8961
8962         struct mlx5_ifc_lagc_bits ctx;
8963 };
8964
8965 struct mlx5_ifc_modify_lag_out_bits {
8966         u8         status[0x8];
8967         u8         reserved_at_8[0x18];
8968
8969         u8         syndrome[0x20];
8970
8971         u8         reserved_at_40[0x40];
8972 };
8973
8974 struct mlx5_ifc_modify_lag_in_bits {
8975         u8         opcode[0x10];
8976         u8         reserved_at_10[0x10];
8977
8978         u8         reserved_at_20[0x10];
8979         u8         op_mod[0x10];
8980
8981         u8         reserved_at_40[0x20];
8982         u8         field_select[0x20];
8983
8984         struct mlx5_ifc_lagc_bits ctx;
8985 };
8986
8987 struct mlx5_ifc_query_lag_out_bits {
8988         u8         status[0x8];
8989         u8         reserved_at_8[0x18];
8990
8991         u8         syndrome[0x20];
8992
8993         u8         reserved_at_40[0x40];
8994
8995         struct mlx5_ifc_lagc_bits ctx;
8996 };
8997
8998 struct mlx5_ifc_query_lag_in_bits {
8999         u8         opcode[0x10];
9000         u8         reserved_at_10[0x10];
9001
9002         u8         reserved_at_20[0x10];
9003         u8         op_mod[0x10];
9004
9005         u8         reserved_at_40[0x40];
9006 };
9007
9008 struct mlx5_ifc_destroy_lag_out_bits {
9009         u8         status[0x8];
9010         u8         reserved_at_8[0x18];
9011
9012         u8         syndrome[0x20];
9013
9014         u8         reserved_at_40[0x40];
9015 };
9016
9017 struct mlx5_ifc_destroy_lag_in_bits {
9018         u8         opcode[0x10];
9019         u8         reserved_at_10[0x10];
9020
9021         u8         reserved_at_20[0x10];
9022         u8         op_mod[0x10];
9023
9024         u8         reserved_at_40[0x40];
9025 };
9026
9027 struct mlx5_ifc_create_vport_lag_out_bits {
9028         u8         status[0x8];
9029         u8         reserved_at_8[0x18];
9030
9031         u8         syndrome[0x20];
9032
9033         u8         reserved_at_40[0x40];
9034 };
9035
9036 struct mlx5_ifc_create_vport_lag_in_bits {
9037         u8         opcode[0x10];
9038         u8         reserved_at_10[0x10];
9039
9040         u8         reserved_at_20[0x10];
9041         u8         op_mod[0x10];
9042
9043         u8         reserved_at_40[0x40];
9044 };
9045
9046 struct mlx5_ifc_destroy_vport_lag_out_bits {
9047         u8         status[0x8];
9048         u8         reserved_at_8[0x18];
9049
9050         u8         syndrome[0x20];
9051
9052         u8         reserved_at_40[0x40];
9053 };
9054
9055 struct mlx5_ifc_destroy_vport_lag_in_bits {
9056         u8         opcode[0x10];
9057         u8         reserved_at_10[0x10];
9058
9059         u8         reserved_at_20[0x10];
9060         u8         op_mod[0x10];
9061
9062         u8         reserved_at_40[0x40];
9063 };
9064
9065 struct mlx5_ifc_alloc_memic_in_bits {
9066         u8         opcode[0x10];
9067         u8         reserved_at_10[0x10];
9068
9069         u8         reserved_at_20[0x10];
9070         u8         op_mod[0x10];
9071
9072         u8         reserved_at_30[0x20];
9073
9074         u8         reserved_at_40[0x18];
9075         u8         log_memic_addr_alignment[0x8];
9076
9077         u8         range_start_addr[0x40];
9078
9079         u8         range_size[0x20];
9080
9081         u8         memic_size[0x20];
9082 };
9083
9084 struct mlx5_ifc_alloc_memic_out_bits {
9085         u8         status[0x8];
9086         u8         reserved_at_8[0x18];
9087
9088         u8         syndrome[0x20];
9089
9090         u8         memic_start_addr[0x40];
9091 };
9092
9093 struct mlx5_ifc_dealloc_memic_in_bits {
9094         u8         opcode[0x10];
9095         u8         reserved_at_10[0x10];
9096
9097         u8         reserved_at_20[0x10];
9098         u8         op_mod[0x10];
9099
9100         u8         reserved_at_40[0x40];
9101
9102         u8         memic_start_addr[0x40];
9103
9104         u8         memic_size[0x20];
9105
9106         u8         reserved_at_e0[0x20];
9107 };
9108
9109 struct mlx5_ifc_dealloc_memic_out_bits {
9110         u8         status[0x8];
9111         u8         reserved_at_8[0x18];
9112
9113         u8         syndrome[0x20];
9114
9115         u8         reserved_at_40[0x40];
9116 };
9117
9118 #endif /* MLX5_IFC_H */